Semiconductor device

Abstract

To realize a semiconductor device with high mobility and high reliability.SOLUTION: A semiconductor device includes, on a substrate, a metal oxide layer containing aluminum as the main component, an oxide semiconductor layer on the metal oxide layer, a gate electrode facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The thickness of the metal oxide layer is from 1 nm or more to 4 nm or less. The thickness of the metal oxide layer may be from 1 nm or more to 3 nm or less.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device using an oxide semiconductor as a channel.

Background Art

[0002] In recent years, development of semiconductor devices using an oxide semiconductor as a channel has been underway instead of amorphous silicon, low-temperature polysilicon, and single-crystalline silicon (for example, Patent Documents 1 to 6). A semiconductor device using an oxide semiconductor as a channel can be formed with a simple structure and a low-temperature process, similar to a semiconductor device using amorphous silicon as a channel. A semiconductor device using an oxide semiconductor as a channel is known to have higher mobility than a semiconductor device using amorphous silicon as a channel.

[0003] In order for a semiconductor device using an oxide semiconductor as a channel to operate stably, it is important to supply oxygen to the oxide semiconductor layer in the manufacturing process to reduce oxygen deficiencies formed in the oxide semiconductor layer. As one method of supplying oxygen to the oxide semiconductor layer, for example, a technique of forming an insulating layer covering the oxide semiconductor layer under conditions where the insulating layer contains more oxygen has been disclosed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, an insulating layer formed under conditions containing more oxygen contains many defects. Due to this influence, characteristic abnormalities of semiconductor devices or characteristic fluctuations in reliability tests, which are considered to be caused by electrons being trapped in these defects, occur. On the other hand, when using an insulating layer with few defects, the amount of oxygen contained in the insulating layer cannot be increased. Therefore, oxygen cannot be sufficiently supplied from the insulating layer to the oxide semiconductor layer. Thus, it is required to realize a structure that can repair oxygen deficiencies formed in the oxide semiconductor layer while reducing defects in the insulating layer that cause characteristic fluctuations in semiconductor devices.

[0006] One of the embodiments of the present invention aims to realize a semiconductor device with high reliability and mobility.

Means for Solving the Problems

[0007] A semiconductor device according to an embodiment of the present invention includes a metal oxide layer mainly composed of aluminum provided on a substrate, an oxide semiconductor layer provided on the metal oxide layer, a gate electrode facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The thickness of the metal oxide layer is 1 nm or more and 4 nm or less.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are naturally included in the scope of the present invention. For the sake of clearer explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each figure, elements that are the same as those described above with respect to the previously shown figures may be given the same reference numerals, and detailed description may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or upward. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or downward. Thus, for the sake of convenience of explanation, the terms up or downward are used for explanation. However, for example, the substrate and the oxide semiconductor layer may be arranged such that their vertical relationship is reversed from that shown in the drawing. In the following description, for example, the expression an oxide semiconductor layer on a substrate merely explains the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. Up or downward means the stacking order in a structure in which a plurality of layers are stacked. When expressing a pixel electrode above a transistor, in a plan view, the transistor and the pixel electrode may have a positional relationship where they do not overlap. On the other hand, when expressing a pixel electrode directly above the transistor in the vertical direction, in a plan view, it means a positional relationship where the transistor and the pixel electrode overlap.

[0011] The "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (for example, a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescence (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer as long as there is no technical contradiction. Therefore, for the embodiments described below, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer will be exemplified and described, but the structure in this embodiment can be applied to a display device including other electro-optical layers described above.

[0012] In this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Further, these expressions do not exclude the case where α includes other elements.

[0013] Note that the following embodiments can be combined with each other as long as there is no technical contradiction.

[0014] [1. First Embodiment] A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 10. The semiconductor device of the embodiment shown below may be used for an integrated circuit (IC) such as a micro-processing unit (MPU) or a memory circuit in addition to a transistor used for a display device.

[0015] [1-1. Configuration of Semiconductor Device 10] The configuration of a semiconductor device 10 according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention.

[0016] As shown in FIG. 1, the semiconductor device 10 is provided above the substrate 100. The semiconductor device 10 includes a gate electrode 105, gate insulating layers 110 and 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as a source-drain electrode 200.

[0017] The gate electrode 105 is provided on the substrate 100. The gate insulating layers 110 and 120 are provided on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. The oxide semiconductor layer 140 is patterned. A part of the metal oxide layer 130 extends beyond the end of the oxide semiconductor layer 140 and outside the pattern of the oxide semiconductor layer 140. However, the metal oxide layer 130 may be patterned in the same planar shape as the oxide semiconductor layer 140.

[0018] The thickness of the metal oxide layer 130 is 1 nm or more and 4 nm or less, or 1 nm or more and 3 nm or less. The ratio of the thickness of the metal oxide layer 130 to the thickness of the oxide semiconductor layer 140 is 1 / 30 or more and 4 / 30 or less, or 1 / 30 or more and 1 / 10 or less. Although details will be described later, by setting the thickness of the metal oxide layer 130 within the above range, a semiconductor device with high mobility and reliability can be realized.

[0019] In other words, the gate insulating layer 120 is provided between the substrate 100 and the metal oxide layer 130. Further in other words, the metal oxide layer 130 is in contact with each of the gate insulating layer 120 and the oxide semiconductor layer 140 between the gate insulating layer 120 and the oxide semiconductor layer 140. Although details will be described later, the gate insulating layer 120 is an insulating layer containing oxygen. Specifically, the gate insulating layer 120 is an insulating layer having a function of releasing oxygen by heat treatment at 600°C or lower. The oxygen released from the gate insulating layer 120 by heat treatment repairs the oxygen deficiency formed in the oxide semiconductor layer 140. The gate insulating layer 120 may be referred to as the "first insulating layer".

[0020] In this embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100.

[0021] In this embodiment, a configuration in which the metal oxide layer 130 is in contact with the gate insulating layer 120 and the oxide semiconductor layer 140 is in contact with the metal oxide layer 130 is illustrated, but the present invention is not limited to this configuration. Other layers may be provided between the gate insulating layer 120 and the metal oxide layer 130. Other layers may be provided between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0022] The gate electrode 160 faces the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. Of the main surfaces of the oxide semiconductor layer 140, the surface in contact with the gate insulating layer 150 is referred to as the upper surface 141. Of the main surfaces of the oxide semiconductor layer 140, the surface in contact with the metal oxide layer 130 is referred to as the lower surface 142. The surface between the upper surface 141 and the lower surface 142 is referred to as the side surface 143. The insulating layers 170 and 180 are provided over the gate insulating layer 150 and the gate electrode 160. The insulating layers 170 and 180 are provided with openings 171 and 173 that reach the oxide semiconductor layer 140. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0023] The gate electrode 105 has a function as a bottom gate of the semiconductor device 10 and a function as a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 has a function as a barrier film that shields impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom gate. The metal oxide layer 130 is a layer containing a metal oxide mainly composed of aluminum and has barrier properties for shielding gases such as oxygen and hydrogen.

[0024] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is the region directly below the gate electrode 160 in the oxide semiconductor layer 140. The source region S is a region in the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 in plan view and is closer to the source electrode 201 than the channel region CH. The drain region D is a region in the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 in plan view and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 140 in the channel region CH has physical properties as a semiconductor. The oxide semiconductor layer 140 in the source region S and the drain region D has physical properties as a conductor.

[0025] The gate electrode 160 functions as a top gate of the semiconductor device 10 and a light-shielding film for the oxide semiconductor layer 140. The gate insulating layer 150 functions as a gate insulating layer for the top gate and has a function of releasing oxygen by heat treatment in the manufacturing process, similar to the gate insulating layer 120. The insulating layers 170 and 180 insulate the gate electrode 160 from the source and drain electrodes 200 and have a function of reducing the parasitic capacitance between them. The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, when the gate electrode 105 is simply used as a light-shielding film, no specific voltage is supplied to the gate electrode 105, and the potential of the gate electrode 105 may be floating. That is, the gate electrode 105 may simply be called a "light-shielding film". In that case, the light-shielding film may be an insulator.

[0026] In this embodiment, as the semiconductor device 10, a configuration in which a dual-gate transistor having gate electrodes provided both above and below the oxide semiconductor layer is used is exemplified, but the present invention is not limited to this configuration. For example, as the semiconductor device 10, a bottom-gate transistor having a gate electrode provided only below the oxide semiconductor layer or a top-gate transistor having a gate electrode provided only above the oxide semiconductor layer may be used. The above configuration is merely an embodiment, and the present invention is not limited to the above configuration.

[0027] Referring to FIGS. 1 and 2, the lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130. In particular, in this embodiment, the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130. In the D1 direction shown in FIG. 2, the width of the gate electrode 105 is larger than the width of the gate electrode 160. The D1 direction is the direction connecting the source electrode 201 and the drain electrode 203, and is the direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of the region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W.

[0028] In this embodiment, a configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130 is exemplified, but the present invention is not limited to this configuration. For example, a part of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered by the metal oxide layer 130, and all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered by the metal oxide layer 130. That is, all or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, a part of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered by the metal oxide layer 130, and the other part of the lower surface 142 may be in contact with the metal oxide layer 130.

[0029] In this embodiment, although an example is given in which the gate insulating layer 150 is formed over the entire surface and openings 171 and 173 are provided in the gate insulating layer 150, the present invention is not limited to this configuration. The gate insulating layer 150 may be patterned into a shape different from the shape in which the openings 171 and 173 are provided. For example, the gate insulating layer 150 may be patterned so as to expose all or part of the oxide semiconductor layer 140 in the source region S and the drain region D. That is, the gate insulating layer 150 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 140 and the insulating layer 170 may be in contact with each other in these regions.

[0030] In FIG. 2, although an example is shown in which the source-drain electrodes 200 do not overlap the gate electrode 105 and the gate electrode 160 in a plan view, the present invention is not limited to this configuration. For example, in a plan view, the source-drain electrodes 200 may overlap at least one of the gate electrode 105 and the gate electrode 160. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0031] [1-2. Materials of Members of Semiconductor Device 10] As the substrate 100, a rigid substrate having translucency such as a glass substrate, a quartz substrate, and a sapphire substrate is used. When the substrate 100 needs to have flexibility, a substrate containing a resin such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate is used as the substrate 100. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the above resin in order to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top emission type display, since the substrate 100 does not need to be transparent, impurities that deteriorate the transparency of the substrate 100 may be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, a substrate that does not have translucency such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, and a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate is used as the substrate 100.

[0032] As the gate electrodes 105, 160, and source / drain electrodes 200, common metal materials are used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and their alloys or compounds are used. As the gate electrodes 105, 160, and source / drain electrodes 200, the above materials may be used in a single layer or in a stacked layer.

[0033] As the gate insulating layers 110, 120 and insulating layers 170, 180, common insulating materials are used. For example, as these insulating layers, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers are used.

[0034] As the gate insulating layer 150, an insulating layer containing oxygen among the above insulating layers is used. For example, as the gate insulating layer 150, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ) and other inorganic insulating layers are used.

[0035] As the gate insulating layer 120, an insulating layer having a function of releasing oxygen by heat treatment is used. The temperature of the heat treatment for the gate insulating layer 120 to release oxygen is, for example, 600 °C or lower, 500 °C or lower, 450 °C or lower, or 400 °C or lower. That is, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when, for example, a glass substrate is used as the substrate 100. As at least one of the insulating layers 170 and 180, an insulating layer having a function of releasing oxygen by heat treatment is used in the same manner as the gate insulating layer 120.

[0036] As the gate insulating layer 150, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layer 150 with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layer 150 is closer to the stoichiometric ratio with respect to the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiO x ) is used for each of the gate insulating layer 150 and the insulating layer 180, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 180. For example, as the gate insulating layer 150, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used.

[0037] The above SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio smaller than that of oxygen (O) (x > y). SiN x O y and AlN x O y are silicon compounds and aluminum compounds containing oxygen in a ratio smaller than that of nitrogen (x > y).

[0038] As the metal oxide layer 130, a metal oxide mainly composed of aluminum is used. For example, as the metal oxide layer 130, inorganic insulating layers such as aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), and aluminum nitride (AlN x ) are used. The "metal oxide layer mainly composed of aluminum" means that the ratio of aluminum contained in the metal oxide layer 130 is 1% or more of the entire metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

[0039] As the oxide semiconductor layer 140, a metal oxide having semiconductor characteristics can be used. 。

[0040] The oxide semiconductor layer 140 may be amorphous or crystalline. Further, the oxide semiconductor layer 140 may be a mixed phase of amorphous and crystal. 。

[0041] In the oxide semiconductor layer 140, when oxygen contained in the oxide semiconductor layer 140 is reduced, oxygen vacancies are formed in the oxide semiconductor layer 140. In the semiconductor device 10, in the heat treatment step of the manufacturing process, hydrogen is released from the layer provided closer to the substrate 100 side than the oxide semiconductor layer 140 (for example, the gate insulating layers 110 and 120), and when the hydrogen reaches the oxide semiconductor layer 140, oxygen vacancies are generated in the oxide semiconductor layer 140. The generation of such oxygen vacancies is more prominent as the pattern size of the oxide semiconductor layer 140 is larger. In order to suppress the generation of such oxygen vacancies, it is necessary to suppress the reach of hydrogen to the lower surface 142 of the oxide semiconductor layer 140.

[0042] On the other hand, the upper surface 141 of the oxide semiconductor layer 140 is affected by processes (for example, patterning processes or etching processes) after the formation of the oxide semiconductor layer 140. In contrast, the lower surface 142 of the oxide semiconductor layer 140 (the surface on the substrate 100 side of the oxide semiconductor layer 140) is not affected by such influences.

[0043] Therefore, the oxygen deficiency formed on the upper surface 141 of the oxide semiconductor layer 140 is more than that formed on the lower surface 142 of the oxide semiconductor layer 140. That is, the oxygen deficiency in the oxide semiconductor layer 140 does not exist uniformly in the thickness direction of the oxide semiconductor layer 140, but exists in a non-uniform distribution in the thickness direction of the oxide semiconductor layer 140. Specifically, the oxygen deficiency in the oxide semiconductor layer 140 is less on the lower surface 142 side of the oxide semiconductor layer 140 and more on the upper surface 141 side of the oxide semiconductor layer 140.

[0044] When an oxygen supply process is uniformly performed on the oxide semiconductor layer 140 having the oxygen deficiency distribution as described above, when an amount of oxygen necessary to repair the oxygen deficiency formed on the upper surface 141 side of the oxide semiconductor layer 140 is supplied, oxygen is excessively supplied to the lower surface 142 side of the oxide semiconductor layer 140. As a result, on the lower surface 142 side, defect levels different from oxygen deficiency are formed by the excess oxygen, and phenomena such as characteristic variations in the reliability test or a decrease in the field-effect mobility occur. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface 141 side of the oxide semiconductor layer 140 while suppressing the oxygen supply to the lower surface 142 side of the oxide semiconductor layer 140.

[0045] The above problems are problems newly recognized in the process leading to the present invention, and are not problems conventionally recognized. In the conventional configurations and manufacturing methods, even if the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer, there is a trade-off relationship between the initial characteristics and the reliability test in that characteristic variations occur in the reliability test. However, with the configuration according to the present embodiment, the above problems are solved, and good initial characteristics and reliability test results of the semiconductor device 10 can be obtained.

[0046] In order to solve the above problems, a metal oxide layer 130 is provided between the gate insulating layer 120 and the oxide semiconductor layer 140. Furthermore, by setting the thickness of the metal oxide layer 130 to be 1 nm or more and 4 nm or less, or 1 nm or more and 3 nm or less, a semiconductor device with high mobility and reliability can be realized.

[0047] [1-3. Manufacturing method of semiconductor device 10] Using FIGS. 3 to 10, a manufacturing method of a semiconductor device according to an embodiment of the present invention will be described. FIG. 3 is a sequence diagram showing a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIGS. 4 to 10 are cross-sectional views showing a manufacturing method of a semiconductor device according to an embodiment of the present invention. In the following description of the manufacturing method, a manufacturing method of the semiconductor device 10 in which aluminum oxide is used as the metal oxide layer 130 will be described.

[0048] As shown in FIGS. 3 and 4, a gate electrode 105 is formed as a bottom gate on the substrate 100, and gate insulating layers 110 and 120 are formed on the gate electrode 105 ("Bottom GI / GE formation" in step S1001 of FIG. 3). As the gate insulating layer 110, for example, silicon nitride is formed. As the gate insulating layer 120, for example, silicon oxide is formed. The gate insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method.

[0049] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block impurities that diffuse from, for example, the substrate 100 side toward the oxide semiconductor layer 140. The silicon oxide used as the gate insulating layer 120 is silicon oxide having a physical property of releasing oxygen by heat treatment.

[0050] As shown in FIGS. 3 and 5, a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the gate insulating layer 120 (the "OS / AlOx film formation" in step S1002 of FIG. 3). The metal oxide layer 130 and the oxide semiconductor layer 140 are formed by a sputtering method or an atomic layer deposition method (ALD: Atomic Layer Deposition).

[0051] The thickness of the metal oxide layer 130 is, for example, 1 nm or more and 4 nm or less, or 1 nm or more and 3 nm or less. Since the thickness of the metal oxide layer 130 is very small, it is necessary to keep the film formation rate of the metal oxide layer 130 low. For this purpose, it is preferable to set the film formation power as low as possible and set the oxygen partial pressure in the process gas during film formation high. The film formation rate of the metal oxide layer 130 is, for example, 0.04 nm / sec to 0.3 nm / sec in the case of sputtering film formation, and 0.005 nm / sec to 0.01 nm / sec in the case of ALD. In the present embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has a high barrier property against gas. In the present embodiment, the aluminum oxide used as the metal oxide layer 130 blocks a part of the hydrogen and oxygen released from the gate insulating layer 120 and adjusts the amount of the released hydrogen and oxygen reaching the oxide semiconductor layer 140.

[0052] The thickness of the oxide semiconductor layer 140 is, for example, 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. In the present embodiment, the thickness of the oxide semiconductor layer 140 is 30 nm. The oxide semiconductor layer 140 before the heat treatment (OS annealing) described later is amorphous.

[0053] Example For example, when the oxide semiconductor layer 140 is formed by a sputtering method, the oxide semiconductor layer 140 is formed while controlling the temperature of the object to be film-formed (the substrate 100 and the structure formed thereon).

[0054] When film formation is performed on an object to be film-formed by a sputtering method, ions generated in the plasma and atoms rebounded by the sputtering target collide with the object to be film-formed. Therefore, the temperature of the object to be film-formed rises with the film formation process. 。Upper As described above, in order to control the temperature of the object to be film-formed, for example, film formation can be performed while cooling the object to be film-formed. For example, the object to be film-formed can be cooled from the surface opposite to the film-formed surface so that the temperature of the film-formed surface of the object to be film-formed (hereinafter referred to as "film formation temperature") becomes 100°C or lower, 70°C or lower, 50°C or lower, or 30°C or lower. 。Na In addition, when an amorphous oxide semiconductor film is used as the active layer of a thin film transistor, the above-described film formation temperature management is not particularly necessary.

[0055] As shown in FIGS. 3 and 6, a pattern of the oxide semiconductor layer 140 is formed (the "OS pattern formation" in step S1003 of FIG. 3). Although not shown, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. As the etching of the oxide semiconductor layer 140, wet etching may be used, or dry etching may be used. As the wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0056] After the pattern formation of the oxide semiconductor layer 140, heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 (the "OS annealing" in step S1004 of FIG. 3). In this embodiment, the oxide semiconductor layer 140 is crystallized by this OS annealing. However, the oxide semiconductor layer 140 does not necessarily have to be crystallized by the OS annealing.

[0057] In this embodiment, a manufacturing method in which only the oxide semiconductor layer 140 is patterned has been exemplified, but the method is not limited to this. For example, the pattern of the metal oxide layer 130 may be substantially the same as the pattern of the oxide semiconductor layer 140. When the oxide semiconductor layer 140 is crystallized by OS annealing, the metal oxide layer 130 may be patterned by etching the metal oxide layer 130 using the oxide semiconductor layer 140 as a mask. On the other hand, when the oxide semiconductor layer 140 remains amorphous even after OS annealing, the metal oxide layer 130 may be patterned by etching the metal oxide layer 130 using the resist used for patterning the oxide semiconductor layer 140 as a mask.

[0058] As shown in FIGS. 3 and 7, a gate insulating layer 150 is formed (``GI formation'' in step S1005 of FIG. 3). For example, silicon oxide is formed as the gate insulating layer 150. The gate insulating layer 150 is formed by a CVD method. For example, in order to form an insulating layer with few defects as described above as the gate insulating layer 150, the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is, for example, 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less. After forming the gate insulating layer 150, a process of implanting oxygen into the gate insulating layer 150 may be performed.

[0059] With the gate insulating layer 150 formed on the oxide semiconductor layer 140, a heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 140 is performed (``oxidation annealing'' in step S1006 of FIG. 3). In the process from when the oxide semiconductor layer 140 is formed until the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen deficiencies occur on the upper surface 141 and side surface 143 of the oxide semiconductor layer 140. By the above oxidation annealing, the oxygen released from the gate insulating layers 120 and 150 is supplied to the oxide semiconductor layer 140, and the oxygen deficiencies are repaired. When the process of implanting oxygen into the gate insulating layer 150 is not performed, oxidation annealing is performed in a state where an insulating layer that releases oxygen by heat treatment is formed on the gate insulating layer 150.

[0060] By oxidation annealing, since part of the oxygen released from the gate insulating layer 120 is blocked by the metal oxide layer 130, it is difficult to supply oxygen to the lower surface 142 of the oxide semiconductor layer 140. On the other hand, the oxygen released from the gate insulating layer 150 is supplied to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. By the above oxidation annealing, hydrogen may be released from the gate insulating layers 110 and 120, but the hydrogen is blocked by the metal oxide layer 130.

[0061] As described above, by the process of oxidation annealing, it is possible to suppress the supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140 with a small amount of oxygen deficiency while supplying oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 with a large amount of oxygen deficiency.

[0062] In order to increase the amount of oxygen supplied from the gate insulating layer 150, a step of implanting oxygen into the gate insulating layer 150 may be added by forming a metal oxide layer similar to the metal oxide layer 130 on the gate insulating layer 150 by sputtering. Further, the above oxidation annealing may be performed in a state where the metal oxide layer is formed on the gate insulating layer 150. By using aluminum oxide having a high barrier property against gas as this metal oxide layer, it is possible to suppress the outward diffusion of the oxygen implanted into the gate insulating layer 150 during oxidation annealing.

[0063] As shown in FIGS. 3 and 8, a gate electrode 160 is formed (``GE formation'' in step S1007 of FIG. 3). The gate electrode 160 is formed by sputtering or atomic layer deposition and patterned through a photolithography process.

[0064] With the gate electrode 160 patterned, the source region S and the drain region D of the oxide semiconductor layer 140 are made to have lower resistance (the "SD lower resistance" in step S1008 of FIG. 3). Specifically, impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 from the gate electrode 160 side by ion implantation. By ion implantation, for example, argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 140. By forming oxygen vacancies in the oxide semiconductor layer 140 by ion implantation, the oxide semiconductor layer 140 has lower resistance. Since the gate electrode 160 is provided above the oxide semiconductor layer 140 that functions as the channel region CH of the semiconductor device 10, no impurities are implanted into the oxide semiconductor layer 140 of the channel region CH.

[0065] As shown in FIGS. 3 and 9, insulating layers 170 and 180 are formed as interlayer films on the gate insulating layer 150 and the gate electrode 160 (the "interlayer film formation" in step S1009 of FIG. 3). The insulating layers 170 and 180 are formed by CVD method. For example, silicon nitride is formed as the insulating layer 170, and silicon oxide is formed as the insulating layer 180. The materials used as the insulating layers 170 and 180 are not limited to the above. The thickness of the insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.

[0066] As shown in FIGS. 3 and 10, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 (the "contact opening" in step S1010 of FIG. 3). The oxide semiconductor layer 140 of the source region S is exposed by the opening 171. The oxide semiconductor layer 140 of the drain region D is exposed by the opening 173. By forming the source / drain electrodes 200 on the oxide semiconductor layer 140 exposed by the openings 171 and 173 and on the insulating layer 180 (the "SD formation" in step S1011 of FIG. 3), the semiconductor device 10 shown in FIG. 1 is completed.

[0067] In the semiconductor device 10 fabricated by the above manufacturing method, in the range where the channel length L of the channel region CH is 2 μm or more and 4 μm or less, and the channel width of the channel region CH is 2 μm or more and 25 μm or less, the mobility is 30 [cm 2 / Vs] or more, 35 [cm 2 / Vs] or more, or 40 [cm 2 / Vs] or more, and thus the electrical characteristics can be obtained. The mobility in the present embodiment is the field-effect mobility in the saturation region of the semiconductor device 10, and means the maximum value of the field-effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is larger than the value (Vg - Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage (Vg) supplied to the gate electrode.

[0068] [1-4. Electrical Characteristics of Semiconductor Device 10] Using FIGS. 11 to 14, the electrical characteristics and reliability test results of the semiconductor device 10 according to the present embodiment will be described.

[0069] FIG. 11 is a diagram showing the electrical characteristics of a semiconductor device according to an embodiment of the present invention. The measurement conditions of the electrical characteristics shown in FIG. 11 are as follows. · Size of channel region CH: W / L = 4.5 μm / 3.0 μm · Voltage between source and drain: 0.1V (dotted line), 10V (solid line) · Gate voltage: -15V to +15V · Measurement environment: room temperature, dark room

[0070] In FIG. 11, the electrical characteristics (Id-Vg characteristics) and mobility of the semiconductor device 10 are shown. As indicated by the arrow in the graph of FIG. 11, the vertical axis for the drain current (Id) is shown on the left side of the graph, and the vertical axis for the mobility calculated from the drain current is shown on the right side of the graph.

[0071] As shown in FIG. 11, the electrical characteristics of the semiconductor device 10 according to the present embodiment exhibit so-called normally-off characteristics in which the drain current Id starts to flow at a voltage higher than 0V for the gate voltage Vg. The mobility calculated from the electrical characteristics is about 40 [cm2 is / Vs.

[0072] FIG. 12 is a diagram showing the film thickness dependence of the true mobility of a semiconductor device according to an embodiment of the present invention. In FIG. 12, in the semiconductor device 10, the true mobility when the thickness of the metal oxide layer 130 is 0 nm to 15 nm is shown.

[0073] The true mobility indicates the mobility with respect to the effective channel length of the transistor, and can be calculated from data showing the channel length L dependence of the mobility obtained from the electrical characteristics shown in FIG. 11. Specifically, the true mobility can be calculated by performing TLM analysis on the data (L length dependence) plotted on a graph with the channel length L on the horizontal axis and the mobility on the vertical axis.

[0074] As shown in FIG. 12, by forming the metal oxide layer 130 with a thickness of 1 nm, the true mobility is improved compared to the case where the metal oxide layer 130 is not provided (condition of 0 nm). Further, by forming the metal oxide layer 130 with a thickness of 2 nm or more, the true mobility is further improved. When the thickness of the metal oxide layer 130 is 2 nm to 4 nm, the true mobility increases as the thickness of the metal oxide layer 130 increases. From this result, if the metal oxide layer 130 is formed with a thickness of 1 nm or more, the effect of improving the true mobility can be obtained. On the other hand, when the thickness of the metal oxide layer 130 is 5 nm or more, the true mobility tends to be lower than that when the thickness is 4 nm. When the thickness of the metal oxide layer 130 is 5 nm or more, the function of blocking hydrogen diffused from the gate insulating layers 110 and 120 becomes stronger, but on the other hand, the defect levels at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 increase, so it is considered that the true mobility decreases. However, even when the thickness of the metal oxide layer 130 is 15 nm, the true mobility is higher than when there is no metal oxide layer 130.

[0075] FIG. 13 is a diagram showing the thickness dependence of the electrical characteristics and reliability test results of a semiconductor device according to an embodiment of the present invention. In FIG. 13, in the semiconductor device 10, the electrical characteristics and reliability test results when the thickness of the metal oxide layer 130 is 0 nm to 15 nm are shown. The electrical characteristics shown in FIG. 13 are the threshold voltage (Vth_ini) in the initial characteristics. The reliability test result shown in FIG. 13 is the amount of change in the threshold voltage (ΔVth) due to Positive Bias Temperature Stress (PBTS). Vth_ini is indicated by "◇". ΔVth is indicated by "bar graph".

[0076] The conditions of the PBTS reliability test are as follows. · Size of the channel region CH: W / L = 2.5 μm / 2.5 μm · Light irradiation conditions: No irradiation (dark room) · Gate voltage: +30 V · Source and drain voltages: 0 V · Stage temperature during stress application: 85 °C · Stress time: 1000 sec

[0077] As shown in FIG. 13, Vth_ini is slightly negative when the thickness of the metal oxide layer 130 is 3 nm or 4 nm, but is positive in other cases. That is, normally-off electrical characteristics are obtained in most cases. ΔVth when the thickness of the metal oxide layer 130 is 1 to 4 nm shows good values of 2 V or less. In particular, ΔVth when the thickness of the metal oxide layer 130 is 1 to 3 nm is smaller than Vth when the metal oxide layer 130 is not provided.

[0078] FIG. 14 is a diagram plotting the correlation between the electrical characteristics and reliability test results of a semiconductor device according to an embodiment of the present invention for each film thickness. In FIG. 14, the horizontal axis is Vth_ini and the vertical axis is ΔVth. As shown in FIG. 14, as the thickness of the metal oxide layer 130 increases, it shows a behavior along arrow A, but at the boundary when the thickness of the metal oxide layer 130 is 4 nm, it shows a behavior along arrow B. That is, when the thickness of the metal oxide layer 130 is 5 nm or more, it is confirmed that ΔVth by the PBTS reliability test tends to increase. From the above results, the thickness of the metal oxide layer 130 is preferably 4 nm or less.

[0079] As described above, as the thickness of the metal oxide layer 130 increases, the increase in ΔVth is considered to be due to the defect levels present in the film of the metal oxide layer 130.

[0080] From the above results, the thickness of the metal oxide layer 130 is preferably 1 nm or more and 4 nm or less, or 1 nm or more and 3 nm or less.

[0081] As described above, according to the semiconductor device 10 according to the present embodiment, by setting the thickness of the metal oxide layer 130 within the above range, a semiconductor device 10 with high mobility and good reliability test results can be realized.

[0082] [2. Second Embodiment] A display device using the semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 15 to 19. In the embodiment shown below, a configuration in which the semiconductor device 10 described in the above first embodiment is applied to the circuit of a liquid crystal display device will be described.

[0083] [2-1. Outline of Display Device 20] FIG. 15 is a plan view showing an overview of a display device according to an embodiment of the present invention. As shown in FIG. 15, the display device 20 includes an array substrate 300, a seal portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the seal portion 310. In a liquid crystal region 22 surrounded by the seal portion 310, a plurality of pixel circuits 301 are arranged in a matrix. The liquid crystal region 22 is a region that overlaps with a liquid crystal element 311, which will be described later, in a plan view.

[0084] A seal region 24 provided with the seal portion 310 is a region around the liquid crystal region 22. The FPC 330 is provided in a terminal region 26. The terminal region 26 is a region where the array substrate 300 is exposed from the counter substrate 320, and is provided outside the seal region 24. The outside of the seal region 24 means the outside of the region where the seal portion 310 is provided and the region surrounded by the seal portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0085] [2-2. Circuit Configuration of Display Device 20] FIG. 16 is a block diagram showing the circuit configuration of a display device according to an embodiment of the present invention. As shown in FIG. 16, a source driver circuit 302 is provided at a position adjacent to the liquid crystal region 22 in the D1 direction (column direction), and a gate driver circuit 303 is provided at a position adjacent to the liquid crystal region 22 in the D2 direction (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the seal region 24 described above. However, the regions where the source driver circuit 302 and the gate driver circuit 303 are provided are not limited to the seal region 24, and any region may be used as long as it is outside the region where the pixel circuit 301 is provided.

[0086] A source wiring 304 extends from a source driver circuit 302 in the D1 direction and is connected to a plurality of pixel circuits 301 arranged in the D1 direction. A gate wiring 305 extends from a gate driver circuit 303 in the D2 direction and is connected to a plurality of pixel circuits 301 arranged in the D2 direction.

[0087] A terminal portion 306 is provided in a terminal region 26. The terminal portion 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected by the connection wiring 307. By connecting an FPC 330 to the terminal portion 306, an external device to which the FPC 330 is connected and the display device 20 are connected, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0088] The semiconductor device 10 shown in the first embodiment is used as a transistor included in the pixel circuit 301, the source driver circuit 302, and the gate driver circuit 303.

[0089] [2-3. Pixel Circuit 301 of Display Device 20] FIG. 17 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. As shown in FIG. 17, the pixel circuit 301 includes elements such as a semiconductor device 10, a holding capacitor 350, and a liquid crystal element 311. The semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to the gate wiring 305. The source electrode 201 is connected to the source wiring 304. The drain electrode 203 is connected to the holding capacitor 350 and the liquid crystal element 311. In the present embodiment, for convenience of explanation, the electrode indicated by the reference numeral "201" is referred to as a source electrode, and the electrode indicated by the reference numeral "203" is referred to as a drain electrode. However, the electrode indicated by the reference numeral "201" may function as a drain electrode, and the electrode indicated by the reference numeral "203" may function as a source electrode.

[0090] [2-4. Cross-sectional Structure of Display Device 20] FIG. 18 is a cross-sectional view of a display device according to an embodiment of the present invention. As shown in FIG. 18, the display device 20 is a display device using the semiconductor device 10. In the present embodiment, a configuration in which the semiconductor device 10 is used for the pixel circuit 301 is illustrated, but the semiconductor device 10 may be used for peripheral circuits including the source driver circuit 302 and the gate driver circuit 303. In the following description, the configuration of the semiconductor device 10 is the same as that of the semiconductor device 10 shown in FIG. 1, and thus the description thereof is omitted.

[0091] An insulating layer 360 is provided over the source electrode 201 and the drain electrode 203. A common electrode 370 provided in common to a plurality of pixels is provided over the insulating layer 360. An insulating layer 380 is provided over the common electrode 370. Openings 381 are provided in the insulating layers 360 and 380. A pixel electrode 390 is provided over the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

[0092] FIG. 19 is a plan view of a pixel electrode and a common electrode of a display device according to an embodiment of the present invention. As shown in FIG. 19, the common electrode 370 has a superimposed region that overlaps the pixel electrode 390 in plan view and a non-superimposed region that does not overlap the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a horizontal electric field is formed from the pixel electrode 390 in the superimposed region toward the common electrode 370 in the non-superimposed region. By the operation of the liquid crystal molecules included in the liquid crystal element 311 due to this horizontal electric field, the gradation of the pixel is determined.

[0093] [3. Third Embodiment] A display device using the semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 20 and 21. In the present embodiment, a configuration in which the semiconductor device 10 described in the above first embodiment is applied to a circuit of an organic EL display device will be described. Since the outline and circuit configuration of the display device 20 are the same as those shown in FIGS. 15 and 16, the description thereof is omitted.

[0094] [3-1. Pixel Circuit 301 of Display Device 20] FIG. 20 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. As shown in FIG. 20, the pixel circuit 301 includes elements such as a driving transistor 11, a selection transistor 12, a holding capacitor 210, and a light-emitting element DO. The driving transistor 11 and the selection transistor 12 have the same configuration as the semiconductor device 10. The source electrode of the selection transistor 12 is connected to the signal line 211, and the gate electrode of the selection transistor 12 is connected to the gate line 212. The source electrode of the driving transistor 11 is connected to the anode power line 213, and the drain electrode of the driving transistor 11 is connected to one end of the light-emitting element DO. The gate electrode of the driving transistor 11 is connected to the drain electrode of the selection transistor 12. The other end of the light-emitting element DO is connected to the cathode power line 214. The holding capacitor 210 is connected to the gate electrode and the drain electrode of the driving transistor 11. A gradation signal for determining the light emission intensity of the light-emitting element DO is supplied to the signal line 211. A signal for selecting a pixel row for writing the above gradation signal is supplied to the gate line 212.

[0095] [3-2. Cross-sectional structure of the display device 20] FIG. 21 is a cross-sectional view of a display device according to an embodiment of the present invention. The configuration of the display device 20 shown in FIG. 21 is similar to that of the display device 20 shown in FIG. 18, but the structure above the insulating layer 360 of the display device 20 in FIG. 21 is different from the structure above the insulating layer 360 of the display device 20 in FIG. 18. Hereinafter, among the configurations of the display device 20 in FIG. 21, the description of the same configurations as those of the display device 20 in FIG. 18 will be omitted, and the differences between the two will be described.

[0096] As shown in FIG. 21, the display device 20 has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 (light-emitting element DO) above the insulating layer 360. The pixel electrode 390 is provided on the insulating layer 360 and inside the opening 381. An insulating layer 362 is provided on the pixel electrode 390. The insulating layer 362 is provided with an opening 363. The opening 363 corresponds to the light-emitting region. That is, the insulating layer 362 defines pixels. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are provided individually for each pixel. On the other hand, the common electrode 394 is provided in common for a plurality of pixels. Different materials are used for the light-emitting layer 392 according to the display color of the pixel.

[0097] In the second and third embodiments, the configurations in which the semiconductor device described in the first embodiment is applied to a liquid crystal display device and an organic EL display device are illustrated. However, the semiconductor device may be applied to display devices other than these display devices (for example, self-emitting display devices other than organic EL display devices or electronic paper type display devices). Further, the semiconductor device can be applied without particular limitation from small and medium-sized display devices to large-sized display devices.

[0098] Each of the embodiments described above as embodiments of the present invention can be implemented in appropriate combination as long as they do not contradict each other. Also, based on the semiconductor device and the display device of each embodiment, those in which those skilled in the art have appropriately added, deleted, or changed the design of components, or added, omitted, or changed the conditions of the process, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0099] Even if there are other operational effects different from those brought about by the aspects of each of the above-described embodiments, those that are obvious from the description in this specification or can be easily predicted by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0100] 10: Semiconductor device, 11: Driving transistor, 12: Selection transistor, 20: Display device, 22: Liquid crystal region, 24: Seal region, 26: Terminal region, 100: Substrate, 105: Gate electrode, 110, 120: Gate insulating layer, 130: Metal oxide layer, 140: Oxide semiconductor layer, 141: Upper surface, 142: Lower surface, 143: Side surface, 150: Gate insulating layer, 160: Gate electrode, 170, 180: Insulating layer, 171, 173: Opening, 200: Source-drain electrode, 201: Source electrode, 203: Drain electrode, 210: Holding capacitor, 211: Signal line, 212: Gate line, 213: Anode power line, 214: Cathode power line, 300: Array substrate, 301: Pixel circuit, 302: Source driver circuit, 303: Gate driver circuit, 304: Source wiring, 305: Gate wiring, 306: Terminal portion, 307: Connection wiring, 310: Seal portion, 311: Liquid crystal element, 320: Counter substrate, 330: Flexible printed circuit board (FPC), 340: IC chip, 350: Holding capacitor, 360, 362, 380: Insulating layer, 363, 381: Opening, 370: Common electrode, 390: Pixel electrode, 392: Light emitting layer, 394: Common electrode, CH: Channel region, D: Drain region, DO: Light emitting element, L: Channel length, S: Source region, W: Channel width

Claims

1. a metal oxide layer containing aluminum as a main component provided on a substrate; an oxide semiconductor layer provided on the metal oxide layer; a gate electrode facing the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and a gate electrode, The thickness of the metal oxide layer is 1 nm or more and 4 nm or less.

2. The semiconductor device according to claim 1 , wherein the metal oxide layer has a thickness of 1 nm or more and 3 nm or less.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is in contact with the metal oxide layer.

4. the oxide semiconductor layer is patterned; The semiconductor device according to claim 1 , wherein a portion of the metal oxide layer extends outside the pattern of the oxide semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the metal oxide layer has a barrier property against oxygen and hydrogen.

6. 5. The semiconductor device according to claim 1, further comprising a first insulating layer containing oxygen, the first insulating layer being provided between the substrate and the metal oxide layer.

7. The semiconductor device according to claim 6 , wherein the first insulating layer has a function of releasing oxygen by heat treatment at 600° C. or less.

8. The semiconductor device according to claim 6 , wherein the metal oxide layer is between the first insulating layer and the oxide semiconductor layer and is in contact with both the first insulating layer and the oxide semiconductor layer.

9. The semiconductor device according to claim 1 , wherein no semiconductor layer is present between said substrate and said metal oxide layer.

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