SiC EPITAXIAL WAFER AND SiC EPITAXIAL WAFER MANUFACTURING METHOD

JP2024042428A5Pending Publication Date: 2026-07-07RESONAC CORP

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
RESONAC CORP
Filing Date
2022-09-15
Publication Date
2026-07-07

AI Technical Summary

Technical Problem

Existing SiC epitaxial wafers exhibit significant variations in carrier concentration, particularly near the edge exclusion region, necessitating improved in-plane uniformity to stabilize device characteristics and increase product yield.

Method used

The method involves increasing the growth rate of the SiC epitaxial layer and adjusting the in-plane temperature distribution to achieve a carrier concentration uniformity of less than 3.8%, with specific temperature control in the inner and outer regions of the wafer.

Benefits of technology

This approach results in a SiC epitaxial wafer with high in-plane uniformity, reducing the need for extensive reliability testing and enhancing the stability and reliability of semiconductor devices.

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Abstract

To provide a SiC epitaxial wafer and a SiC epitaxial wafer manufacturing method with high in-plane uniformity of carrier concentration.SOLUTION: A SiC epitaxial wafer according to an embodiment includes a SiC substrate, and a SiC epitaxial layer laminated on the SiC substrate, and the carrier concentration uniformity of the SiC epitaxial layer is less than 3.8%, and the carrier concentration uniformity is a value obtained by dividing the difference between the maximum value and the minimum value of the carrier concentration of the SiC epitaxial layer measured along a straight line passing through the center of the SiC epitaxial layer when viewed in plan by the average value.SELECTED DRAWING: Figure 1
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Description

[Technical field]

[0001] The present invention relates to a SiC epitaxial wafer and a method for manufacturing a SiC epitaxial wafer. [Background technology]

[0002] Silicon carbide (SiC) has an electric breakdown field one order of magnitude larger than silicon (Si) and a band gap three times larger. Silicon carbide (SiC) also has properties such as a thermal conductivity about three times higher than silicon (Si). For this reason, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices, high-temperature operating devices, and the like. For this reason, SiC epitaxial wafers have come to be used in the above-mentioned semiconductor devices in recent years.

[0003] A SiC epitaxial wafer is obtained by stacking a SiC epitaxial layer on the surface of a SiC substrate. Hereinafter, the substrate before the SiC epitaxial layer is stacked is referred to as a SiC substrate, and the substrate after the SiC epitaxial layer is stacked is referred to as a SiC epitaxial wafer. The SiC substrate is cut from a SiC ingot.

[0004] The carrier concentration of a SiC epitaxial wafer affects the element characteristics of a semiconductor device. If the in-plane uniformity of the carrier concentration of a SiC epitaxial wafer is low, the element characteristics will vary even for semiconductor devices fabricated from the same SiC epitaxial wafer. In order to suppress the variation in element characteristics and increase product yields, SiC epitaxial wafers with high in-plane uniformity of carrier concentration are required.

[0005] For example, Patent Document 1 and Patent Document 2 disclose SiC epitaxial wafers with high in-plane uniformity of carrier concentration. For example, Patent Document 1 describes that the in-plane uniformity of carrier concentration of a SiC epitaxial wafer is improved by using ammonia gas as a carrier gas and reducing the gas flow rate. Also, for example, Patent Document 2 describes that the in-plane uniformity of carrier concentration is improved by adjusting the temperature distribution of a silicon carbide substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6969628 [Patent Document 2] JP 2017-84989 A Summary of the Invention [Problem to be solved by the invention]

[0007] There is a demand for further improving the in-plane uniformity of the carrier concentration of SiC epitaxial wafers. The carrier concentration of SiC epitaxial wafers tends to be specifically high or low in the vicinity of the so-called edge exclusion region, which is located from the outermost periphery to the inside by about several millimeters, and the change tends to become more pronounced toward the periphery. There is a demand for further improving the in-plane uniformity of the carrier concentration of SiC epitaxial wafers by further suppressing the specific change in the carrier concentration.

[0008] The present invention has been made in view of the above problems, and has an object to provide a SiC epitaxial wafer having high in-plane uniformity of carrier concentration and a method for manufacturing the SiC epitaxial wafer. [Means for solving the problem]

[0009] The present inventors have found that it is possible to further improve the in-plane uniformity of the carrier concentration of a SiC epitaxial wafer by increasing the growth rate of the SiC epitaxial layer and adjusting the in-plane temperature distribution of the SiC epitaxial layer.

[0010] (1) A SiC epitaxial wafer according to a first aspect includes a SiC substrate and a SiC epitaxial layer laminated on the SiC substrate. The SiC epitaxial layer has a carrier concentration uniformity of less than 3.8%. The carrier concentration uniformity is a value obtained by dividing the difference between the maximum and minimum carrier concentrations of the SiC epitaxial layer measured along a straight line passing through the center of the SiC epitaxial layer in a plan view by the average value.

[0011] (2) In the SiC epitaxial wafer according to the above aspect, the SiC substrate may have a diameter of 149 mm or more.

[0012] (3) In the SiC epitaxial wafer according to the above aspect, the SiC substrate may have a diameter of 199 mm or more.

[0013] (4) A method for producing a SiC epitaxial wafer according to a second aspect includes a film formation step of forming a SiC epitaxial layer on one surface of a SiC substrate. The growth rate of the SiC epitaxial layer is 61 μm / h or more. The film formation temperature of an inner region of the SiC epitaxial layer in the film formation step has a temperature difference of less than ±1° C. with respect to the average temperature in the inner region. The film formation temperature of an outer region of the SiC epitaxial layer in the film formation step is 2° C. or more and less than 10° C. lower than the temperature of the outermost periphery of the inner region. The inner region is a region inside a concentric circle whose center coincides with the center of the SiC substrate and whose diameter is 80% of the diameter of the SiC substrate. The outer region is a region outside the inner region.

[0014] (5) In the method for producing a SiC epitaxial wafer according to the above aspect, the SiC substrate may have a diameter of 149 mm or more.

[0015] (6) In the method for producing a SiC epitaxial wafer according to the above aspect, the SiC substrate may have a diameter of 199 mm or more. Effect of the Invention

[0016] The SiC epitaxial wafer according to the above aspect has high in-plane uniformity of carrier concentration. Furthermore, by using the SiC epitaxial wafer according to the above aspect, a SiC epitaxial wafer having high in-plane uniformity of carrier concentration can be obtained. [Brief description of the drawings]

[0017] [Figure 1] FIG. 2 is a cross-sectional view of the SiC epitaxial wafer according to the present embodiment. [Diagram 2] FIG. 2 is a plan view of the SiC epitaxial wafer according to the embodiment. [Diagram 3] FIG. 1 is a schematic diagram of an example of a film formation apparatus for a SiC epitaxial wafer according to an embodiment of the present invention. [Figure 4] 2A to 2C are schematic diagrams for explaining a process for forming a SiC epitaxial layer according to the present embodiment. [Diagram 5] FIG. 13 is a diagram showing the measurement results of Example 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The SiC substrate and the like according to this embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic parts in an enlarged scale for the sake of convenience in order to make the characteristics of this embodiment easier to understand, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not limited thereto, and may be appropriately modified and implemented within the scope of the present invention.

[0019] First, the directions are defined. One direction in the plane in which the SiC substrate extends is defined as the x direction, and the direction perpendicular to the x direction in the same plane is defined as the y direction. The x direction is, for example, the <11-20> direction. The y direction is, for example, the <1-100> direction. The z direction is perpendicular to the SiC substrate and perpendicular to the x and y directions.

[0020] "SiC epitaxial wafer" Fig. 1 is a cross-sectional view of a SiC epitaxial wafer 10 according to this embodiment. The SiC epitaxial wafer 10 includes a SiC substrate 1 and a SiC epitaxial layer 2. Fig. 2 is a plan view of the SiC epitaxial wafer 10 according to this embodiment. Fig. 2 is a plan view of the surface of the SiC epitaxial wafer 10 on the SiC epitaxial layer 2 side, as viewed from the z direction.

[0021] The SiC substrate 1 is, for example, n-type SiC. The polytype of the SiC substrate 1 is not particularly limited and may be any of 2H, 3C, 4H, and 6H. The SiC substrate 1 is, for example, 4H—SiC.

[0022] The planar shape of the SiC substrate 1 is substantially circular. The SiC substrate 1 may have an orientation flat OF or a notch for grasping the direction of the crystal axis. The diameter of the SiC substrate 1 is not particularly limited. The diameter of the SiC substrate 1 is, for example, 149 mm or more and 151 mm or less. The diameter of the SiC substrate 1 may be, for example, 199 mm or more and 201 mm or less, 249 mm or more and 251 mm or less, or 299 mm or more and 301 mm or less. The diameter of the SiC substrate 1 may be, for example, 149 mm or more, 199 mm or more, 249 mm or more, or 299 mm or more.

[0023] The SiC epitaxial layer 2 is SiC doped with impurities. The SiC epitaxial layer 2 contains, for example, nitrogen as an impurity that determines the conductivity type. The SiC epitaxial layer 2 may contain impurities such as boron in addition to nitrogen. The SiC epitaxial layer 2 is, for example, n-type SiC.

[0024] The average carrier concentration of the SiC epitaxial layer 2 is, for example, 1.0×10 14 cm -3 Above 9.0×10 16 cm -3 or less, preferably 1.0×10 14 cm -3 Above 9.0×10 15 cm -3 Here, the carrier concentration is the effective carrier concentration, which is the absolute value of the difference between the donor concentration and the acceptor concentration.

[0025] The carrier concentration of the SiC epitaxial layer 2 can be measured by, for example, the mercury probe (Hg-CV) method or the secondary ion mass spectrometry (SIMS) method. The Hg-CV method measures the difference between the donor concentration and the acceptor concentration as the effective carrier concentration. The secondary ion mass spectrometry (SIMS) method is a method in which the layer is scraped in the thickness direction and the emitted secondary ions are subjected to mass analysis. The doping concentration can be measured from the mass analysis.

[0026] The carrier concentration of the SiC epitaxial layer 2 is measured, for example, along a straight line L passing through the center C of the SiC epitaxial layer 2 when viewed in a plan view. The straight line L is, for example, a line extending in the <11-20> direction. The straight line L may be a line extending in the <1-100> direction. The straight line L may also be a plurality of lines. For example, the carrier concentration of the SiC epitaxial layer 2 may be measured along a line extending in a cross direction with the center C as the origin. In addition, since the vicinity of the outermost periphery of the SiC epitaxial wafer 10 is outside the device acquisition area, positions less than 5 mm from the outermost periphery are not included in the measurement points. Here, the outermost periphery of the SiC epitaxial wafer 10 is the outermost periphery of the entire wafer including the bevel portion (the inclined portion at the outer periphery edge). The measurement of the carrier concentration may be performed on the straight line L at equal intervals from the center C, or the intervals may vary. The measurement of the carrier concentration may be performed at intervals of 10 mm, 15 mm, 20 mm, 25 mm, or 30 mm.

[0027] The carrier concentration uniformity of the SiC epitaxial layer 2 is less than 3.8%. The carrier concentration uniformity of the SiC epitaxial layer 2 is preferably 3.0% or less. The carrier concentration uniformity of the SiC epitaxial layer 2 is more preferably 1.0% or less. The carrier concentration uniformity is calculated by dividing the difference between the maximum and minimum carrier concentrations of the SiC epitaxial layer 2 measured along a straight line L passing through the center C of the SiC epitaxial layer 2 when viewed in a plan view from the z direction by the average value.

[0028] As an example, when the diameter of the SiC substrate 1 is 150 mm (6 inches), the carrier concentration is measured at the center and at positions ±15 mm, ±30 mm, ±45 mm, ±60 mm, and ±70 mm from the center along a line L extending in the <11-20> direction with the center C as the reference point, and the carrier concentration uniformity is calculated from the carrier concentrations at these measurement points.

[0029] For example, when the diameter of the SiC substrate 1 is 200 mm (8 inches), the carrier concentration is measured at the center and at positions ±20 mm, ±40 mm, ±60 mm, ±80 mm, and ±95 mm from the center along a straight line L extending in the <11-20> direction with the center C as the reference point, and the carrier concentration uniformity is calculated from the carrier concentrations at these measurement points.

[0030] For example, when the diameter of the SiC substrate 1 is 250 mm (10 inches), the carrier concentration is measured at the center and at positions ±25 mm, ±50 mm, ±75 mm, ±100 mm, and ±120 mm from the center along a straight line L extending in the <11-20> direction with the center C as the reference point, and the carrier concentration uniformity is calculated from the carrier concentrations at these measurement points.

[0031] For example, when the diameter of the SiC substrate 1 is 300 mm (12 inches), the carrier concentration is measured at the center and at positions ±30 mm, ±60 mm, ±90 mm, ±120 mm, and ±145 mm from the center along a straight line L extending in the <11-20> direction with the center C as the reference point, and the carrier concentration uniformity is calculated from the carrier concentrations at these measurement points.

[0032] In the SiC epitaxial wafer 10 according to this embodiment, the carrier concentration uniformity of the SiC epitaxial layer 2 is less than 3.8%. The closer the carrier concentration uniformity value is to zero, the higher the uniformity of the carrier concentration in the in-plane direction is. The SiC devices cut out from the SiC epitaxial wafer 10 according to this embodiment have small variations in carrier concentration and small variations in element characteristics.

[0033] In addition, the SiC epitaxial wafer 10 according to this embodiment has a small in-plane carrier concentration variation, so that some reliability tests can be omitted. When the in-plane carrier concentration variation is large, it is necessary to perform a reliability test on multiple locations on the SiC epitaxial wafer 10. In contrast, when the in-plane carrier concentration variation is small, it is sufficient to perform a reliability test on one representative point. For example, even if the reliability test is performed at three points (e.g., the center, half the radius, and 5 mm inside the radius) when the carrier concentration uniformity of the SiC epitaxial layer 2 is 3.8% or more, if the SiC epitaxial layer 2 has a carrier concentration uniformity of 3.0% or less, it may be sufficient to perform the reliability test at two points (e.g., the center, and 5 mm inside the radius), and if the carrier concentration uniformity is 1.0% or less, it may be sufficient to perform the reliability test at one point (e.g., the center). There are various items in the reliability test. If multiple test items are measured at each measurement point, it takes time and costs more. In contrast, the SiC epitaxial wafer 10 according to this embodiment can omit some of the reliability tests, resulting in low costs.

[0034] "SiC epitaxial wafer manufacturing method" The method for manufacturing a SiC epitaxial wafer includes a step of preparing a SiC substrate 1 and a step of forming a SiC epitaxial layer 2.

[0035] First, the SiC substrate 1 is prepared. The SiC substrate 1 is obtained by slicing a SiC ingot to a predetermined thickness. For example, the SiC ingot is sliced ​​so that the main surface of the SiC substrate 1 has an offset angle of 0.4° or more and 5° or less with respect to the (0001) plane. The SiC ingot is produced by, for example, sublimation. The SiC substrate 1 may be purchased from a store. The diameter of the SiC substrate 1 is not particularly limited. The diameter of the SiC substrate 1 is, for example, 149 mm or more and 151 mm or less. The diameter of the SiC substrate 1 may be, for example, 199 mm or more and 201 mm or less, 249 mm or more and 251 mm or less, or 299 mm or more and 301 mm or less. The diameter of the SiC substrate 1 may be, for example, 149 mm or more, 199 mm or more, 249 mm or more, or 299 mm or more.

[0036] Next, a film formation step is performed to form the SiC epitaxial layer 2 on the SiC substrate 1. The SiC epitaxial layer 2 is formed by, for example, a CVD method.

[0037] Fig. 3 is a schematic diagram of an example of a film formation apparatus 100 for a SiC epitaxial wafer 10 according to the first embodiment. The film formation apparatus 100 has, for example, a chamber 20, a support 30, a susceptor 40, a lower heater 50, and an upper heater 60. Fig. 3 shows a state in which a SiC substrate 1 is placed on the susceptor 40. The film formation apparatus 100 is a vertical furnace having a gas supply port 22 above a surface on which the SiC substrate 1 is placed.

[0038] The chamber 20 has, for example, a main body 21, a gas supply port 22, and a gas exhaust port 23. The main body 21 surrounds the film formation space S. The gas supply port 22 is an inlet for supplying the film formation gas G to the film formation space S. The gas supply port 22 is located, for example, above the mounting surface of the SiC substrate 1. The gas exhaust port 23 is an outlet for exhausting the film formation gas G and the like remaining in the film formation space S. The gas exhaust port 23 is located, for example, below the mounting surface of the SiC substrate 1. The film formation gas G is, for example, a Si-based gas, a C-based gas, a purge gas, or a dopant gas.

[0039] The Si-based gas is a source gas containing Si in its molecules. Examples of the Si-based gas include silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and tetrachlorosilane (SiCl4). Examples of the C-based gas include propane (C3H8), ethylene (C2H4), and the like. The dopant gas is a gas containing an element that serves as a carrier. Examples of the dopant gas include nitrogen and ammonia. The purge gas is a gas that carries these gases to the SiC substrate 1, and is hydrogen or the like that is inactive to SiC.

[0040] The support 30 supports the SiC substrate 1. The support 30 is rotatable about an axis. The SiC substrate 1 is placed on the support 30, for example, with the SiC substrate 1 placed on the susceptor 40. The susceptor 40 is transported into the chamber 20 with the SiC substrate 1 placed thereon. The lower heater 50 is, for example, in the support 30, and heats the SiC substrate 1. The upper heater 60 heats the upper part of the chamber 20. The member exposed in the film formation space S is, for example, a carbon member, and the surface may be covered with SiC or TaC. The film formation process is performed, for example, in a vertical furnace shown in FIG. 3.

[0041] In the film formation process, the film formation temperature of the SiC epitaxial layer 2 is controlled. The film formation temperatures are controlled in each of the inner region A1 and the outer region A2 of the SiC epitaxial layer 2. Fig. 4 is a schematic diagram for explaining the film formation process of the SiC epitaxial layer 2 according to this embodiment.

[0042] The inner region A1 is a region inside a concentric circle whose center coincides with the center of the SiC substrate 1 and whose diameter is 80% of the diameter of the SiC substrate 1. For example, when the diameter of the SiC substrate 1 is 150 mm (6 inches), the region inside the concentric circle with a radius of 60 mm is the inner region A1. For example, when the diameter of the SiC substrate 1 is 200 mm (8 inches), the region inside the concentric circle with a radius of 80 mm is the inner region A1. For example, when the diameter of the SiC substrate 1 is 250 mm (10 inches), the region inside the concentric circle with a radius of 100 mm is the inner region A1. For example, when the diameter of the SiC substrate 1 is 300 mm (12 inches), the region inside the concentric circle with a radius of 120 mm is the inner region A1. The outer region A2 is a region located outside the inner region A1.

[0043] In the film formation process, the film formation temperature in the inner region A1 is controlled so that the temperature difference from the average temperature in the inner region A1 is less than ±1° C. The film formation temperature in the inner region A1 can be controlled, for example, by adjusting the output of the lower heater 50. In addition, the film formation temperature in the inner region A1 may be adjusted by adjusting the structure or emissivity of the susceptor, or the film formation temperature in the inner region A1 may be adjusted by adjusting the output of the upper heater 60.

[0044] In the film formation process, the film formation temperature in the outer region A2 is controlled to be 2°C or more and less than 10°C lower than the temperature in the outermost periphery of the inner region A1. That is, the film formation temperature in the outer region A2 is controlled to be 2°C or more lower than the temperature in the outermost periphery of the inner region A1, but not to be 10°C or more lower. The temperature in the outermost periphery of the inner region A1 is, for example, the average value of the film formation temperatures at several measurement points on the outermost periphery of the inner region A1. The film formation temperature in the outer region A2 can be adjusted in the same manner as the film formation temperature in the inner region A1.

[0045] The film formation temperature in the film formation process can be measured, for example, by a radiation thermometer. Alternatively, the film formation temperature in the film formation process may be obtained using the results of a computer simulation.

[0046] In the film formation process, the growth rate of the SiC epitaxial layer 2 is also controlled. The growth rate of the SiC epitaxial layer 2 is set to 61 μm / h or more. The growth rate of the SiC epitaxial layer 2 can be changed by adjusting the supply amount of source gas (Si-based gas and C-based gas), the temperature of the susceptor 40, etc. The growth rate of the SiC epitaxial layer 2 can be calculated, for example, from the difference in wafer thickness before and after film formation and the film formation time.

[0047] By increasing the growth rate of the SiC epitaxial layer 2, it is possible to suppress the incorporation of elements such as boron, which are different from the elements that determine the conductivity type, as impurities into the SiC epitaxial layer 2. For example, at all measurement points that are the same as the carrier concentration, boron and aluminum were each 1.0×10 14 cm -3 Furthermore, by making the temperature difference in the inner region small, at ±1°C, and making the outer region 2°C to less than 10°C lower than the inner region, and controlling the convection over the entire surface of the wafer, it is possible to control the amount of elements, such as boron, that are different from the elements that determine the conductivity type and are taken in as impurities. For example, at all measurement points that are the same as the carrier concentration, boron and aluminum were each 1.0×10 13 cm -3 Above 1.0×10 14 cm -3 These elements are supplied from the chamber 20, and when they are introduced into the SiC epitaxial layer 2, the effective carrier concentration varies. By preventing elements other than the elements that determine the conductivity type from being introduced into the SiC epitaxial layer 2, the variation in the effective carrier concentration can be suppressed. For example, when the average carrier concentration of the SiC epitaxial layer 2 is 1.0×10 16 cm -3 In the case of , boron and aluminum are 1.0 × 10 13 cm -3 Above 1.0×10 14 cm -3If the concentration is below this, the fluctuation in the effective carrier concentration will be between 0.1% and 1%, and the effect on the effective carrier concentration will be small. Also, the smaller the amount of elements such as boron that are different from the elements that determine the conductivity type contained in the SiC epitaxial layer 2, the longer the carrier lifetime tends to be. On the other hand, if the carrier lifetime is too long, in bipolar devices, the switching characteristics may deteriorate and switching losses may increase. At all measurement points that are the same as the carrier concentration, boron and aluminum were each added at 1.0×10 13 cm -3 Above 1.0×10 14 cm -3 By controlling the following, the carrier lifetime in the device can be further stabilized.

[0048] In addition, in the film formation process, the flow rate of gas supplied to the SiC epitaxial layer 2 is controlled. Examples of gases whose flow rates are controlled include Si-based gas, C-based gas, purge gas, and dopant gas. By controlling the gas flow rates, the variation in carrier concentration in the SiC epitaxial layer 2 can be reduced.

[0049] The method for manufacturing a SiC epitaxial wafer according to this embodiment can reduce the variation in carrier concentration within the surface of the SiC epitaxial wafer 10 by adjusting the deposition temperature and growth rate of the SiC epitaxial layer 2. As described above, the SiC epitaxial wafer 10 having small variation in carrier concentration within the surface can omit a reliability test, and can be suitably used as a substrate for high-voltage semiconductor devices used in power sources for various equipment.

[0050] Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims. EXAMPLES

[0051] "Example 1" A SiC substrate 1 having a diameter of 150 mm was prepared. A SiC epitaxial layer 2 was formed on the SiC substrate 1 using a vertical furnace similar to the film formation apparatus 100 shown in FIG. 3. The thickness of the SiC epitaxial layer 2 after film formation was measured by an infrared spectrophotometer. The thickness of the SiC epitaxial layer 2 after film formation was measured at six points of 0 mm, 15 mm, 30 mm, 45 mm, 60 mm, and 70 mm in the <1-100> direction based on the center C of the SiC epitaxial wafer 10. The growth rate of the SiC epitaxial layer 2, calculated by dividing the average thickness at the six points by the film formation time, was set to 61 μm / h or more.

[0052] The film formation temperatures in the inner region A1 and the outer region A2 in the film formation process were calculated by computer simulation. The temperature at each position of the SiC epitaxial wafer 10 calculated by simulation was approximately equal to the temperature actually measured using a radiation thermometer. The film formation temperatures were calculated at 1 mm intervals in the <1-100> direction based on the center C of the SiC epitaxial wafer 10. The film formation temperatures at each measurement point in the inner region A1 were less than ±1°C relative to the average temperature at these measurement points. The film formation temperature in the outer region A2 during film formation was 3.3°C lower than the temperature at the outermost periphery of the inner region A1. The film formation temperature in the outer region A2 was set to the temperature at a position 70 mm away from the center C in the <1-100> direction. The temperature at the outermost periphery of the inner region A1 was set to the temperature at a position 60 mm away from the center C in the <1-100> direction.

[0053] Then, the carrier concentration of the SiC epitaxial layer 2 after deposition was measured. The carrier concentration was measured at six points in the <1-100> direction, 0 mm, 15 mm, 30 mm, 45 mm, 60 mm, and 70 mm from the center C of the SiC epitaxial wafer 10. The difference between the maximum and minimum carrier concentrations at the measurement points was divided by the average value to obtain the carrier concentration uniformity. The carrier concentration uniformity of the SiC epitaxial wafer 10 of Example 1 was 2.4%.

[0054] "Comparative Example 1" Comparative Example 1 differs from Example 1 in that the growth rate of the SiC epitaxial layer 2 was less than 61 μm / h. In Comparative Example 1, the film formation temperature in the outer region A2 during film formation was 2.9° C. lower than the temperature at the outermost periphery of the inner region A1. The other conditions of Comparative Example 1 were the same as those of Example 1, and the carrier concentration uniformity of the SiC epitaxial wafer 10 of Comparative Example 1 was determined. The carrier concentration uniformity of the SiC epitaxial wafer 10 of Comparative Example 1 was 5.0%.

[0055] "Comparative Example 2" Comparative Example 2 differs from Example 1 in that the film formation temperature in the outer region A2 was changed. In Comparative Example 2, the film formation temperature in the outer region A2 during film formation was 1.97°C lower than the temperature at the outermost periphery of the inner region A1. The other conditions of Comparative Example 2 were the same as those of Example 1, and the carrier concentration uniformity of the SiC epitaxial wafer 10 of Comparative Example 2 was obtained. The carrier concentration uniformity of the SiC epitaxial wafer 10 of Comparative Example 2 was 12.9%.

[0056] The results of Example 1, Comparative Example 1, and Comparative Example 2 are summarized in Table 1 below. The column for the inner region in Table 1 shows the temperature difference at each measurement point relative to the average temperature in the inner region. The column for the outer region in Table 1 shows the temperature difference based on the temperature at the outermost periphery of the inner region.

[0057] [Table 1]

[0058] Example 1, in which the growth rate and film formation temperature were controlled, had a lower carrier concentration uniformity value and smaller in-plane variation in carrier concentration than Comparative Examples 1 and 2. Comparative Example 1 had a slow growth rate, and elements other than those that determine the conductivity type, such as boron, were incorporated near the outermost periphery, which is thought to have caused the carrier concentration to vary within the plane. Comparative Example 2 had a film formation temperature difference between the inner and outer regions that was equal to or less than a predetermined value, which is thought to have caused the carrier concentration to vary within the plane.

[0059] "Example 2" Example 2 differs from Example 1 in that the temperature of the outer region was changed relative to the temperature of the outermost periphery of the inner region. In Example 2, the film formation temperature of the outer region in the film formation process was set to be 2° C. or more and less than 10° C. lower than the temperature of the outermost periphery of the inner region. The measurement results of Examples 1 and 2 are summarized in FIG.

[0060] As shown in Example 2, it was confirmed that the carrier concentration uniformity value can be reduced if the growth rate is equal to or greater than a predetermined value and the temperature difference between the inner region and the outer region is equal to or greater than a predetermined value. [Explanation of symbols]

[0061] Reference Signs List 1: SiC substrate, 2: SiC epitaxial layer, 10: SiC epitaxial wafer, C: center, L: straight line, 20: chamber, 21: main body, 22: gas supply port, 23: gas exhaust port, 30: support, 40: susceptor, 50: lower heater, 60: upper heater, 100: film formation device, A1: inner region, A2: outer region

Claims

1. The device comprises a SiC substrate and a SiC epitaxial layer laminated on the SiC substrate, The carrier concentration uniformity of the SiC epitaxial layer is less than 3.8%. The carrier concentration uniformity is the value obtained by dividing the difference between the maximum and minimum values ​​of the carrier concentration in the SiC epitaxial layer, measured along a straight line passing through the center of the SiC epitaxial layer when viewed in plan, by the average value. A SiC epitaxial wafer in which the measurement points for determining the carrier concentration uniformity of the SiC epitaxial layer include a position 5 mm from the outer edge.

2. The SiC epitaxial wafer according to claim 1, wherein the diameter of the SiC substrate is 149 mm or more.

3. The SiC epitaxial wafer according to claim 1, wherein the diameter of the SiC substrate is 199 mm or more.

4. The SiC epitaxial wafer according to claim 1, wherein the carrier concentration uniformity of the SiC epitaxial layer is 3.0% or less.

5. The SiC epitaxial wafer according to claim 1, wherein the carrier concentration uniformity of the SiC epitaxial layer is 2.4% or less.

6. The SiC epitaxial wafer according to claim 1, wherein the carrier concentration uniformity of the SiC epitaxial layer is 1.0% or less.

7. The SiC epitaxial layer comprises boron or aluminum, The SiC epitaxial wafer according to claim 1, wherein the carrier concentrations of boron and aluminum are, respectively, 1.0 × 10¹⁴ cm⁻³ or less at the same measurement points used to determine the uniformity of the carrier concentration.

8. The process includes a film deposition step for forming a SiC epitaxial layer on one surface of a SiC substrate. The growth rate of the SiC epitaxial layer is 61 μm / h or higher. In the inner region of the SiC epitaxial layer, the film deposition temperature during the film deposition process is less than ±1°C relative to the average temperature within the inner region. The outer region of the SiC epitaxial layer is such that the film deposition temperature in the film deposition process is 2°C or more but less than 10°C lower than the temperature of the outermost periphery of the inner region. The aforementioned inner region is a region inside a concentric circle whose center coincides with the center of the SiC substrate and whose diameter is 80% of the diameter of the SiC substrate. A method for manufacturing a SiC epitaxial wafer, wherein the outer region is a region outside the inner region.

9. The method for manufacturing a SiC epitaxial wafer according to claim 8, wherein the diameter of the SiC substrate is 149 mm or more.

10. The method for manufacturing a SiC epitaxial wafer according to claim 8, wherein the diameter of the SiC substrate is 199 mm or more.

11. The method for manufacturing a SiC epitaxial wafer according to claim 8, wherein in the film deposition step, the film deposition temperature in the outer region of the SiC epitaxial layer is 4°C or lower than the temperature of the outermost periphery of the inner region.