Wafer composite, semiconductor device and method of manufacturing semiconductor circuit

Abstract

To provide a wafer composite, a semiconductor device and a method of manufacturing the semiconductor circuit.SOLUTION: A layer stack (130) is formed that includes a device layer (110) and an insulator layer (120). The device layer (110) includes electronic elements (315). The insulator layer (120) is adjacent to a back surface (112) of the device layer (110). A spacer disk (190) is adhesive bonded on the layer stack (130) on a side opposite the device layer (110). The spacer disk (190) and the layer stack (130) form a wafer composite (100). The wafer composite (100) is divided into a plurality of individual semiconductor chips (900), wherein each semiconductor chip (900) includes a portion of the layer stack (130) and a portion of the spacer disk (190).SELECTED DRAWING: Figure 5C

Description

[Technical field]

[0001] Examples of the present disclosure relate to methods for fabricating semiconductor circuits, particularly SOI devices. The present disclosure also relates to semiconductor wafers and wafer composites that include semiconductor devices. [Background technology]

[0002] The ongoing trend towards thinner silicon devices is driven in part by the desire to reduce parasitic effects in the semiconductor bulk and to reduce expensive semiconductor material. One of the technologies involved is silicon-on-insulator (SOI) technology, which involves the fabrication of silicon semiconductor devices within a layered silicon-insulator-silicon substrate or within a layered silicon-insulator substrate. SOI-based devices differ from conventional devices made from silicon layers without an insulator base in that the active semiconductor layer is on an electrical insulator, usually silicon dioxide. The thinner semiconductor layer reduces parasitic capacitance and the amount of crystalline semiconductor material that is grown.

[0003] In the manufacture of semiconductor devices, especially thin semiconductor devices, there is a constant demand for higher productivity and profitability. Summary of the Invention [Means for solving the problem]

[0004] The need is met by the subject matter of the independent claims.

[0005] An embodiment of the present disclosure relates to a method for manufacturing a semiconductor device. A layer stack is formed, the layer stack including a device layer and an insulator layer. The device layer includes electronic elements. The insulator layer is adjacent a back surface of the device layer. A spacer disk is adhesively bonded to a side of the layer stack opposite the device layer. The spacer disk and the layer stack form a wafer composite. The wafer composite is divided into a plurality of individual semiconductor chips, each semiconductor chip including a portion of the layer stack and a portion of the spacer disk.

[0006] Another embodiment of the present disclosure relates to another method of manufacturing a semiconductor device. A wafer composite is provided, the wafer composite including a layer stack, an adhesive tape, and a spacer disk on an opposite side of the adhesive tape to the layer stack. The layer stack includes at least a device layer and an insulator layer in contact with the device layer. Electronic elements are formed in the device layer. The adhesive tape is on an opposite side of the layer stack to the device layer. The wafer composite is diced into a plurality of individual semiconductor chips, each semiconductor chip including a portion of the layer stack and a portion of the spacer disk.

[0007] Further embodiments of the present disclosure relate to further methods of manufacturing a semiconductor device. A semiconductor chip is provided. The semiconductor chip includes a device layer portion, an insulator layer portion contacting a back surface of the device layer portion, an adhesive layer formed on a side of the insulator layer portion opposite the device layer portion, and a spacer layer formed on a side of the adhesive layer opposite the insulator layer portion. Electronic elements are formed in the device layer portion. Contact pads are formed on a contact side surface of the device layer portion. Electrical connections are formed between the contact pads and the device terminals.

[0008] Another embodiment of the present disclosure relates to a wafer composite, the layer stack includes a device layer and an insulator layer, the device layer includes electronic elements, and the insulator layer contacts the backside of the device layer, the adhesive tape is on an opposite side of the layer stack from the device layer, the spacer disk is on an opposite side of the adhesive tape from the insulator layer, and the lateral shapes and dimensions of the spacer disk and the layer stack are identical.

[0009] Another embodiment of the present disclosure relates to a semiconductor device having a device layer including electronic elements. A contact pad is formed on a contact side of the device layer. An insulator layer contacts a back surface of the device layer. An adhesive layer is on a side of the insulator layer opposite the device layer. A spacer layer is on a side of the adhesive layer opposite the insulator layer.

[0010] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

[0011] The accompanying drawings are included in, and are incorporated in and constitute a part of, the present specification to provide a further understanding of the embodiments. The drawings illustrate embodiments of methods for fabricating wafer composites, semiconductor devices, and semiconductor circuits, and together with the description serve to explain the principles of the embodiments. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are indicated by the same reference numerals in the various drawings unless otherwise stated. [Brief description of the drawings]

[0012] [Figure 1] 1A to 1C show schematic vertical cross-sectional views of a layer stack and a wafer composite including the layer stack (before and after dividing the wafer composite into multiple semiconductor chips) and illustrate a method of manufacturing a semiconductor circuit having a spacer layer according to one embodiment. [Figure 2A] 1 shows a schematic vertical cross-sectional view of a layer stack and a wafer composite including the layer stack (before removal of the substrate carrier), and illustrates a method for manufacturing a semiconductor circuit with a spacer layer using the substrate carrier according to one embodiment. [Figure 2B] 1 shows a schematic vertical cross-sectional view of a layer stack and a wafer composite including the layer stack (before removal of the substrate carrier), and illustrates a method for manufacturing a semiconductor circuit with a spacer layer using the substrate carrier according to one embodiment. [Figure 2C] 1 shows a schematic vertical cross-sectional view of a layer stack and a wafer composite including the layer stack (before removal of the substrate carrier), and illustrates a method for manufacturing a semiconductor circuit with a spacer layer using the substrate carrier according to one embodiment. [Figure 2D] 1 shows a schematic vertical cross-sectional view of a layer stack and a wafer composite including the layer stack (after removal of the substrate carrier), and illustrates a method for manufacturing a semiconductor circuit with a spacer layer using the substrate carrier according to one embodiment. [Figure 3A] 1 shows a schematic vertical cross-sectional view of a layer stack including a further semiconductor layer and a wafer composite including the layer stack (before removal of the substrate carrier), illustrating a method for manufacturing a semiconductor circuit with a spacer layer according to another embodiment. [Figure 3B] 1 shows a schematic vertical cross-sectional view of a layer stack including a further semiconductor layer and a wafer composite including the layer stack (before removal of the substrate carrier), illustrating a method for manufacturing a semiconductor circuit with a spacer layer according to another embodiment. [Figure 3C] 1 shows a schematic vertical cross-sectional view of a layer stack including a further semiconductor layer and a wafer composite including the layer stack (before removal of the substrate carrier), illustrating a method for manufacturing a semiconductor circuit with a spacer layer according to another embodiment. [Figure 3D] 1 shows a schematic vertical cross-sectional view of a layer stack including a further semiconductor layer and a wafer composite including the layer stack (after removal of the substrate carrier), illustrating a method for manufacturing a semiconductor circuit with a spacer layer according to another embodiment. [Figure 4A] A schematic vertical cross-sectional view of a layer stack and a spacer disk (before the spacer disk is attached to the layer stack) is shown, illustrating a method of manufacturing a semiconductor circuit having a spacer layer using a compressive force to attach the spacer layer to the layer stack according to one embodiment. [Figure 4B] A schematic vertical cross-sectional view of a layer stack and a spacer disk (after the spacer disk is attached to the layer stack) is shown, illustrating a method of manufacturing a semiconductor circuit having a spacer layer using a compressive force to attach the spacer layer to the layer stack according to one embodiment. [Figure 5A] 2A-2C show schematic vertical cross-sectional views of a semiconductor chip with a spacer layer (before packaging) and a method of manufacturing a semiconductor circuit with a spacer layer according to another embodiment. [Figure 5B] 2A-2C show schematic vertical cross-sectional views of a semiconductor chip with a spacer layer (during packaging) and a method of manufacturing a semiconductor circuit with a spacer layer according to another embodiment. [Figure 5C]2A-2C show schematic vertical cross-sectional views of a semiconductor device with a spacer layer (after packaging) and a method of manufacturing a semiconductor circuit with a spacer layer according to another embodiment. [Figure 6] 4 shows a schematic vertical cross-sectional view of a semiconductor device having a spacer layer according to a further embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description, and which show by way of illustration specific embodiments in which the wafer composite, semiconductor device, and method for manufacturing the semiconductor device may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used in other embodiments or in conjunction with other embodiments to yield still further embodiments. It is intended that the present disclosure include such modifications and variations. Although the examples are described using specific language, such language should not be construed as limiting the scope of the appended claims.

[0014] Terms such as "having," "including," "comprising," and the like are not limiting and indicate the presence of stated structures, elements, or features, but do not exclude the presence of additional elements or features. Unless the context clearly dictates otherwise, the articles "a," "an," and "the" are intended to include plural as well as singular.

[0015] The term "electrically connected" describes a permanent, low resistance, ohmic connection between the elements that are electrically connected, e.g., a direct contact between the associated elements, or a low resistance connection via metal and / or highly doped semiconductor material.

[0016] Ranges given for physical dimensions are inclusive of the boundary values. For example, a range from a to b for a parameter y can be read as a≦y≦b. The same applies to ranges with a single boundary, such as "at least" and "at least."

[0017] The term "on" should not be construed to mean only "directly on." Rather, when one element is positioned "on" another element (e.g., when a layer is "on" another layer or "on" a substrate), additional components (e.g., additional layers) may be positioned between the two elements (e.g., when a layer is "on" a substrate, an additional layer may be positioned between said layer and the substrate).

[0018] In the context of layers and layer structures, the preposition "opposite" is used to mean placement on opposite major faces of layers. For example, horizontal layer A, which is formed on the opposite side of horizontal layer X from horizontal layer B, is vertically separated from layer B by layer X.

[0019] A method of manufacturing a semiconductor device according to the present disclosure may include forming a layer stack including a device layer and an insulator layer. The device layer includes electronic elements. The insulator layer is adjacent to a back surface of the device layer. A spacer disk is adhesively bonded to an opposite side of the layer stack from the device layer, and the spacer disk and layer stack form a wafer composite. The wafer composite is divided into a plurality of individual semiconductor chips (dies), each semiconductor chip including a portion of the layer stack and a portion of the spacer disk.

[0020] The device layer is based on a monocrystalline semiconductor material and includes doped regions that form the semiconductor parts of the electronic elements. The semiconductor material may be an elemental semiconductor, such as silicon or germanium, or a compound semiconductor, such as a IV / IV compound semiconductor, such as silicon germanium SiGe or silicon carbide SiC, or a III / V compound semiconductor, such as gallium arsenide GaAs or gallium nitride GaN. The device layer may also include other materials, such as insulator materials, such as silicon oxide, silicon nitride and / or doped or undoped glass, and / or highly conductive materials, such as doped polycrystalline silicon, elemental metals, metal compounds and / or metal alloys. The electronic elements may include semiconductor elements such as diodes, bipolar junction transistors (BJTs), insulated gate field effect transistors (IGFETs), junction field effect transistors (JFETs) and / or insulated gate bipolar transistors (IGBTs). For example, the electronic elements may be elements of a gate drive circuit, a power factor correction circuit, a motor control circuit, a wireless charging circuit, a high frequency switch and / or a logic circuit.

[0021] The device layer has a substantially planar front surface (the device layer front surface) in a horizontal plane and a substantially planar back surface (the device layer back surface) opposite the device layer front surface, and at least some doped regions of the electronic elements extend from the front surface into the device layer. A normal to the device layer front surface defines a vertical direction.

[0022] Because the device layer front surface and the device layer rear surface are at least approximately parallel to one another, the thickness of the device layer between the device layer front surface and the device layer rear surface is uniform.

[0023] The insulator layer may be a homogenous layer or a layer stack including two or more sublayers of different composition and / or internal structure. For example, the insulator layer may include a thermally grown silicon oxide layer, a deposited silicon oxide layer, and / or a deposited silicon nitride layer. The insulator layer has a substantially flat front surface (insulator layer front surface) opposite the device layer and a substantially flat back surface (insulator layer back surface) oriented to the device layer. The insulator layer front surface and the insulator layer back surface are at least approximately parallel to each other, so that the thickness of the insulator layer between the insulator layer front surface and the insulator layer back surface is at least approximately uniform. The insulator layer back surface may be in direct contact with the device layer back surface.

[0024] The spacer disk may be a solid or patterned disk. The material of the spacer disk may be homogenous. Alternatively, the spacer disk may comprise two or more vertically stacked layers of different composition and / or internal structure. For example, the spacer disk may consist of or include a metal-containing layer, may consist of or include a layer of a semiconductor material such as single crystal silicon, or may consist of or include an insulator layer, e.g., glass, ceramic or resin, e.g., high-temperature resistant plastic.

[0025] The spacer disk may be adhesively bonded directly to the front side of the insulator layer opposite the device layer, or alternatively, the layer stack may include a further semiconductor layer formed on the front side of the insulator layer, and the spacer disk may be adhesively bonded to the side of the further semiconductor layer opposite the insulator layer.

[0026] The step of adhesively bonding the spacer disk to the insulator layer may include applying an adhesive or glue to the insulator layer front surface and / or the mounting surface of the spacer disk (spacer disk mounting surface) and contacting the insulator layer front surface and the spacer disk mounting surface with the adhesive therebetween. The adhesive may be applied, for example, in a liquid state or as a component of an adhesive tape. The adhesive may be conductive or non-conductive.

[0027] The spacer disk may be conductive or insulating, and apart from being insulating or conductive, the spacer disk may lack any other electrical functionality. In particular, the spacer disk lacks active electronic elements. The spacer disk may have the same lateral shape and dimensions as the layer stack. The spacer disk may be applied without putting the layer stack in a critical state, since the step of adhesively bonding the spacer disk to the layer stack may be completed at ambient temperature or only at a slightly elevated temperature below 200 degrees Celsius and / or with only moderate mechanical forces.

[0028] Separating the wafer composite may include mechanical sawing, laser sawing, chemical etching, and / or chemical-physical etching along first and second kerf streets, the second kerf streets extending perpendicular to the first kerf streets. The separating process dices the wafer composite into a plurality of substantially identical semiconductor chips having a rectangular horizontal cross-section.

[0029] By selecting an appropriate thickness of the spacer disk, the vertical extension length (thickness) of the wafer composite and the thickness of the semiconductor chip manufactured from the wafer composite can be adjusted. In particular, the wafer composite and the semiconductor chip based on the layer stack having a relatively thin device layer and a thin insulator layer can be made to have a thickness sufficient to ensure the compatibility of the wafer composite and the semiconductor chip with conventional test and packaging equipment for further processing of the semiconductor chip.

[0030] The thickness of the device layer may be at most 100 μm, with the sum of the thickness of the layer stack and the thickness of the spacer disk being at least 100 μm.

[0031] In particular, for SOI devices based on insulator layers formed by deposition and / or thermal oxidation, the device layers may have a thickness of less than 1 μm, e.g., less than 100 nm or less than 50 nm, and the insulator layers may have a thickness of less than 50 μm, e.g., less than 10 μm, so that the total thickness of the layer stack may be less than a few micrometers. On the other hand, many tools for assembly, testing and packaging are designed for wafer or chip thicknesses of at least 100 μm, 200 μm or 500 μm. The spacer disks facilitate the use of conventional tools for assembly, testing and packaging without repair (conversion).

[0032] The step of adhesively bonding the spacer disk to the layer stack may include applying an adhesive tape to the layer stack on an opposite side to the device layer, and the adhesive tape may include a partially cross-linked resin.

[0033] The resin is not completely crosslinked, but is partially crosslinked to the extent that the resin does not flow at room temperature. In particular, the resin may be crosslinked to the extent that the resin does not flow at all at room temperature.

[0034] Unlike liquid adhesives, the partially cross-linked resin on the adhesive tape is applied inherently with high consistency, requiring little effort, and the mounting surfaces of the spacer disk and layer stack are highly parallel to each other on either side of the adhesive tape, improving compatibility with existing tools for assembly, testing and packaging.

[0035] The step of adhesively bonding the spacer disk to the layer stack may further include attaching the spacer layer to the adhesive tape on a side of the adhesive tape opposite the layer stack.

[0036] The adhesive tape may be applied to the layer stack first and then the spacer disk may be attached to the adhesive tape on the opposite side of the layer stack. Alternatively, the spacer disk may be attached to the adhesive tape first and then the layer stack may be applied to the adhesive tape on the opposite side of the spacer disk. Alternatively, the spacer disk and layer stack may be attached to the opposite sides of the adhesive tape at the same time.

[0037] Applying the adhesive tape onto the layer stack and / or onto the spacer disk may use a proven and tested lamination process for wafers, e.g., for a die attach foil, a pre-fabricated portion of foil that may have the lateral dimensions of the wafer composite is prepared and bonded to the layer stack.

[0038] The step of adhesively bonding the spacer disk to the insulator layer may further include a step of curing the partially cross-linked resin after applying the adhesive tape onto the insulator layer and after attaching the spacer disk to the adhesive tape.

[0039] After curing, the resin, which was originally only partially crosslinked, is crosslinked to a higher degree than before. For example, after curing, the resin may be fully crosslinked or at least 80% crosslinked. Curing may include a single heating step, with or without compressive stress on the adhesive tape. Heating may be provided solely for the reason of curing the adhesive. Alternatively, curing is a side effect of other manufacturing steps or steps applied to the wafer composite and / or the semiconductor chip obtained from the wafer composite before the end of the packaging process that encapsulates the wafer composite and / or the semiconductor chip obtained from the wafer composite in a mold.

[0040] Curing the partially cross-linked resin may include subjecting the partially cross-linked resin to a compressive stress.

[0041] For example, the first bonding device may first laminate the adhesive tape onto the layer stack mounting surface, and then the first or second bonding device may press the spacer disk onto the adhesive tape opposite the layer stack to generate sufficient bonding force. Alternatively, the first bonding device may first laminate the adhesive tape onto the spacer disk mounting surface, and then the first or second bonding device may press the layer stack onto the adhesive tape opposite the spacer disk to generate sufficient bonding force.

[0042] Forming the layer stack may include depositing and / or thermally growing an insulator layer on a backside of the device layer after forming electronic circuitry in the device layer.

[0043] The method may further include attaching a substrate carrier to the device layer prior to thinning the device layer or prior to forming the insulator layer, and removing the substrate carrier early after adhesively bonding the spacer disk to the insulator layer.

[0044] The substrate carrier may be a solid or patterned disk. The material of the substrate carrier may be homogenous. Alternatively, the substrate carrier may comprise two or more vertically stacked layers of different composition and / or internal structure. For example, the substrate carrier may consist of or include a metal-containing layer, may consist of or include a layer of a semiconductor material such as monocrystalline or polycrystalline silicon, or may consist of or include an insulator layer, e.g., glass or insulating ceramic. The substrate carrier may mechanically stabilize the thin device layer during the formation of the insulator layer and / or may mechanically stabilize the layer stack for the process of adhesively bonding a spacer disk to the layer stack.

[0045] Another method of manufacturing a semiconductor circuit may include providing a wafer composite, the wafer composite including a layer stack, an adhesive tape, and a spacer disk on an opposite side of the adhesive tape to the layer stack. The layer stack may include at least a device layer and an insulator layer in contact with the device layer. Electronic elements may be formed in the device layer. The adhesive tape is on an opposite side of the layer stack to the device layer. The method may further include dicing the wafer composite into a plurality of individual semiconductor chips, each semiconductor chip including a portion of the layer stack and a portion of the spacer disk.

[0046] A further method of manufacturing a semiconductor device may include providing a semiconductor chip, the semiconductor chip may include a device layer portion, an insulator layer portion contacting a back surface of the device layer portion, an adhesive layer formed on a side of the insulator layer portion opposite the device layer portion, and a spacer layer formed on a side of the adhesive layer opposite the insulator layer portion. Electronic elements may be formed in the device layer portion. Contact pads are formed on a contact side surface of the device layer portion. The method may further include forming electrical connections between the contact pads and the device terminals.

[0047] The adhesive layer may be in direct contact with the surface of the insulator layer opposite the device layer. Alternatively, the semiconductor chip may include a substrate layer formed on the insulator layer, and the adhesive layer may be in direct contact with the surface of the substrate layer opposite the insulator layer.

[0048] The step of forming the electrical connections may include a step of wire bonding, where bond wires are formed between the contact pads and the device terminals.

[0049] Another embodiment relates to a wafer composite. The wafer composite may include a layer stack, an adhesive tape, and a spacer disk. The layer stack includes a device layer and an insulator layer, the device layer includes electronic elements, and the insulator layer contacts the back side of the device layer. The adhesive tape is located on the opposite side of the layer stack from the device layer. The spacer disk is on the opposite side of the adhesive tape from the insulator layer, and the lateral shapes and dimensions of the spacer disk and the layer stack may be identical.

[0050] The thickness of the spacer disc is less than 1 mm, for example less than 800 μm. The spacer disc is formed to be permanently structurally connected to the layer stack. The adhesive tape provides a permanent connection between the layer stack and the spacer disc.

[0051] The thickness of the device layer may be at most 100 μm and the sum of the thickness of the layer stack and the thickness of the spacer disk may be at least 100 μm.

[0052] For example, the thickness of the device layer may be at most 10 μm, 1 μm, 100 nm or 50 nm. The sum of the thickness of the layer stack and the thickness of the spacer disk may be at least 200 μm.

[0053] Another embodiment relates to a semiconductor device that may include a device layer portion, an insulator layer portion, an adhesive layer, and a spacer layer. The device layer portion may include electronic elements and contact pads formed on a contact side of the device layer portion. The insulator layer portion contacts a back surface of the device layer portion. The adhesive layer is on an opposite side of the insulator layer portion from the device layer portion. The spacer layer is on an opposite side of the adhesive layer from the insulator layer portion.

[0054] The adhesive layer may be in direct contact with the surface of the insulator layer portion opposite the device layer portion. Alternatively, the semiconductor chip may include a substrate layer formed on the side of the insulator layer portion opposite the device layer portion, and the adhesive layer may be in direct contact with the surface of the substrate layer opposite the insulator layer portion.

[0055] The adhesive layer may be a homogenous layer containing a fully or nearly fully crosslinked resin. Alternatively, the adhesive layer may include a carrier tape, a first adhesive layer between the carrier tape and the insulator layer portion, and a second adhesive layer between the carrier tape and the spacer layer. The first and second adhesive layers may be homogenous layers containing a fully or nearly fully crosslinked resin.

[0056] The thickness of the device layer may be at most 100 μm, such as at most 10 μm or 1 μm. The sum of the thickness of the device layer, the thickness of the insulator layer and the thickness of the spacer layer may be at least 100 μm, such as at least 200 μm.

[0057] The semiconductor device may further include device terminals and wiring connections between the contact pads and the device terminals, the wiring connections providing direct electrical connections between the contact pads and the device terminals.

[0058] 1A through 1C illustrate a method of manufacturing a semiconductor device having a spacer layer.

[0059] FIG. 1A shows a layer stack 130 including a device layer 110 and an insulator layer 120 .

[0060] The device layer 110 is made of single crystal semiconductor material and includes doped regions of electronic elements 315. The electronic elements 315 include diodes, bipolar transistors, insulated gate field effect transistors, junction field effect transistors and / or insulated gate bipolar transistors and form elements of gate drive circuits, power factor correction circuits, motor control circuits, wireless charging circuits, radio frequency switches or logic circuits.

[0061] The device layer 110 has a flat front surface 111 (device layer front surface 111) and a flat back surface 112 (device layer back surface 112), from which at least a part of the doped regions of the electronic elements 315 extend into the device layer 110. The device layer front surface 111 and the device layer back surface 112 extend parallel to each other. A thickness th1 of the device layer 110 between the device layer front surface 111 and the device layer back surface 112 is at most 1 μm, at most 100 nm or at most 50 nm.

[0062] The insulator layer 120 is a silicon oxide layer, including a thermally grown silicon oxide layer and / or a deposited silicon oxide layer. The insulator layer 120 has a flat front surface 121 (insulator layer front surface 121) and a flat back surface 122 (insulator layer back surface 122). The insulator layer front surface 121 and the insulator layer back surface 122 are parallel to each other. The thickness th2 of the insulator layer 120 between the insulator layer front surface 121 and the insulator layer back surface 122 is at most 50 μm or at most 10 μm. The insulator layer back surface 122 is in direct contact with the device layer back surface 112.

[0063] A spacer disk 190 is adhesively bonded to the insulator layer front surface 121 on the side of the layer stack 130 opposite the device layer 110 .

[0064] The spacer disk 190 is a solid disk. The spacer disk 190 may be homogenous or may include two or more vertically stacked layers of different composition and / or internal structure. The spacer disk 190 may consist of or include a metal-containing layer, may consist of or include a layer of semiconductor material, or may consist of or include an insulator layer, such as glass, ceramic, or resin, such as a high-temperature resistant plastic.

[0065] The spacer disk 190 may be conductive or insulating, and apart from being insulating or conductive, the spacer disk 190 lacks any other electrical functionality. In particular, the spacer disk lacks active electronic elements. The spacer disk 190 has the same lateral shape and lateral dimensions as the layer stack 130.

[0066] Adhesive bonding the spacer disk 190 to the layer stack 130 includes applying adhesive 150 to the insulator layer front surface 121 and / or to the mounting surface 191 of the spacer disk 190 and then contacting the mounting surface 191 of the spacer disk 190 to the adhesive 150 on the insulator layer front surface 121. Adhesive bonding may include curing the adhesive 150 present between the insulator layer front surface 121 and the spacer disk 190.

[0067] Figure 1B shows a wafer composite 100 obtained by adhesively bonding a spacer disk 190 to the front side 121 of the insulator layer 120 of Figure 1A. A hardened adhesive 150 mechanically connects the layer stack 130 and the spacer disk 190.

[0068] The wafer composite 100 is separated (diced) into a plurality of individual semiconductor chips 900. Separating the wafer composite 100 may include mechanical sawing, laser sawing, chemical etching, and / or chemical-physical etching along first and second kerfs, the second kerf extending perpendicular to the first kerf.

[0069] FIG. 1C shows a semiconductor chip 900 obtained by dicing the wafer composite 100 of FIG. 1B.

[0070] The separation process dices the wafer composite 100 into a number of identical semiconductor chips 900 having a rectangular horizontal cross-section. Each semiconductor chip 900 includes a device layer portion 910 including a portion of the device layer 110 of FIG. 1B, an insulator layer portion 920 including a portion of the insulator layer 120, an adhesive layer 950 including a portion of the cured adhesive 150, and a spacer layer 990 formed from a portion of the spacer disk 190.

[0071] By selecting an appropriate thickness of the spacer disk 190, the thickness of the wafer composite 100 and the thickness of the semiconductor chip 900 can be adjusted to ensure compatibility of the wafer composite 100 and the semiconductor chip 900 with conventional testing and packaging equipment for further processing of the semiconductor chip 900.

[0072] 2A-2D illustrate a method of manufacturing a semiconductor device having a spacer layer, in which an adhesive tape 155 is used to structurally connect a layer stack 130 to a spacer disk 190. As shown in FIG.

[0073] As described above, the layer stack 130 including the device layer 110 and the insulator layer 120 is mounted on the top surface of the substrate carrier 200 with the device layer front surface 111 oriented towards the substrate carrier 200. For example, the device layer 110 is bonded by the device layer front surface 111 to the top surface of the substrate carrier 200, which may be glueless bonding or adhesive bonding. Alternatively, the layer stack 130 may be electrostatically or pneumatically chucked to the top surface of the substrate carrier 200.

[0074] Prior to thinning the device layer 110 or prior to forming the insulator layer 120, a substrate carrier 200 may be attached to the device layer 110.

[0075] The illustrated substrate carrier 200 is a solid homogenous disk of metal-containing, semiconducting, or insulating material. The substrate carrier 200 may mechanically stabilize the thin device layer 110 during the formation of the insulator layer 120 and / or may stabilize the layer stack 130 for the process of adhesively bonding the spacer disk 190 to the layer stack 130.

[0076] 2A shows a layer stack 130 including a device layer 110 and an insulator layer 120 mounted on the top surface of a substrate carrier 200, as described above. The substrate carrier 200 may be a plate having a flat top surface, the lateral extension of which is greater than the lateral extension of the layer stack. Alternatively, the substrate carrier may be part of a chuck.

[0077] The adhesive tape 155 is applied to the exposed front surface 121 of the insulator layer 120 opposite the substrate carrier 200. The application of the adhesive tape 155 onto the layer stack 130 involves a proven and tested lamination process for wafers, where a pre-fabricated piece of foil having the lateral dimensions of the layer stack 130 is prepared and adhesively bonded to the layer stack 130.

[0078] FIG. 2B shows an adhesive tape 155 on the front surface 121 of the insulator layer 120. The adhesive tape 155 may include a carrier tape, a first adhesive layer formed on a first side of the carrier tape, and a second adhesive layer formed on an opposite second side of the carrier tape. The adhesive layer may include a resin that may be partially cured to such an extent that the resin is fixed on the carrier tape at 25 degrees Celsius. The thickness of the adhesive tape 155 is very uniform. Unlike liquid adhesives, the partially cross-linked resin on the adhesive tape 155 is inherently applied with high consistency, requiring little effort, and allows the mounting surfaces of the spacer disk 190 and layer stack 130 to be very parallel to each other on both sides of the adhesive tape 155, improving compatibility with existing tools for assembly, testing, and packaging.

[0079] A spacer disk 190 is brought into contact with the exposed side of the adhesive tape 155 .

[0080] 2C shows a spacer disk 190 and an insulator layer 120 attached to either side of an adhesive tape 155. Due to the highly uniform thickness of the adhesive tape 155, the mounting surface 191 of the spacer disk 190 and the insulator layer front surface 121 opposite the adhesive tape 155 are aligned substantially parallel to one another.

[0081] The heating hardens the adhesive in the adhesive layer so that after heating, the adhesive is cross-linked to a greater extent than before. The heating completely or nearly completely cross-links the adhesive, e.g., resin. The heating may be a single heating process or may include several heating steps. The heating may start early after the spacer disk 190 is contacted with the adhesive tape 155 and may be completed before the packaged semiconductor device is shipped, e.g., before the substrate carrier 200 is removed or before the wafer composite 100 is diced.

[0082] 2D shows the wafer composite 100 after separation of the wafer composite 100 from the substrate carrier. Alternatively, the substrate carrier 200 may be used during the dicing process and removed only after separating the wafer composite 100 into individual semiconductor chips.

[0083] The wafer composite 100 includes a layer stack 130, an adhesive tape 155, and a spacer disk 190. The layer stack 130 includes a device layer 110 and an insulator layer 120. An electronic element 315 is formed in and / or on the device layer 110. The insulator layer 120 contacts the back surface 112 of the device layer 110. The adhesive tape 155 is located on the opposite side of the layer stack 130 from the device layer 110, and the adhesive tape 155 directly contacts the insulator layer 120. The adhesive tape 155 includes a fully or nearly fully crosslinked adhesive, e.g., a resin. The spacer disk 190 is located on the opposite side of the adhesive tape 155 from the insulator layer 120, and the lateral shapes and dimensions of the spacer disk 190 and the layer stack 130 are identical.

[0084] The thickness of the device layer 110 may be at most 100 μm, with the sum of the thickness th3 of the layer stack 130 and the thickness of the spacer disk 190 being at least 100 μm.

[0085] 3A-3D illustrate a method of manufacturing a semiconductor device that includes a substrate layer between an insulator layer and a spacer layer.

[0086] The layer stack 130 of Fig. 3A differs from the layer stack 130 of Fig. 2A in that the layer stack 130 includes a further semiconductor layer 140 formed on the insulator layer front surface 121. The further semiconductor layer 140 may have a background doping of a first conductivity type. A doped region 145 of an opposite second conductivity type may extend into the further semiconductor layer 140 from the side oriented towards the insulator layer front surface 121. The first conductivity type may be n-type and the second conductivity type may be p-type. The thickness of the further semiconductor layer 140 may be less than 10 μm.

[0087] As shown in FIG. 3B, an adhesive tape 155 is bonded to the side of the further semiconductor layer 140 opposite the insulator layer 120 .

[0088] FIG. 3C shows adhesive tape 155 adhesively bonding spacer disk 190 to further semiconductor layer 140 .

[0089] FIG. 3D shows a wafer composite 100 that differs from the wafer composite 100 shown in FIG. 2D in the following respects: the layer stack 130 includes an additional semiconductor layer 140 formed on the side of the insulator layer 120 opposite the device layer 110, an adhesive tape 155 directly contacts the additional semiconductor layer 140, and a spacer disk 190 is adhesively bonded to the side of the additional semiconductor layer 140 opposite the insulator layer 120.

[0090] 4A-4B relate to the manner in which the bonding apparatus 400 applies a compressive stress to the partially cross-linked resin in the adhesive tape 155, causing the resin to harden.

[0091] Figure 4A shows an adhesive tape 155 laminated to the insulator layer front surface 121 of the layer stack 130, as described with reference to Figure 2B. The composite including the adhesive tape 155, the layer stack 130 and the substrate carrier 200 is placed on a first plate 410 of a bonding apparatus 400 and releasably secured, e.g., electrostatically or pneumatically chucked. A spacer disk 190 is placed on a second plate 420 of the bonding apparatus 400 and releasably secured, e.g., electrostatically or pneumatically chucked.

[0092] The first plate 410 and the second plate 420 are aligned with each other such that the mounting surface 191 and the insulator layer front surface 121 of the spacer disk 190 are parallel to each other and the spacer disk 190 is adjusted laterally relative to the layer stack 130 .

[0093] The bonding apparatus 400 moves the first plate 410 and / or the second plate 420 vertically toward each other to press the spacer disk 190 onto the adhesive tape 155 to create sufficient bonding force.

[0094] 4B shows the first plate 410 and the second plate 420 in a position where the spacer disk 190 is pressed onto the adhesive tape 155. Bonding may include heating the wafer composite 100 including the spacer disk 190, the adhesive tape 155 and the layer stack 130, for example, outside the bonding apparatus 400, in the state shown in FIG.

[0095] 5A to 5C illustrate a method of manufacturing a semiconductor device 800 from a wafer composite 100 as shown in the previous figures.

[0096] As shown in FIG. 1A , the wafer composite 100 including the layer stack 130, the adhesive tape 155, and the spacer disk 190 on the opposite side of the adhesive tape 155 from the layer stack 130 is separated into individual semiconductor chips 900, the layer stack 130 including the device layer 110 and the insulator layer 120 in contact with the device layer 110, the electronic elements 315 formed within the device layer 110, and the adhesive tape 155 formed on the opposite side of the layer stack 130 from the device layer 110.

[0097] 5A shows one of the semiconductor chips 900 obtained by dicing. The semiconductor chip 900 includes a device layer portion 910, an insulator layer portion 920 in contact with a rear surface 912 of the device layer portion 910, an adhesive layer 950 formed on the side of the insulator layer portion 920 opposite the device layer portion 910, and a spacer layer 990 formed on the side of the adhesive layer 950 opposite the insulator layer portion 920. The electronic elements 315 are formed in the device layer portion 910. The contact pads 916 are formed on a contact side surface 911 of the device layer portion 910.

[0098] The semiconductor chip 900 is placed on the mounting side of the lead frame 970 and bonded, for example adhesively bonded, to the lead frame 970. Wiring connections 971 are formed between contact pads 916 of the semiconductor chip 900 and device terminals 972 of the lead frame 970 by wire bonding.

[0099] 5B shows the semiconductor chip 900 mounted on a leadframe 970 with a spacer layer 990 oriented on the mounting side of the leadframe 970. Bond wires electrically connect the contact pads 916 to device terminals 972. Glue and / or solder 974 secure the semiconductor chip 900 onto the mounting portion 973 of the leadframe 970.

[0100] The molding process encapsulates the semiconductor chip 900 and at least partially isolates the device terminals 972 from one another to form the semiconductor device 800.

[0101] 5C shows the semiconductor device 800 including a device layer portion 910, an insulator layer portion 920, an adhesive layer 950, and a spacer layer 990. The device layer portion 910 may include electronic elements 315 and contact pads 916 formed on a contact side surface 911 of the device layer portion 910. The insulator layer portion 920 contacts a back surface 912 of the device layer portion 910. The adhesive layer 950 is on the side of the insulator layer portion 920 opposite the device layer portion 910 and may directly contact the side of the insulator layer portion 920 opposite the device layer portion 910. The spacer layer 990 is on the side of the adhesive layer 950 opposite the insulator layer portion 920.

[0102] The adhesive layer 950 may include an adhesive tape. The adhesive tape may include a carrier tape, a first adhesive layer between the carrier tape and the insulator layer portion 920, and a second adhesive layer between the carrier tape and the spacer layer 990. The first and second adhesive layers include a fully or nearly fully crosslinked resin.

[0103] The thickness of the device layer portion 910 may be at most 100 μm, for example at most 10 μm or 1 μm. The sum of the thickness of the device layer portion 910, the thickness of the insulator layer portion 920, the thickness of the adhesive layer 950 and the thickness of the spacer layer 990 is at least 100 μm.

[0104] The semiconductor device 800 further includes device terminals 972 and wiring connections 971 between the contact pads 916 and the device terminals 972. The mold 980 encapsulates and seals the semiconductor chip 900 and the wiring connections 971, protecting the semiconductor chip 900 and the wiring connections from physical and chemical shocks, external moisture and contaminants. The material of the mold 980 may be a hardened resin.

[0105] The semiconductor device 800 of FIG. 6 differs from the semiconductor device 800 of FIG. 5C in that a semiconductor substrate layer 940 is formed on the insulator layer portion 920. The substrate layer 940 has a background doping of a first conductivity type. A doped region 945 of an opposite second conductivity type may extend into the substrate layer 940 from the side oriented towards the insulator layer portion 920. The first conductivity type may be n-type and the second conductivity type may be p-type. The thickness of the substrate layer 940 may be less than 10 μm. An adhesive layer 950 is in direct contact with the surface of the substrate layer 940 opposite the insulator layer portion 920.

Claims

1. A method for manufacturing a semiconductor circuit, wherein the method is A step of forming a layer stack (130) comprising a device layer (110) and an insulating layer (120), wherein the device layer (110) comprises an electronic element (315), and the insulating layer (120) is adjacent to the back surface (112) of the device layer (110), The step of bonding a spacer disk (190) to the side of the layer stack (130) opposite to the device layer (110), wherein the spacer disk (190) and the layer stack (130) form a wafer composite (100), The steps include dividing the wafer composite (100) into a plurality of individual semiconductor chips (900), wherein each semiconductor chip (900) comprises a portion of the layer stack (130) and a portion of the spacer disk (190), A method that includes this.

2. The thickness th1 of the device layer (110) is at most 100 μm. The sum of the thickness th3 of the layer stack (130) and the thickness th4 of the spacer disk (190) is at least 100 μm. The method according to claim 1.

3. The step of adhesively bonding the spacer disk (190) to the layer stack (130) includes the step of applying adhesive tape (155) to the side of the layer stack (130) opposite to the device layer (110), The adhesive tape (155) comprises a partially crosslinked resin. The method according to claim 1.

4. The step of adhesive bonding the spacer disk (190) to the layer stack (130) further includes the step of attaching the spacer disk (190) to the adhesive tape (155) on the side of the adhesive tape (155) opposite to the layer stack (130), The method according to claim 3.

5. The step of adhesive bonding the spacer disc (190) to the insulating layer (120) further includes the step of curing the partially crosslinked resin after applying the adhesive tape onto the insulating layer (120) and attaching the spacer disc (190) to the adhesive tape (155). The method according to claim 4.

6. The step of curing the partially crosslinked resin further includes the step of applying compressive stress to the partially crosslinked resin. The method according to claim 5.

7. The step of forming the layer stack (130) includes, after forming the electronic element (315) within the device layer (110), the step of depositing the insulating layer (120) on the back surface of the device layer (110) and / or thermal growing it. The method according to claim 1.

8. The aforementioned method, Before thinning the device layer (110) or before forming the insulating layer (120), the substrate carrier (200) is attached to the device layer (110), At the earliest, the process involves the step of adhesive bonding the spacer disk (190) to the insulating layer (120), followed by the step of removing the substrate carrier (200), Further including, The method according to any one of claims 1 to 7.

9. A method for manufacturing a semiconductor circuit, wherein the method is A step of providing a wafer composite (100), wherein the wafer composite (100) comprises a layer stack (130), an adhesive tape (155), and a spacer disk (190) on the side of the adhesive tape (155) opposite to the layer stack (130), the layer stack (130) comprising at least a device layer (110) and an insulating layer (120) in contact with the device layer (110), an electronic element (114) formed within the device layer (110), and the adhesive tape (155) on the side of the layer stack (130) opposite to the device layer (110), The step of dicing the wafer composite (100) into a plurality of individual semiconductor chips (900), wherein each semiconductor chip (900) comprises a portion of the layer stack (130) and a portion of the spacer disk (190), A method that includes this.

10. A method for manufacturing semiconductor devices, The method includes the step of providing a semiconductor chip (900), The semiconductor chip (900) comprises a device layer (910), an insulating layer (920) in contact with the back surface (912) of the device layer (910), an adhesive layer (950) formed on the side of the insulating layer (920) opposite to the device layer (910), and a spacer layer (990) formed on the side of the adhesive layer (950) opposite to the insulating layer (920). The electronic element (315) is formed within the device layer (910), and the contact pad (916) is formed on the contact-side surface of the device layer (910). The method includes the step of forming an electrical connection between the contact pad (916) and the device terminal (972). method.

11. A layer stack (130) comprising a device layer (110) and an insulating layer (120), The adhesive tape (155) on the side of the layer stack (130) opposite to the device layer (110), The spacer disc (190) on the side of the adhesive tape (155) opposite to the insulating layer (120), A wafer composite comprising, The device layer (110) comprises an electronic element (315), and the insulating layer (120) is in contact with the back surface (112) of the device layer (110). The lateral shape and dimensions of the spacer disk (190) and the layer stack (130) are identical. Wafer composite.

12. The thickness th1 of the device layer (110) is at most 100 nm. The sum of the thickness th3 of the layer stack (130) and the thickness th4 of the spacer disk (190) is at least 100 μm. The wafer composite according to claim 11.

13. A semiconductor device, wherein the semiconductor device is Device layer (910) and An insulating layer (920) that contacts the back surface (912) of the device layer (910), The adhesive layer (950) on the side of the insulating layer (920) opposite to the device layer (910), The spacer layer (990) on the side of the adhesive layer (950) opposite to the insulating layer (920), Equipped with, The device layer (910) comprises an electronic element (315) and a contact pad (916) formed on the contact-side surface (911) of the device layer (910). Semiconductor devices.

14. The thickness of the device layer (910) is at most 100 nm. The sum of the thickness of the device layer (910), the thickness of the insulating layer (920), and the thickness of the spacer layer (990) is at least 100 μm. The semiconductor device according to claim 13.

15. The aforementioned semiconductor device is Device terminal (972) and The wiring connection (971) between the contact pad (916) and the device terminal (972), Furthermore, The semiconductor device according to claim 13 or 14.

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