Semiconductor light-emitting element and light-emitting module

Abstract

To provide a semiconductor light-emitting element in which the efficiency of extracting deep-ultraviolet light is increased further.SOLUTION: A semiconductor light-emitting element (100, 200, 300) includes a substrate (10) and a semiconductor layer (20). The substrate includes a first main surface (10a) and a second main surface (10b) on the opposite side of the first main surface. The semiconductor layer includes an n-type semiconductor layer (21) disposed on the first main surface, an active layer (22) disposed on the n-type semiconductor layer and generating deep-ultraviolet light, and a p-type semiconductor layer (23) disposed on the active layer. The semiconductor layer includes a mesa structure (24). The second main surface includes a first region (10ba) facing the mesa structure, and a second region (10bb) around the first region. The first region has a flat surface. The second region includes an uneven structure (10c, 10d). In a plan view, the width of the first region is 0.1 times or more and 3.0 times or less the width of the mesa structure.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to semiconductor light emitting devices. [Background technology]

[0002] For example, JP 2018-174238 A (Patent Document 1) describes a semiconductor light-emitting device. The semiconductor light-emitting device described in Patent Document 1 has a substrate and a semiconductor layer. The substrate has a first main surface and a second main surface that is the opposite surface to the first main surface. The semiconductor layer has an n-type semiconductor layer disposed on the first main surface, an active layer disposed on the n-type semiconductor layer, and a p-type semiconductor layer disposed on the active layer. The semiconductor layer has a mesa structure. Deep ultraviolet light is generated from the active layer. A concave-convex structure is formed on the entire surface of the second main surface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-174238 A Summary of the Invention [Problem to be solved by the invention]

[0004] It has been newly discovered that the intensity of light emitted from the portion of the second main surface facing the mesa structure is weak in the semiconductor light emitting device described in Patent Document 1. Based on this discovery, the present disclosure provides a semiconductor light emitting device with further improved extraction efficiency of deep ultraviolet light. [Means for solving the problem]

[0005] The semiconductor light emitting element of the present disclosure includes a substrate and a semiconductor layer. The substrate has a first main surface and a second main surface opposite to the first main surface. The semiconductor layer has an n-type semiconductor layer disposed on the first main surface, an active layer disposed on the n-type semiconductor layer and generating deep ultraviolet light, and a p-type semiconductor layer disposed on the active layer. The semiconductor layer has a mesa structure. The second main surface has a first region facing the mesa structure and a second region surrounding the first region. The first region is configured as a flat surface. The second region has an uneven structure. In a plan view, the width of the first region is 0.1 to 3.0 times the width of the mesa structure. Effect of the Invention

[0006] According to the semiconductor light emitting device of the present disclosure, it is possible to further increase the extraction efficiency of deep ultraviolet light. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view of a semiconductor light emitting element 100. FIG. [Diagram 2] 2 is a plan view of the semiconductor light emitting device 100 as viewed from the opposite side to that of FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] 10 is a cross-sectional view of a semiconductor light emitting device 100 according to a modified example. [Diagram 5] 1A to 1C are manufacturing process diagrams of the semiconductor light emitting device 100. [Figure 6] FIG. 2 is a cross-sectional view illustrating a preparation step S1. [Figure 7] 10 is a cross-sectional view illustrating a semiconductor layer forming step S2. FIG. [Figure 8] 11 is a cross-sectional view illustrating a mesa structure forming step S3. FIG. [Figure 9] FIG. 11 is a cross-sectional view illustrating a first electrode forming step S4. [Figure 10] FIG. 11 is a cross-sectional view illustrating a second electrode forming step S5. [Figure 11] 11 is a cross-sectional view illustrating a substrate rear surface processing step S6. [Figure 12A] FIG. 11 is a first cross-sectional view illustrating a mask formation step S7. [Figure 12B] FIG. 2 is a second cross-sectional view illustrating the mask formation step S7. [Figure 12C] FIG. 11 is a third cross-sectional view illustrating the mask formation step S7. [Figure 12D] FIG. 4 is a fourth cross-sectional view illustrating a mask formation step S7. [Figure 13] FIG. 11 is a cross-sectional view showing a columnar structure forming step S8. [Figure 14A] 1 is a graph showing the relationship between current and optical output in a semiconductor light emitting device 100A and a semiconductor light emitting device 100B. [Figure 14B] 1 is a graph showing the relationship between current and optical output in the semiconductor light emitting device 100 and the semiconductor light emitting device 100A. [Figure 14C] 1 shows exemplary cross-sectional SEM images of the semiconductor light emitting device 100 and the semiconductor light emitting device 100B. [Figure 15A] 1 is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 100A and the semiconductor light emitting device 100B. [Figure 15B] 1 is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 100 and the semiconductor light emitting device 100B. [Figure 16] 1 is a graph showing the relationship between width W2 and enhancement in the semiconductor light emitting device 100. [Figure 17] 13 is a graph showing the relationship between the thickness T and enhancement in a semiconductor light emitting device 100B. [Figure 18] 2 is a plan view of the semiconductor light emitting element 200. FIG. [Figure 19] 18. FIG. 19 is a plan view of the semiconductor light emitting device 200 as viewed from the opposite side to that of FIG. [Figure 20] 19 is a cross-sectional view taken along the line XX-XX in FIG. 18. [Figure 21] 1 is a cross-sectional view of a semiconductor light emitting device 200 according to a first modified example. [Figure 22] FIG. 11 is a plan view of a semiconductor light emitting device 200 according to a second modification. [Figure 23]23 is a plan view of a semiconductor light emitting device 200 according to Modification 2, as viewed from the opposite side to that in FIG. [Figure 24A] 1 is a graph showing the relationship between current and optical output in a semiconductor light emitting device 200A and a semiconductor light emitting device 200B. [Figure 24B] 1 is a graph showing the relationship between current and optical output in a semiconductor light emitting device 200A and a semiconductor light emitting device 200C. [Figure 24C] 1 is a graph showing the relationship between current and optical output in the semiconductor light emitting device 200 and the semiconductor light emitting device 200A. [Figure 25A] 1 is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 200A and the semiconductor light emitting device 200B. [Figure 25B] 1 is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 200A and the semiconductor light emitting device 200C. [Figure 25C] 1 is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 200 and the semiconductor light emitting device 200B. [Figure 26A] 13 shows the results of a near field pattern (NFP) analysis of the semiconductor light emitting device 200B. [Figure 26B] This is an NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is set to 50 μm. [Figure 26C] This shows the results of an NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is set to 80 μm. [Figure 26D] This shows the results of an NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is set to 100 μm. [Figure 26E] This shows the results of an NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is set to 120 μm. [Figure 26F] This shows the results of an NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is set to 150 μm. [Figure 26G] This shows the results of an NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is set to 300 μm. [Fig. 26H]13 shows the results of an NFP analysis of the semiconductor light emitting device 200C. [Figure 27] 1 is a graph showing the relationship between the diameter D2 and the enhancement in the semiconductor light emitting device 200. [Figure 28A] 13 is a graph showing the relationship between current and optical output in a semiconductor light emitting device 200A and a semiconductor light emitting device 200B in which the number of mesa structures 24 is plural. [Figure 28B] 13 is a graph showing the relationship between current and optical output in a semiconductor light emitting device 200A and a semiconductor light emitting device 200C in which the number of mesa structures 24 is plural. [Figure 28C] 13 is a graph showing the relationship between current and optical output in the semiconductor light emitting device 200 and the semiconductor light emitting device 200A when the number of mesa structures 24 is plural. [Figure 29A] 13 is a graph showing the relationship between current and external quantum efficiency in a semiconductor light emitting device 200A and a semiconductor light emitting device 200B in which the number of mesa structures 24 is plural. [Figure 29B] 13 is a graph showing the relationship between current and external quantum efficiency in a semiconductor light emitting device 200A and a semiconductor light emitting device 200C in which the number of mesa structures 24 is plural. [Figure 29C] 13 is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 200 and the semiconductor light emitting device 200B in which the number of mesa structures 24 is plural. [Diagram 30] 2 is a plan view of the semiconductor light emitting element 300. FIG. [Diagram 31] 30. FIG. 30 is a plan view of the semiconductor light emitting device 300 as viewed from the opposite side to that of FIG. [Diagram 32] 31 is a cross-sectional view taken along line XXXII-XXXII in FIG. 30. [Diagram 33] FIG. 11 is a plan view of a semiconductor light emitting device 300 according to a modified example. [Diagram 34] 34 is a plan view of a semiconductor light emitting device 300 according to a modified example, as viewed from the opposite side to that in FIG. [Figure 35A]13 is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b in the semiconductor light emitting device 300 and the semiconductor light emitting device 300A when the diameter D3 is 210 μm. [Figure 35B] 13 is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b in the semiconductor light emitting device 300 and the semiconductor light emitting device 300A when the diameter D3 is 250 μm. [Figure 35C] 13 is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b in the semiconductor light emitting device 300 and the semiconductor light emitting device 300A when the diameter D3 is 333 μm. [Figure 35D] 13 is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b in the semiconductor light emitting device 300 and the semiconductor light emitting device 300A when the diameter D3 is 500 μm. [Figure 35E] 13 is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b in the semiconductor light emitting device 300 and the semiconductor light emitting device 300A when the diameter D3 is 1000 μm. [Fig. 35F] 13 is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b in the semiconductor light emitting device 300 and the semiconductor light emitting device 300A when the diameter D3 is 2000 μm. [Diagram 36] 13 is a graph showing the relationship between the diameter D3 and the enhancement in the semiconductor light emitting device 300. [Figure 37A] 13 is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting device 300 when the constituent material of the substrate 10 is sapphire. [Figure 37B] 13 is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting device 300 when the constituent material of the substrate 10 is aluminum nitride. [Figure 38A] 1 is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 300 and the semiconductor light emitting device 300A. [Figure 38B] 1 is a graph showing the relationship between current and optical output in the semiconductor light emitting device 300 and the semiconductor light emitting device 300A. [Figure 39] 4 is a cross-sectional view of the light emitting module 400. FIG. [Diagram 40] FIG. 11 is a cross-sectional view of a light-emitting module 400 according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated.

[0009] (First embodiment) A semiconductor light emitting device according to a first embodiment (referred to as a semiconductor light emitting device 100) will be described.

[0010] <Configuration of the semiconductor light emitting element 100> The configuration of the semiconductor light emitting device 100 will be described below.

[0011] FIG 1 is a plan view of the semiconductor light emitting element 100. FIG 2 is a plan view of the semiconductor light emitting element 100 as viewed from the opposite side to that of FIG 1. In FIG 2, the pad electrodes 33 and 34 are omitted. FIG 3 is a cross-sectional view taken along line III-III in FIG 1. As shown in FIG 1 to FIG 3, the semiconductor light emitting element 100 has a substrate 10, a semiconductor layer 20, an n-electrode 31, a p-electrode 32, a pad electrode 33, and a pad electrode 34.

[0012] The substrate 10 has a first main surface 10a and a second main surface 10b. The first main surface 10a and the second main surface 10b are end surfaces in the thickness direction of the substrate 10. The second main surface 10b is the opposite surface to the first main surface 10a. The thickness of the substrate 10 is defined as thickness T. The thickness T is, for example, 30 μm or more. The thickness T is preferably 50 μm or more, and more preferably 90 μm or more. The thickness T is the distance between the first main surface 10a and a portion of the second main surface 10b where the concave-convex structure 10c described later is not formed.

[0013] The constituent material of the substrate 10 is, for example, single crystal aluminum nitride (AlN). The constituent material of the substrate 10 is preferably single crystal aluminum nitride manufactured by a sublimation method (PVT: Physical Vapor Transport). The constituent material of the substrate 10 may be single crystal sapphire. The absorption coefficient of the substrate 10 for deep ultraviolet light is 1 cm -1 More than 50cm -1 Deep purple light is light having a wavelength of 100 nm or more and 350 nm or less, and more narrowly defined as light having a wavelength of 200 nm or more and 300 nm or less.

[0014] The semiconductor layer 20 has an n-type semiconductor layer 21, an active layer 22, and a p-type semiconductor layer 23. The n-type semiconductor layer 21 is disposed on the first major surface 10a. The active layer 22 is disposed on the n-type semiconductor layer 21. The p-type semiconductor layer 23 has an electron blocking layer 23a disposed on the active layer 22, a cladding layer 23b disposed on the electron blocking layer 23a, and a contact layer 23c disposed on the cladding layer 23b.

[0015] The constituent material of the n-type semiconductor layer 21 is, for example, AlGaN or AlInGaN. The constituent material of the n-type semiconductor layer 21 is doped with n-type impurities. The n-type impurities are, for example, silicon (Si), germanium (Ge), tin (Sn), oxygen (O), carbon (C), etc.

[0016] The active layer 22 has, for example, a multiple quantum well (MQW) structure. More specifically, the active layer 22 has well layers and barrier layers that are alternately stacked. The well layers are made of, for example, AlInGaN. The barrier layers are made of, for example, AlGaN or AlInGaN. Deep ultraviolet light is generated from the active layer 22.

[0017] The constituent material of the electron blocking layer 23a is, for example, AlGaN or AlN. The constituent material of the cladding layer 23b is, for example, AlGaN. The constituent material of the contact layer 23c is, for example, GaN. The constituent material of the p-type semiconductor layer 23 is doped with p-type impurities. The p-type impurities are, for example, magnesium (Mg), zinc (Zn), beryllium (Be), etc.

[0018] The semiconductor layer 20 has a mesa structure 24. Around the mesa structure 24, the active layer 22 and the p-type semiconductor layer 23 are removed so as to expose the n-type semiconductor layer 21. The mesa structure 24 has a plurality of straight line portions 24a extending along a first direction DR1 in a plan view. The straight line portions 24a are arranged at intervals in a second direction DR2. The second direction DR2 is a direction perpendicular to the first direction DR1 in a plan view. The mesa structure 24 has, for example, a comb-tooth shape in a plan view. The width of the straight line portion 24a in the second direction DR2 is defined as a width W1.

[0019] The second main surface 10b has a first region 10ba and a second region 10bb. The first region 10ba faces the mesa structure 24. More specifically, the first region 10ba has a portion facing the straight line portion 24a. In a plan view, the center of the first region 10ba in the second direction DR2 preferably overlaps with the region of the straight line portion 24a. In a plan view, the distance between the center of the first region 10ba in the second direction DR2 and the center of the straight line portion 24a in the second direction DR2 is preferably 0.2 times or less than the width W1, and more preferably 0.05 times or less than the width W1. In a plan view, the center of the first region 10ba in the second direction DR2 most preferably coincides with the center of the straight line portion 24a in the second direction DR2. The first region 10ba is configured as a flat surface.

[0020] The width of the first region 10ba facing the straight portion 24a in the second direction DR2 is defined as width W2. Width W2 is preferably 0.1 times or more, and more preferably 0.4 times or more and 1.8 times or less, of width W1. The lower limit of width W2 is preferably 0.8 times or 1.0 times width W1. The upper limit of width W2 is preferably 1.5 times or 1.25 times width W1.

[0021] The second region 10bb has a concave-convex structure 10c. The concave-convex structure 10c is a structure in which protrusions or holes are arranged in a cone shape, a polygonal pyramid shape, a truncated cone shape, a polygonal pyramid shape, a cylindrical shape, or a polygonal column shape. Preferably, the protrusions or holes included in the concave-convex structure 10c are arranged periodically in a planar view. More specifically, the protrusions or holes included in the concave-convex structure 10c are preferably arranged in a lattice shape (a square lattice shape, a houndstooth lattice shape, a regular triangular lattice shape, etc.) in a planar view. The protrusions or holes included in the concave-convex structure 10c may be arranged randomly in a planar view. The aspect ratio of the protrusions or holes included in the concave-convex structure 10c is, for example, 0.6 or more. The lower limit of the aspect ratio of the protrusions or holes included in the concave-convex structure 10c may be 0.8, 1.0, or 1.5, and the upper limit of the aspect ratio of the protrusions or holes included in the concave-convex structure 10c may be 3, 5, or 10. The aspect ratio of the protrusions or holes included in the uneven structure 10c is the height of the protrusions or holes of the uneven structure 10c divided by the width at the bottom of the protrusions or holes of the uneven structure 10c (for example, when the protrusions included in the uneven structure 10c are conical, the diameter at the bottom of the protrusions). The period of the uneven structure 10c is, for example, 1000 nm or less. The period of the uneven structure 10c is the distance between two adjacent protrusions or holes included in the uneven structure 10c.

[0022] The n-electrode 31 is disposed on the n-type semiconductor layer 21 exposed between the mesa structures 24 in a plan view. The p-electrode 32 is disposed on the p-type semiconductor layer 23 (more specifically, the contact layer 23c). The constituent materials of the n-electrode 31 and the p-electrode 32 are, for example, metal materials. The n-electrode 31 is configured, for example, by laminating a titanium (Ti) layer, an aluminum layer, and a gold (Au) layer in this order from the n-type semiconductor layer 21 side. The p-electrode 32 is configured, for example, by laminating a nickel (Ni) layer and a gold layer in this order from the p-type semiconductor layer 23 side.

[0023] The pad electrode 33 is disposed on the n-electrode 31. The pad electrode 33 is made of, for example, a metal material. The pad electrode 33 is configured by laminating a titanium layer, a nickel layer, and a gold layer in this order from the n-electrode 31 side. The pad electrode 34 is disposed on the p-electrode 32. The pad electrode 34 is made of, for example, a metal material. The pad electrode 34 is configured by laminating a titanium layer, a nickel layer, and a gold layer in this order from the p-electrode 32 side.

[0024] <Modification> Fig. 4 is a cross-sectional view of a semiconductor light emitting device 100 according to a modified example. As shown in Fig. 4, the semiconductor light emitting device 100 may further include an antireflection film 40. The antireflection film 40 is disposed on the first region 10ba. The antireflection film 40 is made of, for example, silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0025] <Method of Manufacturing the Semiconductor Light Emitting Device 100> A method for manufacturing the semiconductor light emitting device 100 will now be described.

[0026] Fig. 5 is a manufacturing process diagram of the semiconductor light emitting device 100. As shown in Fig. 5, the manufacturing method of the semiconductor light emitting device 100 includes a preparation step S1, a semiconductor layer formation step S2, a mesa structure formation step S3, a first electrode formation step S4, a second electrode formation step S5, a substrate back surface processing step S6, a mask formation step S7, a columnar structure formation step S8, a concave-convex structure formation step S9, and a singulation step S10.

[0027] In the method for manufacturing the semiconductor light emitting element 100, a preparation step S1 is first performed. FIG. 6 is a cross-sectional view illustrating the preparation step S1. As shown in FIG. 6, a substrate 10 is prepared in the preparation step S1. The substrate 10 prepared in the preparation step S1 does not have a semiconductor layer 20 formed on a first major surface 10a, and does not have a concave-convex structure 10c formed on a second major surface 10b. The thickness of the substrate 10 prepared in the preparation step S1 is greater than the thickness T.

[0028] The semiconductor layer forming step S2 is performed after the preparation step S1. Fig. 7 is a cross-sectional view illustrating the semiconductor layer forming step S2. As shown in Fig. 7, in the semiconductor layer forming step S2, a semiconductor layer 20 is formed. Each layer constituting the semiconductor layer 20 is formed by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). After the semiconductor layer 20 is formed, annealing is performed to activate the p-type semiconductor layer 23.

[0029] The mesa structure forming step S3 is performed after the semiconductor layer forming step S2. FIG. 8 is a cross-sectional view illustrating the mesa structure forming step S3. As shown in FIG. 8, in the mesa structure forming step S3, a mesa structure 24 is formed in the semiconductor layer 20. In the mesa structure forming step S3, first, a mask is formed on the semiconductor layer 20. The mask is made of a metal material such as nickel. Second, anisotropic etching is performed using the mask. As a result, the mesa structure 24 is formed. Third, the mask is removed.

[0030] The first electrode formation step S4 is performed after the mesa structure formation step S3. Fig. 9 is a cross-sectional view illustrating the first electrode formation step S4. As shown in Fig. 9, in the first electrode formation step S4, an n-electrode 31 and a p-electrode 32 are formed. In the first electrode formation step S4, the n-electrode 31 and the p-electrode 32 are formed in sequence, for example, by a vacuum deposition method. After the n-electrode 31 and the p-electrode 32 are formed, annealing is performed.

[0031] The second electrode forming step S5 is performed after the first electrode forming step S4. Fig. 10 is a cross-sectional view illustrating the second electrode forming step S5. As shown in Fig. 10, in the second electrode forming step S5, the pad electrodes 33 and 34 are formed. In the second electrode forming step S5, the pad electrodes 33 and 34 are formed by, for example, a vacuum deposition method.

[0032] The substrate back surface processing step S6 is performed after the second electrode forming step S5. Fig. 11 is a cross-sectional view illustrating the substrate back surface processing step S6. As shown in Fig. 11, in the substrate back surface processing step S6, machining (grinding and polishing) is performed on the second main surface 10b. This reduces the thickness of the substrate 10.

[0033] The mask formation step S7 is performed after the substrate back surface processing step S6. Fig. 12A is a first cross-sectional view illustrating the mask formation step S7. As shown in Fig. 12A, in the mask formation step S7, first, a first layer 50, a second layer 51, and a third layer 52 are formed in sequence on the second main surface 10b. That is, the first layer 50 is formed on the second main surface 10b, the second layer 51 is formed on the first layer 50, and the third layer 52 is formed on the second layer 51.

[0034] The material of the first layer 50 is, for example, a resist. The first layer 50 is formed, for example, by applying the material of the first layer 50 onto the second main surface 10b by spin coating and baking and hardening the applied material of the first layer 50. The material of the second layer 51 includes, for example, an inorganic material such as silicon dioxide. The second layer 51 is formed, for example, by applying the material of the second layer 51 onto the first layer 50 by spin coating and baking and hardening the applied material of the second layer 51. The second layer 51 may be a spin-on-glass (SOG) layer.

[0035] The material of the third layer 52 is, for example, a resist. The third layer 52 is formed, for example, by applying the material of the third layer 52 onto the second layer 51 by spin coating and baking the applied material of the third layer 52 to harden it. The thickness of the first layer 50 is, for example, greater than the thickness of the second layer 51 and the thickness of the third layer 52. The thickness of the third layer 52 is, for example, greater than the thickness of the second layer 51.

[0036] FIG. 12B is a second cross-sectional view explaining the mask forming step S7. As shown in FIG. 12B, in the mask forming step S7, secondly, a recess 52a is formed. The recess 52a is formed, for example, by pressing a mold having a protrusion at a position corresponding to the recess 52a against the third layer 52. At this time, the position of the protrusion of the mold (the position where the recess 52a is formed) is aligned with the mesa structure 24 on the first main surface 10a side. This alignment is performed by viewing the shape of the mesa structure 24 and the alignment mark from the second main surface 10b side using a device capable of double-sided alignment. This alignment may be performed with the edge of the substrate 10 as a reference. FIG. 12C is a third cross-sectional view explaining the mask forming step S7. As shown in FIG. 12C, in the mask forming step S7, thirdly, for example, anisotropic etching is performed to form an opening 51a in the etching second layer 51. By the anisotropic etching, the portion of the third layer 52 at the bottom of the recess 52a is removed to turn the recess 52a into an opening 52b, and the portion of the second layer 51 exposed from the opening 52b is removed to turn into an opening 51a.

[0037] FIG. 12D is a fourth cross-sectional view illustrating the mask formation step S7. As shown in FIG. 12D, in the mask formation step S7, fourthly, for example, anisotropic etching is performed to form the opening 50a. By performing anisotropic etching, the portion of the first layer 50 exposed from the opening 51a is removed to form the opening 50a. In addition, the third layer 52 is also removed by anisotropic etching. As a result, a mask consisting of the first layer 50 having the opening 50a and the second layer 51 having the opening 51a is formed.

[0038] The pillar structure forming step S8 is performed after the mask forming step S7. Fig. 13 is a cross-sectional view showing the pillar structure forming step S8. As shown in Fig. 13, in the pillar structure forming step S8, a pillar structure 60 is formed. The pillar structure 60 is made of a metal material such as nickel. The pillar structure 60 has a shape corresponding to the concave-convex structure 10c.

[0039] In the columnar structure forming step S8, first, the columnar structures 60 are formed on the second main surface 10b exposed from the openings 50a and 51a by vacuum deposition. At this time, a layer made of the same material as the columnar structures 60 is also formed on the second layer 51. Second, the first layer 50 is lifted off from the second main surface 10b together with the second layer 51 and the layer made of the same material as the columnar structures 60 on the second layer 51. The lift-off is performed by immersing the substrate 10 in an organic solvent such as acetone or NMP (N-methyl-2-pyrrolidone) and applying ultrasonic waves to the substrate 10.

[0040] The uneven structure forming step S9 is performed after the mask forming step S7. In the uneven structure forming step S9, anisotropic etching is performed using the columnar structures 60 as a mask. As a result, the shape of the uneven structure 10c is transferred to the second main surface 10b, and the uneven structure 10c is formed on the second main surface 10b. The singulation step S10 is performed after the uneven structure forming step S9. In the singulation step S10, a dicing process is performed to singulate the semiconductor light emitting element 100. In this manner, the semiconductor light emitting element 100 having the structure shown in FIG. 1 to FIG. 3 is manufactured.

[0041] <Effects of the semiconductor light emitting element 100> The effects of the semiconductor light emitting device 100 will be described below in comparison with semiconductor light emitting devices according to comparative examples. The semiconductor light emitting device according to comparative example 1 is designated as semiconductor light emitting device 100A. The semiconductor light emitting device according to comparative example 2 is designated as semiconductor light emitting device 100B.

[0042] In the semiconductor light emitting element 100A, the entire second main surface 10b is configured as a flat surface. Except for this, the configuration of the semiconductor light emitting element 100A is common to the configuration of the semiconductor light emitting element 100. Note that in the semiconductor light emitting element 100A, the second main surface 10b is configured as a flat surface and an anti-reflection film 40 is disposed on the second main surface 10b. In the semiconductor light emitting element 100B, a concave-convex structure 10c is formed on the entire second main surface 10b. Except for this, the configuration of the semiconductor light emitting element 100B is common to the configuration of the semiconductor light emitting element 100.

[0043] FIG. 14A is a graph showing the relationship between current and optical output in the semiconductor light emitting element 100A and the semiconductor light emitting element 100B. As shown in FIG. 14A, the optical output of the semiconductor light emitting element 100B is greater than that of the semiconductor light emitting element 100A. More specifically, when a current of 200 mA is applied, the optical output of the semiconductor light emitting element 100B is 1.18 times that of the semiconductor light emitting element 100A. FIG. 15A is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting element 100A and the semiconductor light emitting element 100B. As shown in FIG. 15A, the external quantum efficiency (EQE) of the semiconductor light emitting element 100B is higher than that of the semiconductor light emitting element 100A. More specifically, when a current of 200 mA is applied, the external quantum efficiency of the semiconductor light emitting element 100B is 1.18 times that of the semiconductor light emitting element 100A.

[0044] From these comparisons, it can be seen that in the semiconductor light-emitting element 100A, deep-ultraviolet light can only be extracted from the portion of the second main surface 10b that faces the mesa structure 24, whereas in the semiconductor light-emitting element 100B, the uneven structure 10c is formed on the second main surface 10b, so that deep-ultraviolet light can also be extracted from the portion of the second main surface 10b that does not face the mesa structure 24. Therefore, the semiconductor light-emitting element 100B has an improved deep-ultraviolet light extraction efficiency compared to the semiconductor light-emitting element 100A.

[0045] However, in the semiconductor light-emitting element 100B, the uneven structure 10c is formed over the entire surface of the second main surface 10b including the first region 10ba, and as a result, a portion of the deep-ultraviolet light extracted from the first region 10ba is diffracted or scattered by the uneven structure 10c in the first region 10ba, resulting in a decrease in the extraction efficiency of the deep-ultraviolet light in the first region 10ba.

[0046] Based on this knowledge, in the semiconductor light emitting device 100, the first region 10ba is configured as a flat surface. That is, in the semiconductor light emitting device 100, the uneven structure 10c is not formed in the first region 10ba. Therefore, in the semiconductor light emitting device 100, the uneven structure 10c is formed in the second region 10bb, which enables extraction of deep ultraviolet light from the portion of the second main surface 10b that does not face the mesa structure 24, while the first region 10ba is configured as a flat surface to suppress diffraction and scattering of deep ultraviolet light in the portion of the second main surface 10b that faces the mesa structure 24, thereby increasing the extraction efficiency of optical ultraviolet light.

[0047] FIG. 14B is a graph showing the relationship between current and optical output in the semiconductor light emitting device 100 and the semiconductor light emitting device 100A. FIG. 15B is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 100 and the semiconductor light emitting device 100B. As shown in FIG. 14B and FIG. 15B, the semiconductor light emitting device 100 has improved deep ultraviolet light extraction efficiency (optical output, external quantum efficiency) compared to the semiconductor light emitting device 100B. More specifically, when a current of 200 mA is applied, the semiconductor light emitting device 100 has optical output and external quantum efficiency 1.42 times that of the semiconductor light emitting device 100A. This also supports the idea that the semiconductor light emitting device 100 improves the deep ultraviolet light extraction efficiency.

[0048] 14A, 14B, 15A, and 15B, the width W1 is set to 90 μm, the chip size of the semiconductor light emitting device is set to 1 mm×1 mm, and the area of ​​the mesa structure 24 in a plan view is set to 0.30 mm 214B and 15B, the width W2 of the semiconductor light emitting device 100 is 110 μm, and the anti-reflection film 40 is disposed on the first region 10ba. FIG. 14C is an exemplary cross-sectional SEM image of the semiconductor light emitting device 100 and the semiconductor light emitting device 100B. In FIG. 14B and 14C, as shown in FIG. 14C, the uneven structure 10c of the semiconductor light emitting device 100 and the semiconductor light emitting device 100B includes conical protrusions with an aspect ratio of 1.0, the period of the uneven structure 10c is 600 nm, and the protrusions included in the uneven structure 10c are arranged in a triangular lattice shape in a plan view.

[0049] Fig. 16 is a graph showing the relationship between the width W2 and the enhancement in the semiconductor light emitting device 100. In Fig. 16, the width W1 of the semiconductor light emitting device 100 is set to 90 µm, the antireflection film 40 is disposed on the first region 10ba, the thickness T is set to 100 µm, and the absorption coefficient of the substrate 10 is set to 28 cm -1 Or 19cm -1 In Fig. 16, the enhancement of the semiconductor light emitting device 100 is the improvement rate of the light output based on the semiconductor light emitting device 100A, that is, the improvement rate of the light extraction efficiency. As shown in Fig. 16, when the width W2 is 40 μm or more and 160 μm or less (i.e., when the width W2 is 0.4 times or more and 1.8 times or less than the width W1), the improvement rate (enhancement) of the deep ultraviolet light extraction efficiency is particularly improved.

[0050] Furthermore, in the semiconductor light-emitting element 100, it can be seen that the extraction efficiency of deep ultraviolet light is further improved when the width W2 is 60 μm or more and 140 μm or less (width W2 is 0.8 times or more and 1.5 times or less than width W1), and that the extraction efficiency of deep ultraviolet light is further improved when the width W2 is 90 μm or more and 110 μm or less (width W2 is 1.0 times or more and 1.25 times or less than width W1).

[0051] FIG. 17 is a graph showing the relationship between the thickness T and the enhancement in the semiconductor light emitting device 100B. As shown in FIG. 17, when using a substrate 10 with a large absorption coefficient such as an aluminum nitride substrate formed by the PVT method, in the semiconductor light emitting device 100B, if the thickness T is small, the extraction efficiency of the deep ultraviolet light can be increased, but if the thickness T is large (for example, 100 μm), the extraction efficiency of the deep ultraviolet light decreases. On the other hand, in the semiconductor light emitting device 100, even if a substrate 10 with a large absorption coefficient is used and the thickness T is large (for example, 100 μm), a high extraction efficiency of the deep ultraviolet light can be maintained (see FIG. 16). Note that the ability to use a substrate 10 with a large thickness T means that the handleability of the substrate 10 during manufacturing is improved.

[0052] Second embodiment A semiconductor light emitting device according to the second embodiment (referred to as semiconductor light emitting device 200) will be described. Here, differences from the semiconductor light emitting device 100 will be mainly described, and overlapping descriptions will not be repeated.

[0053] <Configuration of the semiconductor light emitting element 200> The configuration of the semiconductor light emitting device 200 will be described below.

[0054] FIG. 18 is a plan view of the semiconductor light emitting device 200. FIG. 19 is a plan view of the semiconductor light emitting device 200 as viewed from the opposite side to that of FIG. 18. In FIG. 19, the pad electrodes 33 and 34 are omitted. FIG. 20 is a cross-sectional view taken along the line XX-XX in FIG. 18. As shown in FIGS. 18 to 20, the semiconductor light emitting device 200 has a substrate 10, a semiconductor layer 20, an n-electrode 31, a p-electrode 32, a pad electrode 33, and a pad electrode 34. In this regard, the configuration of the semiconductor light emitting device 200 is common to the configuration of the semiconductor light emitting device 100.

[0055] In the semiconductor light emitting device 200, the mesa structure 24 is circular and the first region 10ba is circular in plan view. In plan view, the center of the first region 10ba preferably overlaps with the region of the mesa structure 24. The diameter of the mesa structure 24 in plan view is defined as diameter D1. In plan view, the distance between the center of the mesa structure 24 and the first region 10ba is preferably 0.2 times or less than the diameter D1, and more preferably 0.05 times or less than the diameter D1. In plan view, the center of the mesa structure 24 most preferably coincides with the center of the first region 10ba. The diameter of the first region 10ba in plan view is defined as diameter D2. The diameter D2 is preferably 0.1 times or more than the diameter D1, and is preferably 0.5 times or more and 3.0 times or less than the diameter D1. The lower limit of the diameter D2 is preferably 0.9 times or 1.0 times the diameter D1. The upper limit of the diameter D2 is preferably 2.5 times, 1.5 times, or 1.25 times the diameter D1. In these respects, the configuration of the semiconductor light emitting device 200 differs from the configuration of the semiconductor light emitting device 100.

[0056] <Modification> Fig. 21 is a cross-sectional view of a semiconductor light emitting device 200 according to Modification 1. As shown in Fig. 21, the semiconductor light emitting device 200 may further include an antireflection film 40 disposed on the first region 10ba. Fig. 22 is a plan view of the semiconductor light emitting device 200 according to Modification 2. Fig. 23 is a plan view of the semiconductor light emitting device 200 according to Modification 2 as viewed from the opposite side to that of Fig. 22. As shown in Figs. 22 and 23, in the semiconductor light emitting device 200, the number of mesa structures 24 and the number of first regions 10ba may be plural.

[0057] <Effects of the semiconductor light emitting element 200> The effects of the semiconductor light emitting device 200 will be described below in comparison with the semiconductor light emitting device according to Comparative Example 3, the semiconductor light emitting device according to Comparative Example 4, and the semiconductor light emitting device according to Comparative Example 5. The semiconductor light emitting device according to Comparative Example 3 is referred to as semiconductor light emitting device 200A, the semiconductor light emitting device according to Comparative Example 4 is referred to as semiconductor light emitting device 200B, and the semiconductor light emitting device according to Comparative Example 5 is referred to as semiconductor light emitting device 200C.

[0058] In the semiconductor light emitting element 200A and the semiconductor light emitting element 200C, the second main surface 10b is configured as a flat surface over the entire surface. Except for this, the configurations of the semiconductor light emitting element 200A and the semiconductor light emitting element 200C are common to the configuration of the semiconductor light emitting element 200. In the semiconductor light emitting element 200C, an anti-reflection film 40 is disposed on the second main surface 10b. In the semiconductor light emitting element 200B, an uneven structure 10c is formed over the entire surface of the second main surface 10b. Except for this, the configuration of the semiconductor light emitting element 200B is common to the configuration of the semiconductor light emitting element 200.

[0059] FIG. 24A is a graph showing the relationship between current and optical output in the semiconductor light emitting element 200A and the semiconductor light emitting element 200B. As shown in FIG. 24A, the optical output of the semiconductor light emitting element 200B is greater than that of the semiconductor light emitting element 200A. More specifically, when a current of 8 mA is applied, the optical output of the semiconductor light emitting element 200B is 1.33 times that of the semiconductor light emitting element 200A. FIG. 24B is a graph showing the relationship between current and optical output in the semiconductor light emitting element 200A and the semiconductor light emitting element 200C. As shown in FIG. 24B, the optical output of the semiconductor light emitting element 200C is higher than that of the semiconductor light emitting element 200A. More specifically, when a current of 8 mA is applied, the optical output of the semiconductor light emitting element 200C is 1.27 times that of the semiconductor light emitting element 200A.

[0060] FIG. 25A is a graph showing the relationship between the current and the external quantum efficiency in the semiconductor light emitting element 200A and the semiconductor light emitting element 200B. As shown in FIG. 25A, the external quantum efficiency of the semiconductor light emitting element 200B is higher than that of the semiconductor light emitting element 200A. More specifically, when a current of 8 mA is applied, the external quantum efficiency of the semiconductor light emitting element 200B is 1.33 times that of the semiconductor light emitting element 200A. FIG. 25B is a graph showing the relationship between the current and the external quantum efficiency in the semiconductor light emitting element 200A and the semiconductor light emitting element 200C. As shown in FIG. 25B, the external quantum efficiency of the semiconductor light emitting element 200C is higher than that of the semiconductor light emitting element 200A. More specifically, when a current of 8 mA is applied, the external quantum efficiency of the semiconductor light emitting element 200C is 1.27 times that of the semiconductor light emitting element 200A.

[0061] From these comparisons, it can be seen that in the semiconductor light-emitting element 200A and the semiconductor light-emitting element 200C, deep-ultraviolet light can only be extracted from the portion of the second main surface 10b that faces the mesa structure 24, whereas in the semiconductor light-emitting element 200B, the uneven structure 10c is formed on the second main surface 10b, so that deep-ultraviolet light can also be extracted from the portion of the second main surface 10b that does not face the mesa structure 24. Therefore, the semiconductor light-emitting element 200B has an improved deep-ultraviolet light extraction efficiency compared to the semiconductor light-emitting element 200A and the semiconductor light-emitting element 200C.

[0062] However, in the semiconductor light emitting device 200B, the uneven structure 10c is formed on the entire surface of the second main surface 10b including the first region 10ba, and as a result, a part of the deep ultraviolet light extracted from the first region 10ba is diffracted or scattered by the uneven structure 10c in the first region 10ba. In the semiconductor light emitting device 200, the uneven structure 10c is formed in the second region 10bb, which enables extraction of deep ultraviolet light from the part of the second main surface 10b that does not face the mesa structure 24, while the first region 10ba is formed as a flat surface, which suppresses diffraction and scattering of deep ultraviolet light in the part of the second main surface 10b that faces the mesa structure 24, thereby increasing the extraction efficiency of the optical ultraviolet light.

[0063] FIG. 24C is a graph showing the relationship between current and optical output in the semiconductor light emitting device 200 and the semiconductor light emitting device 200A. FIG. 25C is a graph showing the relationship between current and external quantum efficiency in the semiconductor light emitting device 200 and the semiconductor light emitting device 200B. As shown in FIG. 24C and FIG. 25C, the semiconductor light emitting device 200 has improved deep ultraviolet light extraction efficiency (optical output, external quantum efficiency) compared to the semiconductor light emitting device 200B. More specifically, when a current of 8 mA is applied, the semiconductor light emitting device 100 has optical output and external quantum efficiency 1.78 times that of the semiconductor light emitting device 200A. This comparison supports the fact that the semiconductor light emitting device 200 improves the deep ultraviolet light extraction efficiency.

[0064] In addition, in Figures 24A, 24B, 24C, 25A, 25B, and 25C, the diameter D1 is 100 μm. In Figures 24C and 25C, the diameter D2 is 120 μm in the semiconductor light emitting element 200, and the anti-reflection film 40 is disposed on the first region 10ba. In Figures 24A, 24C, 25A, and 25B, in the semiconductor light emitting element 200 and the semiconductor light emitting element 200B, the uneven structure 10c includes conical protrusions with an aspect ratio of 1.0, the period of the uneven structure 10c is 600 nm, and the protrusions included in the uneven structure 10c are arranged in a triangular lattice shape in a plan view.

[0065] FIG. 26A shows the results of NFP (Near Field Pattern) analysis of the semiconductor light emitting device 200B. FIG. 26B shows the results of NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is 50 μm. FIG. 26C shows the results of NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is 80 μm. FIG. 26D shows the results of NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is 100 μm. FIG. 26E shows the results of NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is 120 μm. FIG. 26F shows the results of NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is 150 μm. FIG. 26G shows the results of NFP analysis of the semiconductor light emitting device 200 when the diameter D2 is 300 μm. FIG. 26H shows the results of NFP analysis of the semiconductor light emitting device 200C. In addition, in Figures 26A to 26G, the diameter D1 is set to 100 µm.

[0066] As shown in FIG. 26H, in the semiconductor light emitting device 200C, deep ultraviolet light is extracted only from the portion of the second main surface 10b facing the mesa structure 24 (see the black area in the center of FIG. 26H). As shown in FIG. 26A, in the semiconductor light emitting device 200B, deep ultraviolet light can be extracted from the portion of the second main surface 10b not facing the mesa structure 24, but the intensity of the deep ultraviolet light extracted from the portion of the second main surface 10b facing the mesa structure 24 is weak (in FIG. 26A, unlike FIG. 26H, there is no black area in the center). Note that in FIG. 26A to FIG. 26H, there are black areas other than the center, but the intensity of the deep ultraviolet light is the weakest in the black areas other than the center.

[0067] 26B to 26G, in the semiconductor light emitting device 200, deep ultraviolet light can be extracted from a portion of the second main surface 10b not facing the mesa structure 24, and the intensity of the deep ultraviolet light extracted from the portion of the second main surface 10b facing the mesa structure 24 is strong. These comparisons also support the idea that it is possible to suppress diffraction and scattering of deep ultraviolet light in the portion of the second main surface 10b facing the mesa structure 24 while enabling extraction of deep ultraviolet light from the portion of the second main surface 10b not facing the mesa structure 24.

[0068] Fig. 27 is a graph showing the relationship between the diameter D2 and the enhancement in the semiconductor light emitting device 200. In Fig. 27, the semiconductor light emitting device 200 has a width W1 of 100 µm, an antireflection film 40 is disposed on the first region 10ba, a thickness T of 100 µm, and an absorption coefficient of the substrate 10 of 28 cm -1 Or 19cm -1 In Fig. 27, the enhancement of the semiconductor light emitting device 200 is the improvement rate of the light output based on the semiconductor light emitting device 200A, that is, the improvement rate of the light extraction efficiency. As shown in Fig. 27, when the diameter D2 is 50 µm or more and 300 µm or less (i.e., when the diameter D2 is 0.5 times or more and 3.0 times or less than the diameter D1), the extraction efficiency (enhancement) of deep ultraviolet light is particularly improved.

[0069] Furthermore, in the semiconductor light-emitting element 200, it can be seen that the extraction efficiency of deep ultraviolet light is further improved when the diameter D2 is 80 μm or more and 150 μm or less (the width W2 is 0.8 times or more and 1.5 times or less than the width W1), and that the extraction efficiency of deep ultraviolet light is further improved when the diameter D2 is 100 μm or more and 125 μm or less (the diameter D2 is 1.0 times or more and 1.25 times or less than the diameter D1).

[0070] FIG. 28A is a graph showing the relationship between current and optical output in the semiconductor light emitting device 200A and the semiconductor light emitting device 200B when the number of mesa structures 24 is plural. As shown in FIG. 28A, when the number of mesa structures 24 is plural, the optical output of the semiconductor light emitting device 200B is larger than that of the semiconductor light emitting device 200A. More specifically, when a current of 100 mA is applied, the optical output of the semiconductor light emitting device 200B is 1.29 times that of the semiconductor light emitting device 200A. FIG. 28B is a graph showing the relationship between current and optical output in the semiconductor light emitting device 200A and the semiconductor light emitting device 200C when the number of mesa structures 24 is plural. As shown in FIG. 28B, when the number of mesa structures 24 is plural, the optical output of the semiconductor light emitting device 200C is higher than that of the semiconductor light emitting device 200A. More specifically, when a current of 100 mA is applied, the optical output of the semiconductor light emitting device 200C is 1.18 times that of the semiconductor light emitting device 200A.

[0071] FIG. 29A is a graph showing the relationship between the current and the external quantum efficiency in the semiconductor light emitting device 200A and the semiconductor light emitting device 200B when the number of the mesa structures 24 is plural. As shown in FIG. 29A, when the number of the mesa structures 24 is plural, the external quantum efficiency of the semiconductor light emitting device 200B is higher than that of the semiconductor light emitting device 200A. More specifically, when a current of 100 mA is applied, the external quantum efficiency of the semiconductor light emitting device 200B is 1.29 times that of the semiconductor light emitting device 200A. FIG. 29B is a graph showing the relationship between the current and the external quantum efficiency in the semiconductor light emitting device 200A and the semiconductor light emitting device 200C when the number of the mesa structures 24 is plural. As shown in FIG. 29B, when the number of the mesa structures 24 is plural, the external quantum efficiency of the semiconductor light emitting device 200C is higher than that of the semiconductor light emitting device 200A. More specifically, when a current of 100 mA is applied, the external quantum efficiency of the semiconductor light emitting device 200C is 1.18 times that of the semiconductor light emitting device 200A.

[0072] FIG. 28C is a graph showing the relationship between the current and the optical output in the semiconductor light emitting device 200 and the semiconductor light emitting device 200A when the number of the mesa structures 24 is plural. FIG. 29C is a graph showing the relationship between the current and the external quantum efficiency in the semiconductor light emitting device 200 and the semiconductor light emitting device 200B when the number of the mesa structures 24 is plural. As shown in FIG. 28C and FIG. 29C, in the semiconductor light emitting device 200, when the number of the mesa structures 24 is plural, the extraction efficiency (optical output, external quantum efficiency) of the deep ultraviolet light is improved compared to the semiconductor light emitting device 200B. More specifically, when a current of 100 mA is applied, the optical output and external quantum efficiency of the semiconductor light emitting device 100 are 1.68 times that of the semiconductor light emitting device 200A. This comparison supports that the extraction efficiency of the deep ultraviolet light is improved according to the semiconductor light emitting device 200 even when the number of the mesa structures 24 and the number of the first regions 10ba are plural.

[0073] 28A, 28B, 28C, 29A, 29B, and 29C, the diameter D1 is set to 100 μm, the chip size of the semiconductor light emitting device is set to 2 mm×2 mm, the pitch between two adjacent mesa structures 24 is set to 175 μm, the thickness T of the substrate 10 is set to 100 μm, and the absorption coefficient is set to 11 cm. -1 The aluminum nitride single crystal substrate is used, and the total area of ​​the mesa structure 24 in plan view is 0.778 mm 2 28C and 29C, the diameter D2 of the semiconductor light emitting device 200 is set to 120 μm, and the antireflection film 40 is disposed on the first region 10ba.

[0074] Third embodiment A semiconductor light emitting device according to the third embodiment (referred to as semiconductor light emitting device 300) will be described. Here, differences from the semiconductor light emitting device 200 will be mainly described, and overlapping descriptions will not be repeated.

[0075] FIG. 30 is a plan view of the semiconductor light emitting device 300. FIG. 31 is a plan view of the semiconductor light emitting device 300 as viewed from the opposite side to that of FIG. 30. In FIG. 31, the pad electrodes 33 and 34 are omitted. FIG. 32 is a cross-sectional view taken along the line XXXII-XXXII in FIG. 30. As shown in FIGS. 30 to 32, the semiconductor light emitting device 300 has a substrate 10, a semiconductor layer 20, an n-electrode 31, a p-electrode 32, a pad electrode 33, and a pad electrode 34. In this regard, the configuration of the semiconductor light emitting device 300 is common to that of the semiconductor light emitting device 200.

[0076] In the semiconductor light emitting device 300, a plurality of annular protrusions 10d are formed on the second main surface 10b as the uneven structure 10c. The plurality of annular protrusions 10d are concentrically arranged at intervals. The plurality of annular protrusions 10d preferably constitute a Fresnel zone plate structure 11. The radius of the side wall surface of the kth (k is a natural number) annular protrusion 10d from the inside in plan view is defined as radius r k For example, the radius of the side wall surface on the inner periphery of the third annular protrusion 10d from the inside is r5, and the radius of the side wall surface on the outer periphery of the third annular protrusion 10d from the inside is r6.

[0077] In the Fresnel zone plate structure 11, r k =(kλf+k 2 λ 2 / 4) 1 / 2 Here, λ is the wavelength of the deep ultraviolet light generated from the active layer 22, and f is the focal length. It is preferable that f is equal to the thickness T.

[0078] In plan view, it is preferable that the distance between the center of the Fresnel zone plate structure 11 (the center of the annular protrusion 10d) and the center of the mesa structure 24 is 0.05 times or less of the diameter D1. In plan view, it is more preferable that the center of the Fresnel zone plate structure 11 coincides with the center of the mesa structure 24. The height of the annular protrusion 10d is defined as height H. Height H is defined as n air λ / 2(n sub -n air) is preferably satisfied. air is the refractive index of deep ultraviolet light in air, and n sub is the refractive index of deep ultraviolet light in the substrate. air is 1. When the material of the substrate 10 is aluminum nitride, n sub is 2.29, and n sub is 1.83. Therefore, when λ is 265 nm and the material of the substrate 10 is aluminum nitride, it is most preferable that the height H is 103 nm.

[0079] The annular protrusion 10d is preferably trapezoidal in a cross section perpendicular to the extending direction of the annular protrusion 10d. The annular protrusion 10d may be rectangular, triangular, or a shape in which a rectangle and a trapezoid overlap each other in a cross section perpendicular to the extending direction of the annular protrusion 10d. In a cross section perpendicular to the extending direction of the annular protrusion 10d, an angle (taper angle) between the side surface of the annular protrusion 10d and a portion of the second main surface 10b where the annular protrusion 10d is not formed is preferably 50° or more, more preferably 65° or more, and particularly preferably 80° or more. The diameter of the Fresnel zone plate structure 11 is defined as a diameter D3. The diameter D3 is preferably 3 times or more, 5 times or more, 10 times or more, or 20 times or more than the diameter D1. In these respects, the configuration of the semiconductor light emitting device 300 is different from the configuration of the semiconductor light emitting device 200. Although not shown, the semiconductor light emitting element 300 may also have an anti-reflection film 40 disposed on the first region 10ba.

[0080] <Modification> Fig. 33 is a plan view of a semiconductor light emitting device 300 according to a modified example. Fig. 34 is a plan view of the semiconductor light emitting device 300 according to a modified example seen from the opposite side to that of Fig. 33. As shown in Fig. 33 and Fig. 34, in the semiconductor light emitting device 300, the number of mesa structures 24, the number of first regions 10ba, and the number of Fresnel zone plate structures 11 may be plural.

[0081] <Effects of the semiconductor light emitting element 300> The effects of the semiconductor light emitting device 300 will be described below in comparison with the semiconductor light emitting device according to Comparative Example 6. The semiconductor light emitting device according to Comparative Example 6 is taken as semiconductor light emitting device 300A. The configuration of the semiconductor light emitting device 300A is the same as the configuration of the semiconductor light emitting device 300, except that the second main surface 10b is configured as a flat surface (the Fresnel zone plate structure 11 is not formed on the second main surface 10b).

[0082] Fig. 35A is a graph showing the relationship between the emission angle and intensity of the deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting element 300 and the semiconductor light emitting element 300A when the diameter D3 is 210 μm. Fig. 35B is a graph showing the relationship between the emission angle and intensity of the deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting element 300 and the semiconductor light emitting element 300A when the diameter D3 is 250 μm. Fig. 35C is a graph showing the relationship between the emission angle and intensity of the deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting element 300 and the semiconductor light emitting element 300A when the diameter D3 is 333 μm.

[0083] Fig. 35D is a graph showing the relationship between the emission angle and intensity of the deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting element 300 and the semiconductor light emitting element 300A when the diameter D3 is 500 μm. Fig. 35E is a graph showing the relationship between the emission angle and intensity of the deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting element 300 and the semiconductor light emitting element 300A when the diameter D3 is 1000 μm. Fig. 35F is a graph showing the relationship between the emission angle and intensity of the deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting element 300 and the semiconductor light emitting element 300A when the diameter D3 is 2000 μm. 35A to 35F, in the semiconductor light-emitting element 300, the diameter D1 is 100 μm, a single crystal aluminum nitride substrate having a thickness T of 100 μm is used as the substrate 10, λ is 265 nm, the height H is 103 nm, the taper angle is 82°, and the diameter of the first region 10ba at the innermost periphery of the Fresnel zone plate structure 11 is 10.3 μm (0.1 times the diameter D1).

[0084] As shown in FIG. 35A to FIG. 35F, in the semiconductor light emitting device 300, as the emission angle of the deep ultraviolet light extracted from the second main surface 10b deviates from 0°, the intensity of the deep ultraviolet light drops sharply. When the diameter D3 is 500 μm or more (the diameter D3 is 5 times the diameter D1 or more), as the emission angle of the deep ultraviolet light extracted from the second main surface 10b deviates from 0°, the intensity of the deep ultraviolet light drops particularly sharply. On the other hand, in the semiconductor light emitting device 300A, as the emission angle of the deep ultraviolet light extracted from the second main surface 10b deviates from 0°, the intensity of the deep ultraviolet light does not drop sharply. In this way, according to the semiconductor light emitting device 300, the Fresnel zone plate structure 11 formed by the multiple annular protrusions 10d functions as a collimating lens, and it is possible to increase the directivity of the deep ultraviolet light extracted from the second main surface 10b. That is, according to the semiconductor light emitting device 300, it is possible to control the light distribution characteristics of the deep ultraviolet light extracted from the second main surface 10b without using an optical lens (optics-free).

[0085] Fig. 36 is a graph showing the relationship between diameter D3 and enhancement in semiconductor light emitting device 300. In Fig. 36, diameter D1 is set to 100 μm, current is set to 5 mA, and a single crystal aluminum nitride substrate with thickness T of 100 μm is used as substrate 10. As shown in Fig. 36, in semiconductor light emitting device 300, as diameter D3 increases, the extraction efficiency (enhancement) of deep ultraviolet light increases. More specifically, when diameter D3 is 500 μm or more (diameter D3 is 5 times diameter D1), the extraction efficiency of deep ultraviolet light is particularly improved.

[0086] Fig. 37A is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting device 300 when the constituent material of the substrate 10 is sapphire. Fig. 37B is a graph showing the relationship between the emission angle and intensity of deep ultraviolet light extracted from the second main surface 10b of the semiconductor light emitting device 300 when the constituent material of the substrate 10 is aluminum nitride. In Fig. 37A, the thickness T is 330 μm and the diameter D3 is 2500 μm. In Fig. 37B, the thickness T is 392 μm and the diameter D3 is 2500 μm.

[0087] When the constituent material of the substrate 10 is sapphire, the refractive index difference between the semiconductor layer 20 and the substrate 10 is larger than when the constituent material of the substrate 10 is aluminum nitride. Therefore, as shown in FIG. 37A and FIG. 37B, it has been newly found that when the constituent material of the substrate 10 is sapphire, the ghost peak (Airy disk) intensity caused by scattering and diffraction between the substrate 10 and the semiconductor layer 20 is stronger than when the constituent material of the substrate 10 is aluminum nitride, and the directivity of the deep ultraviolet light extracted from the second main surface 10b is reduced. Therefore, in the semiconductor light emitting device 300, by using aluminum nitride as the constituent material of the substrate 10 based on this knowledge, it is possible to further increase the directivity of the deep ultraviolet light extracted from the second main surface 10b.

[0088] Fig. 38A is a graph showing the relationship between current and external quantum efficiency in semiconductor light emitting element 300 and semiconductor light emitting element 300A. Fig. 38B is a graph showing the relationship between current and optical output in semiconductor light emitting element 300 and semiconductor light emitting element 300A. In Fig. 38A and Fig. 38B, diameter D1 is 100 μm, thickness T is 100 μm, pitch between two adjacent mesa structures 24 is 210 μm, λ is 267 nm, and chip size of the semiconductor light emitting element is 2 mm × 2 mm.

[0089] As shown in FIG. 38A and FIG. 38B, when the number of mesa structures 24 is plural, the semiconductor light emitting device 300 has a higher extraction efficiency (external quantum efficiency, optical output) of deep ultraviolet light from the second main surface 10b than the semiconductor light emitting device 300A. More specifically, the external quantum efficiency of the semiconductor light emitting device 300 when a current of 20 mA flows is 1.53 times that of the semiconductor light emitting device 300A, and the external quantum efficiency of the semiconductor light emitting device 300 when a current of 20 mA flows is 1.53 times that of the semiconductor light emitting device 300A. In addition, the optical output of the semiconductor light emitting device 300 when a current of 100 mA flows is 1.47 times that of the semiconductor light emitting device 300A. In this way, the semiconductor light emitting device 300 has a plurality of mesa structures 24, a plurality of first regions 10ba, and a plurality of Fresnel zone plate structures 11, and thus it is possible to increase the extraction efficiency of deep ultraviolet light from the second main surface 10b.

[0090] (Fourth embodiment) A light-emitting module (light-emitting module 400) according to a fourth embodiment will be described.

[0091] <Configuration of Light Emitting Module 400> The configuration of the light emitting module 400 will be described below.

[0092] Fig. 39 is a cross-sectional view of a light-emitting module 400. As shown in Fig. 39, the light-emitting module 400 has a base 70, a submount 71, an insulating layer 72, wiring 73 and wiring 74, connection pads 75 and connection pads 76, bonding wires 77 and bonding wires 78, connection materials 79 and connection materials 80, a transparent member 81, and a liquid 82.

[0093] The base 70 is preferably made of a material having high thermal conductivity, such as a metal material, a resin material, or a ceramic material. The base 70 is preferably made of a material having high thermal conductivity. In this case, the base 70 functions as a heat sink. The submount 71 is disposed on the base 70. The submount 71 is preferably made of a material having high thermal conductivity, such as aluminum nitride, silicon, silicon carbide (SiC), diamond, or the like.

[0094] The insulating layer 72 is disposed on the base 70 so as to surround the outer periphery of the submount 71. The wiring 73 and the wiring 74 are, for example, embedded in the insulating layer 72. The wiring 73 has a pad 73a at one end and is supplied with power from the outside at the other end. The wiring 74 has a pad 74a at one end and is supplied with power from the outside at the other end. The pads 73a and 74a are exposed from the insulating layer 72.

[0095] The connection pad 75 and the connection pad 76 are disposed on the submount 71. The bonding wire 77 is connected to the pad 73a at one end and to the connection pad 75 at the other end. The bonding wire 78 is connected to the pad 74a at one end and to the connection pad 76 at the other end. The connection pad 75 is connected to the pad electrode 33 by a connection material 79. The connection pad 76 is connected to the pad electrode 34 by a connection material 80. The connection material 79 and the connection material 80 are made of a material such as a gold-tin alloy. In this way, the pad electrode 33 is electrically connected to the wiring 73 via the connection material 79 and the bonding wire 77, and the pad electrode 34 is electrically connected to the wiring 74 via the connection material 80 and the bonding wire 78. Therefore, deep ultraviolet light is generated from the active layer 22 based on the current applied between the other end of the wiring 73 and the other end of the wiring 74.

[0096] The transparent member 81 is, for example, hemispherical in shape with a diameter increasing from one end to the other end and opening at the other end. The other end of the transparent member 81 is connected onto the insulating layer 72 by, for example, an adhesive. The transparent member 81 is transparent to the deep ultraviolet light generated from the active layer 22. The transparent member 81 has, for example, a transmittance of 60% or more to the deep ultraviolet light generated from the active layer 22. The constituent material of the transparent member 81 is, for example, an inorganic material or a resin material. Specific examples of inorganic materials include synthetic quartz, quartz glass, alkali-free glass, sapphire, fluorite (CaF), and the like. Specific examples of resin materials include silicone resins without aromatic rings, amorphous fluorine-containing resins, polyimide, epoxy resins, and the like. The resin material may contain an inorganic material.

[0097] The semiconductor light emitting element 100 is disposed inside the transparent member 81. Although not shown, the semiconductor light emitting element 200 or the semiconductor light emitting element 300 may be used instead of the semiconductor light emitting element 100. The transparent member 81 is filled with a liquid 82. Therefore, the semiconductor light emitting element 100 is sealed by the liquid 82. The liquid 82 is transparent to the deep ultraviolet light generated from the active layer 22. The liquid 82 has a transmittance of, for example, 60 percent or more to the deep ultraviolet light generated from the active layer 22. The liquid 82 is, for example, pure water, a liquid organic compound, a salt solution, a particle dispersion solution, or the like.

[0098] <Modification> FIG. 40 is a cross-sectional view of a light emitting module 400 according to a modified example. As shown in FIG. 40, the light emitting module 400 may have a through hole 83 and a through hole 84 formed therein. The through hole 83 and the through hole 84 penetrate the base 70 and the insulating layer 72. The light emitting module 400 may further have a pipe 85, a pipe 86, and a pump 87. The pipe 85 is connected to the through hole 83 at one end. The pipe 86 is connected to the through hole 84 at one end. The other end of the pipe 85 and the other end of the pipe 86 are connected to the pump 87. The pump 87 circulates the liquid 82 inside the transparent member 81 through the pipe 85 and the pipe 86. This promotes cooling of the semiconductor light emitting element 100 by the liquid 82.

[0099] Although the embodiment of the present disclosure has been described above, the above-mentioned embodiment can be modified in various ways. The scope of the present invention is not limited to the above-mentioned embodiment. The scope of the present invention is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0100] 100, 100A, 100B, 200, 200A, 200B, 200C, 300, 300A, semiconductor light emitting element, 10 substrate, 10a first main surface, 10b second main surface, 10ba first region, 10bb second region, 10c uneven structure, 10d ring-shaped protrusion, 11 Fresnel zone plate structure, 20 semiconductor layer, 21 n-type semiconductor layer, 22 active layer, 23 p-type semiconductor layer, 23a electron block layer, 23b cladding layer, 23c contact layer, 24 mesa structure, 24a straight portion, 31 n-electrode, 32 p-electrode, 33 pad electrode, 34 pad electrode, 40 anti-reflection film, 50 first layer, 50a opening, 51 second layer, 51a opening, 52 third layer, 52a recess, 52b opening, 60 Pillar structure, 70 base, 71 submount, 72 insulating layer, 73 wiring, 73a pad, 74 wiring, 74a pad, 75, 76 connection pad, 77, 78 bonding wire, 79, 80 connection material, 81 transparent member, 82 liquid, 83, 84 through hole, 85, 86 piping, 87 pump, 400 light emitting module, T thickness, W1, W2 width, r k Radius, D1, D2, D3 diameter, H height, DR1 first direction, DR2 second direction, S1 preparation process, S2 semiconductor layer formation process, S3 mesa structure formation process, S4 first electrode formation process, S5 second electrode formation process, S6 substrate backside processing process, S7 mask formation process, S8 columnar structure formation process, S9 uneven structure formation process, S10 singulation process.

Claims

1. A substrate; A semiconductor layer; The substrate has a first main surface and a second main surface opposite to the first main surface, the semiconductor layer includes an n-type semiconductor layer disposed on the first principal surface, an active layer disposed on the n-type semiconductor layer and generating deep ultraviolet light, and a p-type semiconductor layer disposed on the active layer; the semiconductor layer has a mesa structure, the second main surface has a first region facing the mesa structure and a second region surrounding the first region; The first region is configured with a flat surface, The second region has a concave-convex structure formed therein, A semiconductor light emitting device, wherein, in a plan view, a width of the first region is 0.1 to 3.0 times a width of the mesa structure.

2. The semiconductor light-emitting element according to claim 1 , wherein the uneven structure is formed in a lattice shape with a period of 1000 nm or less in a plan view.

3. The semiconductor light emitting device according to claim 1 , wherein the mesa structure has a straight portion extending along a first direction in a plan view.

4. 4. The semiconductor light-emitting element according to claim 3, wherein, in a cross-sectional view perpendicular to the first direction, a width in a second direction perpendicular to the first direction of a portion of the first region facing the straight portion is 0.4 to 1.8 times the width of the straight portion in the second direction.

5. 4. The semiconductor light-emitting element according to claim 3, wherein, in a planar view, a distance between a center of the mesa structure in a second direction perpendicular to the first direction and a center of a portion of the first region facing the straight portion in the second direction is 0.05 times or less the width of the mesa structure in the second direction.

6. The semiconductor light emitting device according to claim 1 , wherein the mesa structure and the first region are circular in plan view.

7. The semiconductor light emitting device according to claim 6 , wherein a diameter of the first region in a plan view is 0.5 to 3.0 times a diameter of the mesa structure in a plan view.

8. The semiconductor light emitting element according to claim 6 , wherein in a plan view, a distance between a center of the mesa structure and a center of the first region is equal to or smaller than 0.05 times a diameter of the mesa structure.

9. The semiconductor light emitting device according to claim 1 , further comprising an anti-reflection film disposed on the first region.

10. 2. The semiconductor light-emitting device according to claim 1, wherein the material of the substrate is single crystal aluminum nitride.

11. the mesa structure is circular in plan view; The semiconductor light-emitting element according to claim 1 , wherein the uneven structure is a plurality of annular protrusions arranged concentrically at intervals in a plan view so as to form a Fresnel zone plate structure.

12. The semiconductor light-emitting device according to claim 11, wherein the material of the substrate is single crystal aluminum nitride.

13. The semiconductor light emitting device according to claim 11 , wherein the number of the mesa structures, the number of the first regions, and the number of the Fresnel zone plate structures are plural.

14. The semiconductor light emitting element according to claim 11 , wherein in a plan view, the distance between a center of the mesa structure and a center of the first region is equal to or less than 0.05 times a diameter of the mesa structure.

15. The semiconductor light emitting device according to any one of claims 1 to 14, A transparent member; a liquid; the semiconductor light emitting element is disposed inside the transparent member, the liquid is filled inside the transparent member so as to seal the semiconductor light emitting element, A light-emitting module, wherein the transparent member and the liquid are transparent to the deep ultraviolet light.

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