Photoelectric conversion device and imaging system

Abstract

To provide a photoelectric conversion device that can achieve power saving and increase in correction accuracy.SOLUTION: A photoelectric conversion device has: a pixel array unit that has a plurality of pixels; a plurality of column circuits that is provided respectively in correspondence with a plurality of columns of the pixel array unit, and receives input of respective pixel signals output from the pixels on the corresponding columns; and a plurality of signal lines that supplies signals to the plurality of column circuits. The pixel array unit has a first area in which the pixels having the photoelectric conversion units are arranged and on which light is incident, and a second area in which pixels not having the photoelectric conversion units are arranged and is shielded from light, and the first area and the second area are defined by the columns. The plurality of signal lines has a first signal line that is connected to the column circuit corresponding to the column in the first area and not connected to the column circuit corresponding to the column in the second area, and a second signal line that is connected to the column circuit corresponding to the column in the second area and not connected to the column circuit corresponding to the column in the first area.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and an imaging system. [Background technology]

[0002] In a photoelectric conversion device such as a CMOS image sensor, in order to obtain a signal for correcting a noise component caused by a dark current component of the pixel, a power supply fluctuation, etc., a light-shielded pixel (light-shielded pixel) may be provided in addition to a pixel that outputs a signal according to the amount of incident light. Patent Document 1 describes an imaging device having a pixel array section including a region where pixels having a photoelectric conversion section are arranged and where light is incident, a light-shielded region where pixels having a photoelectric conversion section are arranged, and a light-shielded region where pixels without a photoelectric conversion section are arranged. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-017916 A Summary of the Invention [Problem to be solved by the invention]

[0004] The imaging device described in Patent Document 1 can reduce streaky unevenness caused by shading due to dark current components of pixels and their in-plane distribution, power supply fluctuations, etc. However, the technology described in Patent Document 1 may not necessarily be desirable from the viewpoints of power saving and high-precision correction.

[0005] An object of the present invention is to provide a technique for achieving power saving and high-precision correction in a photoelectric conversion device and an imaging system having a function of correcting noise components using signals from light-shielded pixels. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device having a pixel array section having a plurality of pixels arranged in a plurality of columns, a plurality of column circuits corresponding to each of the plurality of columns, each of which receives a pixel signal output from the pixel of the corresponding column, and a plurality of signal lines supplying signals to the plurality of column circuits, wherein the pixel array section has a first region in which pixels having a photoelectric conversion section are arranged and into which light is incident, and a second region in which pixels not having a photoelectric conversion section are arranged and which is light-shielded, the first region and the second region being defined by columns, and the plurality of signal lines including a first signal line connected to each of the column circuits corresponding to the columns of the first region and not connected to the column circuit corresponding to the column of the second region, and a second signal line connected to each of the column circuits corresponding to the columns of the second region and not connected to the column circuit corresponding to the column of the first region.

[0007] According to another disclosure of the present specification, there is provided a photoelectric conversion device comprising: a pixel array section having a plurality of pixels arranged in a plurality of columns; a plurality of column circuits provided corresponding to each of the plurality of columns, each of which receives a pixel signal output from a pixel in a corresponding column; and a plurality of signal lines supplying signals to the plurality of column circuits, wherein the pixel array section has a first region in which pixels having a photoelectric conversion section are arranged and into which light is incident, a second region in which pixels not having a photoelectric conversion section are arranged and which is light-shielded, and a third region in which pixels having a photoelectric conversion section are arranged and which is light-shielded, wherein the first region, the second region, and the third region are defined by columns, and the plurality of signal lines include a first signal line connected to each of the column circuits corresponding to the columns of the third region and not connected to the column circuit corresponding to the column of the second region, and a second signal line connected to each of the column circuits corresponding to the columns of the second region and not connected to the column circuit corresponding to the column of the third region. Effect of the Invention

[0008] According to the present invention, it is possible to realize power saving and high-precision correction in a photoelectric conversion device and an imaging system having a function of correcting noise components using signals from light-shielded pixels. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 2] 1 is a circuit diagram (part 1) showing an example of the configuration of a pixel in a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 3] 2 is a circuit diagram (part 2) showing an example of the configuration of a pixel in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 4] 1 is a circuit diagram (part 1) showing a configuration example of a column circuit in a photoelectric conversion device according to a first embodiment of the present invention. [Diagram 5] 4 is a circuit diagram (part 2) showing a configuration example of a column circuit in the photoelectric conversion device according to the first embodiment of the present invention. FIG. [Figure 6] 1 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Figure 7] FIG. 11 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 8] FIG. 11 is a timing chart showing a method for driving a photoelectric conversion device according to a second embodiment of the present invention. [Figure 9] FIG. 11 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a third embodiment of the present invention. [Figure 10] FIG. 11 is a timing chart showing a method for driving a photoelectric conversion device according to a third embodiment of the present invention. [Figure 11] FIG. 13 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 12] FIG. 13 is a circuit diagram showing an example of the configuration of a switching unit in a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 13] FIG. 11 is a timing chart showing a method for driving a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 14] FIG. 13 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a modified example of the fourth embodiment of the present invention. [Figure 15] FIG. 13 is a circuit diagram showing an example of the configuration of a column circuit in a photoelectric conversion device according to a fifth embodiment of the present invention. [Figure 16] FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to a sixth embodiment of the present invention. [Figure 17] FIG. 13 is a diagram showing an example of the configuration of an imaging system and a moving object according to a seventh embodiment of the present invention. [Figure 18] FIG. 13 is a block diagram showing a schematic configuration of an apparatus according to an eighth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [First embodiment] A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described with reference to Figs. 1 to 6. Fig. 1 is a block diagram showing a schematic configuration of the photoelectric conversion device according to this embodiment. Figs. 2 and 3 are circuit diagrams showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Figs. 4 and 5 are circuit diagrams showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment. Fig. 6 is a schematic diagram showing an example of the configuration of the photoelectric conversion device according to this embodiment.

[0011] 1, the photoelectric conversion device 100 according to this embodiment includes a pixel array unit 10, a vertical scanning circuit 30, readout circuits 40A and 40B, reference signal generation circuits 48A and 48B, and counter circuits 58A and 58B. The photoelectric conversion device 100 further includes horizontal scanning circuits 70A and 70B, output circuits 80A and 80B, and a control circuit 90.

[0012] The pixel array section 10 includes a plurality of pixels 12, 14, and 16 arranged in a matrix across a plurality of rows and a plurality of columns. The pixel array section 10 includes regions 10A, 10B, and 10C defined by columns. Note that the number of rows constituting the pixel array section 10 and the number of columns included in each of the regions 10A, 10B, and 10C are not particularly limited.

[0013] A plurality of pixels 12 are arranged in the region 10A, a plurality of pixels 14 are arranged in the region 10B, and a plurality of pixels 16 are arranged in the region 10C. The pixel 12 includes a photoelectric conversion unit consisting of a photoelectric conversion element such as a photodiode and a readout circuit for reading out a signal from the photoelectric conversion unit, and serves to output a signal according to the amount of incident light. The pixel 14 includes a photoelectric conversion unit and a readout circuit like the pixel 12, but is shielded from light and serves to output a signal according to the dark current of the photoelectric conversion element. The pixel 16 includes a readout circuit similar to the pixels 12 and 14, but does not include a photoelectric conversion unit, is shielded from light, and serves to output a signal including noise caused by the components of the readout circuit. Although the pixels 14 and 16 do not strictly generate signals for forming an image, they include circuit elements common to the pixel 12 and are referred to as "pixels" for convenience in this specification. The specific configurations of the pixels 12, 14, and 16 will be described later.

[0014] In each row of the pixel array section 10, a control line 18 is arranged extending in a first direction (horizontal direction in FIG. 1). Each of the control lines 18 is connected to the pixels 12, 14, 16 aligned in the first direction, respectively, and serves as a signal line common to these pixels 12, 14, 16. The first direction in which the control lines 18 extend may be called the row direction or horizontal direction. The control lines 18 are connected to a vertical scanning circuit 30. Note that the control lines 18 in each row may include multiple signal lines.

[0015] In each column of the pixel array section 10, a vertical output line 20A or a vertical output line 20B is arranged to extend in a second direction (vertical direction in FIG. 1) intersecting the first direction. The vertical output lines 20A and 20B are arranged alternately in each column. For example, the vertical output lines 20A are arranged in odd-numbered columns, and the vertical output lines 20B are arranged in even-numbered columns. Each of the vertical output lines 20A and 20B is connected to the pixels 12, 14, or 16 arranged in the second direction, respectively, and forms a common signal line for these pixels 12, 14, or 16. The second direction in which the vertical output lines 20A and 20B extend may be called the column direction or vertical direction. The vertical output line 20A is connected to a readout circuit 40A. The vertical output line 20B is connected to a readout circuit 40B.

[0016] The vertical scanning circuit 30 is a control circuit having a function of receiving a control signal from the control circuit 90, generating a control signal for driving the pixels 12, 14, and 16, and outputting the control signal to the pixels 12, 14, and 16 via the control line 18. The vertical scanning circuit 30 may include logic circuits such as a shift register and an address decoder. The vertical scanning circuit 30 sequentially outputs control signals to the control lines 18 of each row, and sequentially drives the pixels 12, 14, and 16 of the pixel array section 10 on a row-by-row basis. The signals read out from the pixels 12, 14, and 16 on a row-by-row basis are input to a readout circuit 40A or a readout circuit 40B via a vertical output line 20A or a vertical output line 20B arranged in each column of the pixel array section 10.

[0017] The readout circuit 40A has a number of column circuits 42 corresponding to the number of columns in which the vertical output lines 20A are arranged. In FIG. 1, the column circuits 42 constituting the readout circuit 40A are represented by the symbols 42A, 42B, and 42C, respectively, for the columns in the region 10A, 42B, and 42C, respectively. The column circuits 42A, 42B, and 42C of the readout circuit 40A are connected to the vertical output lines 20A of the corresponding columns. Similarly, the readout circuit 40B has a number of column circuits 42 corresponding to the number of columns in which the vertical output lines 20B are arranged. In FIG. 1, the column circuits 42 constituting the readout circuit 40B are represented by the symbols 42A, 42B, and 42C, respectively, for the columns in the region 10A, 42B, and 42C, respectively. The column circuits 42A, 42B, and 42C of the readout circuit 40B are connected to the vertical output lines 20B of the corresponding columns.

[0018] The column circuit 42A is a processing circuit that performs a predetermined process on pixel signals read from the pixels 12 of the corresponding column. The column circuit 42B is a processing circuit that performs a predetermined process on pixel signals read from the pixels 14 of the corresponding column. The column circuit 42C is a processing circuit that performs a predetermined process on pixel signals read from the pixels 16 of the corresponding column. The processes performed by the column circuits 42A, 42B, and 42C include signal processes such as amplification and analog-digital conversion (AD conversion). The column circuits 42A, 42B, and 42C have a signal holding circuit (memory) for holding the pixel signals after processing. In the following description, when the column circuits 42A, 42B, and 42C are described in common, the distinction between A, B, and C may be omitted and they may be referred to as the column circuit 42.

[0019] The reference signal generating circuit 48A is connected to the read circuit 40A. The reference signal generating circuit 48A has a function of receiving a control signal from the control circuit 90, generating a reference signal to be used in AD conversion, and outputting it to the read circuit 40A. Similarly, the reference signal generating circuit 48B is connected to the read circuit 40B. The reference signal generating circuit 48B has a function of receiving a control signal from the control circuit 90, generating a reference signal to be used in AD conversion, and outputting it to the read circuit 40B.

[0020] The reference signal used for AD conversion may be a signal having a predetermined amplitude according to the range of the pixel signal, and the signal level of which changes over time. The reference signal is not particularly limited, but may be, for example, a ramp signal whose signal level monotonically increases or decreases over time. The change in the signal level does not necessarily have to be continuous, but may be step-like. The change in the signal level does not necessarily have to be linear with respect to time, but may be curved with respect to time (for example, a sine wave or a cosine wave).

[0021] The counter circuit 58A is connected to the read circuit 40A. The counter circuit 58A performs a counting operation in response to a control signal from the control circuit 90, and has a function of outputting a count signal indicating the count value to the read circuit 40A. The counter circuit 58A starts the counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal generating circuit 48A starts to change. Similarly, the counter circuit 58B is connected to the read circuit 40B. The counter circuit 58B performs a counting operation in response to a control signal from the control circuit 90, and has a function of outputting a count signal indicating the count value to the read circuit 40B. The counter circuit 58B starts the counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal generating circuit 48B starts to change.

[0022] The horizontal scanning circuit 70A is a control circuit having a function of receiving a control signal from the control circuit 90, generating a control signal for reading out pixel signals from the column circuits 42A, 42B, and 42C of the readout circuit 40A, and outputting the control signal to the readout circuit 40A. The horizontal scanning circuit 70A sequentially scans the column circuits 42A, 42B, and 42C of the readout circuit 40A, and causes the pixel signals held therein to be output to the output circuit 80A via the horizontal output line 72A. Similarly, the horizontal scanning circuit 70B is a control unit having a function of receiving a control signal from the control circuit 90, generating a control signal for reading out pixel signals from the column circuits 42A, 42B, and 42C of the readout circuit 40B, and outputting the control signal to the readout circuit 40B. The horizontal scanning circuit 70B sequentially scans the column circuits 42A, 42B, and 42C of the readout circuit 40B, and causes the pixel signals held therein to be output to the output circuit 80B via the horizontal output line 72B. The horizontal scanning circuits 70A and 70B may include logic circuits such as a shift register and an address decoder.

[0023] The output circuit 80A is a processing circuit that is composed of a buffer amplifier, a differential amplifier, etc., and performs a predetermined signal processing on pixel signals of a column selected by the horizontal scanning circuit 70A, and outputs the processed pixel data. Similarly, the output circuit 80B is a processing circuit that is composed of a buffer amplifier, a differential amplifier, etc., and performs a predetermined signal processing on pixel signals of a column selected by the horizontal scanning circuit 70B, and outputs the processed pixel data. Examples of the signal processing performed by the output circuits 80A and 80B include correction processing using correlated double sampling (CDS) and amplification processing.

[0024] The control circuit 90 generates control signals for controlling the operation of the vertical scanning circuit 30, the readout circuits 40A and 40B, the reference signal generating circuits 48A and 48B, the counter circuits 58A and 58B, and the horizontal scanning circuits 70A and 70B, and outputs the control signals to each functional block. Note that at least some of the control signals for controlling the operation of the vertical scanning circuit 30, the readout circuits 40A and 40B, the reference signal generating circuits 48A and 48B, the counter circuits 58A and 58B, and the horizontal scanning circuits 70A and 70B may be supplied from outside the photoelectric conversion device 100.

[0025] 1 shows an example in which two readout circuit blocks are provided: a readout circuit block including a readout circuit 40A, a horizontal scanning circuit 70A, an output circuit 80A, etc., and a readout circuit block including a readout circuit 40B, a horizontal scanning circuit 70B, an output circuit 80B, etc. However, the number of readout circuit blocks does not necessarily need to be two, and one readout circuit block may be used.

[0026] Each of the pixels 12 and 14 constituting the pixel array unit 10 may be composed of a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, as shown in Fig. 2. The pixel 14 is similar to the pixel 12 except that it is shielded from light by a light-shielding layer (not shown).

[0027] The photoelectric conversion element PD is, for example, a photodiode, and has an anode connected to a reference voltage node and a cathode connected to a source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to a source of the reset transistor M2 and a gate of the amplification transistor M3. A node FD to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a so-called floating diffusion part. The floating diffusion part includes a capacitance component (floating diffusion capacitance) and has a function as a charge holding part. The floating diffusion capacitance may include a pn junction capacitance, a wiring capacitance, and the like. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M3 is connected to a drain of the selection transistor M4. The source of the selection transistor M4 is connected to the vertical output line 20A (or the vertical output line 20B).

[0028] In the case of the pixel configuration of FIG. 2, the control line 18 of each row includes three signal lines connected to the gate of the transfer transistor M1, the gate of the reset transistor M2, and the gate of the selection transistor M4. A control signal PTX is supplied to the gate of the transfer transistor M1 from the vertical scanning circuit 30. A control signal PRES is supplied to the gate of the reset transistor M2 from the vertical scanning circuit 30. A control signal PSEL is supplied to the gate of the selection transistor M4 from the vertical scanning circuit 30. When each transistor is an N-type MOS transistor, the corresponding transistor is turned on when a high-level control signal is supplied from the vertical scanning circuit 30. Also, the corresponding transistor is turned off when a low-level control signal is supplied from the vertical scanning circuit 30.

[0029] In this embodiment, the description will be made on the assumption that, of the electron-hole pairs generated in the photoelectric conversion element PD by the incidence of light, the electrons are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixels 12 and 14 may be composed of an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is the opposite conductivity type to that described in this embodiment. In addition, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by the opposite names.

[0030] The photoelectric conversion element PD converts incident light into an electric charge according to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the node FD. The electric charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential according to the amount of the electric charge transferred from the photoelectric conversion element PD through charge-voltage conversion by the floating diffusion capacitance.

[0031] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the vertical output line 20A (or the vertical output line 20B). The amplification transistor M3 has a configuration in which a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source (current source 44 described later) not shown via the selection transistor M4, forming an amplification section (source follower circuit) with the gate as an input node. As a result, the amplification transistor M3 outputs a signal based on the voltage of the node FD to the vertical output line 20A (or the vertical output line 20B) via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are an output section that outputs a pixel signal according to the amount of charge held in the node FD.

[0032] The reset transistor M2 has a function of controlling the supply of a voltage (voltage VDD) to the FD node for resetting the node FD as a charge holding unit. The reset transistor M2 resets the node FD to a voltage according to the voltage VDD by being turned on.

[0033] As described above, pixel 14 is a light-shielded pixel in which the photoelectric conversion element PD is shielded from light. Although pixel 14 is light-shielded, since pixel 14 has the photoelectric conversion element PD, it is possible to obtain the dark current component of the photoelectric conversion element PD from the output signal of pixel 14. Therefore, by correcting the output signal of pixel 12 using the output signal of pixel 14, it is possible to remove the dark current component from the output signal of pixel 12.

[0034] Each of the pixels 16 constituting the pixel array unit 10 may be composed of a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, as shown in FIG. 3. The connections between these components in the pixel 16 are similar to those in the pixels 12 and 14. The source of the transfer transistor M1 may be configured to be floating or connectable to a predetermined voltage node. The pixel 16 differs from the pixels 12 and 14 in that it does not have a photoelectric conversion element PD. The pixel 16 also differs from the pixel 12 and is similar to the pixel 14 in that the pixel 16 is shielded from light by a light-shielding layer (not shown).

[0035] Since the pixel 16 does not have a photoelectric conversion element PD, it is not possible to obtain a dark current component of the photoelectric conversion element PD from the pixel 16. However, since the pixel 16 does not have a photoelectric conversion element PD, there is an advantage that the pixel 16 is not affected by pixels (white spot pixels) that have a particularly large dark current component, and a correction signal for noise components other than dark current can be obtained with high accuracy. For example, the power supply voltage (voltage VDD) supplied to the drains of the reset transistor M2 and the amplification transistor M3 may contain power supply noise caused by the elements that generate the power supply voltage. If this power supply noise is coupled to the node FD via a parasitic capacitance (for example, the gate-drain capacitance of the amplification transistor M3), noise superimposed in the form of horizontal stripes may occur in the acquired image. By detecting this horizontal stripe-like noise component with the pixel 16 and correcting the output signal of the pixel 12 using the output signal of the pixel 16, it is possible to reduce the horizontal stripe-like noise.

[0036] Each of the column circuits 42A, 42B, 42C constituting the readout circuit 40A may be composed of a current source 44, a comparison circuit 54, and memories 62W, 62R, as shown in Fig. 4, for example. The comparison circuit 54 has two input nodes (a non-inverting input node (+) and an inverting input node (-)) to which two signals to be compared are input, and one output node to which a signal indicating the comparison result is output, and may be composed of, for example, a differential amplifier circuit. The memory 62W has two input nodes and one output node. The memory 62R has two input nodes and one output node.

[0037] The vertical output line 20A is connected to the current source 44 of the column circuit 42 of the corresponding column and one input node (inverting input node) of the comparison circuit 54. The current source 44 serves as a load current source for the amplification transistors M3 of the pixels 12, 14, and 16. A signal VOUT is input to the one input node of the comparison circuit 54 from the vertical output line 20A. The other input node (non-inverting input node) of the comparison circuit 54 is connected to a reference signal line 50. A reference signal VRAMP is input to the other input node of the comparison circuit 54 from the reference signal generation circuit 48A via the reference signal line 50.

[0038] One input node of the memory 62W is connected to the output node of the comparison circuit 54. The other input node of the memory 62W is connected to the count signal line 60. The count signal COUNT is input to the other input node of the memory 62W from the counter circuit 58A via the count signal line 60. One input node of the memory 62R is connected to the output node of the memory 62W. The other input node of the memory 62R is connected to the horizontal scanning circuit 70A. The output node of the memory 62R is connected to the horizontal output line 72A.

[0039] The comparison circuit 54 compares the level of the signal VOUT supplied from the vertical output line 20A with the level of the reference signal VRAMP supplied from the reference signal line 50, and outputs a signal according to the result of the comparison. For example, the comparison circuit 54 outputs a high-level signal when the level of the reference signal VRAMP is lower than the level of the signal VOUT. The comparison circuit 54 outputs a low-level signal when the level of the reference signal VRAMP is higher than the level of the signal VOUT. The relationship between the magnitude of the input signal and the level of the output signal may be reversed.

[0040] The memory 62W holds the count value indicated by the count signal COUNT supplied from the counter circuit 58A at the timing when the level of the output node of the comparison circuit 54 is inverted as digital data of the pixel signal. The memory 62R holds the digital data of the pixel signal transferred from the memory 62W. The digital data held in the memory 62R is transferred to the output circuit 80A via the horizontal output line 72A sequentially for each column in response to a control signal supplied from the horizontal scanning circuit 70A. By providing the memory 62R at the subsequent stage of the memory 62W, it is possible to perform an AD conversion operation in parallel with the transfer operation to the output circuit 80A.

[0041] Instead of providing the counter circuit 58A, the memory 62W of the column circuit 42 may have the function of a counter circuit. In this case, the memory 62W of the column circuit 42 of each column receives a common clock signal output from the control circuit 90 and counts the pulses of the clock signal. The count value at the timing when the level of the output signal of the comparison circuit 54 is inverted becomes digital data held by the memory 62W.

[0042] The column circuits 42A, 42B, 42C of the readout circuit 40B are arranged in columns different from the columns in which the column circuits 42A, 42B, 42C of the readout circuit 40A are arranged, and are otherwise the same as the column circuits 42A, 42B, 42C of the readout circuit 40A, and therefore will not be described again. Hereinafter, the description will focus on the column circuits 42A, 42B, 42C of the readout circuit 40A, but the same is true for the column circuits 42A, 42B, 42C of the readout circuit 40B. In the following description, when the readout circuits 40A, 40B and the reference signal generation circuits 48A, 48B, etc. are described in common, the distinction between A and B may be omitted and they may be referred to as the readout circuit 40, the reference signal generation circuit 48, etc.

[0043] 4, in the photoelectric conversion device according to the present embodiment, the comparison circuit 54 of the column circuit 42A, the comparison circuit 54 of the column circuit 42B, and the comparison circuit 54 of the column circuit 42C are provided with different control lines. That is, a control signal pwr1 is supplied from the control circuit 90 via the control line 52 to the column circuit 42A of each column corresponding to the region 10A. A control signal pwr2 is supplied from the control circuit 90 via the control line 52 to the column circuit 42B of each column corresponding to the region 10B. A control signal pwr3 is supplied from the control circuit 90 via the control line 52 to the column circuit 42C of each column corresponding to the region 10C.

[0044] The control signals pwr1, pwr2, and pwr3 may be, for example, control signals for controlling a switch (not shown) that turns on and off the current path of the comparison circuit 54. For example, when the comparison circuit 54 is configured with a differential amplifier circuit, the control signals pwr1, pwr2, and pwr3 may be control signals for a switch that turns on and off the tail current source, or control signals for controlling the value of a current flowing through the tail current source.

[0045] By configuring the comparison circuits 54 of the column circuits 42A, 42B, and 42C in this way, it is possible to optimize the operation of the readout circuit 40 depending on the situation. For example, when horizontal stripe noise correction using the output signal of the pixel 16 is not performed, the current consumption of the comparison circuits 54 of the column circuits 42A and 42B is not reduced, and the current consumption of the comparison circuit 54 of the column circuit 42C is reduced, thereby making it possible to save power. Furthermore, when emphasis is placed on high image quality, in order to perform correction processing using the output signals of the pixels 14 and 16, it is possible to put the comparison circuits 54 of the column circuits 42B and 42C in an operating state in addition to the comparison circuit 54 of the column circuit 42A. Furthermore, when emphasis is placed on low power consumption, it is possible to keep the current consumption of the comparison circuit 54 of the column circuit 42A as it is, and reduce the current consumption of the comparison circuits 54 of the column circuits 42B and 42C. In addition, when low power consumption is important and the accumulation time is long and the dark current component is large, it is possible to keep the current consumption of the comparison circuit 54 in the column circuit 42A, 42B unchanged while reducing the current consumption of the comparison circuit 54 in the column circuit 42C.

[0046] In the configuration example of Fig. 4, different control lines are provided for the comparison circuits 54 of the column circuits 42A, 42B, 42C, but different control lines may be provided for the comparison circuits 54 of the column circuits 42A, 42B and the comparison circuit 54 of the column circuit 42C, for example, as shown in Fig. 5. For example, a control signal pwr1 is supplied from the control circuit 90 via the control line 52 to the column circuits 42A, 42B of each column corresponding to the regions 10A, 10B. A control signal pwr2 is supplied from the control circuit 90 via the control line 52 to the column circuits 42C of each column corresponding to the region 10C.

[0047] In the case of the configuration example of Fig. 5, the variation of operation is reduced compared to the configuration example of Fig. 4, but power saving is possible by putting the comparison circuit 54 of the column circuit 42C into a low current consumption state. The configuration example of Fig. 5 has the advantage that the number of signal lines supplying control signals to the comparison circuit 54 can be reduced compared to the configuration example of Fig. 4.

[0048] The photoelectric conversion device 100 of this embodiment may be configured so that all of the above-mentioned circuit blocks are arranged on a single substrate, or may be configured as a stacked type in which multiple substrates are stacked together, with separate circuit blocks being created on each substrate.

[0049] 6(a) is a schematic diagram of a case where a pixel substrate 110 on which the pixel array section 10 is arranged is laminated with a circuit substrate 120 on which other circuit blocks are arranged. By arranging the pixel substrate 110 and the circuit substrate 120 on separate substrates, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10.

[0050] 6(b) is a schematic diagram of a case where a pixel substrate 110 on which the pixel array section 10 is arranged is stacked with circuit substrates 120 and 130 on which other circuit blocks are arranged. In this case as well, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10.

[0051] It should be noted that the circuit elements constituting one functional block do not necessarily have to be arranged on the same substrate, and may be arranged on separate substrates.

[0052] As described above, according to this embodiment, in a photoelectric conversion device having a function of correcting noise components using signals from light-shielded pixels, it is possible to achieve power saving and high-precision correction.

[0053] [Second embodiment] A photoelectric conversion device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Figs. 7 and 8. The same components as those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and their description will be omitted or simplified. Fig. 7 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment. Fig. 8 is a timing chart showing a method for driving the photoelectric conversion device according to this embodiment.

[0054] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment except for the configuration of the column circuits 42A, 42B, and 42C. In this embodiment, the differences from the photoelectric conversion device of the first embodiment will be mainly described, and the description of the same parts as those of the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0055] In the photoelectric conversion device according to the present embodiment, the reference signal input to the comparison circuit 54 of the column circuits 42A and 42B is different from the reference signal input to the comparison circuit 54 of the column circuit 42C. That is, the reference signal VRAMPH is input to the comparison circuit 54 of the column circuits 42A and 42B from the reference signal generation circuit 48 via the reference signal line 50H, and the reference signal VRAMPL is input to the comparison circuit 54 of the column circuit 42C from the reference signal generation circuit 48 via the reference signal line 50L. The reference signal VRAMPH and the reference signal VRAMPL have different rates of change in signal level with respect to time. Specifically, the rate of change in signal level with respect to time of the reference signal VRAMPH is greater than that of the reference signal VRAMPL. In other words, the amplitude of the reference signal VRAMPH is greater than that of the reference signal VRAMPL. For example, when the reference signals VRAMPH and VRAMPL are ramp signals, the slope of the reference signal VRAMPH is greater than that of the reference signal VRAMPL. By configuring the photoelectric conversion device in this manner, the output signals of the pixels 16 can be AD converted with high precision, and horizontal stripe noise correction using the output signals of the pixels 16 can be performed with higher precision.

[0056] Next, the operation of the photoelectric conversion device according to this embodiment will be described in more detail with reference to Fig. 8. The timing diagram in Fig. 8 shows waveforms of the control signals PTX and PRES, the reference signals VRAMPH and VRAML, the voltage (voltage VOUTA) of the vertical output line 20A connected to the pixel 12, and the voltage (voltage VOUTC) of the vertical output line 20A connected to the pixel 16.

[0057] First, a description will be given of the AD conversion operation of the signal (voltage VOUTA) output from the pixel 12 to the vertical output line 20A. Note that the AD conversion operation of the signal (voltage VOUTB) output from the pixel 14 to the vertical output line 20A is the same as the AD conversion operation of the signal (voltage VOUTA) output from the pixel 12 to the vertical output line 20A.

[0058] Just before time t0, the control signal PSEL (not shown) of the row to be read is at a high level. This turns on the selection transistors M4 of the pixels 12 in that row, and each of these pixels 12 is in a state in which it can output a pixel signal to the vertical output line 20A of the corresponding column. Also, just before time t0, the control signals PTX and PRES of the row to be read are at a low level, and the reference signal VRAMP is at a predetermined reference voltage.

[0059] During the period from time t0 to time t1, the vertical scanning circuit 30 controls the control signal PRES of the row to be read out to a high level. This turns on the reset transistor M2 of the pixel 12 belonging to that row, and resets the node FD to a voltage corresponding to the voltage VDD. A voltage VOUTA (a pixel signal at the reset level of the pixel 12) corresponding to the reset voltage of the node FD is output to the vertical output line 20A connected to the pixel 12.

[0060] At the next time t2, the reference signal generating circuit 48A starts a slope operation in which the voltage of the reference signal VRAMPH changes over time. The counter circuit 58A starts counting up at the same time as the slope operation starts, and outputs a count signal COUNT indicating the count value to the column circuit 42A of each column via the count signal line 60.

[0061] The comparison circuit 54 of the column circuit 42A compares the level of the voltage VOUTA with the level of the reference signal VRAMPH. The level of the output signal of the comparison circuit 54 is inverted at the timing when the magnitude relationship between the level of the voltage VOUTA and the level of the reference signal VRAMPH changes, for example, at time t3 in FIG.

[0062] The memory 62W of the column circuit 42A holds the count value indicated by the count signal COUNT output from the counter circuit 58A at the timing when the level of the output signal of the comparison circuit 54 is inverted, as digital data of the pixel signal of the reset level of the pixel 12. In this manner, AD conversion is performed on the pixel signal of the reset level of the pixel 12. The digital data held in the memory 62W is transferred to the memory 62R, and then transferred to the output circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0063] At the following time t4, the reference signal generating circuit 48A resets the reference signal VRAMPH to the level of the reference voltage.

[0064] In the subsequent period from time t5 to time t6, the vertical scanning circuit 30 controls the control signal PTX of the row to be read out to a high level. This turns on the transfer transistor M1 of the pixel 12 belonging to that row, and the charge accumulated in the photoelectric conversion element PD during the predetermined exposure period is transferred to the node FD. This causes the voltage of the node FD to decrease according to the amount of charge transferred from the photoelectric conversion element PD, and the voltage VOUTA of the vertical output line 20A also decreases. A voltage VOUTA (a pixel signal at the optical signal level of the pixel 12) according to the voltage of the node FD is output to the vertical output line 20A.

[0065] At the next time t7, the reference signal generating circuit 48A starts a slope operation in which the voltage of the reference signal VRAMPH changes over time.

[0066] At the same time as the start of the counting, the count signal COUNT indicating the count value is output to the column circuit 42A of each column. The comparison circuit 54 of the column circuit 42A performs a comparison operation between the level of the voltage VOUTA and the level of the reference signal VRAMPH. The level of the output signal of the comparison circuit 54 is inverted at a timing when the magnitude relationship between the level of the voltage VOUTA and the level of the reference signal VRAMPH changes, for example, at time t9 in FIG.

[0067] The memory 62W of the column circuit 42A holds the count value indicated by the count signal COUNT output from the counter circuit 58A at the timing when the level of the output signal of the comparison circuit 54 is inverted, as digital data of the pixel signal of the optical signal level of the pixel 12. In this manner, AD conversion is performed on the pixel signal of the optical signal level of the pixel 12. The digital data held in the memory 62W is transferred to the memory 62R, and then transferred to the output circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0068] The digital data of the pixel signal thus obtained is subjected to a correction process by digital CDS (Correlated Double Sampling) in the output circuit 80A at the subsequent stage. In the correction process by digital CDS, the digital data of the pixel signal at the reset level is subtracted from the digital data of the pixel signal at the optical signal level, and noise components superimposed on the pixel signal at the optical signal level are removed.

[0069] Next, the AD conversion operation of the signal (voltage VOUTC) output from the pixel 16 to the vertical output line 20A will be described with respect to the difference from the AD conversion operation of the voltage VOUTA.

[0070] Since the pixel 16 does not have a photoelectric conversion element PD, the signal level of the vertical output line 20A remains almost unchanged even after the control signal PTX becomes high level from time t5 to time t6. Therefore, the slope of the reference signal VRAMPL used for AD conversion of the signal of the vertical output line 20A can be made smaller than the slope of the reference signal VRAMPH, as shown in FIG. 8. This makes it possible to reduce the voltage value per LSB and perform AD conversion with higher accuracy. Therefore, by performing horizontal stripe noise correction using the output signal of the pixel 16 using the configuration of this embodiment, it is possible to perform horizontal stripe noise correction with higher accuracy.

[0071] As described above, according to this embodiment, in a photoelectric conversion device having a function for correcting noise components using signals from light-shielded pixels, it is possible to improve the correction accuracy and obtain a high-quality image.

[0072] [Third embodiment] A photoelectric conversion device and a driving method thereof according to a third embodiment of the present invention will be described with reference to Figs. 9 and 10. Components similar to those of the photoelectric conversion device according to the first or second embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 9 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment. Fig. 10 is a timing chart showing a method of driving the photoelectric conversion device according to this embodiment.

[0073] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first or second embodiment except for the configuration of the column circuits 42A, 42B, and 42C. In this embodiment, the differences from the photoelectric conversion device of the first embodiment will be mainly described, and the description of the same parts as those of the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0074] Each of the column circuits 42A, 42B, 42C of the photoelectric conversion device according to this embodiment further includes capacitances C1, C2, and switches SW1, SW2 in addition to a current source 44, a comparison circuit 54, and memories 62W, 62R, as shown in Fig. 9. The comparison circuit 54 is formed of, for example, a differential amplifier circuit, and has a non-inverting input node (+), an inverting input node (-), a non-inverting output node (+), and an inverting output node (-).

[0075] The vertical output line 20A of each column is connected to the current source 44 of the corresponding column circuit 42 and one electrode of the capacitance C1. The inverting input node of the comparison circuit 54 is connected to the other electrode of the capacitance C1. The signal VOUT is input to the inverting input node of the comparison circuit 54 from the vertical output line 20A via the capacitance C1. The reference signal line 50 is connected to one electrode of the capacitance C2. The non-inverting input node of the comparison circuit 54 is connected to the other electrode of the capacitance C2. The reference signal VRAMP is input to the non-inverting input node of the comparison circuit 54 from the reference signal line 50 via the capacitance C2. A switch SW1 is connected between the inverting input node and the non-inverting output node of the comparison circuit 54. A switch SW2 is connected between the non-inverting input node and the inverting output node of the comparison circuit 54. The non-inverting output node of the comparison circuit 54 is connected to the memory 62W.

[0076] The switches SW1 and SW2 of the column circuits 42A and 42B are controlled by a control signal AZ1 supplied from the control circuit 90 via a clamp control line 56. The switches SW1 and SW2 of the column circuit 42C are controlled by a control signal AZ2 supplied from the control circuit 90 via a clamp control line 56. The switches SW1 and SW2 are switches for controlling a reset operation that resets the threshold voltage of the comparison circuit 54.

[0077] The comparison circuit 54 compares the level of the signal VOUT supplied from the vertical output line 20A via the capacitor C1 with the level of the reference signal VRAMP supplied from the reference signal line 50 via the capacitor C2, and outputs a signal according to the comparison result. For example, the comparison circuit 54 outputs a high-level signal when the level of the reference signal VRAMP is lower than the level of the signal VOUT. Also, the comparison circuit 54 outputs a low-level signal when the level of the reference signal VRAMP is higher than the level of the signal VOUT. Note that the relationship between the magnitude of the input signal and the level of the output signal may be reversed.

[0078] Note that the comparison circuit 54 is not limited to the configuration shown in the figure, as long as it has a node to which a pixel signal is input and a node to which a reference signal is input, and is capable of performing an offset clamp operation that sets an offset based on the voltages of the pixel signal and the reference signal.

[0079] In this way, in the photoelectric conversion device of this embodiment, a common control signal AZ1 is input to the comparison circuits 54 of the column circuits 42A and 42B, while an individual control signal AZ2 is input to the comparison circuit 54 of the column circuit 42C. By configuring the photoelectric conversion device in this way, it is possible to prevent power supply fluctuations caused by the inversion operations of the comparison circuits 54 of the column circuits 42A and 42B from affecting the inversion operation of the comparison circuit 54 of the column circuit 42C and causing a deterioration in the AD conversion accuracy of the column circuit 42C. This allows the output signals of the pixels 16 to be AD converted with high accuracy, and makes it possible to perform horizontal stripe noise correction using the output signals of the pixels 16 with higher accuracy.

[0080] Next, the operation of the photoelectric conversion device according to this embodiment will be described in more detail with reference to Fig. 10. The timing diagram of Fig. 10 shows the waveforms of the control signals PTX and PRES, the reference signal VRAMP, the signals rmp1, rmp2, vouta, and voutc, and the control signals AZ1 and AZ2. Here, the signal rmp1 indicates the voltage of the non-inverting input node of the comparison circuit 54 of the column circuit 42A, and the signal rmp2 indicates the voltage of the non-inverting input node of the comparison circuit 54 of the column circuit 42C. In addition, the signal vouta indicates the voltage of the inverting input node of the comparison circuit 54 of the column circuit 42A, and the signal voutc indicates the voltage of the inverting input node of the comparison circuit 54 of the column circuit 42C.

[0081] First, a description will be given of the AD conversion operation of the signal (voltage VOUTA) output from the pixel 12 to the vertical output line 20A. Note that the AD conversion operation of the signal (voltage VOUTB) output from the pixel 14 to the vertical output line 20A is the same as the AD conversion operation of the signal (voltage VOUTA) output from the pixel 12 to the vertical output line 20A.

[0082] In a period before time t0, the control signal PSEL (not shown) of the row to be read is at a high level. As a result, the selection transistors M4 of the pixels 12 belonging to the row are turned on, and each of these pixels 12 is in a state in which it can output a pixel signal to the vertical output line 20A of the corresponding column. Also, just before time t0, the control signal PTX of the row to be read is at a low level, the control signals PRES, AZ1, and AZ2 of the row to be read are at a high level, and the reference signal VRAMP is at a predetermined first reference level.

[0083] In the period up to time t0, the control signal PRES of the row to be read out is at a high level, which turns on the reset transistor M2 of the pixel 12 in that row, and resets the node FD to a voltage corresponding to the voltage VDD.

[0084] At time t0, the vertical scanning circuit 30 changes the control signal PRES of the row to be read from high to low. This turns off the reset transistor M2 of the pixel 12 in the row, and the reset state of the node FD is released. A voltage VOUTA (a pixel signal of the reset level of the pixel 12) corresponding to the reset voltage of the node FD is output to the vertical output line 20A connected to the pixel 12.

[0085] In addition, in the period until time t0, the control signal AZ1 is at a high level. As a result, the switches SW1 and SW2 of the column circuit 42A are turned on, and the inverting input node and the non-inverting input node of the comparison circuit 54 are reset to the reset level voltage. That is, at the time point of time t0, one electrode of the capacitance C1 is at the reset level voltage of the pixel 12, and the other electrode of the capacitance C1 is at the reset level voltage of the comparison circuit 54. In addition, one electrode of the capacitance C2 is at the first reference level voltage of the reference signal VRAMP, and the other electrode of the capacitance C2 is at the reset level voltage of the comparison circuit 54. The threshold voltage of the comparison circuit 54 is reset to a voltage corresponding to the potential difference between the reset level voltage of the pixel 12 and the first reference level voltage of the reference signal VRAMP.

[0086] The threshold voltage of the comparison circuit 54 is a voltage equivalent to the difference between the signal level of the pixel signal and the signal level of the reference signal when the level of the comparison signal output from the comparison circuit 54 changes. That is, the comparison circuit 54 outputs a comparison signal indicating a different level depending on whether the difference between the signal level of the pixel signal and the signal level of the reference signal is smaller than the threshold voltage or larger than the threshold voltage.

[0087] At the next time t1, the control circuit 90 controls the control signal AZ1 to a low level, which turns off the switches SW1 and SW2 of the column circuit 42A, clamps the reset level of the pixel 12 to the capacitor C1, and clamps the first reference level of the reference signal VRAMP to the capacitor C2.

[0088] At the next time t2, the reference signal generating circuit 48A changes the reference signal VRAMP from the first reference level to a second reference level higher than the first reference level, thereby increasing the level of the signal rmp1 by the voltage difference between the first reference level and the second reference level.

[0089] At the next time t4, the reference signal generating circuit 48A increases the reference signal VRAMP from the base voltage to a predetermined start voltage. Then, at the next time t5, the reference signal generating circuit 48A starts a slope operation in which the voltage of the reference signal VRAMP changes over time. Also, the counter circuit 58A starts counting up at the same time as the slope operation starts, and outputs a count signal COUNT indicating the count value to the column circuit 42A via the count signal line 60.

[0090] The comparison circuit 54 of the column circuit 42A performs a comparison operation between the level of the voltage VOUTA (signal vouta) input via the capacitor C1 and the level of the reference signal VRAMP (signal ramp1) input via the capacitor C2. The level of the output signal of the comparison circuit 54 is inverted at the timing when the magnitude relationship between the levels of the signals rmp1 and vouta changes, for example, at time t7 in FIG.

[0091] The memory 62W of the column circuit 42A holds the count value indicated by the count signal COUNT output from the counter circuit 58A at the timing when the level of the output signal of the comparison circuit 54 is inverted, as digital data of the pixel signal of the reset level of the pixel 12. In this manner, AD conversion is performed on the pixel signal of the reset level of the pixel 12. The digital data held in the memory 62W is transferred to the memory 62R, and then transferred to the output circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0092] At the following time t8, the reference signal generating circuit 48A resets the reference signal VRAMP to the first reference level.

[0093] In the subsequent period from time t9 to time t10, the vertical scanning circuit 30 controls the control signal PTX of the row to be read out to a high level. This turns on the transfer transistor M1 of the pixel 12 belonging to that row, and the charge accumulated in the photoelectric conversion element PD during the predetermined exposure period is transferred to the node FD. This causes the voltage of the node FD to decrease according to the amount of charge transferred from the photoelectric conversion element PD, and the voltage VOUTA of the vertical output line 20A also decreases. A voltage VOUTA (a pixel signal at the optical signal level of the pixel 12) according to the voltage of the node FD is output to the vertical output line 20A.

[0094] At the next time t11, the reference signal generating circuit 48A increases the reference signal VRAMP from the base voltage to a predetermined start voltage. Then, at the next time t12, the reference signal generating circuit 48A starts a slope operation in which the voltage of the reference signal VRAMP changes over time. Also, the counter circuit 58A starts counting up at the same time as the slope operation starts, and outputs a count signal COUNT indicating the count value to the column circuit 42A of each column via the count signal line 60.

[0095] The comparison circuit 54 of the column circuit 42A performs a comparison operation between the level of the voltage VOUTA (signal vouta) input via the capacitor C1 and the level of the reference signal VRAMP (signal rmp1) input via the capacitor C2. The level of the output signal of the comparison circuit 54 is inverted at the timing when the magnitude relationship between the levels of the signals rmp1 and vouta changes, for example, at time t14 in FIG.

[0096] The memory 62W of the column circuit 42A holds the count value indicated by the count signal COUNT output from the counter circuit 58A at the timing when the level of the output signal of the comparison circuit 54 is inverted, as digital data of the pixel signal of the optical signal level of the pixel 12. In this manner, AD conversion is performed on the pixel signal of the optical signal level of the pixel 12. The digital data held in the memory 62W is transferred to the memory 62R, and then transferred to the output circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0097] The digital data of the pixel signal obtained in this manner is subjected to a correction process by digital CDS in the output circuit 80A at the subsequent stage. In the correction process by digital CDS, the digital data of the pixel signal at the reset level is subtracted from the digital data of the pixel signal at the optical signal level, and noise components superimposed on the pixel signal at the optical signal level are removed.

[0098] Next, the AD conversion operation of the signal (voltage VOUTC) output from the pixel 16 to the vertical output line 20A will be described with respect to the difference from the AD conversion operation of the voltage VOUTA.

[0099] In the column circuit 42C, the control signal AZ2 is controlled to a low level at time t3, which is after time t2 when the reference signal VRAMP is set to the second reference level. That is, in the column circuit 42C, at time t3 when the switches SW1 and SW2 are turned off, the reset level of the pixel 16 is clamped in the capacitor C1, and the second reference level of the reference signal VRAMP is clamped in the capacitor C2. Due to this operation, during AD conversion of the pixel signal of the reset level of the pixel 16, the magnitude relationship between the level of the signal rmp2 and the level of the signal voutc is inverted at time t6, which is earlier than time t7. Also, during AD conversion of the pixel signal of the optical signal level of the pixel 16, the magnitude relationship between the level of the signal rmp2 and the level of the signal voutc is inverted at time t13, which is earlier than time t14.

[0100] In this manner, in this embodiment, the clamp control signal (control signal AZ1) supplied to the comparison circuit 54 of the column circuits 42A and 42B and the clamp control signal (control signal AZ2) supplied to the comparison circuit 54 of the column circuit 42C are separate control signals. By appropriately controlling the control signals AZ1 and AZ2, the output signal of the comparison circuit 54 of the column circuit 42C is inverted at an earlier timing than the output signal of the comparison circuit 54 of the column circuit 42A. Therefore, according to this embodiment, it is possible to reduce the influence of power supply fluctuations caused by the inversion operation of the comparison circuit 54 of the column circuits 42A and 42B on the inversion operation of the comparison circuit 54 of the column circuit 42C, and to suppress deterioration of the AD conversion accuracy in the column circuit 42C. This makes it possible to perform AD conversion of the output signal of the pixel 16 with higher accuracy, and to perform horizontal stripe noise correction with higher accuracy.

[0101] As described above, according to this embodiment, in a photoelectric conversion device having a function for correcting noise components using signals from light-shielded pixels, it is possible to improve the correction accuracy and obtain a high-quality image.

[0102] [Fourth embodiment] A photoelectric conversion device according to a fourth embodiment of the present invention and a driving method thereof will be described with reference to Figs. 11 to 14. The same components as those in the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 11 is a circuit diagram showing a configuration example of a column circuit in a photoelectric conversion device according to this embodiment. Fig. 12 is a circuit diagram showing a configuration example of a switching unit in a photoelectric conversion device according to this embodiment. Fig. 13 is a timing chart showing a method for driving the photoelectric conversion device according to this embodiment. Fig. 14 is a circuit diagram showing a configuration example of a column circuit in a photoelectric conversion device according to a modified example of this embodiment.

[0103] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion devices according to the first to third embodiments, except for the configuration of the column circuits 42A, 42B, and 42C. In this embodiment, the differences from the photoelectric conversion device of the second embodiment will be mainly described, and the description of the same parts as those of the photoelectric conversion device of the second embodiment will be omitted as appropriate.

[0104] As shown in FIG. 11, each of the column circuits 42A, 42B, 42C of the photoelectric conversion device according to this embodiment further includes switches SW3, SW4, a switching unit 64, and a judgment result holding unit 66 in addition to a current source 44, a comparison circuit 54, and memories 62W, 62R.

[0105] A reference signal line 50L, to which the reference signal VRAMPL is output from the reference signal generating circuit 48A, is connected to a non-inverting input node of the comparing circuit 54 via a switch SW3. A reference signal line 50H, to which the reference signal VRAMPH is output from the reference signal generating circuit 48A, is connected to a non-inverting input node of the comparing circuit 54 via a switch SW4. The switching unit 64 is connected to a control line 68. The judgment result holding unit 66 is connected to the output node of the comparing circuit 54, the switching unit 64, and the memory 62W.

[0106] The switching unit 64 is controlled by a control signal mux or a control signal mux' output from the control circuit 90 via a control line 68. The switches SW3 of the column circuits 42A, 42B are controlled by a control signal L output from the switching unit 64. The switches SW4 of the column circuits 42A, 42B are controlled by a control signal H output from the switching unit 64. The switch SW3 of the column circuit 42C is controlled by a control signal L' output from the switching unit 64. The switch SW4 of the column circuit 42C is controlled by a control signal H' output from the switching unit 64.

[0107] The switching unit 64 may be configured with a two-input NOR circuit LC1 and a NOT circuit LC2, as shown in FIG. 12, for example. The output node of the NOR circuit LC1 is connected to the input node of the NOT circuit LC2. The control signal mux from the control circuit 90 and the judgment signal jdg from the judgment result holding unit 66 are input to the NOR circuit LC1 of the switching unit 64 of the column circuits 42A and 42B. The output signal of the NOR circuit LC1 is input to the NOT circuit LC2. The output signal of the NOR circuit LC1 is the control signal L, and the output signal of the NOT circuit LC2 is the control signal H. That is, the switching unit 64 of the column circuits 42A and 42B outputs control signals L and H according to the control signal mux and the judgment signal jdg. In addition, the control signal mux' from the control circuit 90 and the judgment signal jdg' from the judgment result holding unit 66 are input to the NOR circuit LC1 of the switching unit 64 of the column circuit 42C. The output signal of the NOR circuit LC1 is input to the NOT circuit LC2. The output signal of the NOR circuit LC1 is the control signal L', and the output signal of the NOT circuit LC2 is the control signal H'. That is, the switching unit 64 of the column circuit 42C outputs the control signals L', H' according to the control signal mux' and the determination signal jdg'.

[0108] Next, the operation of the photoelectric conversion device according to this embodiment will be described in more detail with reference to Fig. 13. The timing diagram of Fig. 13 shows the waveforms of the control signals PTX and PRES, the reference signals VRAMPH and VRAMPL, the control signals mux, mux', L, H, L', and H', the judgment signals jdg and jdg', the signals rmp and rmp', and the voltages VOUTA and VOUTC. Here, the signal rmp indicates a signal input to the non-inverting input node of the comparison circuit 54 of the column circuit 42A, and the signal rmp' indicates a signal input to the non-inverting input node of the comparison circuit 54 of the column circuit 42C. In addition, the voltage VOUTA indicates the voltage of the vertical output line 20A connected to the pixel 12, and the voltage VOUTC indicates the voltage of the vertical output line 20A connected to the pixel 16.

[0109] First, a description will be given of the AD conversion operation of the signal (voltage VOUTA) output from the pixel 12 to the vertical output line 20A. Note that the AD conversion operation of the signal (voltage VOUTB) output from the pixel 14 to the vertical output line 20A is the same as the AD conversion operation of the signal (voltage VOUTA) output from the pixel 12 to the vertical output line 20A.

[0110] Just before time t0, the control signal PSEL (not shown) of the row to be read is at a high level. This turns on the selection transistors M4 of the pixels 12 in that row, and each of these pixels 12 is in a state in which it can output a pixel signal to the vertical output line 20A of the corresponding column. Also, just before time t0, the control signals PTX and PRES of the row to be read are at a low level, and the reference signals VRAMPH and VRAMPL are at a predetermined reference voltage.

[0111] Also, immediately before time t0, the control signal mux and the determination signal jdg are at low level. That is, the switching unit 64 of the column circuit 42A outputs a high level control signal L and a low level control signal H in response to the input of the low level control signal mux and the low level determination signal jdg. The switch SW3 of the column circuit 42A is turned on in response to the high level control signal L, and the switch SW4 of the column circuit 42A is turned off in response to the low level control signal H.

[0112] During the period from time t0 to time t1, the vertical scanning circuit 30 controls the control signal PRES of the row to be read out to a high level. This turns on the reset transistor M2 of the pixel 12 belonging to that row, and resets the node FD to a voltage corresponding to the voltage VDD. A voltage VOUTA (a pixel signal at the reset level of the pixel 12) corresponding to the reset voltage of the node FD is output to the vertical output line 20A connected to the pixel 12.

[0113] At the next time t2, the reference signal generating circuit 48A starts a slope operation in which the voltages of the reference signals VRAMPH and VRAMPL change over time. At this time, since the switch SW3 is on and the switch SW4 is off in the column circuit 42A, the reference signal VRAMPL out of these reference signals is input to the non-inverting input node of the comparison circuit 54 in the column circuit 42A. In FIG. 13, this signal input to the non-inverting input node of the comparison circuit 54 in the column circuit 42A is shown as a signal rmp. In addition, the counter circuit 58A starts counting up at the same time as the slope operation starts, and outputs a count signal COUNT indicating the count value to the column circuit 42A of each column via a count signal line 60.

[0114] The comparison circuit 54 of the column circuit 42A performs a comparison operation between the level of the voltage VOUTA and the level of the signal rmp (reference signal VRAMPL). The level of the output signal of the comparison circuit 54 is inverted, for example, from a high level to a low level at a timing when the magnitude relationship between the level of the voltage VOUTA and the level of the signal rmp changes, for example, at time t3 in FIG.

[0115] The memory 62W of the column circuit 42A holds the count value indicated by the count signal COUNT output from the counter circuit 58A at the timing when the level of the output signal of the comparison circuit 54 is inverted, as digital data of the pixel signal of the reset level of the pixel 12. In this manner, AD conversion is performed on the pixel signal of the reset level of the pixel 12. The digital data held in the memory 62W is transferred to the memory 62R, and then transferred to the output circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0116] At the next time t4, the reference signal generating circuit 48A shifts the reference signals VRAMPH and VRAMPL to a predetermined level that is a criterion for luminance value judgment. That is, when the signal level of the vertical output line 20A falls below the signal level set in the reference signals VRAMPH and VRAMPL, the subject is judged to have low luminance.

[0117] In the subsequent period from time t5 to time t6, the vertical scanning circuit 30 controls the control signal PTX of the row to be read out to a high level. This turns on the transfer transistor M1 of the pixel 12 belonging to that row, and the charge accumulated in the photoelectric conversion element PD during the predetermined exposure period is transferred to the node FD. This causes the voltage of the node FD to decrease according to the amount of charge transferred from the photoelectric conversion element PD, and the voltage VOUTA of the vertical output line 20A also decreases. A voltage VOUTA (a pixel signal at the optical signal level of the pixel 12) according to the voltage of the node FD is output to the vertical output line 20A.

[0118] When the signal level of the vertical output line 20A falls below the level of the signal rmp (reference signal VRAMPL) by transferring the signal charge to the node FD, that is, when the subject is not dark or low luminance, the level of the output signal of the comparison circuit 54 is inverted from low level to high level. The determination result holding unit 66 holds the output signal from the comparison circuit 54, and at the following time t7, reflects the held result in the determination signal jdg. That is, at time t7, the level of the determination signal jdg transitions from low level to high level. The switching unit 64 of the column circuit 42A outputs a low level control signal L and a high level control signal H in response to the input of a low level control signal mux and a high level determination signal jdg. Then, the switch SW3 of the column circuit 42A is turned off in response to the low level control signal L, and the switch SW4 of the column circuit 42A is turned on in response to the high level control signal H. That is, the signal rmp supplied to the non-inverting input node of the comparison circuit 54 is switched from the reference signal VRAMPL to the reference signal VRAMPH.

[0119] In addition, when the relationship between the signal level of the vertical output line 20A and the level of the signal rmp (reference signal VRAMPL) does not change even if the signal charge is transferred to the node FD, that is, when the subject is dark or has low brightness, the level of the output signal of the comparison circuit 54 remains at a low level. The determination result holding unit 66 holds the output signal from the comparison circuit 54, and at the following time t7, reflects the held result in the determination signal jdg. However, since the level of the output signal of the comparison circuit 54 is at a low level, the determination signal jdg remains at a low level. Therefore, the switch SW3 of the column circuit 42A remains on, the switch SW4 of the column circuit 42A remains off, and the signal rmp supplied to the non-inverting input node of the comparison circuit 54 remains at the reference signal VRAMPL. In addition, in FIG. 13, the waveforms of the determination signal jdg, the control signals H and L, and the signal rmp when the subject is dark or has low brightness are shown by dashed lines.

[0120] Also at time t7, the reference signal generating circuit 48A resets the reference signals VRAMPH and VRAMPL to a predetermined reference voltage.

[0121] At the next time t8, the reference signal generating circuit 48A starts a slope operation in which the voltages of the reference signals VRAMPH and VRAMPL change over time. At this time, in the column circuit 42A, the switch SW3 is off and the switch SW4 is on, so that the signal rmp input to the non-inverting input node of the comparison circuit 54 in the column circuit 42A is the reference signal VRAMPH among these reference signals. The counter circuit 58A starts counting up at the same time as the slope operation starts, and outputs a count signal COUNT indicating the count value to the column circuit 42A of each column via the count signal line 60.

[0122] The comparison circuit 54 of the column circuit 42A performs a comparison operation between the level of the voltage VOUTA and the level of the signal rmp (reference signal VRAMPH). The level of the output signal of the comparison circuit 54 is inverted, for example, from a high level to a low level at a timing when the magnitude relationship between the level of the voltage VOUTA and the level of the signal rmp changes, for example, at time t10 in FIG.

[0123] The memory 62W of the column circuit 42A holds the count value indicated by the count signal COUNT output from the counter circuit 58A at the timing when the level of the output signal of the comparison circuit 54 is inverted, as digital data of the pixel signal of the optical signal level of the pixel 12. In this manner, AD conversion is performed on the pixel signal of the optical signal level of the pixel 12. The memory 62W of the column circuit 42A also holds the data (determination signal jdg) held by the determination result holding unit 66 as luminance determination data. The digital data and luminance determination data held in the memory 62W are transferred to the memory 62R and then transferred to the output circuit 80A in response to a control signal from the horizontal scanning circuit 70A.

[0124] The digital data of the pixel signal obtained in this manner is subjected to a correction process by digital CDS in the output circuit 80A at the subsequent stage. In the correction process by digital CDS, the digital data of the pixel signal at the reset level is subtracted from the digital data of the pixel signal at the optical signal level, and noise components superimposed on the pixel signal at the optical signal level are removed.

[0125] In this case, the reference signal VRAMPH used in the AD conversion of the optical signal level has a larger slope than the reference signal VRAMPL used in the AD conversion of the reset level, so the AD conversion result is smaller by the slope ratio. Therefore, in digital CDS processing, a digital gain corresponding to the slope ratio is applied to the digital data of the optical signal level, and then the digital data of the reset level is subtracted. Note that when the subject is dark or has low brightness, the reference signal VRAMPL is also used for the AD conversion of the optical signal level, so digital CDS processing is performed directly on the digital data of the optical signal level without applying digital gain.

[0126] The digital gain processing for the digital data of the optical signal level can be performed based on the luminance judgment data transferred to the output circuit 80A together with the digital data of the pixel signal. That is, when the luminance judgment data has a value (e.g., '1') corresponding to the high level of the judgment signal jdg, the digital gain processing is performed for the digital data of the optical signal level. When the luminance judgment data has a value (e.g., '0') corresponding to the low level of the judgment signal jdg, the digital gain processing is not performed for the digital data of the optical signal level.

[0127] In this way, the photoelectric conversion device according to this embodiment is configured to be able to switch the reference signal used for AD conversion depending on the luminance of the object, whereby when the luminance of the object is low, a reference signal with a small slope can be used to perform high-precision AD conversion, and when the luminance of the object is high, a reference signal with a large slope can be used to perform high-speed AD conversion.

[0128] Next, the AD conversion operation of the signal (voltage VOUTC) output from the pixel 16 to the vertical output line 20A will be described with respect to the difference from the AD conversion operation of the voltage VOUTA.

[0129] In the column circuit 42C, control signals mux', L', H' and a judgment signal jdg' are used instead of the control signals mux, L, H and the judgment signal jdg. Just before time t0, the control signal mux' and the judgment signal jdg' are assumed to be at low level. The switching unit 64 of the column circuit 42C outputs a high level control signal L' and a low level control signal H' in response to the input of a low level control signal mux' and a low level judgment signal jdg'. The switch SW3 of the column circuit 42C is turned on in response to a high level control signal L', and the switch SW4 of the column circuit 42C is turned off in response to a low level control signal H'.

[0130] The operation of the column circuit 42C until time t7 is basically the same as that of the column circuit 42A, except that the control signals mux', L', H' and the judgment signal jdg' are used instead of the control signals mux, L, H and the judgment signal jdg. However, since the pixel 16 is a light-shielded pixel that does not include a photoelectric conversion unit, the level of the voltage VOUTC does not change even if the transfer transistor is turned on during the period from time t5 to time t6, and the output signal of the comparison circuit 54 is also maintained at a low level. Therefore, the switch SW3 of the column circuit 42C is on, the switch SW4 of the column circuit 42C is off, and the signal rmp' supplied to the non-inverting input node of the comparison circuit 54 remains unchanged as the reference signal VRAMPL.

[0131] At the next time t7, the control circuit 90 controls the control signal mux' from low level to high level. As a result, the switching unit 64 of the column circuit 42C always outputs a low level control signal L' and a high level control signal H' regardless of the level of the determination signal jdg'. Then, the switch SW3 of the column circuit 42C is turned on in response to the low level control signal L', and the switch SW4 of the column circuit 42C is turned on in response to the high level control signal H'. In other words, the AD conversion of the pixel signal of the optical signal level in the column circuit 42C is always performed using the reference signal RAMPH. As a result, data for correcting the AD conversion result of the pixel signal of the pixel 12 when the subject is high luminance can be obtained from the column circuit 42C.

[0132] As described above, when the subject has high luminance, the reference signal VRAMPL is used for AD conversion of the pixel signal of the reset level in the column circuit 42A, and the reference signal VRAMPH is used for AD conversion of the pixel signal of the optical signal level in the column circuit 42A. However, the time required for the inversion delay, that is, the time from when the levels of the two input signals to the comparison circuit 54 become equal to when the level of the output signal is inverted, differs between the cases where the reference signal VRAMPL is used and the reference signal VRAMPH is used. In addition, this time difference is not proportional to the ratio of the slope of the reference signal VRAMPL to the slope of the reference signal VRAMPH. Therefore, in the digital CDS process in which the digital data of the optical signal level is subjected to digital gain and then the digital data of the reset level is subtracted, the noise components superimposed on the digital data of the optical signal level cannot be completely removed. As a result, there is a risk that correction residue will be left in the data after the digital CDS process, deteriorating the image quality.

[0133] Therefore, in this embodiment, the AD conversion of the pixel signal of the light signal level in the column circuit 42C is always performed under the same condition as the AD conversion condition used in the column circuit 42A when the subject is high brightness. Then, for the digital data acquired by the column circuit 42C, as with the digital data acquired by the column circuit 42A, a digital CDS process is performed in which the digital data of the light signal level is subjected to a digital gain and then digital data of the reset level is subtracted. This makes it possible to obtain, from the digital data acquired by the column circuit 42C, a noise component equivalent to the correction residue generated after the digital CDS process of the digital data acquired by the column circuit 42A. Therefore, by subtracting the data after the digital CDS process of the data acquired by the column circuit 42C from the data after the digital CDS process of the data acquired by the column circuit 42A, data with reduced correction residue can be obtained.

[0134] 11, the control signal mux of the switching unit 64 of the column circuit 42A and the control signal mux' of the switching unit 64 of the column circuit 42C are provided separately, so that the AD conversion gain in the column circuit 42C and the AD conversion gain in the column circuit 42A are controlled independently. However, the method of controlling the AD conversion gain in the column circuit 42C independently from the AD conversion gain in the column circuit 42A is not limited to this. For example, instead of providing the control line 68, a control line for the switching units 64 of the column circuits 42A and 42B and a control line for the switching unit 64 of the column circuit 42C may be provided separately, and they may be controlled independently.

[0135] 14, for example, buffer circuits 74, 76 may be provided in the column circuits 42A, 42B, 42C, and the reference signals VRAMPL, VRAMPH may be input to the comparison circuit 54 via the buffer circuits 74, 76. By configuring the column circuits 42A, 42B, 42C in this manner, it is possible to suppress fluctuations in the load capacitance of the reference signal lines 50L, 50H depending on the selection state of the reference signals in the column circuits 42A, 42B, 42C, thereby improving image quality.

[0136] As described above, according to this embodiment, in a photoelectric conversion device having a function for correcting noise components using signals from light-shielded pixels, it is possible to improve the correction accuracy and obtain a high-quality image.

[0137] [Fifth embodiment] A photoelectric conversion device and a driving method thereof according to a fifth embodiment of the present invention will be described with reference to Fig. 15. The same components as those in the photoelectric conversion devices according to the first to fourth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 15 is a circuit diagram showing an example of the configuration of a column circuit in the photoelectric conversion device according to this embodiment.

[0138] In the fourth embodiment, a configuration is shown in which an AD conversion gain during AD conversion of a pixel signal of an optical signal level is selected according to the brightness of the object, but a configuration in which the gain of the amplifier circuit is selected according to the brightness of the object may also be used. In this embodiment, a configuration example in which the gain of the amplifier circuit is selected according to the brightness of the object will be described.

[0139] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment except for the configuration of the column circuits 42A, 42B, and 42C. In this embodiment, the differences from the photoelectric conversion device of the first embodiment will be mainly described, and the description of the same parts as those of the photoelectric conversion device of the first embodiment will be omitted as appropriate.

[0140] As shown in FIG. 15, each of the column circuits 42A, 42B, 42C of the photoelectric conversion device according to this embodiment further includes an amplifier circuit including an amplifier 78, capacitances C0 and Cv, and a judgment unit 82, in addition to a current source 44, a comparison circuit 54, and memories 62W and 62R.

[0141] The vertical output line 20A of each column is connected to the current source 44 of the corresponding column circuit 42 and one electrode of the capacitance C0. The other electrode of the capacitance C0 is connected to the input node of the amplifier 78. The output node of the amplifier 78 is connected to the inverting input node of the comparison circuit 54 and the judgment unit 82. A capacitance Cv is connected between the input node and the output node of the amplifier 78. The capacitance Cv is a variable capacitance circuit configured to be able to change the capacitance value according to the signal output from the judgment unit 82. The capacitance Cv can take at least a first capacitance value and a second capacitance value larger than the first capacitance value according to the signal from the judgment unit 82. Since the gain of the amplifier circuit is represented by the ratio (C0 / Cv) between the capacitance value of the capacitance C0 and the capacitance value of the capacitance Cv, it is possible to switch the gain of the amplifier circuit by switching the capacitance value of the capacitance Cv. A control signal gain is input from the control circuit 90 via a control line 84 to the judgment unit 82 of the column circuits 42A and 42B. Moreover, a control signal gain′ is input from the control circuit 90 via a control line 84 to the determination unit 82 of the column circuit 42C.

[0142] The determination unit 82 has a function of controlling the gain of the amplifier circuit according to the signal level of the vertical output line 20A. More specifically, the determination unit 82 determines whether or not the amount of change in the signal level of the vertical output line 20A when the charge held by the photoelectric conversion element PD is transferred to the node FD exceeds a predetermined value. Then, the determination unit 82 outputs a signal for controlling the capacitance value of the capacitance Cv to the capacitance Cv according to the determination result and the control signal gain or the control signal gain'. By separating the control signal gain input to the determination unit 82 of the column circuits 42A and 42B from the control signal gain' input to the determination unit 82 of the column circuit 42C, it becomes possible to set the gain of the amplifier circuit of the column circuits 42A and 42B and the gain of the amplifier circuit of the column circuit 42C separately.

[0143] The gain of the amplifier circuit in the column circuits 42A, 42B, and 42C can be set in the same manner as the AD conversion gain in the fourth embodiment. That is, the gain of the amplifier circuit in the column circuits 42A and 42B during AD conversion of the pixel signal of the optical signal level is appropriately set according to the luminance of the subject. Specifically, when the change in the signal level of the vertical output line 20A is less than a predetermined value, that is, when the subject is dark or has low luminance, the determination unit 82 of the column circuits 42A and 42B sets the capacitance Cv to a first capacitance value and sets the gain of the amplifier circuit to a first gain. Also, when the change in the signal level of the vertical output line 20A is equal to or greater than a predetermined value, that is, when the subject is highly luminance, the determination unit 82 of the column circuits 42A and 42B sets the capacitance Cv to a second capacitance value and sets the gain of the amplifier circuit to a second gain lower than the first gain. On the other hand, the gain of the amplifier circuit in the column circuit 42C during AD conversion of the pixel signal at the optical signal level is set to a second gain by setting the capacitance Cv to a second capacitance value regardless of the luminance of the subject.

[0144] By setting the gain of the amplifier circuit in this way, as in the fourth embodiment, a noise component corresponding to a correction residue generated after digital CDS processing of the digital data acquired by the column circuit 42A can be acquired from the digital data acquired by the column circuit 42C. Therefore, by subtracting the data after digital CDS processing of the data acquired by the column circuit 42C from the data after digital CDS processing of the data acquired by the column circuit 42A, data with a reduced correction residue can be acquired.

[0145] As described above, according to this embodiment, in a photoelectric conversion device having a function for correcting noise components using signals from light-shielded pixels, it is possible to improve the correction accuracy and obtain a high-quality image.

[0146] [Sixth embodiment] An imaging system according to a sixth embodiment of the present invention will be described with reference to Fig. 16. Fig. 16 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0147] The photoelectric conversion device 100 described in the first to fifth embodiments can be applied to various imaging systems. Examples of the applicable imaging systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the imaging system. FIG. 16 illustrates a block diagram of a digital still camera as an example of these.

[0148] 16 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to fifth embodiments, and converts the optical image formed by the lens 202 into image data.

[0149] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output from the imaging device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) in which a photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor substrate different from the semiconductor layer in which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor substrate as the imaging device 201.

[0150] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out on the recording medium 214. The recording medium 214 may be built into the imaging system 200, or may be removable.

[0151] Furthermore, the imaging system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the imaging system 200 only needs to have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0152] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201, and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0153] In this way, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to fifth embodiments is applied.

[0154] [Seventh embodiment] An imaging system and a moving object according to a seventh embodiment of the present invention will be described with reference to Fig. 17. Fig. 17 is a diagram showing the configuration of an imaging system and a moving object according to this embodiment.

[0155] FIG. 17(a) shows an example of an imaging system related to an on-vehicle camera. The imaging system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fifth embodiments. The imaging system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 300. The imaging system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0156] The imaging system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0157] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 17(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). A vehicle information acquisition device 320 sends instructions to the imaging system 300 or imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0158] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the imaging system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to devices that use object recognition widely, such as intelligent transport systems (ITS).

[0159] [Eighth embodiment] An apparatus according to an eighth embodiment of the present invention will be described with reference to Fig. 18. Fig. 18 is a block diagram showing a schematic configuration of the apparatus according to this embodiment.

[0160] FIG. 18 is a schematic diagram showing an apparatus EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 according to any one of the first to fifth embodiments. All or a part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used as, for example, an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0161] The photoelectric conversion device APR may have a structure (a chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected to each other by through-hole vias (TSVs), inter-chip wiring by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0162] The photoelectric conversion device APR may include a package PKG that houses the semiconductor device IC in addition to the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connection members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device IC.

[0163] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes a signal output from the photoelectric conversion device APR, and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL, and is transmitted to the outside by a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and the arithmetic circuit unit provided in the photoelectric conversion device APR.

[0164] The device EQP shown in FIG. 18 may be an electronic device such as an information terminal having a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP may also be a transportation device (moving object) such as a vehicle, a ship, or an aircraft. The device EQP may also be a medical device such as an endoscope or a CT scanner. The device EQP may also be a medical device such as an endoscope or a CT scanner.

[0165] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (operation) by using a photographing function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing for operating the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0166] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser and / or user. Therefore, if the photoelectric conversion device APR is installed in equipment EQP, the value of the equipment EQP can also be increased. Therefore, when manufacturing and selling equipment EQP, deciding to install the photoelectric conversion device APR of this embodiment in the equipment EQP is advantageous in increasing the value of the equipment EQP.

[0167] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0168] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0169] In addition, in the above second to fifth embodiments, the column circuits 42A and 42B are controlled by control signals supplied through the same control line, but as in the first embodiment, the column circuits 42A and 42B may be individually controlled by control signals supplied through separate control lines.

[0170] In addition, in the above first to fifth embodiments, one vertical output line 20 is provided for each column of the pixel array section 10, but the number of vertical output lines 20 provided for each column of the pixel array section 10 is not limited to one, and may be two or more.

[0171] The circuit configurations of the pixels 12, 14, and 16 shown in Figures 2 and 3 are merely examples and can be modified as appropriate. For example, each of the pixels 12 and 14 may have two or more photoelectric conversion elements. In this case, a configuration may be adopted in which a plurality of photoelectric conversion elements share one FD node. Also, a configuration may be adopted in which a plurality of photoelectric conversion elements share one microlens to form a pupil-split pixel capable of detecting a phase difference. Also, the pixels 12, 14, and 16 do not necessarily need to have a selection transistor M4. Also, a configuration may be adopted in which the capacitance value of the node FD is switchable.

[0172] Furthermore, the imaging systems shown in the sixth and seventh embodiments are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 16 and 17.

[0173] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0174] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

[0175] The disclosure of the above embodiment includes the following configurations and methods. (Configuration 1) a pixel array section having a plurality of pixels arranged in a plurality of columns; a plurality of column circuits each provided corresponding to each of the plurality of columns, each of which receives a pixel signal output from a pixel in the corresponding column; a plurality of signal lines for supplying signals to the plurality of column circuits; The pixel array unit includes: a first region in which pixels having photoelectric conversion units are arranged and into which light is incident; a second region in which pixels not having a photoelectric conversion unit are arranged and which is shielded from light; the first region and the second region are defined by columns; The plurality of signal lines include a first signal line connected to each of the column circuits corresponding to the columns in the first region and not connected to the column circuits corresponding to the columns in the second region; a second signal line connected to each of the column circuits corresponding to the columns in the second region and not connected to the column circuits corresponding to the columns in the first region; A photoelectric conversion device comprising: (Configuration 2) The liquid crystal display further includes a third region in which pixels having photoelectric conversion units are arranged and which is shielded from light, The plurality of signal lines further includes a third signal line that is connected to each of the column circuits corresponding to the columns of the third region and is not connected to the column circuits corresponding to the columns of the first region and the column circuits corresponding to the columns of the second region. 2. The photoelectric conversion device according to configuration 1. (Configuration 3) The liquid crystal display further includes a third region in which pixels having photoelectric conversion units are arranged and which is shielded from light, The first signal lines are connected to the column circuits corresponding to the columns in the third region. 2. The photoelectric conversion device according to configuration 1. (Configuration 4) a pixel array section having a plurality of pixels arranged in a plurality of columns; a plurality of column circuits each provided corresponding to each of the plurality of columns, each of which receives a pixel signal output from a pixel in the corresponding column; a plurality of signal lines for supplying signals to the plurality of column circuits; The pixel array unit includes: a first region in which pixels having photoelectric conversion units are arranged and into which light is incident; a second region in which pixels not having a photoelectric conversion unit are arranged and which is shielded from light; a third region in which pixels having photoelectric conversion units are arranged and which is shielded from light; a third region in which pixels not having a photoelectric conversion unit are arranged and which is shielded from light; the first region, the second region, and the third region are defined by columns; The plurality of signal lines include a first signal line connected to each of the column circuits corresponding to the columns in the third region and not connected to the column circuits corresponding to the columns in the second region; a second signal line connected to each of the column circuits corresponding to the columns in the second region and not connected to the column circuits corresponding to the columns in the third region; A photoelectric conversion device comprising: (Configuration 5) each of the plurality of column circuits includes a comparison circuit that compares the pixel signal with a reference signal; Each of the first signal line and the second signal line is a signal line connected to the comparison circuit. 5. The photoelectric conversion device according to any one of configurations 1 to 4. (Configuration 6) The first signal line and the second signal line are signal lines for supplying a control signal for controlling the current consumption of the comparison circuit. 6. The photoelectric conversion device according to configuration 5. (Configuration 7) The first signal line and the second signal line are signal lines that supply a control signal for controlling a reset operation of the comparator circuit. 6. The photoelectric conversion device according to configuration 5. (Configuration 8) the first signal line is a signal line that supplies a first reference signal to the comparison circuit; The second signal line is a signal line that supplies a second reference signal different from the first reference signal to the comparison circuit. 6. The photoelectric conversion device according to configuration 5. (Configuration 9) The amplitude of the first reference signal is different from the amplitude of the second reference signal. 9. The photoelectric conversion device according to configuration 8. (Configuration 10) Each of the plurality of column circuits includes a comparison circuit that compares the pixel signal with a reference signal, and a switching unit that switches the reference signal input to the comparison circuit; The first signal line and the second signal line are signal lines that supply control signals for controlling the switching unit. 5. The photoelectric conversion device according to any one of configurations 1 to 4. (Configuration 11) Each of the plurality of column circuits further includes a buffer circuit connected between the comparison circuit and a signal line to which the reference signal is supplied. 11. The photoelectric conversion device according to configuration 10. (Configuration 12) each of the plurality of column circuits includes an amplifier circuit that amplifies the pixel signal; The first signal line and the second signal line are signal lines that supply a control signal for controlling the gain of the amplifier circuit. 12. The photoelectric conversion device according to any one of configurations 1 to 11. (Method 1) A method for driving a photoelectric conversion device according to configuration 10, comprising the steps of: when performing AD conversion on the pixel signal of a reset level, a control signal for selecting a first reference signal is output via the first signal line to the switching section of the column circuit corresponding to a column of the first region, and a control signal for selecting the first reference signal is output via the second signal line to the switching section of the column circuit corresponding to a column of the second region; When the pixel signal of the optical signal level is AD converted, When the subject has low luminance, a control signal for selecting the first reference signal is output via the first signal line to the switching section of the column circuit corresponding to a column of the first region, and a control signal for selecting a second reference signal having an amplitude larger than that of the first reference signal is output via the second signal line to the switching section of the column circuit corresponding to a column of the second region; When the subject has high luminance, a control signal for selecting the second reference signal is output via the first signal line to the switching section of the column circuit corresponding to the column of the first region, and a control signal for selecting the second reference signal is output via the second signal line to the switching section of the column circuit corresponding to the column of the second region. A method for driving a photoelectric conversion device comprising the steps of: (Configuration 13) A photoelectric conversion device according to any one of structures 1 to 12, a signal processing device that processes a signal output from the photoelectric conversion device; An imaging system comprising: (Configuration 14) A mobile object, A photoelectric conversion device according to any one of structures 1 to 12, a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising: (Configuration 15) A photoelectric conversion device according to any one of structures 1 to 12, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on information obtained by the photoelectric conversion device; A display device that displays information obtained by the photoelectric conversion device; and a storage device for storing information obtained by the photoelectric conversion device; An apparatus comprising: [Explanation of symbols]

[0176] SW1, SW2...Switches 10...Pixel array section 12,14,16…pixels 20A,20B…Vertical output line 42...column circuit 50,50L,50H…Reference signal line 52,68,84…Control lines 54…Comparison circuit 56…Clamp control line 90...Control circuit 100...Photoelectric conversion device

Claims

1. a pixel array unit having a plurality of pixels arranged in a plurality of columns; a plurality of column circuits provided corresponding to the plurality of columns, each of which receives a pixel signal output from a pixel in the corresponding column; a plurality of signal lines for supplying signals to the plurality of column circuits; The pixel array unit a first region in which pixels having photoelectric conversion units are arranged and into which light is incident; a second region in which pixels not having a photoelectric conversion unit are arranged and which is shielded from light, the first region and the second region are defined by columns; The plurality of signal lines are a first signal line connected to each of the column circuits corresponding to the columns in the first region and not connected to the column circuits corresponding to the columns in the second region; a second signal line connected to each of the column circuits corresponding to the columns in the second region and not connected to the column circuits corresponding to the columns in the first region; A photoelectric conversion device characterized by:

2. a third region in which pixels having photoelectric conversion units are arranged and which is shielded from light; The plurality of signal lines further include a third signal line that is connected to each of the column circuits corresponding to the columns of the third region and is not connected to the column circuits corresponding to the columns of the first region and the column circuits corresponding to the columns of the second region.

2. The photoelectric conversion device according to claim 1.

3. a third region in which pixels having photoelectric conversion units are arranged and which is shielded from light; The first signal lines are connected to the column circuits corresponding to the columns in the third region.

2. The photoelectric conversion device according to claim 1.

4. a pixel array unit having a plurality of pixels arranged in a plurality of columns; a plurality of column circuits provided corresponding to the plurality of columns, each of which receives a pixel signal output from a pixel in the corresponding column; a plurality of signal lines for supplying signals to the plurality of column circuits; The pixel array unit a first region in which pixels having photoelectric conversion units are arranged and into which light is incident; a second region in which pixels not having a photoelectric conversion unit are arranged and which is shielded from light; a third region in which pixels having photoelectric conversion units are arranged and which is shielded from light; and the first region, the second region, and the third region are defined by columns; The plurality of signal lines are a first signal line connected to each of the column circuits corresponding to the columns in the third region and not connected to the column circuits corresponding to the columns in the second region; a second signal line connected to each of the column circuits corresponding to the columns in the second region and not connected to the column circuits corresponding to the columns in the third region; A photoelectric conversion device characterized by:

5. each of the plurality of column circuits includes a comparison circuit that compares the pixel signal with a reference signal; Each of the first signal line and the second signal line is a signal line connected to the comparison circuit.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. The first signal line and the second signal line are signal lines that supply control signals that control the current consumption of the comparison circuit.

6. The photoelectric conversion device according to claim 5.

7. The first signal line and the second signal line are signal lines that supply control signals that control the reset operation of the comparator circuit.

6. The photoelectric conversion device according to claim 5.

8. the first signal line is a signal line that supplies a first reference signal to the comparison circuit, The second signal line is a signal line that supplies a second reference signal different from the first reference signal to the comparator circuit.

6. The photoelectric conversion device according to claim 5.

9. The amplitude of the first reference signal is different from the amplitude of the second reference signal.

9. The photoelectric conversion device according to claim 8.

10. each of the plurality of column circuits includes a comparison circuit that compares the pixel signal with a reference signal, and a switching unit that switches the reference signal input to the comparison circuit; The first signal line and the second signal line are signal lines that supply control signals that control the switching unit.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

11. Each of the plurality of column circuits further includes a buffer circuit connected between the comparison circuit and a signal line to which the reference signal is supplied.

11. The photoelectric conversion device according to claim 10.

12. each of the plurality of column circuits includes an amplifier circuit that amplifies the pixel signal; The first signal line and the second signal line are signal lines that supply a control signal that controls the gain of the amplifier circuit.

5. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

13. A method for driving a photoelectric conversion device, comprising: The photoelectric conversion device is a pixel array unit having a plurality of pixels arranged in a plurality of columns; a plurality of column circuits provided corresponding to the plurality of columns, each of which receives a pixel signal output from a pixel in the corresponding column; a plurality of signal lines for supplying signals to the plurality of column circuits; The pixel array unit a first region in which pixels having photoelectric conversion units are arranged and into which light is incident; a second region in which pixels not having a photoelectric conversion unit are arranged and which is shielded from light, the first region and the second region are defined by columns; The plurality of signal lines are a first signal line connected to each of the column circuits corresponding to the columns in the first region and not connected to the column circuits corresponding to the columns in the second region; a second signal line connected to each of the column circuits corresponding to the columns in the second region and not connected to the column circuits corresponding to the columns in the first region; each of the plurality of column circuits includes a comparison circuit that compares the pixel signal with a reference signal, a switching unit that switches the reference signal input to the comparison circuit, and a buffer circuit connected between the comparison circuit and a signal line to which the reference signal is supplied; the first signal line and the second signal line are signal lines that supply control signals for controlling the switching unit, When AD converting the pixel signal of a reset level, a control signal for selecting a first reference signal is output via the first signal line to the switching unit of the column circuit corresponding to the column of the first region, and a control signal for selecting the first reference signal is output via the second signal line to the switching unit of the column circuit corresponding to the column of the second region; When AD converting the pixel signal of the optical signal level, When the subject has low luminance, a control signal for selecting the first reference signal is output via the first signal line to the switching unit of the column circuit corresponding to the column of the first region, and a control signal for selecting a second reference signal having an amplitude larger than that of the first reference signal is output via the second signal line to the switching unit of the column circuit corresponding to the column of the second region; When the subject has high luminance, a control signal for selecting the second reference signal is output via the first signal line to the switching unit of the column circuit corresponding to the column of the first region, and a control signal for selecting the second reference signal is output via the second signal line to the switching unit of the column circuit corresponding to the column of the second region. A method for driving a photoelectric conversion device.

14. The photoelectric conversion device according to any one of claims 1 to 4, a signal processing device that processes a signal output from the photoelectric conversion device; An imaging system comprising:

15. A mobile object, The photoelectric conversion device according to any one of claims 1 to 4, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

16. The photoelectric conversion device according to any one of claims 1 to 4, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

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