Switching element

Abstract

To suppress current concentration in the vicinity of each connection region.SOLUTION: A switching element in which when a semiconductor substrate is viewed from above, a connection region connecting a body region and a deep region form a plurality of columns linearly arranged along a second direction. An intersection between an inter-trench semiconductor layer and a column includes a connection intersection where the connection region is provided and a non-connection intersection where no connection region is provided. The standard number of non-connected intersections are placed in the interval between adjacent connected intersections. The standard number is 3 or 4. When counting Manhattan distances in units of intersections, the Manhattan distance to the connected intersection at each non-connected intersection is 1.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a switching element.

[0002] Patent Document 1 discloses a trench-gate type switching element. In this switching element, multiple p-type deep layers are provided inside an n-type drift layer. In the thickness direction of the semiconductor substrate, each deep layer is disposed below the lower end of the trench. In addition, each deep layer may be disposed in a range including the lower end of the trench in the thickness direction of the semiconductor substrate. In addition, the switching element of Patent Document 1 has multiple p-type connection regions. Each connection region connects each deep layer to a p-type body layer. By providing the deep layers and connection regions in this way, the electric field applied to the gate insulating film covering the lower end of the trench can be suppressed.

[0003] In Patent Document 1, when the semiconductor substrate is viewed from above, the connection regions are distributed and arranged so as to maintain a predetermined interval in the x and y directions. In other words, when the semiconductor substrate is viewed from above, the connection regions are distributed and arranged so that the density of the connection regions is low.

[0004] Inside the switching element, a diode (so-called body diode) is formed by the interface between the p-type body layer and the n-type drift layer. When the voltage applied to the body diode switches from the forward direction to the reverse direction, a recovery current flows through the switching element, causing a recovery surge. If the density of the connection region is low, as in Patent Document 1, the recovery surge can be suppressed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2022-083790 Summary of the Invention [Problem to be solved by the invention]

[0006] During operation of a switching element, a recovery current or an avalanche current may flow from the drift region to each connection region. In the switching element of Patent Document 1, when a recovery current or an avalanche current flows through the drift region, the current tends to concentrate in the vicinity of each connection region. This specification proposes a technology for suppressing the concentration of current in the vicinity of each connection region in a switching element in which multiple connection regions are distributed. [Means for solving the problem]

[0007] The switching element disclosed in this specification has a semiconductor substrate, a gate insulating film, a gate electrode, and a source electrode. A plurality of trenches are provided on the upper surface of the semiconductor substrate. Each of the trenches extends linearly in a first direction on the upper surface of the semiconductor substrate. Each of the trenches is arranged at intervals in a second direction intersecting the first direction on the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of each of the trenches. The gate electrode is arranged in each of the trenches and is insulated from the semiconductor substrate by the gate insulating film. The source electrode is in contact with the upper surface of the semiconductor substrate. The semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched by the plurality of the trenches. Each of the inter-trench semiconductor layers has an n-type source region in contact with the gate insulating film and the source electrode, and a p-type body region in contact with the gate insulating film below the source region. The semiconductor substrate has a drift region, a plurality of deep regions, and a plurality of connection regions. The drift region is an n-type region that is distributed across the lower portions of the plurality of inter-trench semiconductor layers and is in contact with the gate insulating film below the body region in each inter-trench semiconductor layer. The plurality of deep regions are p-type regions that are arranged in a range surrounded by the drift region, spaced apart from the body region and arranged below the body region, and arranged in a range including the lower end of the trench or below the lower end of the trench in the thickness direction of the semiconductor substrate. The plurality of connection regions are p-type regions that connect the body region and the deep region. When the semiconductor substrate is viewed from above, the connection regions are arranged in a plurality of rows in a straight line at intervals along the second direction, and the plurality of rows are arranged at intervals in the first direction. When the semiconductor substrate is viewed from above, the intersections between the plurality of inter-trench semiconductor layers and the plurality of rows have connection intersections where the connection regions are provided and non-connection intersections where the connection regions are not provided. The connecting intersections and the non-connecting intersections are repeatedly arranged in the first direction and the second direction according to a reference pattern.Within a range in which the connection intersections and the non-connection intersections are repeatedly arranged according to the reference pattern, the connection intersections and the non-connection intersections satisfy the following conditions: within each of the inter-trench semiconductor layers, the connection intersections are arranged in the first direction with a reference number of the non-connection intersections arranged in the spaces between adjacent connection intersections, within the row, the connection intersections are arranged in the second direction with the reference number of the non-connection intersections arranged in the spaces between adjacent connection intersections, the reference number is 3 or 4, and when counting Manhattan distances in units of the intersections, the Manhattan distance to the connection intersection at each non-connection intersection is 1.

[0008] In a switching element, if there is a non-connection intersection that is extremely far from the connection intersection, recovery current and avalanche current are unlikely to flow near the non-connection intersection that is extremely far from the connection intersection. In this case, the density of recovery current and avalanche current is high near the connection region. In contrast, in the switching element disclosed in this specification, within a range in which the connection intersections and non-connection intersections are repeatedly arranged according to the reference pattern, the Manhattan distance from each non-connection intersection to the connection intersection is 1. In other words, there is no non-connection intersection that is extremely far from the connection intersection. Therefore, in this switching element, current concentration in the vicinity of each connection region is suppressed. [Brief description of the drawings]

[0009] [Figure 1] 1 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a first embodiment. [Diagram 2] 7 is a cross-sectional view showing a vertical section along the x direction at a position including a deep region of the switching element of the first embodiment (the position of line II-II in FIG. 6). [Diagram 3] 8 is a cross-sectional view showing a vertical section along the x direction at a position (position of line III-III in FIG. 6) not including a deep region of the switching element of the first embodiment. FIG. [Figure 4]7 is a cross-sectional view showing a vertical cross section along the y direction at a position not including a trench of the switching element of Example 1 (the position of line IV-IV in FIG. 6). [Diagram 5] 7 is a cross-sectional view showing a vertical section along the y direction at a position including a trench of the switching element of the first embodiment (the position of line VV in FIG. 6). [Figure 6] FIG. 2 is a plan view showing the arrangement of connection intersections and non-connection intersections of the switching element of the first embodiment. [Figure 7] FIG. 4 is a diagram showing a reference pattern P. [Figure 8] FIG. 2 is a diagram showing a plurality of reference patterns P arranged adjacent to each other. [Figure 9] FIG. 13 is a diagram showing a reference pattern of a comparative example. [Figure 10] FIG. 11 is a perspective view including a vertical cross section along the x and y directions of a switching element of a first modified example. [Figure 11] FIG. 11 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a second embodiment. [Figure 12] FIG. 11 is a plan view showing the arrangement of connection intersections and non-connection intersections of a switching element according to a second embodiment. [Figure 13] FIG. 11 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a third embodiment. [Figure 14] FIG. 11 is a plan view showing the arrangement of connection intersections and non-connection intersections of a switching element according to a third embodiment. [Figure 15] FIG. 11 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a fourth embodiment. [Figure 16] FIG. 11 is a plan view showing the arrangement of connection intersections and non-connection intersections of a switching element according to a fourth embodiment. [Figure 17] FIG. 13 is a perspective view including a vertical cross section along the x and y directions of a switching element of a second modified example. [Figure 18] FIG. 13 shows a reference pattern Q when the reference number is 4. [Figure 19] FIG. 1 shows a plurality of reference patterns Q arranged adjacent to each other. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In one example switching element disclosed in this specification, multiple deep regions may extend linearly along the second direction and be spaced apart in the first direction so that each deep region extends along a corresponding column when the semiconductor substrate is viewed from above.

[0011] In the switching element disclosed in the present specification as an example, each of the connection regions may be in contact with the gate insulating film at side surfaces of the trench located on both sides thereof.

[0012] In this configuration, the inversion layer formed in the body layer does not function as a channel at the intersection where each connection region exists. According to the configuration disclosed in this specification, since each connection region can be distributed, intersections that do not function as channels can be distributed. Therefore, the main current that flows when the switching element is on can be distributed within the semiconductor substrate.

[0013] In the switching element disclosed in the present specification as an example, a p-type contact region that connects the body region and the source electrode may be provided on an upper portion of each of the connection regions. EXAMPLES

[0014] The switching element 10 of the first embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si and GaN. In the following, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z-direction. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in the x-direction on the upper surface 12a. The trenches 14 are arranged at intervals in the y-direction on the upper surface 12a. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is arranged in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. An interlayer insulating film 20 is arranged in each trench 14. Each interlayer insulating film 20 covers the upper surface of the gate electrode 18.

[0015] As shown in Figures 2 to 5, a source electrode 22 is provided on the upper part of the semiconductor substrate 12. Note that the source electrode 22 is not shown in Figure 1. The source electrode 22 covers the upper surface of the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0016] Fig. 6 shows the upper surface 12a of the semiconductor substrate 12. As described above, a plurality of trenches 14 extending linearly in the x direction are arranged at intervals in the y direction on the upper surface 12a. The inter-trench semiconductor layer 30 shown in Fig. 6 shows a semiconductor layer sandwiched between two trenches 14 (i.e., a semiconductor layer arranged between two trenches 14). Each inter-trench semiconductor layer 30 extends linearly in the x direction on the upper surface 12a. Each inter-trench semiconductor layer 30 is arranged at intervals in the y direction on the upper surface 12a.

[0017] As shown in FIG. 1, the semiconductor substrate 12 includes a source region 40, a body region 42, a drift region 44, and a drain region 46.

[0018] The source region 40 is an n-type region having a high n-type impurity concentration. The source region 40 is disposed in the inter-trench semiconductor layer 30. As shown in Figures 2 and 3, the source region 40 contacts the source electrode 22 in the inter-trench semiconductor layer 30. The source region 40 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0019] The body region 42 is a p-type region having a low p-type impurity concentration. The body region 42 is disposed in the inter-trench semiconductor layer 30. As shown in FIGS. 2 and 3, the body region 42 is disposed in the inter-trench semiconductor layer 30, and disposed below the source region 40. The body region 42 contacts the gate insulating film 16 below the source region 40. That is, the body region 42 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0020] The drift region 44 is an n-type region having a low n-type impurity concentration. As shown in FIGS. 2 and 3, the drift region 44 is distributed across the lower portions of the inter-trench semiconductor layers 30. As shown in FIG. 3, the upper end portion of the drift region 44 extends into each inter-trench semiconductor layer 30. The drift region 44 contacts the body region 42 from the lower side in each inter-trench semiconductor layer 30. The drift region 44 contacts the gate insulating film below the body region 42. That is, the drift region 44 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of each inter-trench semiconductor layer 30.

[0021] The drain region 46 is an n-type region having a high n-type impurity concentration. The n-type impurity concentration of the drain region 46 is higher than the n-type impurity concentration of the drift region 44. As shown in FIGS. 2 to 5, the drain region 46 contacts the drift region 44 from below. The drain region 46 contacts the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.

[0022] The semiconductor substrate 12 has a plurality of p-type deep regions 50. As shown in FIGS. 2 and 4, each deep region 50 is disposed in a range surrounded by the drift region 44. Each deep region 50 is disposed below the body region 42 with a gap therebetween. The drift region 44 is distributed in the gap between each deep region 50 and the body region 42. The dot-hatched region in FIG. 6 indicates the distribution range of the deep regions 50. As shown in FIG. 6, when the semiconductor substrate 12 is viewed from above, each deep region 50 extends linearly in the y direction. When the semiconductor substrate 12 is viewed from above, each deep region 50 is disposed with a gap therebetween in the x direction. As shown in FIGS. 1, 2, and 5, each deep region 50 is disposed in a range including the lower end of the trench 14 in the z direction. Therefore, each deep region 50 contacts the gate insulating film 16 at the lower end of each trench 14.

[0023] As shown in FIG. 1, the semiconductor substrate 12 has a plurality of connection regions 52 and a plurality of contact regions 54. As shown in FIGS. 1, 2, and 4, the connection region 52 is a p-type region that connects the body region 42 and the deep region 50. The contact region 54 is a p-type region that connects the body region 42 and the source electrode 22. That is, the contact region 54 extends upward from the body region 42 and contacts the source electrode 22 at its upper end. In this embodiment, the contact region 54 and the connection region 52 extend continuously in the z direction. That is, the contact region 54 is disposed above the connection region 52. The semiconductor substrate 12 has a plurality of sets of the contact region 54 and the deep region 50. Each deep region 50 is connected to the source electrode 22 via the connection region 52 and the contact region 54.

[0024] 6, the hatched region indicates a set of connection region 52 and contact region 54. The set of connection region 52 and contact region 54 is partially provided on the upper part of deep region 50. When semiconductor substrate 12 is viewed from above as shown in FIG. 6, the multiple connection regions 52 are arranged to form multiple rows 53 linearly extending in the y direction. Note that in FIG. 6, rows 53 extending in the y direction overlap with deep region 50. The multiple rows 53 are arranged at intervals in the x direction.

[0025] The intersection 60 shown in FIG. 6 is a portion where the inter-trench semiconductor layer 30 and the row 53 intersect when the semiconductor substrate 12 is viewed from above. As described above, each inter-trench semiconductor layer 30 extends linearly in the x direction, and each row 53 extends linearly in the y direction. Therefore, when the semiconductor substrate 12 is viewed from above, a plurality of intersections 60 are arranged in a matrix along the x direction and the y direction. As shown in FIG. 6, a set of a connection region 52 and a contact region 54 is provided in a portion of the plurality of intersections 60. As shown in FIGS. 1, 2, and 6, each connection region 52 contacts the gate insulating film 16 on the side surfaces of the trench 14 located on both sides of the intersection 60. In addition, the contact region 54 contacts the gate insulating film 16 on the side surfaces of the trench 14 located on both sides of the intersection 60. Hereinafter, the intersection 60 where the connection region 52 is provided is referred to as a connection intersection 60a, and the intersection 60 where the connection region 52 is not provided is referred to as a non-connection intersection 60b.

[0026] The reference pattern P in FIG. 6 shows a pattern of the arrangement of the connection intersections 60a and the non-connection intersections 60b. The connection intersections 60a and the non-connection intersections 60b are provided so that the reference pattern P is repeated in the x and y directions. FIG. 7 shows the reference pattern P in a schematic manner. Each cell in FIG. 7 shows an intersection 60. In FIG. 7, the cells hatched with diagonal lines are the connection intersections 60a, and the blank cells are the non-connection intersections 60b. FIG. 8 shows a plurality of reference patterns P arranged in a matrix in the x and y directions. In FIG. 8, the central reference pattern P is indicated by reference symbol P1, and the surrounding reference patterns P are indicated by reference symbols P2 to P9. The reference pattern P is set to satisfy the following conditions 1 to 4 within a range in which the connection intersections 60a and the non-connection intersections 60b are repeatedly arranged according to the reference pattern P.

[0027] (Condition 1) In each inter-trench semiconductor layer 30, the connection intersections 60a are arranged at regular intervals in the x direction, and three non-connection intersections 60b are arranged within each interval. That is, as shown in Figures 7 and 8, in each inter-trench semiconductor layer 30, the connection intersections 60a are arranged at intervals in the x direction such that one connection intersection 60a appears for three non-connection intersections 60b.

[0028] (Condition 2) In each row 53, the connection intersections 60a are arranged at regular intervals in the y direction, and three non-connection intersections 60b are arranged within each interval. That is, as shown in Figures 7 and 8, in each row 53, the connection intersections 60a are arranged at intervals in the y direction such that one connection intersection 60a appears for every three non-connection intersections 60b.

[0029] (Condition 3) Within a continuous range of the reference pattern P, the Manhattan distance from each unconnected intersection 60b to a connected intersection 60a (more specifically, to the nearest connected intersection 60a) is 1 for every unconnected intersection 60b.

[0030] The Manhattan distance here is a value counted for each intersection 60. For example, in FIG. 8, the non-connection intersection 60b-1 is adjacent to the connection intersection 60a in the y direction, so the Manhattan distance of the non-connection intersection 60b-1 to the connection intersection 60a is 1. In addition, in FIG. 8, the non-connection intersection 60b-2 is adjacent to the connection intersection 60a in the x direction, so the Manhattan distance of the non-connection intersection 60b-2 to the connection intersection 60a is 1. In FIG. 8, the non-connection intersection 60b-3 is adjacent to the connection intersection 60a of the adjacent reference pattern P2 in the y direction, so the Manhattan distance of the non-connection intersection 60b-3 to the connection intersection 60a is 1. In all the non-connection intersections 60b in the central reference pattern P1 shown in FIG. 8, the Manhattan distance to the connection intersection 60a is 1. In this way, within the range in which the reference pattern P is continuous, the Manhattan distance to the connection intersection 60a is 1 at all the non-connection intersections 60b in the reference pattern P.

[0031] In the following, the position of each cell in the reference pattern P in FIG. 7 is represented by coordinates (x, y). In FIG. 7, the leftmost column is represented as x=1, and the rightmost column is represented as x=4. In FIG. 7, the bottommost row is represented as y=1, and the topmost row is represented as y=4. In the pattern P, the cells with coordinates (1, 4), (2, 3), (3, 4), and (4, 3) are connected intersections 60a, and the other cells are non-connected intersections 60b. By following such a reference pattern P, the Manhattan distance of each non-connected intersection 60b within a range where the reference pattern P is continuous can be set to 1.

[0032] The switching element 10 of the first embodiment is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). Normally, a higher potential is applied to the drain electrode 24 than to the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, an inversion layer is formed in the body region 42, and the source region 40 and the drift region 44 are connected by the inversion layer. This causes the switching element 10 to turn on, and a current flows from the drain electrode 24 to the source electrode 22. In addition, since the contact region 54 and the connection region 52 are provided above and below the body region 42 at the connection intersection 60a, almost no current flows at the connection intersection 60a. At the non-connection intersection 60b, a current flows in the inversion layer. In the switching element 10 of the first embodiment, only a part of the multiple intersections 60 are the connection intersections 60a, and the remaining intersections 60 are the non-connection intersections 60b. Since the number of connection intersections 60a is small, a current can flow at high density in the semiconductor substrate 12 when the switching element 10 is turned on. Therefore, the on-resistance of the switching element 10 is low.

[0033] When the potential of the gate electrode 18 is lowered to a potential lower than the gate threshold, the switching element 10 is turned off and the current stops. When the switching element 10 is turned off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44, and a depletion layer spreads from the body region 42 to the drift region 44. In addition, since the deep region 50 is connected to the body region 42 by the connection region 52, the potential of the deep region 50 is approximately equal to the potential of the body region 42. Therefore, a reverse voltage is applied to the pn junction at the interface between the deep region 50 and the drift region 44, and a depletion layer spreads from the deep region 50 to the drift region 44. The depletion layer extending from the deep region 50 prevents a high electric field from being applied to the gate insulating film 16 at the lower end of each trench 14.

[0034] A higher potential than that of the drain electrode 24 may be applied to the source electrode 22. In this case, a diode (so-called body diode) formed by a pn junction at the interface between the body region 42 and the drift region 44 turns on, and a current flows from the source electrode 22 to the drain electrode 24. When the body diode is on, holes flow from the body region 42 to the drift region 44, so that many holes exist in the drift region 44. After that, when the potential of the drain electrode 24 becomes higher than the potential of the source electrode 22, the body diode turns off. Then, the holes existing in the drift region 44 flow to the deep region 50 as shown by the arrow 100 in FIG. 2. The holes flowing from the drift region 44 to the deep region 50 flow to the source electrode 22 via the connection region 52 and the contact region 54. The current generated when the body diode turns off in this way is called a recovery current. As shown in FIG. 2, the recovery current flows more easily to the drift region 44 at the connection intersection 60a where the connection region 52 is provided than at the non-connection intersection 60b where the connection region 52 is not provided.

[0035] Moreover, an overvoltage may be applied to the switching element 10 in a direction in which the drain electrode 24 has a higher potential than the source electrode 22. In this case, an avalanche current is generated in the drift region 44. The avalanche current flows to the deep region 50 as shown by an arrow 100 in FIG. 2. The avalanche current that flows from the drift region 44 to the deep region 50 flows to the source electrode 22 via the connection region 52 and the contact region 54. As shown in FIG. 2, the avalanche current is more likely to flow to the drift region 44 at the connection intersection 60a where the connection region 52 is provided than at the non-connection intersection 60b where the connection region 52 is not provided.

[0036] As described above, at the connection intersection 60a, the recovery current and the avalanche current flow more easily in the drift region 44 than at the non-connection intersection 60b. At the non-connection intersection 60b, the recovery current and the avalanche current flow less easily the farther the distance to the connection intersection 60a is from the non-connection intersection 60b.

[0037] FIG. 9 shows a reference pattern of the switching element of the comparative example. In the reference pattern shown in FIG. 9, the non-connection intersection 60b-4 is not adjacent to any of the connection intersections 60a. Therefore, the Manhattan distance of the non-connection intersection 60b-4 to the connection intersection 60a is 2. In this way, the recovery current and the avalanche current are unlikely to flow in the non-connection intersection 60b-4, which has a long Manhattan distance to the connection intersection 60a. Therefore, in the reference pattern of FIG. 9, the avalanche current is likely to concentrate at the connection intersection 60a. Therefore, the avalanche resistance of the switching element of the comparative example may decrease. In contrast, in the switching element 10 of the first embodiment, the Manhattan distance to the connection intersection 60a is 1 at all the non-connection intersections 60b within the range where the reference pattern P is continuous. Therefore, in the switching element 10 of the first embodiment, the avalanche current is unlikely to concentrate at the connection intersection 60a. Therefore, in the switching element of Example 1, it is possible to reduce the stress that the semiconductor substrate 12 receives when an avalanche current flows. Therefore, according to the structure of the switching element of Example 1, it is possible to achieve higher reliability.

[0038] As shown in Fig. 10, a gap may be provided between the connection region 52 and the gate insulating film 16, and the drift region 44 may be distributed within the gap. As shown in Fig. 10, a gap may be provided between the contact region 54 and the gate insulating film 16, and the source region 40 may be provided within the gap. With this configuration, when the switching element is turned on, a current also flows through the connection intersection 60a. Therefore, the on-resistance of the switching element can be further reduced. EXAMPLES

[0039] 11 and 12 show a switching element 200 according to a second embodiment. In the second embodiment, each deep region 50 extends linearly in the x direction. The deep regions 50 are arranged at intervals in the y direction. Each deep region 50 is arranged below the center of the inter-trench semiconductor layer 30 in the y direction.

[0040] Each deep region 50 is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Fig. 12, the connection regions 52 are arranged to form a plurality of rows 53 that extend linearly in the y direction. The rows 53 are arranged at intervals in the x direction.

[0041] As shown in FIG. 12, a set of the connection region 52 and the contact region 54 is provided at some of the multiple intersections 60. As in the first embodiment, the connection intersections 60a and the non-connection intersections 60b are arranged according to the same reference pattern P as in FIGS. 7 and 8. That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 3. Therefore, in the second embodiment, within the range where the reference pattern P is continuous, there is no non-connection intersection 60b whose Manhattan distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 200 of the second embodiment, the concentration of the recovery current and the avalanche current is unlikely to occur at the connection intersection 60a. According to the structure of the switching element of the second embodiment, high reliability can be achieved.

[0042] In the second embodiment, the drift region 44 may be distributed between the connection region 52 and the gate insulating film 16, as in the case of Fig. 10. The source region 40 may be provided between the contact region 54 and the gate insulating film 16, as in the case of Fig. 10. EXAMPLES

[0043] 13 and 14 show a switching element 300 according to a third embodiment. In the third embodiment, each deep region 50 extends linearly in the x direction. The deep regions 50 are arranged at intervals in the y direction. Each deep region 50 is arranged in the lower part of a trench 14.

[0044] Each deep region 50 is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Fig. 14, the connection regions 52 are arranged to form a plurality of rows 53 that extend linearly in the y direction. The rows 53 are arranged at intervals in the x direction.

[0045] As shown in FIG. 14, a set of the connection region 52 and the contact region 54 is provided at some of the multiple intersections 60. As in the first embodiment, the connection intersections 60a and the non-connection intersections 60b are arranged according to the same reference pattern P as in FIGS. 7 and 8. That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 3. Therefore, in the third embodiment, within the range where the reference pattern P is continuous, there is no non-connection intersection 60b whose Manhattan distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 300 of the third embodiment, the concentration of the recovery current and the avalanche current is unlikely to occur at the connection intersection 60a. According to the structure of the switching element of the third embodiment, high reliability can be achieved. EXAMPLES

[0046] 15 and 16 show a switching element 400 of Example 4. The switching element 400 of Example 4 has two types of deep regions 50x and 50y. Each deep region 50y extends linearly in the y direction. The deep regions 50y are arranged at intervals in the x direction. Each deep region 50y is arranged at a depth including the lower end of the trench 14. Each deep region 50x is arranged below each deep region 50y. Each deep region 50x extends linearly in the x direction. The deep regions 50x are arranged at intervals in the y direction. The upper end of each deep region 50x is arranged at a depth overlapping the lower end of each deep region 50y. Each deep region 50x and each deep region 50y are connected to each other at the intersection.

[0047] Each deep region 50y is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Fig. 16, the connection regions 52 are arranged to form a plurality of rows 53 linearly extending in the y direction. In Fig. 16, the rows 53 extending in the y direction overlap with the deep regions 50y. The rows 53 are arranged at intervals in the x direction.

[0048] As shown in FIG. 16, a set of the connection region 52 and the contact region 54 is provided at some of the multiple intersections 60. As in the first embodiment, the connection intersections 60a and the non-connection intersections 60b are arranged according to the same reference pattern P as in FIGS. 7 and 8. That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 3. Therefore, in the fourth embodiment, within the range where the reference pattern P is continuous, there is no non-connection intersection 60b whose Manhattan distance to the connection intersection 60a is 2 or more. Therefore, in the switching element 400 of the fourth embodiment, the concentration of the recovery current and the avalanche current is unlikely to occur at the connection intersection 60a. According to the structure of the switching element of the fourth embodiment, high reliability can be achieved.

[0049] In addition, in the fourth embodiment, the deep regions 50x and 50y extend along the x and y directions. Therefore, the deep regions 50x and 50y in each of the non-connected intersections 60b are connected to the connection region 52 by a current path with a Manhattan distance within a range of 1. In this manner, since the deep regions 50x and 50y in each of the non-connected intersections 60b are connected to the connection region 52 by a short current path, the potentials of the deep regions 50x and 50y can be stabilized.

[0050] In the fourth embodiment described above, the deep region 50y is disposed above the deep region 50x. However, the deep region 50x may be disposed above the deep region 50y. Moreover, the deep region 50x and the deep region 50y may be disposed at the same depth.

[0051] In the above-described first to fourth embodiments, each deep region 50 is disposed at a depth including the lower end of the trench 14. However, each deep region 50 may be disposed below the lower end of the trench 14. For example, in the first embodiment, each deep region 50 may be disposed below the lower end of the trench 14 as shown in FIG.

[0052] In addition, in the above-described Examples 1 to 4, the contact regions 54 are provided above the connection regions 52. However, the positions of the connection regions 52 and the contact regions 54 may be shifted in the x-direction. Furthermore, the number of connection regions 52 and the number of contact regions 54 may be different.

[0053] In the above-mentioned first to fourth embodiments, the connection intersections 60a and the non-connection intersections 60b are arranged according to the reference pattern P shown in Figs. 7 and 8. However, the connection intersections 60a and the non-connection intersections 60b may be arranged in any manner as long as they follow a reference pattern that satisfies the above-mentioned conditions 1 to 3. For example, a reference pattern obtained by shifting the reference pattern P shown in Figs. 7 and 8 in the x and y directions may be adopted, a reference pattern obtained by rotating the reference pattern P by 90 degrees or 180 degrees to the right or left may be adopted, or a reference pattern obtained by inverting the reference pattern P vertically or horizontally may be adopted.

[0054] In the above-described first to fourth embodiments, three non-connection intersections 60b are arranged in the interval between the connection intersections 60a in the x and y directions. That is, the number of non-connection intersections 60b arranged in the interval (that is, the reference number) is three. However, the reference number may be four. That is, four non-connection intersections 60b may be arranged in the interval between the connection intersections 60a in the x and y directions. In this case, the connection intersections 60a and the non-connection intersections 60b may be arranged according to the reference pattern Q shown in FIGS. 18 and 19. In the reference pattern Q, the cells with the coordinates (1,5), (2,2), (3,4), (4,1), and (5,3) are the connection intersections 60a, and the other cells are the non-connection intersections 60b. Within the range where the reference pattern Q is repeated, the Manhattan distance to the connection intersections 60a is 1 for all the non-connection intersections 60b in the reference pattern Q. In addition, a reference pattern obtained by shifting reference pattern Q in the x and y directions may be adopted, or a reference pattern obtained by rotating reference pattern Q 90 degrees or 180 degrees to the right or left may be adopted, or a reference pattern obtained by inverting reference pattern Q vertically or horizontally may be adopted.

[0055] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A switching element, A semiconductor substrate having a plurality of trenches provided on an upper surface of the semiconductor substrate, each of the trenches extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches being spaced apart from each other in a second direction intersecting the first direction on the upper surface of the semiconductor substrate; a gate insulating film covering an inner surface of each of the trenches; a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; a source electrode in contact with the top surface of the semiconductor substrate; having the semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched between a plurality of the trenches, Each inter-trench semiconductor layer is an n-type source region in contact with the gate insulating film and the source electrode; a p-type body region below the source region and in contact with the gate insulating film; having The semiconductor substrate is an n-type drift region that is distributed across the lower portions of the plurality of inter-trench semiconductor layers and is in contact with the gate insulating film below the body region in each of the inter-trench semiconductor layers; a plurality of p-type deep regions, which are arranged in a range surrounded by the drift region, are arranged below the body region with a gap therebetween, and are arranged in a range including a lower end of the trench or below the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of p-type connection regions connecting the body region and the deep region; having When the semiconductor substrate is viewed from above, the connection regions are arranged in a plurality of rows in a linear manner at intervals along the second direction, and the plurality of rows are arranged at intervals in the first direction, When the semiconductor substrate is viewed from above, intersections between a plurality of the inter-trench semiconductor layers and a plurality of the columns include connection intersections where the connection regions are provided and non-connection intersections where the connection regions are not provided, the connecting intersections and the non-connecting intersections are repeatedly arranged according to a reference pattern in the first direction and the second direction; Within a range in which the connection intersections and the non-connection intersections are repeatedly arranged according to the reference pattern, the connection intersections and the non-connection intersections satisfy the following condition, i.e., In each of the inter-trench semiconductor layers, the connection intersections are arranged in the first direction with a reference number of the non-connection intersections being disposed in a space between adjacent connection intersections. the connection intersections are arranged in the second direction with the reference number of the non-connection intersections being disposed in the spaces between the adjacent connection intersections in the row, the reference number is 3 or 4; When counting Manhattan distances in units of the intersections, the Manhattan distance to the connecting intersection at each non-connecting intersection is 1; Satisfying the condition that Switching element. (Configuration 2) A switching element as described in configuration 1, wherein a plurality of the deep regions extend linearly along the second direction and are spaced apart in the first direction so that each deep region extends along a corresponding column when the semiconductor substrate is viewed from above. (Configuration 3) 3. The switching element according to configuration 1 or 2, wherein each of the connection regions is in contact with the gate insulating film at side surfaces of the trench located on both sides thereof. (Configuration 4) 4. The switching element according to any one of configurations 1 to 3, wherein a p-type contact region that connects the body region and the source electrode is provided on an upper portion of each of the connection regions.

[0056] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0057] 14: trench, 18: gate electrode, 30: inter-trench semiconductor layer, 42: body region, 44: drift region, 50: deep region, 52: connection region, 53: column, 54: contact region, 60: intersection, 60a: connection intersection, 60b: non-connection intersection

Claims

1. A switching element, A semiconductor substrate (12) having a plurality of trenches (14) formed on an upper surface of the semiconductor substrate, each of the trenches extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches being spaced apart in a second direction on the upper surface of the semiconductor substrate that intersects the first direction; a gate insulating film (16) covering the inner surface of each of the trenches; a gate electrode (18) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; a source electrode (22) in contact with the top surface of the semiconductor substrate; having The semiconductor substrate has a plurality of inter-trench semiconductor layers (30) sandwiched between a plurality of the trenches; Each inter-trench semiconductor layer is an n-type source region (40) in contact with the gate insulating film and the source electrode; a p-type body region (42) below the source region and in contact with the gate insulating film; having The semiconductor substrate is an n-type drift region (44) that is distributed across the lower portions of the plurality of inter-trench semiconductor layers and that contacts the gate insulating film below the body region in each inter-trench semiconductor layer; a plurality of p-type deep regions (50) that are arranged in a range surrounded by the drift region, that are spaced apart from the body region and that are lower than the body region, and that are arranged in a range that includes a lower end of the trench or lower than the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of p-type connection regions (52) connecting the body region and the deep region; having When the semiconductor substrate is viewed from above, a plurality of rows (53) are configured in which the connection regions are linearly arranged at intervals along the second direction, and the plurality of rows are arranged at intervals in the first direction, When the semiconductor substrate is viewed from above, intersections (60) between the plurality of inter-trench semiconductor layers and the plurality of columns have connection intersections (60a) where the connection regions are provided and non-connection intersections (60b) where the connection regions are not provided, In the first direction and the second direction, the connection intersections and the non-connection intersections are repeatedly arranged according to a reference pattern (P); Within a range in which the connection intersections and the non-connection intersections are repeatedly arranged according to the reference pattern, the connection intersections and the non-connection intersections satisfy the following condition, i.e., In each of the inter-trench semiconductor layers, the connection intersections are arranged in the first direction with a reference number of the non-connection intersections being disposed in a space between adjacent connection intersections. In the row, the connection intersections are arranged in the second direction with the reference number of the non-connection intersections being disposed in the spaces between the adjacent connection intersections. The reference number is 3 or 4; When counting Manhattan distances in units of the intersections, the Manhattan distance to the connecting intersection at each non-connecting intersection is 1; Satisfying the condition that Switching element.

2. 2. The switching element of claim 1, wherein a plurality of the deep regions extend linearly along the second direction and are spaced apart in the first direction so that each deep region extends along a corresponding column when the semiconductor substrate is viewed from above.

3. 3. The switching element according to claim 1, wherein each of the connection regions is in contact with the gate insulating film at side surfaces of the trench located on both sides of the connection region.

4. 3. The switching element according to claim 1, further comprising a p-type contact region (54) provided on an upper portion of each of the connection regions to connect the body region and the source electrode.

Images