Semiconductor device and manufacturing method for the same
Patent Information
- Application Number
- JP2022193404
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-12-02
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2042-12-02
AI Technical Summary
In semiconductor devices with an RC-IGBT configuration, the formation of mountain-like distributions of p-type impurity concentration between the cathode and buffer regions can hinder the attainment of desired diode characteristics.
A semiconductor device design and manufacturing method that includes forming multiple mountain-like distributions of p-type and n-type impurity concentrations in the collector and cathode regions, respectively, ensuring the n-type cathode region connects directly to the buffer region, thereby preventing the formation of a p-type region between them.
This configuration enhances diode characteristics by ensuring smooth current flow and reduces forward voltage drop, improving the overall performance of the RC-IGBT.
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Abstract
Description
[Technical field]
[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.
[0002] The IGBT (insulated gate bipolar transistor) disclosed in Patent Document 1 has a p-type collector region and an n-type buffer region (field stop layer). The collector region is disposed in an area including the lower surface of the semiconductor substrate and is in contact with a lower electrode. The buffer region is in contact with the collector region from above.
[0003] In Patent Document 1, p-type impurities are implanted multiple times at different depths in the ion implantation into the collector region. Therefore, multiple mountain-shaped distributions of p-type impurity concentration along the thickness direction of the semiconductor substrate are formed in the collector region. By forming the collector region in this manner, it is possible to increase the p-type impurity concentration in the collector region in the vicinity of the buffer region. This improves the short circuit resistance of the IGBT. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] JP 2020-043301 A Summary of the Invention [Problem to be solved by the invention]
[0005] A semiconductor element in which a diode is provided adjacent to an IGBT is known. This type of semiconductor device may be called an RC-IGBT (reverse conducting IGBT). In the RC-IGBT, a cathode region (i.e., an n-type region) of a diode is provided adjacent to a collector region of the IGBT. The buffer region is in contact with the collector region and the cathode region from above. When forming the above-mentioned multiple mountain-shaped distributions in the collector region in the RC-IGBT, the following steps are usually performed. First, p-type impurities are injected multiple times at different depths into the ranges corresponding to the collector region and the cathode region. Next, n-type impurities are injected into the range corresponding to the cathode region at a higher concentration than the p-type impurities. This forms an n-type cathode region. However, in this method, the region in which the p-type impurity concentration is distributed in a mountain-like shape may remain as a p-type region between the cathode region and the buffer region. If a p-type region remains between the cathode region and the buffer region in this way, the diode cannot obtain the desired characteristics. This specification proposes a technique for obtaining good diode characteristics in an RC-IGBT in which multiple hill-shaped distributions of p-type impurity concentration are formed in the collector region. [Means for solving the problem]
[0006] The semiconductor device disclosed in this specification has a semiconductor substrate, a lower electrode in contact with the lower surface of the semiconductor substrate, and a gate electrode. The semiconductor substrate has a p-type collector region in contact with the lower electrode and an n-type cathode region in contact with the lower electrode. When the semiconductor substrate is viewed in the thickness direction, a portion including the collector region is a transistor portion, and when the semiconductor substrate is viewed in the thickness direction, a portion including the cathode region is a diode portion. The semiconductor substrate has a buffer region, a drift region, a body region, an emitter region, and an anode region. The buffer region is distributed across the transistor portion and the diode portion, and is in contact with the collector region and the cathode region from above. The drift region is distributed across the transistor portion and the diode portion, is an n-type region having a lower n-type impurity concentration than the buffer region, and is in contact with the buffer region from above. The body region is disposed in the transistor portion, and is a p-type region in contact with the drift region. The emitter region is an n-type region disposed in the transistor section and separated from the drift region by the body region. The anode region is a p-type region disposed in the diode section and in contact with the drift region. The gate electrode faces the body region via a gate insulating film. The p-type impurity concentrations in the collector region and the cathode region are distributed such that a first mountain-shaped distribution and a second mountain-shaped distribution located above the first mountain-shaped distribution are formed in a concentration distribution along the thickness direction, and the first mountain-shaped distribution and the second mountain-shaped distribution are formed across the collector region and the cathode region. The n-type impurity concentration in the cathode region is distributed such that a third mountain-shaped distribution having a higher concentration than the first mountain-shaped distribution is formed within a thickness range of the first mountain-shaped distribution, and a fourth mountain-shaped distribution having a higher concentration than the second mountain-shaped distribution is formed within a thickness range of the second mountain-shaped distribution, in a concentration distribution along the thickness direction.
[0007] According to this configuration, within the thickness range of the first mountain-shaped distribution of the p-type impurity, a third mountain-shaped distribution of the n-type impurity having a higher concentration than the first mountain-shaped distribution is formed, so that this range can be made n-type. Also, within the thickness range of the second mountain-shaped distribution of the p-type impurity, a fourth mountain-shaped distribution having a higher concentration than the second mountain-shaped distribution is formed, so that this range can be made n-type. Therefore, an n-type cathode region can be formed in the depth range from the lower electrode to the buffer region, and it is possible to prevent a p-type region from remaining between the cathode region and the buffer region. Therefore, according to this configuration, good diode characteristics can be obtained.
[0008] This specification also proposes a method for manufacturing a semiconductor device. The semiconductor device manufactured by this manufacturing method has a semiconductor substrate, a lower electrode in contact with the lower surface of the semiconductor substrate, and a gate electrode. The semiconductor substrate has a collector region, a cathode region, a buffer region, a drift region, a body region, an emitter region, and an anode region. The collector region is a p-type region in contact with the lower electrode. The cathode region is an n-type region in contact with the lower electrode. The buffer region is an n-type region having a lower n-type impurity concentration than the cathode region, and is in contact with the collector region and the cathode region from above. The drift region is an n-type region having a lower n-type impurity concentration than the buffer region, and is in contact with the buffer region from above. The body region is a p-type region disposed above the collector region and in contact with the drift region. The emitter region is an n-type region disposed above the collector region and separated from the drift region by the body region. The anode region is disposed above the cathode region and is a p-type region in contact with the drift region. The gate electrode faces the body region via a gate insulating film. The manufacturing method includes a first implantation step, a second implantation step, a third implantation step, and a fourth implantation step. In the first implantation step, p-type impurities are implanted into an implantation range corresponding to the cathode region and the collector region on the lower surface of the semiconductor substrate so as to form a first mountain-shaped distribution in the thickness direction of the semiconductor substrate. In the second implantation step, p-type impurities are implanted into an implantation range corresponding to the cathode region and the collector region on the lower surface of the semiconductor substrate so as to form a second mountain-shaped distribution in the thickness direction of the semiconductor substrate. In the third implantation step, n-type impurities are implanted into an implantation range corresponding to the cathode region on the lower surface of the semiconductor substrate so as to form a third mountain-shaped distribution in the thickness direction of the semiconductor substrate. In the fourth implantation step, n-type impurities are implanted into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region so as to form a fourth mountain-shaped distribution in a thickness direction of the semiconductor substrate.The first injection process, the second injection process, the third injection process, and the fourth injection process are performed such that the second hill-shaped distribution is located above the first hill-shaped distribution, the third hill-shaped distribution having a higher concentration than the first hill-shaped distribution is formed within a thickness range of the first hill-shaped distribution, and the fourth hill-shaped distribution having a higher concentration than the second hill-shaped distribution is formed within a thickness range of the second hill-shaped distribution.
[0009] The first injection step, the second injection step, the third injection step and the fourth injection step may be carried out in any order.
[0010] According to this configuration, a semiconductor device having good diode characteristics can be manufactured. [Brief description of the drawings]
[0011] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 4 is a graph showing the impurity concentration distribution in the collector region 40. [Diagram 3] 4 is a graph showing the impurity concentration distribution in the cathode region 42. [Figure 4] 13 is a graph showing an impurity concentration distribution in a cathode region 42 of a semiconductor device of a comparative example. [Diagram 5] 2A to 2C are explanatory diagrams of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are explanatory diagrams of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] 13 is a graph showing the relationship between the dose in the third implantation step and the forward voltage drop of a diode. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 9] 5A to 5C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 12] 11A to 11C are explanatory diagrams of a manufacturing method of a semiconductor device according to a fourth embodiment. [Figure 13]10 is a graph showing an impurity concentration distribution in a cathode region 42 of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0012] In the semiconductor device disclosed in the present specification, the region of the cathode region having the third mountain-shaped distribution may be a first cathode region, and the region of the cathode region having the fourth mountain-shaped distribution may be a second cathode region. The semiconductor substrate may have a p-type boundary region that is disposed within the diode portion and adjacent to the transistor portion, is continuous with the collector region, and contacts the first cathode region from above.
[0013] With this configuration, the on-voltage of the IGBT can be reduced.
[0014] In one example of a semiconductor device disclosed in this specification, a plurality of trenches may be provided on the upper surface of the semiconductor substrate at intervals in a lateral direction from the transistor section toward the diode section. The gate electrode may be disposed in each of the trenches in the transistor section. A dummy electrode having a potential independent of the gate electrode may be disposed in each of the trenches in the diode section. A gap may be provided along the lateral direction between the trench located closest to the diode section among the trenches in which the gate electrode is disposed and an end of the cathode region on the transistor section side.
[0015] With this configuration, the on-voltage of the IGBT can be reduced.
[0016] In the semiconductor device disclosed in this specification as an example, a plurality of the cathode regions may be provided at intervals within the diode portion.
[0017] This configuration makes it possible to reduce the recovery surge of the diode.
[0018] In the semiconductor device disclosed in this specification as an example, the fourth mountain-shaped distribution may have a plurality of maximum values in the concentration distribution along the thickness direction.
[0019] In one example manufacturing method disclosed in the present specification, an end of the implantation range in the third implantation step on the collector region side may be positioned closer to the collector region than an end of the implantation range in the fourth implantation step on the collector region side.
[0020] With this configuration, the on-voltage of the IGBT can be reduced.
[0021] In one example manufacturing method disclosed in this specification, in the third implantation step and the fourth implantation step, n-type impurities may be implanted into a plurality of implantation ranges spaced apart on the lower surface of the semiconductor substrate.
[0022] This configuration makes it possible to reduce the recovery surge of the diode.
[0023] In one example of the manufacturing method disclosed in this specification, in the fourth implantation step, the n-type impurity may be implanted multiple times at different implantation depths to form the fourth mountain-shaped distribution having multiple maximum values.
[0024] The manufacturing method of the example disclosed in the present specification may further include a step of activating the n-type impurity in the cathode region by laser annealing. 15 cm -2 The n-type impurity may be implanted in the above dose amounts.
[0025] This configuration makes it possible to reduce the forward voltage drop of the diode. EXAMPLES
[0026] A semiconductor device 10 of the first embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon. A lower electrode 14 is provided on a lower surface 12b of the semiconductor substrate 12. The lower electrode 14 covers almost the entire lower surface 12b. A p-type collector region 40 and an n-type cathode region 42 are provided in the interior of the semiconductor substrate 12 and in a range facing the lower surface 12b of the semiconductor substrate 12. The collector region 40 and the cathode region 42 are in ohmic contact with the lower electrode 14. In the following, a semiconductor region including the collector region 40 when the semiconductor substrate 12 is viewed along the thickness direction is referred to as a transistor portion 30, and a semiconductor region including the cathode region 42 when the semiconductor substrate 12 is viewed along the thickness direction is referred to as a diode portion 32. In the following description, a direction along the top surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction along the top surface 12a and perpendicular to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction. The x-direction is the direction from the transistor portion 30 toward the diode portion 32. The y-direction is the direction along the boundary between the transistor portion 30 and the diode portion 32.
[0027] A plurality of trenches 16 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 16 extends linearly in the y direction on the upper surface 12a. The trenches 16 are arranged at intervals in the x direction. A plurality of trenches 16 are provided in each of the transistor section 30 and the diode section 32. The inner surface of each trench 16 is covered with a gate insulating film 18. A gate electrode 20 is provided in each trench 16 in the transistor section 30. Each gate electrode 20 is insulated from the semiconductor substrate 12 by the gate insulating film 18. A dummy electrode 22 is provided in each trench 16 in the diode section 32. Each dummy electrode 22 is insulated from the semiconductor substrate 12 by the gate insulating film 18. The upper surfaces of the gate electrodes 20 and the dummy electrodes 22 are covered with an interlayer insulating film 24. An upper electrode 26 is provided on the upper portion of the semiconductor substrate 12. The upper electrode 26 covers the upper surface of the interlayer insulating film 24 and the upper surface 12a of the semiconductor substrate 12. The dummy electrode 22 is connected to the upper electrode 26 at a position not shown. Therefore, the potential of the dummy electrode 22 is equal to the potential of the upper electrode 26. The gate electrode 20 is insulated from the upper electrode 26 and the dummy electrode 22. Therefore, the potential of the dummy electrode 22 is independent from the potential of the gate electrode 20. The gate electrode 20 is connected to a gate pad not shown. The potential of the gate electrode 20 is controlled by an external driving circuit via the gate pad.
[0028] The semiconductor substrate 12 includes a buffer region 44, a drift region 46, a body region 48, an anode region 50, an emitter region 52, and a dummy emitter region 54.
[0029] The buffer region 44 is an n-type region having a lower n-type impurity concentration than the cathode region 42. The buffer region 44 is distributed across the transistor portion 30 and the diode portion 32. The buffer region 44 contacts the collector region 40 and the cathode region 42 from above.
[0030] The drift region 46 is an n-type region having a lower n-type impurity concentration than the buffer region 44. The drift region 46 is distributed across the transistor section 30 and the diode section 32. The buffer region 44 contacts the buffer region 44 from above within the transistor section 30 and the diode section 32. The upper end of the drift region 46 is located above the lower end of each trench 16. The drift region 46 contacts the gate insulating film 18 on the side surface of each trench 16.
[0031] The body region 48 and the anode region 50 are p-type regions in contact with the drift region 46 from above. The body region 48 is provided in the transistor section 30, and the anode region 50 is provided in the diode section 32. In other words, of the p-type region arranged above the drift region 46, the portion within the transistor section 30 is the body region 48, and the portion within the diode section 32 is the anode region 50.
[0032] The body region 48 has a low concentration region 48a and a contact region 48b. The p-type impurity concentration of the low concentration region 48a is lower than the p-type impurity concentration of the contact region 48b. The low concentration region 48a contacts the drift region 46 from above. The low concentration region 48a contacts the gate insulating film 18 above the drift region 46. The contact region 48b contacts the low concentration region 48a from above. The contact region 48b is in ohmic contact with the upper electrode 26.
[0033] The anode region 50 has a low concentration region 50a and a contact region 50b. The p-type impurity concentration of the low concentration region 50a is lower than the p-type impurity concentration of the contact region 50b. The low concentration region 50a contacts the drift region 46 from above. The low concentration region 50a contacts the gate insulating film 18 above the drift region 46. The contact region 50b contacts the low concentration region 50a from above. The contact region 50b is in ohmic contact with the upper electrode 26.
[0034] The emitter regions 52 are n-type regions, and a plurality of them are arranged in the transistor section 30. Each emitter region 52 contacts the low concentration region 48a from above. Each emitter region 52 is in ohmic contact with the upper electrode 26. Each emitter region 52 contacts the gate insulating film 18 above the low concentration region 48a. Each emitter region 52 is separated from the drift region 46 by the low concentration region 48a. Each gate electrode 20 faces the low concentration region 48a located between the emitter region 52 and the drift region 46 via the gate insulating film 18.
[0035] The dummy emitter regions 54 are n-type regions, and a plurality of dummy emitter regions 54 are arranged in the diode section 32. Each dummy emitter region 54 contacts the low concentration region 50a from above. Each dummy emitter region 54 contacts the gate insulating film 18 above the low concentration region 50a. Each dummy emitter region 54 is separated from the drift region 46 by the low concentration region 50a. Each dummy emitter region 54 is in ohmic contact with the upper electrode 26. Note that the dummy emitter region 54 does not necessarily have to be provided in the diode section 32.
[0036] Fig. 2 shows the impurity concentration distribution at the position of line II-II in Fig. 1. That is, Fig. 2 shows the impurity concentration distribution in the z direction of the collector region 40 and the buffer region 44. As shown in Fig. 2, the p-type impurity concentration is higher than the n-type impurity concentration in the collector region 40, and the n-type impurity concentration is higher than the p-type impurity concentration in the buffer region 44.
[0037] In the buffer region 44, the n-type impurity concentration is distributed so as to form a mountain-shaped distribution NMb having a maximum value Nb.
[0038] In the collector region 40, the p-type impurity concentration is distributed to form two mountain-shaped distributions PM1 and PM2. The mountain-shaped distribution PM1 is a mountain-shaped distribution having a maximum value PH1, and the mountain-shaped distribution PM2 is a mountain-shaped distribution having a maximum value PH2. The mountain-shaped distribution PM2 is disposed above the mountain-shaped distribution PM1 (i.e., at a position closer to the buffer region 44). Note that, although the maximum value PH1 is higher than the maximum value PH2 in FIG. 2, the maximum value PH1 may be lower than the maximum value PH2. A minimum value PL1 is formed at the boundary between the mountain-shaped distributions PM1 and PM2.
[0039] Fig. 3 shows the impurity concentration distribution at the position of line III-III in Fig. 1. That is, Fig. 3 shows the impurity concentration distribution in the z direction of the cathode region 42 and the buffer region 44.
[0040] The mountain-shaped distribution NMb of the n-type impurity concentration in the buffer region 44 is formed across the transistor section 30 and the diode section 32. That is, the mountain-shaped distribution NMb is formed continuously in the x direction and the y direction. Therefore, as shown in FIG. 3, the mountain-shaped distribution NMb is also formed in the buffer region 44 in the diode section 32.
[0041] The mountain-shaped distributions PM1, PM2 of the p-type impurity concentration are formed across the transistor section 30 and the diode section 32 within the depth range of the collector region 40 (i.e., the range in the z direction). That is, the mountain-shaped distributions PM1, PM2 of the p-type impurity concentration are formed across the collector region 40 and the cathode region 42. In other words, the mountain-shaped distributions PM1, PM2 are formed continuously in the x direction and the y direction. Therefore, as shown in FIG. 3, the mountain-shaped distributions PM1, PM2 are also formed in the cathode region 42.
[0042] In the cathode region 42, the n-type impurity concentration is higher than the p-type impurity concentration. In the cathode region 42, the n-type impurity concentration is distributed to form two mountain-shaped distributions NM1 and NM2. The mountain-shaped distribution NM1 is a mountain-shaped distribution having a maximum value NH1, and the mountain-shaped distribution NM2 is a mountain-shaped distribution having a maximum value NH2. The mountain-shaped distribution NM2 is disposed above the mountain-shaped distribution NM1 (i.e., at a position closer to the buffer region 44). Note that in FIG. 3, the maximum value NH1 is higher than the maximum value NH2, but the maximum value NH1 may be lower than the maximum value NH2. A minimum value NL1 is formed at the boundary between the mountain-shaped distributions NM1 and NM2. The minimum value NL1 is smaller than the maximum values PH1 and PH2. The mountain-shaped distribution NM1 is formed at a position overlapping with the mountain-shaped distribution PM1. Either of the maximum value NH1 of the mountain-shaped distribution NM1 and the maximum value PH1 of the mountain-shaped distribution PM1 may be located on the upper side (i.e., on the buffer region 44 side). The mountain-shaped distribution NM2 is formed at a position overlapping the mountain-shaped distribution PM2. Either of the maximum value NH2 of the mountain-shaped distribution NM2 and the maximum value PH2 of the mountain-shaped distribution PM2 may be located on the upper side (i.e., on the buffer region 44 side). The mountain-shaped distributions NM1 and NM2 are formed so as to overlap with the mountain-shaped distributions PM1 and PM2, so that the n-type impurity concentration is higher than the p-type impurity concentration in the entire cathode region 42. Hereinafter, the region of the cathode region 42 where the mountain-shaped distribution NM1 is formed is referred to as the first cathode region 42a, and the region where the mountain-shaped distribution NM2 is formed is referred to as the second cathode region 42b.
[0043] In the transistor section 30, an IGBT is formed by the emitter region 52, the body region 48, the drift region 46, the buffer region 44, the collector region 40, the gate electrode 20, and the gate insulating film 18. When the potential of the lower electrode 14 is higher than the potential of the upper electrode 26 and the potential of the gate electrode 20 is higher than the gate threshold, the IGBT is turned on and a current flows from the lower electrode 14 to the upper electrode 26 in the transistor section 30. In the collector region 40, two mountain-shaped distributions PM1 and PM2 are formed in the z direction. Since the mountain-shaped distribution PM2 is formed near the buffer region 44, the collector region 40 has a high p-type impurity concentration near the buffer region 44. Therefore, the IGBT has a high short-circuit resistance.
[0044] In the diode section 32, a diode is formed by the anode region 50, the drift region 46, the buffer region 44, and the cathode region 42. When the potential of the upper electrode 26 is higher than the potential of the lower electrode 14, the diode is turned on and a current flows in the diode section 32 from the upper electrode 26 to the lower electrode 14.
[0045] FIG. 4 shows the impurity concentration distribution in the buffer region 44 and the cathode region 42 of the semiconductor device of the comparative example. FIG. 4 differs from FIG. 3 in that the mountain-shaped distribution NM2 is not formed. If the mountain-shaped distribution NM2 is not formed as in FIG. 4, the p-type impurity concentration is higher than the n-type impurity concentration in the range of the mountain-shaped distribution PM2. Therefore, a p-type region 45 is formed between the first cathode region 42a and the buffer region 44. If the p-type region 45 is formed between the first cathode region 42a and the buffer region 44 in this way, it becomes difficult for a current to flow through the diode, and the forward voltage drop of the diode becomes extremely high. Therefore, high loss occurs in the diode. In contrast, in the semiconductor device of the first embodiment, the mountain-shaped distribution NM2 is formed, so that the first cathode region 42a and the buffer region 44 are connected by the n-type second cathode region 42b. Therefore, loss occurring in the diode can be suppressed.
[0046] Next, a description will be given of a method for manufacturing the semiconductor device 10. Note that this manufacturing method is characterized by a collector region forming process and a cathode region forming process, and therefore these processes will be described below.
[0047] In the collector region forming step, as shown in FIG. 5, p-type impurities are implanted into the lower surface 12b of the semiconductor substrate 12 on which the buffer region 44 is formed. Here, the p-type impurities are implanted into the entire lower surface 12b of the semiconductor substrate 12. That is, the p-type impurities are implanted into the range of the lower surface 12b corresponding to the cathode region 42 and the range of the collector region 40. The collector region forming step has a first implantation step and a second implantation step with different implantation depths. In the first implantation step, the p-type impurities are implanted so that the average stop position of the p-type impurities is at the depth of the maximum value PH1. In the second implantation step, the p-type impurities are implanted so that the average stop position of the p-type impurities is at the depth of the maximum value PH2. That is, in the second implantation step, the implantation energy of the p-type impurities is made higher than in the first implantation step, and the p-type impurities are implanted deeper than in the first implantation step. By performing the first implantation step and the second implantation step in this way, when the p-type impurities are diffused and activated thereafter, mountain-shaped distributions PM1 and PM2 are formed.
[0048] Next, a cathode region forming step is performed. In the cathode region forming step, as shown in FIG. 6, a mask 60 is formed on the lower surface 12b of the semiconductor substrate 12. The mask 60 has an opening 60a. A range of the lower surface 12b corresponding to the cathode region 42 is exposed in the opening 60a. A range of the lower surface 12b corresponding to the collector region 40 is covered by the mask 60. Next, n-type impurities are implanted into the lower surface 12b of the semiconductor substrate 12 through the mask 60. Here, n-type impurities are not implanted into the range corresponding to the collector region 40, and n-type impurities are implanted into the range corresponding to the cathode region 42. The cathode region forming step has a third implantation step and a fourth implantation step with different implantation depths. In the third implantation step, n-type impurities are implanted so that the average stop position of the n-type impurities is at the depth of the maximum value NH1. In the fourth implantation step, n-type impurities are implanted so that the average stop position of the n-type impurities is at the depth of the maximum value NH2. That is, in the fourth implantation step, the implantation energy of the n-type impurity is made higher than that in the third implantation step, and the n-type impurity is implanted deeper than that in the third implantation step. By performing the third and fourth implantation steps in this manner, when the n-type impurity is diffused and activated thereafter, mountain-shaped distributions NM1 and NM2 are formed. The dose of the third implantation step (i.e., the dose for the mountain-shaped distribution NM1) is higher than the dose of the first implantation step (i.e., the dose for the mountain-shaped distribution PM1). Also, the dose of the fourth implantation step (i.e., the dose for the mountain-shaped distribution NM2) is higher than the dose of the second implantation step (i.e., the dose for the mountain-shaped distribution PM2). After the implantation of the n-type impurity, the mask 60 is removed.
[0049] Next, the semiconductor substrate 12 is annealed by irradiating the lower surface 12b of the semiconductor substrate 12 with a laser. This heats the implantation range of the n-type impurities and p-type impurities, diffusing and activating the implanted n-type impurities and p-type impurities. When the n-type impurities and p-type impurities are diffused, the impurity concentration distributions shown in FIGS. 2 and 3 are obtained. In order to recover the crystal defects to the depth of the mountain-shaped distributions NM2 and PM2, it is necessary to irradiate the lower surface 12b with a laser at high energy. When the laser is irradiated with high energy, the diffusion distance of the n-type impurities becomes long in the range of the mountain-shaped distribution NM1, and the n-type impurity concentration may become low in the range of the mountain-shaped distribution NM1. When the n-type impurity concentration becomes low in the range of the mountain-shaped distribution NM1, the contact resistance of the first cathode region 42a to the lower electrode 14 becomes high, and the forward voltage drop of the diode becomes high. FIG. 7 shows the relationship between the dose in the third implantation step (i.e., the dose relative to the mountain-shaped distribution NM1) and the forward voltage drop Vf of the diode when irradiating a laser with high energy to restore crystal defects to the depth of the mountain-shaped distributions NM2 and PM2. Note that the forward voltage drop Vf shown in FIG. 7 is the forward voltage drop when 400 A is passed through the diode. Even when irradiating a laser with high energy, as shown in FIG. 7, the dose in the third implantation step is set to 2×10 15 cm -2 By setting the above, a sufficiently high n-type impurity concentration can be obtained in the first cathode region 42a, and the forward voltage drop Vf can be stabilized at a low value.
[0050] As described above, in this manufacturing method, in the collector region forming step, p-type impurities are implanted not only in the area corresponding to the collector region 40 but also in the area corresponding to the cathode region 42. Therefore, no mask is required, and p-type impurities can be easily implanted. In addition, in this manufacturing method, mountain-shaped distributions PM1 and PM2 can be formed in the collector region 40, so that an IGBT having high short circuit resistance can be formed. In addition, in this manufacturing method, in the collector region forming step, the third and fourth implantation steps are performed with different implantation depths, thereby forming mountain-shaped distributions NM1 and NM2. Therefore, it is possible to prevent a p-type region from being formed between the first cathode region 42a and the buffer region 44. EXAMPLES
[0051] 8, an end 42ax of the first cathode region 42a on the collector region 40 side is disposed closer to the collector region 40 than an end 42bx of the second cathode region 42b on the collector region 40 side. A p-type boundary region 58 is disposed on the upper part of the first cathode region 42a near the collector region 40. The boundary region 58 is disposed within the diode portion 32 and adjacent to the transistor portion 30, and is continuous with the collector region 40. The boundary region 58 contacts the first cathode region 42a from above.
[0052] In the semiconductor device of Example 2, when the IGBT is on, holes flow from the collector region 40 and the boundary region 58 into the drift region 46 in the transistor section 30. This makes it easy for the hole density to increase in the drift region 46 in the transistor section 30. Therefore, in Example 2, the on-resistance of the IGBT can be further reduced. Also, in the semiconductor device of Example 2, when the diode is on, no current flows through the boundary region 58, so the current flowing through the diode is low. This makes it difficult for a recovery surge to occur in the diode.
[0053] Next, a method for manufacturing a semiconductor device according to Example 2 will be described. In Example 2, the first implantation step, the second implantation step, and the third implantation step are performed in the same manner as in Example 1. In the fourth implantation step (i.e., the implantation step for the mountain-shaped distribution NM2) of Example 2, n-type impurities are implanted into the lower surface 12b through a mask 61 as shown in FIG. 9. An opening 61a of the mask 61 is smaller than an opening 60a of the mask 60. The mask 61 covers a range of the lower surface 12b that corresponds to the collector region 40 and the boundary region 58. Therefore, in the fourth implantation step, n-type impurities are not formed in the range that corresponds to the boundary region 58, and a p-type boundary region 58 is formed. EXAMPLES
[0054] In the semiconductor device of Example 3 shown in FIG. 10, a gap C is provided in the x direction between the end of the cathode region 42 and the trench 16 located closest to the cathode region 42 among the trenches 16 in which the gate electrode 20 is provided (i.e., the trenches 16 in the transistor section 30). When the gap C is provided in this manner, the collector region 40 becomes wider, so that the on-resistance of the IGBT can be reduced. In addition, the cathode region 42 becomes narrower, so that the current that flows when the diode is on becomes lower. Therefore, a recovery surge is less likely to occur in the diode. EXAMPLES
[0055] In the semiconductor device of Example 4 shown in Fig. 11, a plurality of cathode regions 42 are provided at intervals in the diode section 32. A p-type ineffective region 43 is disposed in the space between the cathode regions 42. In this configuration, when the diode is on, no current flows through the ineffective region 43, so that the current flowing through the diode is low. Therefore, a recovery surge is unlikely to occur in the diode.
[0056] In the manufacturing method of the semiconductor device of Example 4, in the third and fourth implantation steps, n-type impurities are implanted into the lower surface 12b through a mask 62 as shown in Fig. 12. The mask 62 has a plurality of openings 62a spaced apart from one another. Therefore, a plurality of cathode regions 42 can be formed as shown in Fig. 11.
[0057] In the above-described embodiment, the mountain-shaped distribution NM2 has one maximum value NH2. However, as shown in FIG. 13, the mountain-shaped distribution NM2 in the second cathode region 42b may have multiple maximum values NH2-1, NH2-2. Such a distribution can be obtained by injecting n-type impurities multiple times at different implantation depths in the fourth implantation step. Even with this configuration, it is possible to prevent a p-type region from being formed between the first cathode region 42a and the buffer region 44.
[0058] In the above embodiment, the first implantation step, the second implantation step, the third implantation step, and the fourth implantation step are performed in this order. However, these steps may be performed in any order. In the above embodiment, the collector region and the cathode region are formed after the buffer region 44, but the impurity implantation into the buffer region 44 may be performed after the collector region and the cathode region.
[0059] In the above-described embodiment, the dummy electrode 22 having a potential independent of the gate electrode 20 is disposed in the trench 16 in the diode portion 32. However, an electrode that is in electrical conduction with the gate electrode 20 may be disposed in the trench 16 in the diode portion 32. Also, a trench may not be provided in the diode portion 32.
[0060] In the above-described embodiment, a trench type IGBT is formed in the transistor section, but a planar type IGBT may be formed in the transistor section.
[0061] The mountain-like distribution PM1 is an example of a first mountain-like distribution. The mountain-like distribution PM2 is an example of a second mountain-like distribution. The mountain-like distribution NM1 is an example of a third mountain-like distribution. The mountain-like distribution NM2 is an example of a fourth mountain-like distribution.
[0062] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A semiconductor device comprising: A semiconductor substrate; a lower electrode in contact with a lower surface of the semiconductor substrate; A gate electrode, having The semiconductor substrate is a p-type collector region in contact with the lower electrode; an n-type cathode region in contact with the lower electrode; having When the semiconductor substrate is viewed in a thickness direction, a portion including the collector region is a transistor portion, When the semiconductor substrate is viewed in a thickness direction, a portion including the cathode region is a diode portion, The semiconductor substrate is a buffer region that is distributed across the transistor portion and the diode portion and is in contact with the collector region and the cathode region from above; a drift region that is an n-type region having a lower n-type impurity concentration than the buffer region and that is distributed across the transistor portion and the diode portion and is in contact with the buffer region from above; a p-type body region disposed in the transistor portion and in contact with the drift region; an n-type emitter region disposed within the transistor portion and separated from the drift region by the body region; a p-type anode region disposed within the diode portion and in contact with the drift region; having the gate electrode faces the body region via a gate insulating film, a p-type impurity concentration in the collector region and the cathode region is distributed such that a first mountain-shaped distribution and a second mountain-shaped distribution located above the first mountain-shaped distribution are formed in a concentration distribution along a thickness direction, and the first mountain-shaped distribution and the second mountain-shaped distribution are formed across the collector region and the cathode region; the n-type impurity concentration in the cathode region is distributed such that, in a concentration distribution along a thickness direction, a third mountain-shaped distribution having a higher concentration than the first mountain-shaped distribution is formed within a thickness range of the first mountain-shaped distribution, and a fourth mountain-shaped distribution having a higher concentration than the second mountain-shaped distribution is formed within a thickness range of the second mountain-shaped distribution. Semiconductor device. (Configuration 2) Among the cathode regions, a region having the third mountain-like distribution is a first cathode region, and a region having the fourth mountain-like distribution is a second cathode region; the semiconductor substrate is disposed within the diode portion and adjacent to the transistor portion, is continuous with the collector region, and has a p-type boundary region in contact with the first cathode region from above; 2. The semiconductor device according to configuration 1. (Configuration 3) a plurality of trenches are provided at intervals in a lateral direction from the transistor portion toward the diode portion on an upper surface of the semiconductor substrate; the gate electrode is disposed in each of the trenches in the transistor portion; a dummy electrode having a potential independent of the gate electrode is disposed in each of the trenches in the diode portion; a gap is provided along the lateral direction between the trench in which the gate electrode is disposed and the trench located closest to the diode section and an end of the cathode region on the transistor section side; 3. The semiconductor device according to configuration 1 or 2. (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein a plurality of the cathode regions are provided at intervals within the diode portion. (Configuration 5) 5. The semiconductor device according to any one of configurations 1 to 4, wherein the fourth mountain-shaped distribution has a plurality of maximum values in the concentration distribution along the thickness direction. (Configuration 6) A method for manufacturing a semiconductor device, comprising: The semiconductor device comprises: A semiconductor substrate; a lower electrode in contact with a lower surface of the semiconductor substrate; A gate electrode, having The semiconductor substrate is a p-type collector region in contact with the lower electrode; an n-type cathode region in contact with the lower electrode; a buffer region which is an n-type region having a lower n-type impurity concentration than the cathode region and which is in contact with the collector region and the cathode region from above; a drift region that is an n-type region having a lower n-type impurity concentration than the buffer region and is in contact with the buffer region from above; a p-type body region disposed above the collector region and in contact with the drift region; an n-type emitter region disposed above the collector region and separated from the drift region by the body region; a p-type anode region disposed above the cathode region and in contact with the drift region; having the gate electrode faces the body region via a gate insulating film, The manufacturing method comprises: a first implantation step of implanting a p-type impurity into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region and the collector region so as to form a first mountain-shaped distribution in a thickness direction of the semiconductor substrate; a second implantation step of implanting p-type impurities into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region and the collector region so as to form a second mountain-shaped distribution in a thickness direction of the semiconductor substrate; a third implantation step of implanting an n-type impurity into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region so as to form a third mountain-shaped distribution in a thickness direction of the semiconductor substrate; a fourth implantation step of implanting an n-type impurity into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region so as to form a fourth mountain-shaped distribution in a thickness direction of the semiconductor substrate; having the first implantation step, the second implantation step, the third implantation step, and the fourth implantation step are performed such that the second hill-shaped distribution is located above the first hill-shaped distribution, the third hill-shaped distribution having a higher concentration than the first hill-shaped distribution is formed within a thickness range of the first hill-shaped distribution, and the fourth hill-shaped distribution having a higher concentration than the second hill-shaped distribution is formed within a thickness range of the second hill-shaped distribution. Manufacturing method. (Configuration 7) 7. The manufacturing method according to configuration 6, wherein an end of the implantation range on the collector region side in the third implantation step is positioned closer to the collector region than an end of the implantation range on the collector region side in the fourth implantation step. (Configuration 8) The semiconductor device according to any one of configurations 6 to 7, wherein in the third implantation step and the fourth implantation step, n-type impurities are implanted into a plurality of implantation ranges arranged at intervals on the lower surface of the semiconductor substrate. (Configuration 9) The semiconductor device according to any one of configurations 6 to 8, wherein in the fourth implantation step, the fourth mountain-shaped distribution having a plurality of maximum values is formed by implanting n-type impurities a plurality of times with different implantation depths. (Configuration 10) activating n-type impurities in the cathode region by laser annealing; In the third injection step, 2×10 15 cm -2 10. The semiconductor device according to any one of configurations 6 to 9, wherein the n-type impurity is implanted in the above dose amount.
[0063] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]
[0064] 10: semiconductor device, 12: semiconductor substrate, 30: transistor portion, 32: diode portion, 40: collector region, 42: cathode region, 42a: first cathode region, 42b: second cathode region
Claims
1. A semiconductor device comprising: A semiconductor substrate (12); a lower electrode (14) in contact with the lower surface of the semiconductor substrate; A gate electrode (20), having The semiconductor substrate is a p-type collector region (40) in contact with the lower electrode; an n-type cathode region (42) in contact with the lower electrode; having When the semiconductor substrate is viewed in the thickness direction, a portion including the collector region is a transistor portion (30), When the semiconductor substrate is viewed in the thickness direction, a portion including the cathode region is a diode portion (32), The semiconductor substrate is a buffer region (44) distributed across the transistor portion and the diode portion and in contact with the collector region and the cathode region from above; a drift region (46) that is an n-type region having a lower n-type impurity concentration than the buffer region and that is distributed across the transistor portion and the diode portion, and that is in contact with the buffer region from above; a p-type body region (48) disposed within the transistor portion and in contact with the drift region; an n-type emitter region (52) disposed within the transistor portion and separated from the drift region by the body region; a p-type anode region (50) disposed within the diode portion and in contact with the drift region; having the gate electrode faces the body region via a gate insulating film, a p-type impurity concentration in the collector region and the cathode region is distributed such that a first mountain-shaped distribution (PM1) and a second mountain-shaped distribution (PM2) located above the first mountain-shaped distribution are formed in a concentration distribution along a thickness direction, and the first mountain-shaped distribution and the second mountain-shaped distribution are formed across the collector region and the cathode region; the n-type impurity concentration in the cathode region is distributed such that, in a concentration distribution along a thickness direction, a third mountain-shaped distribution (NM1) having a higher concentration than the first mountain-shaped distribution is formed within a thickness range of the first mountain-shaped distribution, and a fourth mountain-shaped distribution (NM2) having a higher concentration than the second mountain-shaped distribution is formed within a thickness range of the second mountain-shaped distribution; Semiconductor device.
2. Among the cathode regions, the region having the third mountain-like distribution is a first cathode region (42a), and the region having the fourth mountain-like distribution is a second cathode region (42b); the semiconductor substrate has a p-type boundary region (58) disposed within the diode section and adjacent to the transistor section, the p-type boundary region (58) being continuous with the collector region and contacting the first cathode region from above; The semiconductor device according to claim 1 .
3. A plurality of trenches (16) are provided in a top surface of the semiconductor substrate at intervals in a lateral direction from the transistor portion toward the diode portion; the gate electrode is disposed in each of the trenches in the transistor portion; a dummy electrode (22) having a potential independent of the gate electrode is disposed in each of the trenches in the diode portion; a gap (C) is provided along the lateral direction between the trench in which the gate electrode is disposed and the end of the cathode region closest to the diode section, the trench being disposed in the lateral direction and the end of the cathode region on the transistor section side; 3. The semiconductor device according to claim 1 or 2.
4. 3. The semiconductor device according to claim 1, wherein a plurality of said cathode regions are provided at intervals within said diode portion.
5. 3. The semiconductor device according to claim 1, wherein said fourth mountain-shaped distribution has a plurality of maximum values in the concentration distribution along the thickness direction.
6. A semiconductor device as described in claim 1 or 2, wherein a minimum value formed at the boundary between the third hill-shaped distribution and the fourth hill-shaped distribution is smaller than the maximum value of the first hill-shaped distribution and the maximum value of the second hill-shaped distribution.
7. A semiconductor device as described in claim 1 or 2, wherein the maximum value of the first hill-shaped distribution in the collector region and the cathode region is greater than the maximum value of the second hill-shaped distribution.
8. A method for manufacturing a semiconductor device, comprising: The semiconductor device comprises: A semiconductor substrate; a lower electrode in contact with a lower surface of the semiconductor substrate; A gate electrode, having The semiconductor substrate is a p-type collector region in contact with the lower electrode; an n-type cathode region in contact with the lower electrode; a buffer region, which is an n-type region having a lower n-type impurity concentration than the cathode region and is in contact with the collector region and the cathode region from above; a drift region, which is an n-type region having a lower n-type impurity concentration than the buffer region and is in contact with the buffer region from above; a p-type body region disposed above the collector region and in contact with the drift region; an n-type emitter region disposed above the collector region and separated from the drift region by the body region; a p-type anode region disposed above the cathode region and in contact with the drift region; having the gate electrode faces the body region via a gate insulating film, The manufacturing method comprises: a first implantation step of implanting a p-type impurity into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region and the collector region so as to form a first mountain-shaped distribution in a thickness direction of the semiconductor substrate; a second implantation step of implanting p-type impurities into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region and the collector region so as to form a second mountain-shaped distribution in a thickness direction of the semiconductor substrate; a third implantation step of implanting an n-type impurity into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region so as to form a third mountain-shaped distribution in a thickness direction of the semiconductor substrate; a fourth implantation step of implanting an n-type impurity into an implantation range on the lower surface of the semiconductor substrate corresponding to the cathode region so as to form a fourth mountain-shaped distribution in a thickness direction of the semiconductor substrate; having the first implantation step, the second implantation step, the third implantation step, and the fourth implantation step are performed such that the second hill-shaped distribution is located above the first hill-shaped distribution, the third hill-shaped distribution having a higher concentration than the first hill-shaped distribution is formed within a thickness range of the first hill-shaped distribution, and the fourth hill-shaped distribution having a higher concentration than the second hill-shaped distribution is formed within a thickness range of the second hill-shaped distribution. Manufacturing method.
9. 9. The method according to claim 8, wherein an end of the implantation range on the collector region side in the third implantation step is located closer to the collector region than an end of the implantation range on the collector region side in the fourth implantation step.
10. 10. The manufacturing method according to claim 8, wherein in the third implantation step and the fourth implantation step, n-type impurities are implanted into a plurality of implantation ranges spaced apart on the lower surface of the semiconductor substrate.
11. 10. The manufacturing method according to claim 8, wherein in the fourth implantation step, the n-type impurity is implanted a plurality of times at different implantation depths, thereby forming the fourth mountain-shaped distribution having a plurality of maximum values.
12. activating n-type impurities in the cathode region by laser annealing; In the third implantation step, 2×10 １５ cm －２ 10. The method according to claim 8, wherein the n-type impurity is implanted in a dose amount equal to or greater than the dose amount.
13. A manufacturing method as described in claim 8 or claim 9, wherein in the third injection process and the fourth injection process, n-type impurities are injected so that a minimum value of n-type impurity concentration that is smaller than the maximum value of the first mountain-shaped distribution and the maximum value of the second mountain-shaped distribution is formed at the boundary between the third mountain-shaped distribution and the fourth mountain-shaped distribution.
14. A manufacturing method as described in claim 8 or claim 9, wherein in the first injection process and the second injection process, p-type impurities are injected so that the maximum value of the first hill-shaped distribution is greater than the maximum value of the second hill-shaped distribution.