Switching element

Abstract

To mitigate an electric field concentration at an outer peripheral portion of an element part of a switching element.SOLUTION: A switching element comprises a gate electrode disposed in a trench. An element part in which the trench is provided includes a central portion and an outer peripheral portion. The element part includes an n-type source region. The element part and the outer peripheral portion include a p-type body region, an n-type drift region, and a plurality of p-type electric field mitigation regions. The electric field mitigation regions are disposed in a depth range including lower ends of the trenches or a depth range at a lower side of the lower ends of the trenches, and disposed at intervals in a lateral direction of a semiconductor substrate. The drift regions are disposed within the interval between the electric field mitigation regions. A value Wp / Wn obtained by dividing a width Wp of the electric field mitigation region in the lateral direction by a width Wn of the interval between the electric field mitigation regions is greater in the outer peripheral portion, than in the central portion.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a switching element.

[0002] Patent Document 1 discloses a switching element having a trench-type gate electrode. When the switching element is turned off, the drift region is depleted and an electric field is generated in the drift region. In this type of switching element, the electric field is likely to concentrate at the lower end of the trench. A technique is known in which a p-type electric field relaxation region is provided to suppress the electric field concentration at the lower end of the trench. The electric field relaxation region is disposed in a depth range including the lower end of the trench, or in a depth range below the lower end of the trench. When the electric field relaxation region is provided, the depletion layer is likely to spread around the lower end of the trench, and the electric field concentration at the lower end of the trench is relaxed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-167208 A Summary of the Invention [Problem to be solved by the invention]

[0004] It has been found that even in a switching element provided with an electric field relaxation region, the electric field tends to concentrate at the bottom end of the trench in the outer periphery of the element portion (i.e., the portion where the trench is provided). This specification proposes a technology for relaxing the electric field concentration in the outer periphery of the element portion. [Means for solving the problem]

[0005] The switching element disclosed in this specification includes a semiconductor substrate having a plurality of trenches on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The portion of the semiconductor substrate where the plurality of trenches are disposed is an element portion. The element portion has a central portion and an outer peripheral portion. The element portion has an n-type source region contacting the gate insulating film on the side surface of each of the trenches. The element portion and the outer peripheral portion have a body region, a drift region, and an electric field relaxation region. The body region is a p-type region contacting the gate insulating film on the side surface of each of the trenches. The drift region is disposed below the body region, is separated from the source region by the body region, and is an n-type region contacting the gate insulating film on the side surface of each of the trenches. The electric field buffer regions are arranged in a depth range including the bottom end of each of the trenches or in a depth range below the bottom end of each of the trenches, are connected to the body region, and are a plurality of p-type regions arranged at intervals in the lateral direction of the semiconductor substrate. The drift region is distributed within the interval between the electric field buffer regions. A value Wp / Wn obtained by dividing the width Wp of each of the electric field buffer regions in the lateral direction by the width Wn of the interval between the electric field buffer regions is larger in the outer periphery than in the central portion.

[0006] In this switching element, the electric field at the bottom end of each trench is relaxed by the electric field relaxation region. The electric field relaxation region is also arranged so that the value Wp / Wn is larger in the outer periphery than in the central portion. That is, within the depth range of the electric field relaxation region, the ratio of p-type regions is larger in the outer periphery than in the element portion. Therefore, in the outer periphery, the depletion layer is more likely to spread from the electric field relaxation region to its periphery than in the element portion. Therefore, the electric field concentration at the bottom end of the trench in the outer periphery is effectively relaxed. In this way, this switching element can relax the electric field concentration in the outer periphery of the element portion. [Brief description of the drawings]

[0007] [Figure 1] FIG. [Diagram 2] FIG. [Diagram 3] FIG. 3 is a vertical cross-sectional view of a central portion 60a along the x direction (that is, a vertical cross-sectional view taken along line III-III in FIG. 1). [Figure 4] FIG. 4 is a vertical cross-sectional view of the outer peripheral portion 60b along the x direction (that is, a vertical cross-sectional view taken along line IV-IV in FIG. 1). [Diagram 5] FIG. 2 is a vertical cross-sectional view of a central portion 60a along the y direction (that is, a vertical cross-sectional view taken along line VV in FIG. 1). [Figure 6] FIG. 6 is a vertical cross-sectional view of the outer peripheral portion 60b along the y direction (that is, a vertical cross-sectional view taken along line VI-VI in FIG. 1). [Figure 7] FIG. 11 is a cross-sectional perspective view of a switching element according to a first modified example. [Figure 8] FIG. 11 is a cross-sectional perspective view of a switching element according to a second modified example. [Figure 9] FIG. 11 is a cross-sectional perspective view of a switching element according to a third modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] An example switching element disclosed in this specification may further include a source electrode (22) covering the upper surface of the semiconductor substrate in the central portion and the peripheral portion and contacting the body region and the source region, and an insulating layer (28) covering the upper surface of the source electrode in the peripheral portion.

[0009] This configuration can prevent a high electric field from being applied to the gate insulating film in the outer periphery in a high temperature environment.

[0010] In the switching element disclosed in the present specification as an example, the outer periphery does not need to have the source region.

[0011] According to this configuration, the current flowing to the outer periphery can be suppressed, thereby stabilizing the operation of the switching element.

[0012] As shown in FIG. 1, the switching element 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si and GaN. In the following, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, a direction parallel to the upper surface 12a and perpendicular to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction. A source electrode 22 and a plurality of electrode pads 23 are provided on the upper surface 12a of the semiconductor substrate 12. The plurality of electrode pads 23 include an electrode pad for controlling the gate potential, an electrode pad for outputting the potential of the source electrode 22, an electrode pad for outputting the temperature of the semiconductor substrate 12, and the like. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12 within a range covered by the source electrode 22. Each trench 14 extends linearly in the y direction. Each trench 14 is arranged at intervals in the x direction. A main part of the switching element 10 is formed in the range where the plurality of trenches 14 are provided. Hereinafter, the area of ​​the semiconductor substrate 12 where the multiple trenches 14 are provided when the semiconductor substrate 12 is viewed from above (i.e., the area overlapping with the source electrode 22) is referred to as an element portion 60. The element portion 60 has a central portion 60a and an outer peripheral portion 60b. The outer peripheral portion 60b is provided around the central portion 60a.

[0013] 2 to 4 show the structure of the element section 60. More specifically, FIGS. 2 and 3 show the structure of the central section 60a, and FIG. 4 shows the structure of the peripheral section 60b. In FIG. 2, the source electrode 22 is omitted. As shown in FIGS. 2 to 4, the inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20.

[0014] The source electrode 22 is made of AlSi. As shown in FIG. 3, in the central portion 60a, the source electrode 22 is covered with a Ni layer 26. Although not shown, the Ni layer 26 is connected to an external electrode block by solder. As shown in FIG. 4, in the peripheral portion 60b, the source electrode 22 is covered with an insulating resin layer 28 (e.g., a polyimide layer). The insulating resin layer 28 has low thermal conductivity. Therefore, the central portion 60a has higher heat dissipation properties than the peripheral portion 60b.

[0015] 2 to 4, a drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0016] As shown in FIGS. 2 to 4, the semiconductor substrate 12 has a plurality of source regions 40, a body region 42, a drift region 44, a drain region 46, and a plurality of electric field reduction regions 48.

[0017] Each source region 40 is an n-type region having a high n-type impurity concentration. As shown in FIGS. 2 and 3, each source region 40 is disposed in an area sandwiched between trenches 14. Each source region 40 is in ohmic contact with the source electrode 22. Each source region 40 is in contact with the gate insulating film 16 on the side surface of the trench 14. The source region 40 is provided in the central portion 60a. As shown in FIG. 4, the source region 40 is not provided in the outer peripheral portion 60b.

[0018] As shown in FIGS. 2 to 4, the body region 42 is distributed across the central portion 60a and the peripheral portion 60b. The body region 42 has a plurality of contact regions 42a and low-concentration regions 42b having a lower p-type impurity concentration than each of the contact regions 42a. Each of the contact regions 42a is disposed in a range sandwiched between the trenches 14. Each of the contact regions 42a is in ohmic contact with the source electrode 22. The low-concentration regions 42b are in contact with the source regions 40 and the contact regions 42a from below. The low-concentration regions 42b are in contact with the gate insulating film 16 on the side surface of the trench 14. In the central portion 60a, the low-concentration regions 42b are in contact with the gate insulating film 16 below each of the source regions 40.

[0019] As shown in FIGS. 2 to 4, the drift region 44 is distributed across the central portion 60a and the outer peripheral portion 60b. The drift region 44 is an n-type region having a lower n-type impurity concentration than the source region 40. The drift region 44 is distributed across the lower portions of the multiple trenches 14. As shown in FIG. 2, the upper end of the drift region 44 extends into the range between the trenches 14. The drift region 44 contacts the low concentration region 42b from below within the range between the trenches 14. The drift region 44 contacts the gate insulating film 16 below the low concentration region 42b.

[0020] 2 to 4, the drain region 46 is distributed across the central portion 60a and the outer periphery 60b. The drain region 46 is an n-type region having a higher n-type impurity concentration than the drift region 44. The drain region 46 contacts the drift region 44 from below. The drain region 46 is in ohmic contact with the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.

[0021] As shown in FIGS. 2 to 4, the electric field relaxation regions 48 are provided in the central portion 60a and the outer peripheral portion 60b. Each electric field relaxation region 48 is disposed in a range surrounded by the drift region 44. Each electric field relaxation region 48 is disposed below the low concentration region 42b with a gap therebetween. A drift region 44 is distributed in the gap between each electric field relaxation region 48 and the low concentration region 42b. Each electric field relaxation region 48 extends linearly in the x direction. Each electric field relaxation region 48 is disposed with a gap in the y direction. A drift region 44 is distributed in each gap between the electric field relaxation regions 48. Hereinafter, the drift region 44 in each gap between the electric field relaxation regions 48 is referred to as a gap portion 44a. Each electric field relaxation region 48 is disposed in a range including the lower end of the trench 14 in the z direction. Therefore, each electric field relaxation region 48 contacts the gate insulating film 16 at the lower end of each trench 14.

[0022] 2, the semiconductor substrate 12 has a p-type connection region 52. The connection region 52 connects the electric field relaxation region 48 and the low concentration region 42b. Although one connection region 52 is shown in FIG. 2, at least one connection region 52 is provided for each electric field relaxation region 48. Therefore, the potential of each electric field relaxation region 48 is approximately equal to the potential of the body region 42.

[0023] 5 and 6, the symbol Wp indicates the width of each electric field relief region 48 in the y direction, and the symbol Wn indicates the width of each gap between the electric field relief regions 48 in the y direction (i.e., the width of the gap 44a). As shown in FIGS. 5 and 6, the width Wp of the electric field relief region 48 is narrower in the central portion 60a than in the outer peripheral portion 60b. Also, the width Wn of the gap 44a is wider in the central portion 60a than in the outer peripheral portion 60b. Therefore, the value Wp / Wn obtained by dividing the width Wp by the width Wn is smaller in the central portion 60a than in the outer peripheral portion 60b. The value Wp / Wn represents the ratio of the electric field relief region 48 to the gap 44a within the range in the z direction in which the electric field relief region 48 exists.

[0024] Next, the operation of the switching element 10 will be described. The switching element 10 is used in a state where a voltage is applied in a direction in which the drain electrode 24 has a higher potential than the source electrode 22. When a potential equal to or higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the body region 42 near the gate insulating film 16, and the source region 40 and the drift region 44 are connected by the channel. Therefore, electrons flow from the source electrode 22 to the drift region 44 via the source region 40 and the channel. The electrons that flow from the channel to the drift region 44 flow through the gap 44a to the drift region 44 below the electric field relaxation region 48. The electrons flow from the drift region 44 to the drain electrode 24 via the drain region 46. In this way, when a potential equal to or higher than the gate threshold is applied to the gate electrode 18, the switching element 10 is turned on.

[0025] As described above, when the switching element 10 is turned on, electrons pass through the gap 44a. In the central portion 60a, which is the main portion of the element portion 60, the value Wp / Wn is small, so the ratio of the gap 44a (i.e., the n-type region) is large within the depth range where the electric field relaxation region 48 exists. Therefore, in the central portion 60a, the resistance of the gap 44a is small. Therefore, electrons can flow with low loss in the central portion 60a. In addition, in the outer peripheral portion 60b, the value Wp / Wn is large, so the resistance of the gap 44a is high. However, fewer electrons flow in the outer peripheral portion 60b than in the central portion 60a. In particular, in this embodiment, since the source region 40 is not provided in the outer peripheral portion 60b, very few electrons flow in the gap 44a in the outer peripheral portion 60b. Therefore, even if the resistance of the gap 44a is large in the outer peripheral portion 60b, not much loss occurs. Therefore, the on-resistance of the switching element 10 is low.

[0026] In the manufacturing process, it is difficult to form the trenches 14 with high accuracy over the entire element portion 60, and the shape accuracy of the trenches 14 is likely to decrease in the outer peripheral portion 60b. Therefore, when a high current flows through the outer peripheral portion 60b, an abnormality is likely to occur in the outer peripheral portion 60b. In the switching element 10 of the embodiment, since the source region 40 is not provided in the outer peripheral portion 60b, almost no current flows through the outer peripheral portion 60b. This realizes stable operation of the switching element 10.

[0027] When the potential of the gate electrode 18 is lowered to a potential lower than the gate threshold, the channel disappears and the switching element 10 is turned off. When the switching element 10 is turned off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44. In addition, since the electric field relaxation region 48 has approximately the same potential as the body region 42, a reverse voltage is also applied to the pn junction at the interface between the electric field relaxation region 48 and the drift region 44. Therefore, a depletion layer extends from the body region 42 and the electric field relaxation region 48 to the drift region 44. The depleted drift region 44 holds the voltage between the drain electrode 24 and the source electrode 22. The depletion layer extending from the electric field relaxation region 48 to the drift region 44 depletes the drift region 44 around the lower end of the trench 14. In this way, the drift region 44 is depleted around the lower end of the trench 14, thereby suppressing electric field concentration in the gate insulating film 16 covering the lower end of the trench 14.

[0028] In addition, since there is no trench 14 outside the element portion 60, the electric field is particularly likely to concentrate at the lower end of the trench 14 in the outer peripheral portion 60b. In contrast, in the switching element 10 of the embodiment, the value Wp / Wn is large in the outer peripheral portion 60b, and the ratio of the electric field relaxation region 48 (i.e., p-type region) to the interval portion 44a (i.e., n-type region) is large. Therefore, in the outer peripheral portion 60b, the depletion layer is likely to spread from the electric field relaxation region 48 to its periphery. Therefore, the electric field concentration relaxation effect by the electric field relaxation region 48 is higher in the outer peripheral portion 60b than in the central portion 60a. Therefore, the electric field concentration at the lower end of the trench 14 in the outer peripheral portion 60b can be suppressed. Note that, as described above, the outer peripheral portion 60b has lower heat dissipation than the central portion 60a, and the outer peripheral portion 60b is more likely to become hotter than the central portion 60a. If a high electric field is applied to the gate insulating film 16 in a high temperature state, the gate insulating film 16 is likely to deteriorate. By suppressing the electric field concentration on the gate insulating film 16 in the outer periphery 60b which is prone to high temperatures, deterioration of the gate insulating film 16 can be suppressed more effectively.

[0029] In the above-described embodiment, the electric field relaxation regions 48 extend linearly in the x direction (i.e., the direction intersecting the trenches 14) and are spaced apart in the y direction. However, the electric field relaxation regions 48 may extend linearly in the y direction (i.e., the direction parallel to the trenches 14) and be spaced apart in the x direction. In this case, as shown in FIG. 7, the electric field relaxation regions 48 may be arranged between the trenches 14 in the x direction, or as shown in FIG. 8, the electric field relaxation regions 48 may be arranged at positions overlapping with the trenches 14 in the x direction (i.e., below the trenches 14). Even in the configurations of FIGS. 7 and 8, the electric field concentration on the gate insulating film 16 in the outer periphery 60b can be suppressed by making the value Wp / Wn larger in the outer periphery 60b than in the central portion 60a.

[0030] In the above-described embodiment, the electric field relaxation region 48 is disposed in a depth range including the lower end of the trench 14, but the electric field relaxation region 48 may be disposed in a depth range below the lower end of the trench 14. For example, when the electric field relaxation region 48 extends linearly in a direction intersecting the trench 14, the electric field relaxation region 48 may be disposed below the lower end of the trench 14 as shown in FIG. 9. Also, when the electric field relaxation region 48 extends linearly parallel to the trench 14 as shown in FIGS. 7 and 8, the electric field relaxation region 48 may be disposed below the lower end of the trench 14. Even when the electric field relaxation region 48 is disposed below the lower end of the trench 14, electric field concentration at the lower end of the trench 14 can be suppressed.

[0031] In the above-described embodiment, the source region 40 is not provided in the outer periphery 60b, but the source region 40 may be provided in the outer periphery 60b.

[0032] In the above-described embodiment, the width Wp is wider in the outer peripheral portion 60b than in the central portion 60a, and the width Wn is narrower in the outer peripheral portion 60b than in the central portion 60a. However, as long as the condition that the value Wp / Wn is larger in the outer peripheral portion 60b than in the central portion 60a is satisfied, the widths Wp and Wn may be set in any manner in the central portion 60a and the outer peripheral portion 60b. For example, the width Wp may be wider in the outer peripheral portion 60b than in the central portion 60a, and the width Wn may be equal in the outer peripheral portion 60b and the central portion 60a. Also, for example, the width Wp may be equal in the outer circumferential portion 60b and the central portion 60a, and the width Wn may be narrower in the outer circumferential portion 60b than in the central portion 60a.

[0033] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0034] 18: gate electrode, 22: source electrode, 24: drain electrode, 28: insulating resin layer, 40: source region, 42: body region, 44: drift region, 44a: gap, 46: drain region, 48: electric field relaxation region, 60a: central portion, 60b: peripheral portion

Claims

1. A switching element, A semiconductor substrate having a plurality of trenches (14) formed on an upper surface thereof; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; having A portion of the semiconductor substrate in which the plurality of trenches are provided is an element portion (60), The element portion has a central portion (60a) and an outer peripheral portion (60b), the element portion has an n-type source region (40) in contact with the gate insulating film on a side surface of each of the trenches, The central portion has the source region (40); The outer periphery does not have the source region (40); The element portion and the outer periphery portion a p-type body region (42) contacting the gate insulating film on the side surface of each of the trenches; an n-type drift region (44) disposed below the body region, separated from the source region by the body region, and in contact with the gate insulating film on the side of each of the trenches; a plurality of p-type electric field relaxation regions (48) arranged in a depth range including the lower end of each of the trenches or in a depth range below the lower end of each of the trenches, connected to the body region, and arranged at intervals in the lateral direction of the semiconductor substrate; having the drift region is distributed within the interval between the electric field reduction regions; A value Wp / Wn obtained by dividing the width Wp of each of the electric field buffer regions in the lateral direction by the width Wn of the space between the electric field buffer regions is larger in the outer periphery than in the central portion. Switching element.

2. a source electrode (22) covering the upper surface of the semiconductor substrate at the central portion and the peripheral portion, contacting the body region and the source region at the central portion and contacting the body region at the peripheral portion; an insulating layer (28) covering the upper surface of the source electrode at the outer periphery; Further comprising The switching element according to claim 1 .

Images