Semiconductor device and manufacturing method for the same

Abstract

To provide a technique of suppressing collapse of a charge balance between an n-type column and a p-type column in a semiconductor device with a super junction structure.SOLUTION: A semiconductor device (1, 2, 3) includes a semiconductor layer (10) with a super junction structure in which first columns (14a, 14b) of a first conductivity type and second columns (14a, 14b) of a second conductivity type are alternately disposed repeatedly along at least one direction. The first column includes a first column high-concentration layer (142, 146) and a first column low-concentration layer (144, 148) that is adjacent to the first column high-concentration layer in the one direction and has lower carrier concentration than the first column high-concentration layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present specification relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A superjunction structure in which n-type columns and p-type columns are alternately arranged repeatedly along at least one direction has been proposed as a structure that achieves both low on-resistance and high breakdown voltage. Patent documents 1 to 3 disclose examples of semiconductor devices equipped with such a superjunction structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-245082 A [Patent Document 2] JP 2009-188177 A [Patent Document 3] JP 2010-056154 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to further improve the compatibility between low on-resistance and high breakdown voltage, it is necessary to increase the impurity concentration of each of the n-type columns and p-type columns constituting the superjunction structure. If the impurity concentration of each of the n-type columns and p-type columns becomes high, it becomes difficult to form the n-type columns and p-type columns by counter-doping p-type ions in the n-type semiconductor layer, for example. This is because a large amount of p-type ions must be implanted into the high-concentration n-type semiconductor layer, which causes problems such as defects. For this reason, in order to manufacture a semiconductor device that highly satisfies both low on-resistance and high breakdown voltage, each of the n-type columns and p-type columns must be formed by ion implantation. When each of the n-type columns and p-type columns is formed by ion implantation, if the position of the n-type columns and the p-type columns in the repeating direction is misaligned, the charge balance between the n-type columns and the p-type columns is lost, and a situation in which the desired characteristics cannot be exhibited may occur.

[0005] The present specification provides a technique for suppressing disruption of the charge balance between n-type columns and p-type columns in a semiconductor device having a superjunction structure. [Means for solving the problem]

[0006] The semiconductor device (1, 2, 3) disclosed in the present specification may include a semiconductor layer (10) including a superjunction structure in which first columns (14a, 14b) of a first conductivity type and second columns (14a, 14b) of a second conductivity type are alternately and repeatedly arranged along at least one direction. The first columns may include a first column high concentration layer (142, 146) and a first column low concentration layer (144, 148) adjacent to the first column high concentration layer in the one direction and having a carrier concentration lower than that of the first column high concentration layer. Here, the first column may be an n-type column and the second column may be a p-type column, or the first column may be a p-type column and the second column may be an n-type column. The second column may also include a second column high concentration layer and a second column low concentration layer. In this semiconductor device, the charge amount of the first column substantially depends on the first column high concentration layer. Therefore, if the first column high concentration layer is not formed at a position overlapping with the second column, the charge amount of the first column will be a desired value. In this semiconductor device, the first column low concentration layer is provided adjacent to the first column high concentration layer, so that the positional deviation of the first column high concentration layer can be contained within the range of the first column low concentration layer. Therefore, even if the first column high concentration layer is misaligned, the first column high concentration layer is prevented from being formed at a position overlapping with the second column. As a result, the charge amount of the first column can be a desired value, and thus disruption of the charge balance between the first column and the second column is prevented.

[0007] This specification can disclose one method for manufacturing the semiconductor device. This manufacturing method may include the steps of: forming a first shielding layer (52, 54) on the surface of the semiconductor layer, the first shielding layer having an opening corresponding to the formation range of the first column low concentration layer; measuring the alignment error of the first shielding layer; forming the first column low concentration layer by implanting ions into the semiconductor layer through the opening of the first shielding layer; forming a second shielding layer (56, 58) on the surface of the semiconductor layer, the second shielding layer having an opening corresponding to the formation range of the first column high concentration layer according to the measured alignment error; and forming the first column high concentration layer by implanting ions into the semiconductor layer through the opening of the second shielding layer. According to this manufacturing method, the tendency of the alignment error can be grasped by measuring the alignment error when the first shielding layer is formed. Therefore, the alignment error of the second shielding layer can be suppressed by forming the second shielding layer under conditions that suppress the tendency of the alignment error. As a result, the positional error of the first column high concentration layer can be suppressed.

[0008] This specification may disclose another method for manufacturing the semiconductor device. This manufacturing method may include the steps of: forming a first shielding layer (52, 54) on the surface of the semiconductor layer, the first shielding layer having an opening corresponding to the range of formation of the first column low concentration layer; measuring the opening width (52W, 54W) of the first shielding layer; forming the first column low concentration layer by implanting ions into the semiconductor layer through the opening of the first shielding layer; forming a second shielding layer (56, 58) on the surface of the semiconductor layer, the second shielding layer having an opening corresponding to the range of formation of the first column high concentration layer according to the measured opening width; and forming the first column high concentration layer by implanting ions into the semiconductor layer through the opening of the second shielding layer. According to this manufacturing method, by measuring the opening width of the first shielding layer when the first shielding layer is formed, it is possible to grasp whether the opening width tends to be wider or narrower than the design value. By forming the second shielding layer under conditions that suppress the tendency of the opening width to be wider or narrower, the opening width of the second shielding layer can be made closer to a design value, and as a result, the charge amount of the first column high-concentration layer can be made to a desired value. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a main part of a semiconductor device according to a first embodiment disclosed in this specification. [Diagram 2] 2A to 2C are schematic cross-sectional views of essential parts of the process for manufacturing the semiconductor device shown in FIG. [Diagram 3] 2A to 2C are schematic cross-sectional views of essential parts of the process for manufacturing the semiconductor device shown in FIG. [Figure 4] 2A to 2C are schematic cross-sectional views of essential parts of the process for manufacturing the semiconductor device shown in FIG. [Diagram 5] 2A to 2C are schematic cross-sectional views of essential parts of the process for manufacturing the semiconductor device shown in FIG. [Figure 6] 2A to 2C are schematic cross-sectional views of essential parts of the process for manufacturing the semiconductor device shown in FIG. [Figure 7] 1 is a schematic cross-sectional view of a main part of a semiconductor device according to a second embodiment disclosed in this specification. [Figure 8] 1 is a schematic cross-sectional view of a main part of a semiconductor device according to a second embodiment disclosed in this specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the semiconductor device of each embodiment will be described with reference to the drawings. Components common to each embodiment will be given the same reference numerals, and their description may be omitted. For the purpose of clarity of illustration, only one of the components that is repeatedly arranged will be given the reference numeral.

[0011] (First embodiment) 1 is a schematic cross-sectional view of a main part of a semiconductor device 1. The semiconductor device 1 is a type of power semiconductor device called a MOSFET, and includes a semiconductor layer 10, a drain electrode 22 covering the lower surface of the semiconductor layer 10, a source electrode 24 covering the upper surface of the semiconductor layer 10, and a plurality of trench gates 30 provided in the upper layer portion of the semiconductor layer 10.

[0012] The semiconductor layer 10 is not particularly limited, but may be, for example, a 4H silicon carbide layer. The crystal plane of the upper surface of the semiconductor layer 10 may be inclined by an off angle with respect to the (0001) Si plane. The off angle is not particularly limited, but may be, for example, 4°. Instead of a silicon carbide layer, the semiconductor layer 10 may be a silicon layer, a nitride semiconductor layer, or a gallium oxide layer. The semiconductor layer 10 may be a n + A drain region 12 of n-type, a drift region 14 of n-type, a body region 16 of p-type, and + A source region 18 of p + and a body contact region 19 of the same type.

[0013] The drain region 12 is disposed in the lower layer of the semiconductor layer 10, and is provided at a position exposed on the lower surface of the semiconductor layer 10. The drain region 12 is in ohmic contact with a drain electrode 22 that covers the lower surface of the semiconductor layer 10.

[0014] The drift region 14 is provided between the drain region 12 and the body region 16, and has a plurality of n-type columns 14a and a plurality of p-type columns. The n-type columns 14a and the p-type columns 14b are arranged so as to be alternately repeated along at least one direction in the cross section of the semiconductor layer 10, forming a superjunction structure. The direction in which the n-type columns 14a and the p-type columns 14b are alternately repeated in the cross section of the semiconductor layer 10 is hereinafter referred to as the "repeating direction." The n-type columns 14a and the p-type columns 14b are not particularly limited, and may be arranged, for example, in a stripe pattern when viewed from a direction perpendicular to the top surface of the semiconductor layer 10 (hereinafter referred to as "when viewed in a plan view").

[0015] The n-column 14a has an n-column high concentration layer 142 and a pair of n-column low concentration layers 144. The n-column high concentration layer 142 extends between the drain region 12 and the body region 16 and has a flat plate shape. Each of the pair of n-column low concentration layers 144 also extends between the drain region 12 and the body region 16 and has a flat plate shape. The pair of n-column low concentration layers 144 contact both side surfaces of the n-column high concentration layer 142 in the repeating direction. The n-type impurity carrier concentration of the n-column low concentration layer 144 is lower than the n-type impurity carrier concentration of the n-column high concentration layer 142. The n-type impurity carrier concentration of the n-column low concentration layer 144 is not particularly limited, but may be, for example, 1 / 5 or less of the n-type impurity carrier concentration of the n-column high concentration layer 142, or may be 1 / 10 or less. When the carrier concentration of n-type impurities is measured along the repeating direction, it is confirmed that there is an inflection point between the n-type column high concentration layer 142 and the n-type column low concentration layer 144, and that there are at least two layers with different carrier concentrations in the n-type column 14a, the n-type column high concentration layer 142 and the n-type column low concentration layer 144. The width of the n-type column low concentration layer 144 in the repeating direction is smaller than the width of the n-type column high concentration layer 142.

[0016] The p-column 14b has a p-column high concentration layer 146 and a pair of p-column low concentration layers 148. The p-column high concentration layer 146 extends between the drain region 12 and the body region 16 and has a flat plate shape. Each of the pair of p-column low concentration layers 148 also extends between the drain region 12 and the body region 16 and has a flat plate shape. The p-column low concentration layer 148 contacts both side surfaces of the p-column high concentration layer 146 in the repeating direction. The carrier concentration of n-type impurities in the p-column low concentration layer 148 is lower than the carrier concentration of p-type impurities in the p-column high concentration layer 146. The carrier concentration of n-type impurities in the p-column low concentration layer 148 is not particularly limited, but may be, for example, 1 / 5 or less, or even 1 / 10 or less, of the carrier concentration of p-type impurities in the p-column high concentration layer 146. When the carrier concentration of the p-type impurity is measured along the repeating direction, it is confirmed that there is an inflection point between the p-type column high concentration layer 146 and the p-type column low concentration layer 148, and that there are at least two layers with different carrier concentrations in the p-type column 14b, the p-type column high concentration layer 146 and the p-type column low concentration layer 148. The width of the p-type column low concentration layer 148 in the repeating direction is smaller than the width of the p-type column high concentration layer 146.

[0017] In the manufacturing method described below, the n-type column high concentration layer 142, the n-type column low concentration layer 144, the p-type column high concentration layer 146, and the p-type column low concentration layer 148 are each formed by ion implantation. However, either the n-type column low concentration layer 144 or the p-type column low concentration layer 148 may be an epitaxial layer.

[0018] When the drift region 14 is depleted, the n-columns 14a are positively charged and the p-columns 14b are negatively charged. When the amount of positive charge in the n-columns 14a and the amount of negative charge in the p-columns 14b are balanced at a high concentration, the drift region 14 is depleted well, and the breakdown voltage of the semiconductor device 1 is improved. In the semiconductor device 1, the amount of charge in the n-columns 14a depends on the n-column high concentration layer 142, which is high in concentration and wide. Similarly, in the semiconductor device 1, the amount of charge in the p-columns 14b depends on the p-column high concentration layer 146, which is high in concentration and wide. Therefore, the semiconductor device 1 is designed to achieve charge balance between the n-column high concentration layer 142 and the p-column high concentration layer 146.

[0019] The body region 16 is provided on the drift region 14 and is disposed in the upper layer portion of the semiconductor layer 10. The body region 16 is provided between the n-type column 14a of the drift region 14 and the source region 18, contacts both the n-type column 14a and the source region 18, and separates the n-type column 14a from the source region 18. The carrier concentration of the p-type impurity in the body region 16 is adjusted according to a desired gate threshold voltage.

[0020] The source region 18 is provided on the body region 16, is disposed in the upper portion of the semiconductor layer 10, and is provided at a position exposed on the surface of the semiconductor layer 10. The source region 18 contacts a side surface of the trench gate 30. The source region 18 is in ohmic contact with a source electrode 24 that covers the surface of the semiconductor layer 10.

[0021] The body contact region 19 is provided on the body region 16, is disposed in the upper layer portion of the semiconductor layer 10, and is provided at a position exposed on the surface of the semiconductor layer 10. The body contact region 19 is in ohmic contact with a source electrode 24 that covers the surface of the semiconductor layer 10.

[0022] The trench gate 30 is filled in a trench formed in the upper layer portion of the semiconductor layer 10, and penetrates the source region 18 and the body region 16 to reach the n-type column 14a of the drift region 14. In this example, the trench gate 30 extends along the longitudinal direction of the n-type column 14a and the p-type column 14b when the semiconductor layer 10 is viewed in a plan view. Instead of this example, the trench gate 30 may extend along the repeating direction of the n-type column 14a and the p-type column 14b, that is, along a direction perpendicular to the longitudinal direction of the n-type column 14a and the p-type column 14b when the semiconductor layer 10 is viewed in a plan view. The trench gate 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is formed of polysilicon containing impurities and faces the semiconductor layer 10 via the gate insulating film 34. In particular, the gate electrode 32 faces the body region 16 at a portion separating the n-type column 14a of the drift region 14 from the source region 18 via the gate insulating film 34. The gate insulating film 34 is made of silicon oxide and covers the inner wall of the trench.

[0023] Next, the operation of the semiconductor device 1 will be described with reference to FIG. 1. When the potential of the gate electrode 32 of the trench gate 30 is controlled to be more positive than the source electrode 24 and higher than the threshold value in a state in which the potential of the drain electrode 22 is more positive than the potential of the source electrode 24, the semiconductor device 1 turns on. At this time, an inversion layer is formed in the body region 16 at a portion separating the source region 18 and the n-type column 14a of the drift region 14. Electrons supplied from the source region 18 reach the n-type column 14a of the drift region 14 via the channel of the inversion layer. The electrons that reach the n-type column 14a flow to the drain region 12 via the n-type column 14a. In particular, the n-type column 14a has an n-type column high concentration layer 142 with a high carrier concentration of n-type impurities, so that the semiconductor device 1 can have a characteristic of low on-resistance.

[0024] When the potential of the gate electrode 32 of the trench gate 30 is controlled to be the same as the potential of the source electrode 24, the channel of the inversion layer disappears and the semiconductor device 1 is turned off. The multiple n-type columns 14a and multiple p-type columns 14b constituting the superjunction structure are substantially completely depleted, and a wide range of the drift region 14 is depleted. In addition, since the drift region 14 has a superjunction structure, the electric field distribution of the drift region 14 is leveled in the thickness direction. Therefore, the drift region 14 can bear a large potential difference, and the semiconductor device 1 can have a high breakdown voltage characteristic.

[0025] Next, a description will be given of a process for forming a superjunction structure in the manufacturing method of the semiconductor device 1. For other processes for manufacturing the semiconductor device 1, known manufacturing techniques can be used.

[0026] First, as shown in Figure 2, + First, an n-type silicon carbide substrate, that is, drain region 12, is prepared. Next, an n-type silicon carbide epitaxial layer 140 is grown from the surface of drain region 12 by using an epitaxial growth technique such as, but not limited to, a CVD (Chemical Vapor Deposition) method. Note that epitaxial layer 140 constitutes at least a part of semiconductor layer 10, and may be referred to as a semiconductor layer.

[0027] Next, as shown in FIG. 3, a shielding layer 52 is formed on the epitaxial layer 140 using a photolithography technique. The shielding layer 52 is an example of a first shielding layer. The shielding layer 52 is patterned to have an opening corresponding to the range in which the n-type column low concentration layer 144 is formed. Here, an opening width 52W of the shielding layer 52 is measured. The opening width 52W of the shielding layer 52 is the width in the short direction of the opening of the shielding layer 52, and is the width in the repeating direction of the superjunction structure. Next, n-type impurity ions are implanted into the epitaxial layer 140 through the opening of the shielding layer 52 using an ion implantation technique to form the n-type column low concentration layer 144. The n-type impurity ions are not particularly limited, but may be, for example, nitrogen ions. After the ion implantation, the shielding layer 52 is removed.

[0028] Next, as shown in FIG. 4, a shielding layer 54 is formed on the epitaxial layer 140 using a photolithography technique. The shielding layer 54 is an example of a first shielding layer. The shielding layer 54 is patterned to have an opening corresponding to the formation range of the p-type column low concentration layer 148. Here, an opening width 54W of the shielding layer 54 is measured. The opening width 54W of the shielding layer 54 is the width in the short direction of the opening of the shielding layer 54, and is the width in the repeating direction of the superjunction structure. Next, p-type impurity ions are implanted into the epitaxial layer 140 through the opening of the shielding layer 54 using an ion implantation technique to form the p-type column low concentration layer 148. The p-type impurity ions are not particularly limited, but may be, for example, aluminum ions. After the ion implantation, the shielding layer 54 is removed. The p-type column low concentration layer 148 may be formed before the n-type column low concentration layer 144 (see FIG. 3).

[0029] Next, as shown in FIG. 5, a shielding layer 56 is formed on the epitaxial layer 140 by using a photolithography technique. The shielding layer 56 is an example of a second shielding layer. The shielding layer 56 is patterned to have an opening corresponding to the formation range of the n-type column high concentration layer 142. Here, a plurality of types of photomasks for exposing the shielding layer 56 are prepared, and are appropriately selected according to the measured opening width 52W (see FIG. 3) of the shielding layer 52. For example, when the measured opening width 52W of the shielding layer 52 is wider than the design value, the opening width tends to be wider than the design value, so a type of photomask for exposing the shielding layer 56 with an opening width narrower than the design value is selected. Conversely, when the measured opening width 52W of the shielding layer 52 is narrower than the design value, the opening width tends to be narrower than the design value, so a type of photomask for exposing the shielding layer 56 with an opening width wider than the design value is selected. This allows the opening width 56W of the shielding layer 56 to be close to the design value. Next, using ion implantation technology, n-type impurity ions are implanted into the epitaxial layer 140 through the openings in the shielding layer 56 to form the n-type column high concentration layer 142. The n-type impurity ions are not particularly limited, but may be, for example, nitrogen ions. As described above, since the opening width 56W of the shielding layer 56 is close to the design value, the carrier concentration of the n-type impurity in the n-type column high concentration layer 142 is at a desired value. After the ion implantation, the shielding layer 56 is removed.

[0030] Next, as shown in FIG. 6, a shielding layer 58 is formed on the epitaxial layer 140 by using a photolithography technique. The shielding layer 58 is an example of a second shielding layer. The shielding layer 58 is patterned to have an opening corresponding to the formation range of the p-type column high concentration layer 146. Here, a plurality of types of photomasks for exposing the shielding layer 58 are prepared, and are appropriately selected according to the measured opening width 54W of the shielding layer 54 (see FIG. 4). For example, when the measured opening width 54W of the shielding layer 54 is wider than the design value, the opening width tends to be wider than the design value, so a type of photomask for exposing the shielding layer 58 is selected whose opening width is narrower than the design value. Conversely, when the measured opening width 54W of the shielding layer 54 is narrower than the design value, the opening width tends to be narrower than the design value, so a type of photomask for exposing the shielding layer 58 is selected whose opening width is wider than the design value. This allows the opening width 58W of the shielding layer 58 to be close to the design value. Next, using ion implantation technology, n-type impurity ions are implanted into the epitaxial layer 140 through the opening of the shielding layer 58 to form the p-type column high concentration layer 146. The p-type impurity ions are not particularly limited, but aluminum ions may be used, for example. As described above, since the opening width 58W of the shielding layer 58 is close to the design value, the carrier concentration of the p-type impurity in the p-type column high concentration layer 146 is a desired value. After the ion implantation, the shielding layer 58 is removed. The p-type column high concentration layer 146 may be formed before the n-type column high concentration layer 142 (see FIG. 5).

[0031] Through these steps, a superjunction structure in which n-columns 14a and p-columns 14b are alternately and repeatedly arranged in the semiconductor layer 10 can be formed. In the above manufacturing method, the n-column high concentration layer 142 and the p-column high concentration layer 146 are not formed in a positional relationship in which they are in direct contact with each other. Since the n-column low concentration layer 144 is provided adjacent to the n-column high concentration layer 142, even if the position of the opening of the shielding layer 56 for forming the n-column high concentration layer 142 is shifted in the repeating direction, the n-column high concentration layer 142 is formed to be within the range of the n-column low concentration layer 144. Similarly, since the p-column low concentration layer 148 is provided adjacent to the p-column high concentration layer 146, even if the position of the opening of the shielding layer 58 for forming the p-column high concentration layer 146 is shifted in the repeating direction, the p-column high concentration layer 146 is formed to be within the range of the p-column low concentration layer 148. In this manner, in the above-described manufacturing method, even if the shielding layers 56, 58 are misaligned in the repeating direction, the n-type column high concentration layer 142 and the p-type column high concentration layer 146 are prevented from being formed to overlap each other.

[0032] As described above, the semiconductor device 1 is designed so that the charge balance between the n-columns 14a and the p-columns 14b is ensured by achieving charge balance between the n-column high concentration layer 142 and the p-column high concentration layer 146. In the semiconductor device 1, the n-column high concentration layer 142 and the p-column high concentration layer 146 are prevented from being formed so as to overlap, so that the charge balance between the n-columns 14a and the p-columns 14b is prevented from being disrupted. Therefore, the semiconductor device 1 manufactured by the above manufacturing method can achieve both low on-resistance and high withstand voltage.

[0033] Furthermore, in the above manufacturing method, by measuring the opening widths 52W, 54W of the shielding layers 52, 54, it is possible to grasp whether the opening widths 52W, 54W tend to be wider or narrower than the design value. Thus, by forming the shielding layers 56, 58 using a photomask that suppresses the tendency of the opening width to be wider or narrower, the opening widths 56W, 58W of the shielding layers 56, 58 can be made closer to the design value. As a result, the charge amount of the n-type column high concentration layer 142 and the p-type column high concentration layer 146 can be made to a desired value. In this respect, the semiconductor device 1 manufactured by the above manufacturing method can achieve both low on-resistance and high breakdown voltage.

[0034] In the above manufacturing method, the alignment deviation of the shielding layer 52 may be measured when the shielding layer 52 is formed. The alignment deviation refers to a positional deviation from a design position in a relative positional relationship with respect to the alignment mark. The alignment deviation is not particularly limited, but may be described, for example, in a coordinate system defined based on the alignment mark. For example, when an XY orthogonal coordinate system is defined based on the alignment mark, the alignment mark deviation is described as a positional deviation of two components in the X direction and the Y direction. In the above manufacturing method, the tendency of the alignment deviation can be grasped by measuring the alignment deviation when the shielding layer 52 is formed. Therefore, when the shielding layer 56 is formed, the shielding layer 56 is formed under conditions that suppress the tendency of the alignment deviation. Specifically, by forming the shielding layer 56 at a position taking into consideration an alignment error with respect to the center of the low concentration n-column layer 144 so that the center of the low concentration n-column layer 144 coincides with the center of the high concentration n-column layer 142, the center of the opening of the shielding layer 56 coincides with the center of the low concentration n-column layer 144, thereby forming the shielding layer 56. As a result, the high concentration n-column layer 142 is formed within the range of the low concentration n-column layer 144.

[0035] Similarly, in the above manufacturing method, the misalignment of the shielding layer 54 may be measured when the shielding layer 54 is formed. In the above manufacturing method, when the shielding layer 58 is formed, the shielding layer 58 is formed under conditions that suppress the tendency of misalignment. Specifically, the shielding layer 58 is formed at a position that takes into account the misalignment with respect to the center of the low concentration p-column layer 148 so that the center of the low concentration p-column layer 148 and the center of the high concentration p-column layer 146 coincide with each other, so that the shielding layer 58 is formed with the center of the opening of the shielding layer 58 coinciding with the center of the low concentration p-column layer 148. As a result, the high concentration p-column layer 146 is formed to be within the range of the low concentration p-column layer 148.

[0036] It is to be noted that the step of feeding back the misalignment of the shielding layer does not need to be performed together with the step of feeding back the opening width of the shielding layer. Only the step of feeding back the misalignment of the shielding layer may be performed without performing the step of feeding back the opening width of the shielding layer.

[0037] Second embodiment FIG. 7 is a schematic cross-sectional view of a main part of the semiconductor device 2. In the semiconductor device 2, the p-columns 14b are composed of only the p-column high-concentration layers 146. That is, the p-columns 14b have a constant concentration distribution of p-type impurities along the repeating direction. In this example, the n-column low-concentration layers 144 are provided between the n-column high-concentration layers 142 and the p-column high-concentration layers 146, so that the n-column high-concentration layers 142 and the p-column high-concentration layers 146 are prevented from being formed to overlap each other. Since the charge balance between the n-columns 14a and the p-columns 14b is prevented from being disturbed, the semiconductor device 2 can achieve both low on-resistance and high breakdown voltage.

[0038] The n-column low concentration layer 144 may be an epitaxial layer. In this case, the n-column high concentration layer 142 and the p-column high concentration layer 146 are formed in an epitaxial layer having a low concentration of n-type impurities at a distance from each other in the repeating direction, thereby manufacturing the semiconductor device 2. Since the number of steps can be reduced, the semiconductor device 2 can be manufactured at low manufacturing costs. Also, a p-column low concentration layer may be provided instead of the n-column low concentration layer 144.

[0039] Third embodiment FIG. 8 is a schematic cross-sectional view of a main part of the semiconductor device 3. The semiconductor device 3 is a modified example of the semiconductor device 2, and the n-column low concentration layer 144 is adjacent to the bottom surface of the n-column high concentration layer 142 as well. In this example, the n-column low concentration layer 144 is also adjacent to the bottom surface of the p-column 14b. In the semiconductor device 3, even if the bottom surface of the p-column 14b is formed deep, the n-column low concentration layer 144 is provided adjacent to the bottom surface of the n-column high concentration layer 142, so that an increase in resistance due to the JFET effect can be suppressed. Note that the p-column low concentration layer may be provided so as to contact the bottom surface of the p-column high concentration layer 146.

[0040] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0041] (Feature 1) A semiconductor device (1, 2, 3), a semiconductor layer (10) including a superjunction structure in which first columns (14a, 14b) of a first conductivity type and second columns (14a, 14b) of a second conductivity type are alternately and repeatedly arranged along at least one direction; the first column includes a first column high concentration layer (142, 146) and a first column low concentration layer (144, 148) adjacent to the first column high concentration layer in the one direction and having a carrier concentration lower than that of the first column high concentration layer.

[0042] (Feature 2) 2. The semiconductor device according to feature 1, wherein the first column low concentration layer has a carrier concentration equal to or less than 1 / 5 of the carrier concentration of the first column high concentration layer.

[0043] (Feature 3) 3. The semiconductor device according to feature 1 or 2, wherein the second column has a constant concentration distribution along the one direction.

[0044] (Feature 4) 4. The semiconductor device according to any one of Features 1 to 3, wherein the first column low-concentration layer is also adjacent to a bottom surface of the first column high-concentration layer.

[0045] (Feature 5) the first column is an n-type column; 5. The semiconductor device according to claim 4, wherein the second column is a p-type column.

[0046] (Feature 6) 6. The semiconductor device according to feature 5, wherein the first column low concentration layer is also adjacent to a bottom surface of the second column.

[0047] (Feature 7) a semiconductor layer (10) including a superjunction structure in which first columns (14a, 14b) of a first conductivity type and second columns (14a, 14b) of a second conductivity type are alternately and repeatedly arranged along at least one direction; a first column having a first column high concentration layer (142, 146) and a first column low concentration layer (144, 148) adjacent to the first column high concentration layer in the one direction and having a carrier concentration lower than that of the first column high concentration layer, forming a first shielding layer (52, 54) on a surface of the semiconductor layer, the first shielding layer having an opening corresponding to a region in which the first column low concentration layer is to be formed; measuring the misalignment of the first shielding layer; implanting ions into the semiconductor layer through the openings in the first shielding layer to form the first columnar low concentration layer; forming a second shielding layer (56, 58) on the surface of the semiconductor layer, the second shielding layer having an opening corresponding to a formation range of the first column high concentration layer in accordance with the measured alignment deviation; and forming the first column high concentration layer by implanting ions into the semiconductor layer through the opening in the second shielding layer.

[0048] (Feature 8) a semiconductor layer (10) including a superjunction structure in which first columns (14a, 14b) of a first conductivity type and second columns (14a, 14b) of a second conductivity type are alternately and repeatedly arranged along at least one direction; a first column having a first column high concentration layer (142, 146) and a first column low concentration layer (144, 148) adjacent to the first column high concentration layer in the one direction and having a carrier concentration lower than that of the first column high concentration layer, forming a first shielding layer (52, 54) on a surface of the semiconductor layer, the first shielding layer having an opening corresponding to a region in which the first column low concentration layer is to be formed; Measuring the opening width (52W, 54W) of the first shielding layer; implanting ions into the semiconductor layer through the openings in the first shielding layer to form the first columnar low concentration layer; forming a second shielding layer (56, 58) on the surface of the semiconductor layer, the second shielding layer having an opening corresponding to a formation range of the first column high concentration layer in accordance with the measured opening width; and forming the first column high concentration layer by implanting ions into the semiconductor layer through the opening in the second shielding layer.

[0049] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful. [Explanation of symbols]

[0050] 1, 2, 3: semiconductor device, 10: semiconductor layer, 12: drain region, 14: drift region, 14a: n-type column, 14b: p-type column, 16: body region, 18: source region, 19: body contact region, 22: drain electrode, 24: source electrode, 30: trench gate, 32: gate electrode, 34: gate insulating film, 142: n-type column high concentration layer, 144: n-type column low concentration layer, 146: p-type column high concentration layer, 148: p-type column low concentration layer

Claims

1. A semiconductor device (1, 2, 3), The present invention comprises a semiconductor layer (10) including a superjunction structure in which first columns (14a) of a first conductivity type and second columns (14b) of a second conductivity type are alternately and repeatedly arranged along at least one direction, the first column is an n-type column; the second column is a p-type column; the first column includes a first column high concentration layer (142) and a first column low concentration layer (144) adjacent to both sides of the first column high concentration layer in the one direction and having a carrier concentration lower than that of the first column high concentration layer; the second column includes a second column high concentration layer (146) and a second column low concentration layer (148) adjacent to both side surfaces of the second column high concentration layer in the one direction and having a carrier concentration lower than that of the second column high concentration layer.

2. 2. The semiconductor device according to claim 1, wherein the carrier concentration of said first column low concentration layer is equal to or less than 1 / 5 of the carrier concentration of said first column high concentration layer.

3. 2. The semiconductor device according to claim 1, wherein said first columnar lightly doped layer is also adjacent to a bottom surface of said first columnar heavily doped layer.

4. 2. The semiconductor device according to claim 1, wherein said first column low-concentration layer is also adjacent to a bottom surface of said second column.

5. A semiconductor layer (10) including a superjunction structure in which first columns (14a, 14b) of a first conductivity type and second columns (14a, 14b) of a second conductivity type are alternately and repeatedly arranged along at least one direction, a first column having a first column high concentration layer (142, 146) and a first column low concentration layer (144, 148) adjacent to the first column high concentration layer in the one direction and having a carrier concentration lower than that of the first column high concentration layer, forming a first shielding layer (52, 54) on a surface of the semiconductor layer, the first shielding layer having an opening corresponding to a region in which the first column low concentration layer is to be formed; measuring the misalignment of the first shielding layer; implanting ions into the semiconductor layer through the openings in the first shielding layer to form the first columnar low concentration layer; forming a second shielding layer (56, 58) on the surface of the semiconductor layer, the second shielding layer having an opening corresponding to a formation range of the first column high concentration layer in accordance with the measured alignment deviation; and forming the first column high concentration layer by implanting ions into the semiconductor layer through the opening in the second shielding layer.

6. A semiconductor layer (10) including a superjunction structure in which first columns (14a, 14b) of a first conductivity type and second columns (14a, 14b) of a second conductivity type are alternately and repeatedly arranged along at least one direction, a first column having a first column high concentration layer (142, 146) and a first column low concentration layer (144, 148) adjacent to the first column high concentration layer in the one direction and having a carrier concentration lower than that of the first column high concentration layer, forming a first shielding layer (52, 54) on a surface of the semiconductor layer, the first shielding layer having an opening corresponding to a region in which the first column low concentration layer is to be formed; Measuring the opening widths (52W, 54W) of the first shielding layer; implanting ions into the semiconductor layer through the openings in the first shielding layer to form the first columnar low concentration layer; forming a second shielding layer (56, 58) on the surface of the semiconductor layer, the second shielding layer having an opening corresponding to a formation range of the first column high concentration layer in accordance with the measured opening width; and forming the first column high concentration layer by implanting ions into the semiconductor layer through the opening in the second shielding layer.

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