Method for passivating cleaved semiconductor structure

Abstract

To provide a method for passivating a cleaved semiconductor structure in order to use it as an end surface light emission laser device.SOLUTION: A method and a system passivating a cleaved semiconductor structure 202 in order to use it as an end surface light emission laser device, further comprises: providing an enclosure having a first chamber and a second chamber, a transfer arm that receives and transmits a predetermined structure, and a fixture that attaches the predetermined structure thereon in the second chamber; filling the cleaved semiconductor structure that defines a first facet 202A in the first chamber onto the transfer arm therein; transferring the cleaved semiconductor structure by using the transfer arm; exposing the first facet of the cleaved semiconductor structure to a cleaning beam from a cleaning source; and forming a discipline oxide layer onto the first facet of the cleaved semiconductor structure by exposing the first facet of the cleaved semiconductor structure to an oxidant from an oxidation source.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates to passivating semiconductor devices. More specifically, this disclosure relates to a method for passivating a cleaved semiconductor structure for use as an edge-emitting laser device.

[0002] Semiconductor lasers, or diode lasers, are electro-optical devices operable to convert electrical energy into light for implementation in many applications. In particular, semiconductor lasers based on III-V semiconductor compounds are widely used in high-speed optical recording, high-speed printing, various networks and transmissions, Doppler optical radar, optical signal processing, high-speed optical microwave sources, pump sources for other solid-state lasers, fiber amplifiers, medical applications, and the like.

[0003] Such diode lasers, with their multiple controllable properties and diverse applications, create a continuous need for suitable improvements to one or more desired properties of the emitted light and / or device reliability. For example, in high power applications, a maximum amount of output power is desired for operation. However, the output power is often limited by progressive damage to the device itself. Here, the main root cause of failure of high power semiconductor lasers is known as catastrophic optical mirror damage (COMD), a phenomenon that impairs the maximum output power of high power edge-emitting laser chips. The root cause of failure due to COMD is surface defects at the output facet(s) of the laser chip. The light emitted by the semiconductor laser is partially absorbed by the surface, and the defects act as non-radiative recombination centers, resulting in increased heat generation due to recombination of charge carriers excited by the partially absorbed light. Typically, as the temperature increases, the effective band gap of the material decreases, resulting in more absorption and non-radiative recombination. Meanwhile, an increase in temperature also leads to a redistribution of molecular bonds, which generally leads to a higher defect density in the absence of strong well-ordered molecular bonds at the interface. Furthermore, prolonged operation at high output power generates a significant amount of heat that can cause degradation of one or more mirrors disposed on one or more facets of the semiconductor laser.

[0004] As a result of degradation, the corresponding mirror damage shortens the lifetime of the semiconductor laser, thereby increasing the operational costs due to the need for frequent laser replacement. Moreover, such effects hinder the positive feedback loop, resulting in rapid microexplosions of the facets when the optical power threshold level of COMD is exceeded. In an exemplary scenario, it has been observed that aluminum (Al)-containing compound semiconductor lasers are the most sensitive to COMDs due to their extremely high tendency to interact with oxygen, which is often the source of defect states. Apart from Al and oxygen (O) bonds having a natural tendency to form defect states, it is also extremely difficult to reduce such defects due to their thermodynamic stability. As a result, most of the known methods to avoid Al-O bonds at the surface relate to preventing the facets from being exposed to oxygen before coating.

[0005] Several attempts have been made to solve the above-mentioned problems. In some examples, argon (Ar) ion beam etching (either positive or negative), remote plasma etching, or atomic hydrogen oxide reduction are used to remove the surface oxide layer, followed by silicon, silicon nitride SiNx, silicon hydride (SiH), or crystalline ZnSe deposition to passivate the surface with reduced defect state density and protect the facets from further oxidation. In other examples, ultra-high vacuum (UHV) systems are typically configured to utilize cleaning methods followed by deposition of at least 10 nm thick crystalline passivation layers, e.g., ZnSe. Further herein, steps such as sample loading, cleaning, deposition, and flipping are performed in different chambers of the system. However, the system does not have vacuum breaks (or exposure to ambient) during any of the steps. However, it is still very complex and slow compared to processes and / or systems that can be performed in a single chamber. Furthermore, in some examples, a ZnSe crystalline layer is used as a protective / passivation coating. Here, atomic hydrogen etching as a cleaning method is utilized to avoid defect generation from the etching itself. For non-Al compound semiconductors, such methods can provide high quality interfaces. However, atomic hydrogen by itself may not provide efficient removal of Al-O bonds. Furthermore, in some instances, low energy hydrogen plasma is utilized for cleaning, followed by overcoating with hydrogenated amorphous silicon (a-Si:H), and low energy Ar+ ion beam or plasma is utilized to remove the surface native oxide, followed by Si coating.

[0006] All the passivation methods mentioned above require the removal of the native oxide prior to or simultaneously with the passivation process. Another technique involves completely avoiding the Al-O bonds present on the laser facets, known as the E2 technique. The E2 technique involves avoiding oxide formation on the surface by preventing the facets of the device from being exposed to their surroundings until they are cleaved from the processed wafer. This cleavage is performed in UHV "in-situ", after which the device is coated with a thin layer of either silicon (Si), germanium (Ge), or antimony (Sb), the surface coating must have an absorption edge to facilitate the propagation of light from the device while at the same time protecting the active region interface from interaction with oxygen from the surroundings. However, one of the main drawbacks of the E2 method is the need to cleave the processed wafer into bars in UHV, which is a very complicated process, has a very low throughput, and requires very expensive equipment. It will be appreciated that when laser bars are cleaved "ex-situ", i.e. outside of UHV, oxidation of the laser facets is inevitable, resulting in defect states from the native oxide present on the laser facets.

[0007] The present disclosure seeks to provide a method and system for passivating a cleaved semiconductor structure for use as an edge-emitting laser device. The present disclosure further seeks to provide an edge-emitting laser device formed by the method. It is an object of the present disclosure to provide a solution that at least partially overcomes the problems encountered in the prior art.

[0008] In one aspect, an embodiment of the present disclosure provides a method of passivating a cleaved semiconductor structure for use as an edge-emitting laser device, the method comprising: providing an enclosure having a first chamber and a second chamber, a transfer arm for receiving and transferring a given structure from the first chamber to the second chamber, and a fixture for mounting the given structure thereon in the second chamber, with each of the first chamber and the second chamber adapted to provide a vacuum condition therein; loading a cleaved semiconductor structure defining a first facet onto a transfer arm within a first chamber; transferring the cleaved semiconductor structure from the first chamber to the second chamber using the transfer arm to mount the cleaved semiconductor structure on a fixture in the second chamber; exposing the first facet of the cleaved semiconductor structure in the second chamber to a cleaning beam from a cleaning source facing the first facet by manipulating a fixture therein to remove any native oxide layer that may have formed on the first facet of the cleaved semiconductor structure; exposing a first facet of the cleaved semiconductor structure in the second chamber to thermal energy from a heating source facing the first facet by manipulating a fixture therein to heat the first facet of the cleaved semiconductor structure; exposing a first facet of the cleaved semiconductor structure in the second chamber to an oxidant from an oxidation source facing the first facet by manipulating a fixture therein to form an ordered oxide layer on the first facet of the cleaved semiconductor structure.

[0009] In another aspect, an embodiment of the present disclosure provides a system for passivating a cleaved semiconductor structure for use as an edge-emitting laser device, the system comprising: an enclosure having a first chamber and a second chamber; a pump configured to create a vacuum within each of the first chamber and the second chamber; a cleaning source mounted within the second chamber; and a heat source mounted within the second chamber; and an oxidation source mounted within the second chamber; and a transfer arm configured to receive and transfer a cleaved semiconductor structure defining a first facet from the first chamber to the second chamber; a fixture adapted to mount the given structure thereon within the second chamber; The fixture further comprises: exposing a first facet of the cleaved semiconductor structure in the second chamber to a cleaning beam from a cleaning source by positioning the first facet against the cleaning source; exposing a first facet of the cleaved semiconductor structure in the second chamber to thermal energy from a heat source by positioning the first facet against the heat source; exposing the first facet of the cleaved semiconductor structure in the second chamber to an oxidizing agent from the oxidation source by positioning the first facet facing the oxidation source; The device is configured to be operated in such a manner.

[0010] In yet another aspect, the present disclosure also provides an edge-emitting laser device formed by the above-described method, the edge-emitting laser device comprising: a cleaved semiconductor structure having a multiple quantum well structure adapted to generate light of a specified wavelength; at least one facet defined by cleaving the semiconductor structure along a crystallographic direction thereof, the at least one facet comprising an ordered native oxide layer formed thereon.

[0011] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure substantially eliminate or at least partially address the aforementioned problems in the prior art and provide an improved method for passivating cleaved semiconductor structures for use as edge-emitting laser devices.

[0012] Additional aspects, advantages, features, and objects of the present disclosure will become apparent from the drawings and detailed description of illustrative embodiments taken in conjunction with the appended claims. [Brief description of the drawings]

[0013] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following drawings, in which: [Figure 1A] 1 is a flow chart listing steps involved in a method of passivating a cleaved semiconductor structure for use as an edge-emitting laser device, according to an embodiment of the present disclosure. [Figure 1B] 1 is an exemplary flow chart listing steps involved in a method of passivating a cleaved semiconductor structure for use as an edge-emitting laser device, according to an embodiment of the present disclosure. [Figure 2A] FIG. 2 is a representative diagram of an exemplary semiconductor cleaved bar including multiple semiconductor structures therein, according to one embodiment of the present disclosure. [Figure 2B] FIG. 2B is a representative diagram of one of the cleaved semiconductor structures of the semiconductor bar of FIG. 2A according to one embodiment of the present disclosure. [Figure 2C] FIG. 1 illustrates an exemplary schematic diagram of a system for passivating a cleaved semiconductor structure for use as an edge-emitting laser device, according to an embodiment of the present disclosure. [Figure 3A] FIG. 2 is a representative view of an exemplary cleaved semiconductor structure prior to cleaning of its first facet in accordance with one or more embodiments of the present disclosure. [Figure 3B] FIG. 2 is a representative diagram of an exemplary cleaved semiconductor structure after cleaning a first facet in accordance with one or more embodiments of the present disclosure. [Figure 3C] FIG. 2 is a representative diagram of an exemplary cleaved semiconductor structure having its first facet passivated with an ordered native oxide layer in accordance with one or more embodiments of the present disclosure. [Figure 4A] 1 is a schematic diagram of an exemplary lamination fixture of a system according to one or more embodiments of the present disclosure. [Figure 4B]FIG. 2 is a detailed view of an exemplary fixture holding multiple cleaved semiconductor structures in accordance with one or more embodiments of the present disclosure. [Diagram 5] FIG. 2 is a schematic diagram of an exemplary second chamber for passivating a cleaved semiconductor structure, in accordance with one or more embodiments of the present disclosure. [Figure 6] 1 is a graphical representation of temperature change in a cleaved semiconductor structure as a measure of distance from a heating source, according to one embodiment of the present disclosure. [Figure 7] 1 is a graphical representation of differential scanning tunneling spectroscopy IV curves versus voltage for a cleaved semiconductor structure according to an embodiment of the present disclosure. Detailed Description of the Embodiments

[0014] The following detailed description illustrates embodiments of the present disclosure and how they may be implemented. Although several modes of implementing the present disclosure have been disclosed, those skilled in the art will recognize that other embodiments are possible for implementing or practicing the present disclosure.

[0015] In one aspect, an embodiment of the present disclosure provides a method of passivating a cleaved semiconductor structure for use as an edge-emitting laser device, the method comprising: providing an enclosure having a first chamber and a second chamber, a transfer arm for receiving and transferring a given semiconductor structure from the first chamber to the second chamber, and a fixture for mounting the given semiconductor structure thereon in the second chamber, with each of the first chamber and the second chamber adapted to provide a vacuum condition therein; loading a cleaved semiconductor structure defining a first facet onto a transfer arm within a first chamber; transferring the cleaved semiconductor structure from the first chamber to the second chamber using the transfer arm to mount the cleaved semiconductor structure on a fixture in the second chamber; exposing the first facet of the cleaved semiconductor structure in the second chamber to a cleaning beam from a cleaning source facing the first facet by manipulating a fixture therein to remove any native oxide layer that may have formed on the first facet of the cleaved semiconductor structure; exposing a first facet of the cleaved semiconductor structure in the second chamber to thermal energy from a heating source facing the first facet by manipulating a fixture therein to heat the first facet of the cleaved semiconductor structure; exposing a first facet of the cleaved semiconductor structure in the second chamber to an oxidant from an oxidation source facing the first facet by manipulating a fixture therein to form an ordered oxide layer on the first facet of the cleaved semiconductor structure.

[0016] The term "passivation" as used herein refers to the process of fabrication (or formation) of a passivation layer configured to protect the internal structure of a semiconductor device from contaminants and oxidation. Contamination and oxidation can result in defects at the atomic level that reduce the power efficiency of the semiconductor device, causing reliability issues, lowering manufacturing yields and thus increasing costs. Thus, passivation allows for the reduction of surface defect densities to unprecedented levels, thus increasing the efficiency and manufacturing yields of III-V semiconductor-based devices. The passivation layer is formed, for example, from an oxide and / or nitride layer on a cleaved semiconductor structure.

[0017] The term "semiconductor structure" refers to a layer or block of material on or within which the elements of a semiconductor device are fabricated or attached. Typically, the semiconductor structure may be a layer of any metal, nonmetal, semiconductor material, or combination of metal, nonmetal and semiconductor materials, any layer of material deposited on a supporting substrate, or the supporting structure itself. In this embodiment, the semiconductor structure, the semiconductor chip, may be a GaAs or Indium Phosphide (InP) based structure suitable for forming edge-emitting laser devices, as well as other HEMT and MESFET structures. However, the semiconductor structure may be formed from any material desired to produce the desired patterns (e.g., sub-half micron) in accordance with the present disclosure.

[0018] The semiconductor structures can be formed using a variety of conventional techniques, including techniques such as molecular beam epitaxy or metalorganic chemical vapor deposition to form integrated circuits or electronic structures. As can be appreciated, upon formation of the semiconductor structures, bars of semiconductor structures are cleaved via conventional techniques and further processed via methods for utilization as edge-emitting laser devices. It will be appreciated that multiple cleaved semiconductor structures, laser chips, may be part of a single semiconductor bar, the entire semiconductor bar may be processed at a given time, or preferably, multiple such stacked semiconductor bars may be processed at a given time for improved mass production and efficiency of the disclosed methods and systems.

[0019] An edge-emitting laser device is fabricated using the cleaved semiconductor structure by implementing the method of the present disclosure, thereby achieving all the features and advantages of the present disclosure. Optionally, the edge-emitting laser device fabricated on the cleaved semiconductor structure is adapted to provide target lasing characteristics, the term "lasing characteristics" referring to the spectral emission characteristics and / or properties of the laser generated by the semiconductor device. The target lasing characteristics of the semiconductor device are adapted based on the implementation by varying inputs such as input current, voltage, power, cavity spacing, etc. to provide the desired lasing action of the semiconductor device.

[0020] The method includes providing an enclosure having a first chamber and a second chamber, a transfer arm for receiving and transferring a given semiconductor structure from the first chamber to the second chamber, and a fixture for mounting the given structure in the second chamber thereon, with each of the first and second chambers adapted to provide a vacuum condition therein. An "enclosure" refers to an external body comprising a multi-chamber system for inertly storing a given semiconductor structure and preventing exposure from the environment. As used herein, the enclosure comprises a first chamber in which a given semiconductor structure (i.e., a cleaved semiconductor structure) can be loaded or transferred, and a transfer arm configured to transfer or receive the given semiconductor structure to or from the first or second chamber. Additionally, the enclosure comprises a fixture configured to mount the given structure (once transferred) to the second chamber.

[0021] As used herein, the term "transfer arm" refers to a manually or automatically actuated arm or robotic arm configured to transfer or reorient a given semiconductor structure and / or fixture to a desired position or orientation within an enclosure. Typically, a transfer arm is a movable and extendable arm within an enclosure between a first and a second chamber, allowing to pick up a semiconductor structure / fixture in one chamber and transfer it with a precise (linear) motion to another chamber or move within one chamber while maintaining vacuum integrity.

[0022] The term "fixture" refers to a customized support device configured to reliably position, support, mount, and allow external manipulation of cleaved semiconductor structures. In one example, the fixture may be a type of fixture (such as a stacking fixture, a plate fixture, a channel fixture, etc.). In another example, the fixture may be a metal frame configured to mount multiple cleaved semiconductor structures. Optionally, the fixture may have an opening through which at least one facet of each cleaved semiconductor structure is exposed for processing. It will be further understood that the fixture may be mounted with other fixtures having stacked cleaved semiconductor structures, which may thereby be processed together according to the present method. Advantageously, such an arrangement of cleaved semiconductor structures improves the efficiency of the present method by enabling mass production due to a larger number of semiconductor structures that may be processed in parallel at one time via the present method. In some embodiments, semiconductor bars having multiple cleaved semiconductor structures are stacked on top of each other in a fixture (such as a stacking fixture). For example, such a fixture may include 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90, or 100 cleaved (semiconductor) structures stacked on top of each other to form a semiconductor bar. Optionally, such multiple semiconductor bars may be separated by spacing structures, e.g., GaAs structures, to prevent stacking of the cleaved semiconductor structures due to the presence of contact metal therein.

[0023] The method further includes loading the cleaved semiconductor structure defining a first facet onto a transfer arm therein in the first chamber. Typically, the cleaved semiconductor structure defining a first facet is loaded onto a lamination fixture (e.g., a lamination jig) and thereby loaded into the first chamber for further transfer and / or operation.

[0024] Conventionally, semiconductor structures are mounted on handling fixtures to be moved between different chambers for exposure to different processing processes, which may even require leaving an enclosure with its inherent risk of exposure to the atmosphere. To overcome the above-mentioned inefficiencies, the present disclosure provides a novel approach whereby multiple facets of a semiconductor structure may be exposed, cleaned, heated, passivated, etc., in a single chamber.

[0025] The method further includes transferring the cleaved semiconductor structures from the first chamber to the second chamber using a transfer arm to mount the cleaved semiconductor structures on a fixture in the second chamber. In some examples, during operation, the cleaved semiconductor structures may first be loaded onto a stacking fixture before being loaded into the first chamber, and the entire stacking fixture together with the cleaved semiconductor structures may be transferred to the second chamber using the transfer arm without leaving the enclosure (and thus without exposure to atmosphere) for further processing of the cleaved semiconductor structures loaded in the enclosure. In particular, a semiconductor bar having a plurality of cleaved semiconductor structures is mounted on a fixture for simultaneous processing of each of the plurality of cleaved semiconductor structures therein. Preferably, a plurality of such semiconductor bars may be stacked in the fixture for simultaneous processing of the cleaved semiconductor structures, allowing for high volume production and high throughput.

[0026] Herein, the cleaved semiconductor structures are mounted on a fixture such that the first facets of the multiple cleaved semiconductor structures are aligned in the same direction, and the processing steps of the method affect each of the first facets in a similar manner. Furthermore, once the cleaved semiconductor structures are loaded into the first chamber, the cleaved semiconductor structures are transferred along with the stacking fixture to a second chamber where the first facets of the cleaved semiconductor structures may be further cleaned and / or passivated, after which the second facets of the semiconductor structures are similarly exposed (by manipulation of the transfer arm), heated, cleaned, and passivated in the second chamber. Advantageously, during operation, a single chamber, i.e., the second chamber, is utilized and both facets, i.e., the first facet and the second facet, can be processed, cleaned, and passivated without using another chamber or leaving an enclosure during processing, making the method faster and more efficient.

[0027] In one or more embodiments, the fixture is adapted to be coupled to the transfer arm and have multiple degrees of freedom to be manipulated relative to the transfer arm, and the cleaved semiconductor structure is loaded onto the stacking fixture and thereon in the first chamber. The stacking fixture loaded with the cleaved semiconductor structure is then transferred to a fixture in the second chamber for further processing. The fixture is adapted to be coupled to the transfer arm, and the coupling allows multiple degrees of freedom (DoF) to be manipulated relative to the transfer arm, thereby allowing convenient and efficient transfer and loading of the cleaved semiconductor structure. In one example, the fixture coupled to the transfer arm allows complete freedom of movement along one or more of the translational axes x, y, z-axis and one or more of the rotational axes α, β, and γ-.

[0028] The method further includes exposing the first facet of the cleaved semiconductor structure in the second chamber to a cleaning beam from a cleaning source facing the first facet by manipulating a fixture therein to remove any native oxide layer that may have formed on the first facet of the cleaved semiconductor structure. It will be appreciated that contaminants on a given semiconductor structure may severely impact the yield of manufacturing laser devices during semiconductor manufacturing, and thus removal or cleaning of such contaminants from the facet of the given semiconductor structure may be required during passivation of the semiconductor structure. Thus, upon transferring the cleaved semiconductor structure to the second chamber, the first facet of the cleaved semiconductor structure is exposed to a cleaning beam from a cleaning source by manipulating a fixture therein.

[0029] As used herein, the term "cleaning beam" refers to an irradiation beam from a cleaning beam source configured to remove (or clean) the surface (or facet) of the cleaved semiconductor structure of any possible oxide layer or other contaminants (e.g., dust, rust, grease, etc.). In one example, the method can use a micro-pulse laser or a high-power laser, i.e., a short-pulse laser with high power, to remove the native oxide layer, which can clean without damaging the surface. Here, the power input (or peak power) to the high-power short-pulse laser is very high for a shorter duration, so the heat affected zone (HAZ) is lower than other types of lasers and the cleaning process takes less time compared to other types of lasers. Moreover, beneficially, such implementation requires only one or two lasers for the entire passivation method. In another example, the method can use a continuous wavelength laser with different wavelengths and powers. In another example, the method can use an ion beam to remove the possible native oxide layer. In yet another example, the method can use a continuous wavelength laser, or a pulsed laser of different wavelengths or powers, based on the implementation. It will be appreciated that the method can vary essential laser parameters such as laser intensity, wavelength, pulse duration, pulse width, and incidence angle to potentially improve cleaning effectiveness, and can use any cleaning source and corresponding cleaning beam technique based on implementation needs.

[0030] Such a cleaning step removes any possible contaminants from the first facet of the cleaved semiconductor structure prior to further processing of the given semiconductor structure. Advantageously, the removal of these contaminants and native oxide is essential for forming an ordered oxide layer thereon (also known as a Kontrox® layer, i.e., a thin long-range ordered oxide layer) and for depositing and growing other oxide films on the semiconductor structure. It will be appreciated that otherwise it may not be possible to generate a long-range oxide. If a decontaminant is present, long-range ordered oxide formation will not be successful. Therefore, it is necessary to remove the decontaminant and native oxide. In some instances, the attachment of oxygen to form a long-range ordered oxide may be assisted by providing predetermined temperature conditions.

[0031] In one or more embodiments, the cleaning beam comprises at least one of an atomic beam of hydrogen, argon, xenon, or mixtures thereof, an ion beam comprising an ionized noble gas (helium, argon, etc.) and / or nitrogen. In some embodiments, the cleaning beam utilized by the present method is an ion beam comprising an ionized noble gas (helium, argon, etc.) and / or nitrogen, i.e., a beam of energetic ions directed at the cleaved semiconductor structure to remove any possible contaminants. In particular, the ionized beam has an energy level of 100 electron volts or less to optimize the cleaning process. In other embodiments, the cleaning beam utilized by the present method is an atomic beam comprising at least one of atomic hydrogen, argon, xenon, or mixtures thereof, i.e., a beam of energetic atoms directed at the semiconductor structure to remove any possible native oxide layer.

[0032] The method further includes exposing the first facet of the cleaved semiconductor structure in the second chamber to a heat beam from a heating source facing the first facet by manipulating the fixture therein to heat the first facet of the cleaved semiconductor structure. It can be understood that the heating can be applied before, during and / or after the oxidation step. Generally, the cleaved semiconductor structure is heated during the cleaning process, but heating may not necessarily be required during or after oxidation. Herein, the entire fixture may be manipulated or repositioned to uniformly accommodate (or directly face) the incident heat beam from the heating source. Advantageously, the maximum amount of the heat beam is received by the exposed first facet of the cleaved semiconductor structure due to the manipulation, thereby efficiently and precisely heating the first facet due to the more precise control of the laser radiation and increased energy efficiency.

[0033] As used herein, the term "thermal beam" refers to an irradiation beam from a heat source configured to provide thermal energy toward a desired location to heat or clean the surface (or facet) of the cleaved semiconductor structure of any possible contaminants (e.g., moisture). In one example, the method can use a micro-pulse laser or a high-power laser, i.e., a short-pulse laser with high power, that can heat without damaging the surface, to heat the first facet of the cleaved semiconductor structure. Here, the power input (or peak power) to the high-power short-pulse laser is very high for a shorter duration, so the heat affected zone (HAZ) is lower than other types of lasers and the heating process takes less time compared to other types of lasers. In yet another example, the method can use a continuous wavelength laser, or a pulsed laser of different wavelengths or power, based on the implementation. It will be understood that the method can change essential laser parameters such as laser intensity, wavelength, pulse duration, pulse width, and incidence angle to potentially improve the heating effect, and can use any heating source and corresponding heating beam technique based on the needs of the implementation. In this example, the heating source can be a type of laser, such as a solid-state laser, a gas laser, etc. In some examples, the heating source can be configured to direct a heat beam toward the first facet of the cleaved semiconductor structure to heat the first facet to clean and / or remove potentially present contaminants prior to further processing. For example, the heating can remove any moisture, gases, and other contaminants on the cleaned first facet. In particular, the temperature measured in the second chamber during heating may remain constant (e.g., room temperature) during operation, in contrast to existing systems and processes, due to the localized heating effect of the heat beam provided by the heating source, i.e., the heat beam is localized only to the exposed first facet of the cleaved semiconductor structure. Advantageously, through such application of the heating source, the thermal load applied to the entire cleaved semiconductor structure is lower compared to prior art where heating was performed from the non-exposed facet, thereby preventing a corresponding high risk of damage due to exposure to high temperatures throughout the structure.

[0034] The heating source directs a heat beam toward the first facet of the cleaved semiconductor structure to heat the first facet to clean and / or remove potentially present contaminants prior to further processing. For example, the heating can remove any moisture, gases, and other contaminants on the cleaned first facet. The temperature measured in the second chamber during heating remains substantially constant (e.g., room temperature) during heating, and the exposure to radiation (either IR radiation or laser radiation) may be localized to the exposed first facet or varied for different periods of time. For example, the first facet of the cleaved semiconductor structure may be heated for 5 minutes, 10 minutes, 15 minutes, 20 minutes, 30 minutes, 60 minutes, etc. One skilled in the art would understand that the pressure, temperature, and exposure time may be varied based on the implementation without limiting the scope of the present disclosure.

[0035] Optionally, the heat beam is provided by at least one of laser irradiation, infrared radiation. In other words, the heating source utilized to provide the heat beam to heat the first facet of the cleaved semiconductor structure is a laser source, i.e. irradiation via a laser (e.g., solid-state laser, gas laser, semiconductor laser), or an infrared source, i.e. radiation from an infrared (IR) light source (e.g., an IR lamp). The IR light or laser radiation heats the cleaved semiconductor structure to remove moisture and contaminants (e.g., adsorbed particles, N2, CO2, or O2, among other contaminants) physically adsorbed on the surface of the first facet after cleaving. Advantageously, the laser radiation provides high accuracy and precise control of the heat beam power, resulting in minimal distortion and / or stress on the cleaned first facet during operation, while the infrared radiation improves the efficiency of the method due to lower energy consumption.

[0036] In one or more embodiments, the heating source is mounted outside the second chamber, and the method further includes providing a transparent viewport that allows the heat beam from the heating source to reach the cleaved semiconductor structure. The term "viewport" refers to an access port configured to allow the heat beam from the heating source to reach the exposed first facet of the cleaved semiconductor structure, i.e., after or during the cleaning and / or oxidation process. It will be understood that based on the needs of the implementation, the location of the heating source and / or the beam shaper may be changed, i.e., mounted outside or inside the second chamber or enclosure. In some examples, the heating source and / or the beam shaper used by the method may be located inside the enclosure while being mounted inside the first chamber and / or the second chamber to reduce the physical footprint of the implementation. In this embodiment, the heating source and / or beam shaper used by the method may be located inside the enclosure, mounted externally to the first and / or second chambers, or may be located outside the enclosure entirely and accessible through an entrance or access port, i.e. a transparent viewport.

[0037] The method further includes exposing the first facet of the cleaved semiconductor structure in the second chamber to an oxidant from an oxidation source facing the first facet by manipulating a fixture therein to form a long-range ordered oxide layer on the first facet of the cleaved semiconductor structure. That is, during or at the time of heating the cleaned first facet of the cleaved semiconductor structure, the method further includes exposing the heated first facet to an oxidant from an oxidation source to form an ordered oxide layer by manipulating a fixture in the second chamber. Traditionally, existing methods or systems have utilized materials from the III-V group, resulting in a natural amorphous native oxide. However, such materials are known to provide disordered native oxides that provide low quality oxides, thereby resulting in lower quality laser devices. To overcome the aforementioned problems, the method includes controlling the oxidation process, i.e., the formation of an ordered oxide layer, by controlling various operating parameters such as pressure, temperature, amount of oxidant used, and application time to form a long-range ordered oxide, i.e., an ordered oxide layer. That is, the method includes converting a cleaned first facet of a semiconductor structure into an ordered oxide layer exhibiting long-range order using an oxidizing source.

[0038] As used herein, an "ordered oxide layer" refers to a thin ordered layer of oxide, such as any native oxide or any other oxide, where the oxide layer may be protective, decorative, or functional in nature. The ordered oxide layer acts as a passivation layer on the surface of the cleaved semiconductor structure, preventing external effects (such as corrosion) from exposure to the environment. Thus, such an ordered oxide layer provides an increased energy barrier for edge-emitting laser devices to improve carrier confinement within a stacked configuration of multiple cleaved semiconductor structures. Here, the atomic positions of the ordered oxide layer exhibit long-range order or translational periodicity. Here, for example, the positions of III-V atoms in the ordered oxide layer spatially repeat in a regular array. Furthermore, the ordered oxide layer may be a crystalline layer having both long-range order and short-range order, without any limitation to the present disclosure. It will be understood by those skilled in the art that the ordered oxide layer is formed by oxidizing the cleaned first facet of the cleaved semiconductor structure (and in particular, not by deposition of any additional oxide, such as by conventional deposition techniques). Furthermore, the crystal symmetry of the ordered oxide layer may be the same as or different from the crystal structure of the III-V semiconductor material. Some III-V materials have more than one possibility for the crystal oxide structure. The different structures can be achieved by performing transformations of the III-V semiconductor surface at different temperatures, oxygen doses, oxygen flow rates, oxygen partial pressures, and / or processing times. Edge-emitting laser devices formed from the cleaved semiconductor structures of the present invention include an ordered oxide layer. As will be described in more detail below, the introduction of an ordered oxide layer can cause an increase in the energy band gap in the semiconductor device. Advantageously, the higher energy gap gives the edge-emitting laser device the ability to operate at higher temperatures, where otherwise the energy band gap typically shrinks with increasing temperature, which presents problems during the operation of conventional semiconductors.

[0039] In one or more embodiments, the oxidant is molecular oxygen, oxygen plasma, ozone, NO x, CO. The oxidizing agent is selected based on the material of the cleaved semiconductor structure, the operating conditions to optimize the efficiency of the method, and may vary based on the implementation without limiting the scope of the present disclosure. For example, any other oxidizing agent such as other oxygen-containing gases (e.g., chlorine dioxide, carbon dioxide), other halogens (e.g., chlorine, fluorine, bromine, etc.). Herein, the oxygen source can generate molecular oxygen and / or ozone molecules by natural oxidation of oxygen molecules in air (e.g., thermal dissociation of oxygen by ultraviolet radiation or corona discharge, etc.) or by atomic dissociation using oxygen plasma in the second chamber. Beneficially, such a process of ordered oxide layer formation is thermodynamically stable and produces an effective passivation layer that prevents further undesired oxidation. As a result, the number of defect states is reduced, thereby preventing further COMD, resulting in improved device lifetime, and a clean first facet of the cleaved semiconductor is utilized to obtain high-quality single crystal growth of the ordered oxide layer.

[0040] In one or more embodiments, the method further includes exposing the first facet of the cleaved semiconductor structure in the second chamber to group III atoms from a deposition source facing the first facet by manipulating a fixture therein to deposit group III atoms on the first facet of the cleaved semiconductor structure prior to exposing the first facet to an oxidizing agent from the oxidizing source. Typically, prior to forming an ordered oxide layer on the heated first facet of the cleaved semiconductor structure, the method further includes depositing at least one of group III atoms, namely boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl), on the first facet of the cleaved semiconductor structure. Advantageously, the deposited layer acts as an additional passivation layer and further prevents any potential damage (corrosion, erosion, etc.) from ambient exposure, thereby improving the lifetime of edge-emitting laser devices utilizing the cleaved semiconductor structure.

[0041] In one or more embodiments, the method includes: growing a first facet of a cleaved semiconductor structure over an ordered oxide layer formed on the first facet of the cleaved semiconductor structure; ... x and depositing at least one layer of. Typically, in forming an ordered oxide layer on the first facet of the cleaved semiconductor structure, the method further includes depositing a layer of amorphous silicon, or silicon dioxide, or silicon nitride on the ordered oxide layer. Here, the deposited layer acts as an insulating layer configured to provide higher stability against passivation, thereby preventing degradation of the passivation layer and providing additional protection therefor. Furthermore, when depositing on the ordered oxide layer, it prevents further oxidation due to potential oxidation at the surface due to exposure to external environment such as humidity from the atmosphere, thereby eliminating possible problems. It will be understood that the choice of the deposited layer is based on the implementation and can be changed without limiting the scope of the present disclosure. For example, sapphire can be used for high performance radio frequency (RF) and radiation sensitive applications, and silicon dioxide can be used to reduce short channel effects in other microelectronic devices.

[0042] In one or more embodiments, the plurality of cleaved semiconductor structures are loaded into the first chamber and stacked on top of one another at their respective lateral facets, the first facets being orthogonal to corresponding lateral facets in each cleaved semiconductor structure, and the method further includes manipulating a fixture in the second chamber to expose a first facet of each of the cleaved semiconductor structures of the plurality of cleaved semiconductor structures to one or more of a cleaning beam from a cleaning source, a heat beam from a heating source, and an oxidizing agent from an oxidation source. That is, in embodiments in which the plurality of cleaved semiconductor structures are loaded into the first chamber, each of the subsequent cleaved semiconductor structures (except for the first structure in each stack) are stacked on top of one another at their respective lateral facets, and the fixture is configured to securely position, support, mount, and enable external manipulation of the plurality of cleaved semiconductor structures. It will be further understood that the fixture may be mounted with other fixtures having stacked cleaved semiconductor structures, which may then be processed together via the method. Advantageously, such an arrangement of cleaved semiconductor structures improves the efficiency of the method by allowing for mass production, since a greater number of semiconductor structures may be processed in parallel at one time via the method. In some embodiments, the cleaved semiconductor structures are mounted on a fixture (such as a stacking fixture) on top of one another and provided to the second chamber. For example, such a fixture may include 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90, or 100 cleaved semiconductor structures stacked on top of one another and provided to the second chamber. Optionally, the cleaved semiconductor structures may be separated by spacing structures, such as GaAs structures. The method further includes manipulating the fixture in the second chamber, i.e., repositioning and / or reorienting the fixture containing the cleaved semiconductor structures, to expose a first facet of each cleaved semiconductor structure to one or more of a cleaning beam from a cleaning source, a heat beam from a heating source, and an oxidizing agent from an oxidation source.

[0043] In one or more embodiments, the cleaved semiconductor structure further defines a second facet therein, and the method further includes manipulating a fixture in the second chamber to expose the second facet of the cleaved semiconductor structure to one or more of a cleaning beam from a cleaning source, a heat beam from a heating source, and an oxidizing agent from an oxidation source in the second chamber without removing the semiconductor structure from the enclosure. In some implementations, it is preferred to form a passivation layer on both opposing facets of the cleaved semiconductor structure, i.e., the first facet and the second facet, to prevent the formation of contaminants and amorphous oxide layers thereon. Here, to form a passivation layer on the second facet, the orientation of the cleaved semiconductor structure in the second chamber is modified by manipulating the fixture such that the second facet may be exposed to one or more of a cleaning beam from a cleaning source, a heat beam from a heating source, and an oxidizing agent from an oxidation source in the second chamber. In contrast to the prior art, the transfer arm and fixture configuration allows the second facet to be exposed to the process without having to remove the semiconductor structure from the enclosure.

[0044] Optionally, the method further includes manipulating the fixture to expose a second facet of the laminated semiconductor structure, the manipulating the fixture including reorienting or repositioning the fixture with the attached cleaved semiconductor structure from a first orientation to a second, different orientation in the second chamber such that the second facet is exposed to further processing. Advantageously, passivating both facets of the cleaved semiconductor structure provides a higher level of protection, thus effectively preventing contaminant deposition on the cleaned facet and preventing reformation of the amorphous oxide layer. Furthermore, passivating both facets of the cleaved semiconductor structure improves resistance to withstand high temperatures, thereby resulting in improved laser device lifetime.

[0045] The present disclosure also provides a system for passivating a cleaved semiconductor structure for use as an edge-emitting laser, to which the various embodiments and variations disclosed above apply mutatis mutandis without any limitation.

[0046] The system includes an enclosure having a first chamber and a second chamber, and a pump configured to generate a vacuum condition inside each of the first chamber and the second chamber. As used herein, a "pump" refers to a vacuum pump configured to draw gas molecules from an enclosed space (such as the enclosure, the first chamber, the second chamber, etc.) to create a partial vacuum, i.e., to generate a vacuum condition inside the chamber. For example, the pump may be selected from at least one of, but is not limited to, a positive displacement pump, a regenerative pump, and an entrapment pump.

[0047] The system further comprises a cleaning source and an oxidation source mounted in the second chamber. In particular, the system comprises a first port for mounting the cleaning source in the second chamber and a second port for mounting the oxidation source in the second chamber. The term "port" refers to an aperture or opening extending through the wall of the enclosure, and the shape, size, and curvature of the port may be varied according to the requirements of the implementation. In one or more embodiments, the cleaning source comprises at least one of a radio frequency (RF) plasma source, an ion sputtering source, and the selection of the cleaning source is made based on the implementation to optimize the method. In one or more embodiments, the oxidation source comprises a radio frequency (RF) plasma source. It will be understood that other oxidation sources may also be used, including, but not limited to, mass flow controllers, vacuum leak valves, and the like, without limiting the scope of the present disclosure.

[0048] In one or more embodiments, the system further comprises a heat source mounted within the second chamber, in particular, the system comprises a third port for mounting a heat source within the second chamber, where the heat source is configured to expose a first facet of the cleaved semiconductor structure to a heat beam from the heat source by positioning the first facet against the heat source.

[0049] The second or third port may advantageously be dimensioned to effectively accommodate a heating source or an oxidation source, respectively. In one or more embodiments, the heating source includes at least one of a laser and an infrared lamp. The selection of the heating source may be based on the material of the cleaved semiconductor structure and the conditions for effectively and efficiently performing the heating process. In this embodiment, the heating source is configured to provide a directed heat beam by at least one of laser irradiation and infrared radiation.

[0050] In one or more embodiments, the system further comprises a deposition source mounted in the second chamber. In particular, the system comprises a fourth port for mounting the deposition source in the second chamber, and the fixture is further configured to be operated to expose a first facet of the cleaved semiconductor structure in the second chamber to group III atoms from the deposition source by positioning the first facet opposite the deposition source prior to exposing the first facet to an oxidizing agent from the oxidation source. A "deposition source" refers to a system or device configured to deposit a thin layer of material (such as group III atoms) on a facet of the cleaved semiconductor structure. For example, the deposition source is a thermal evaporation source. In one or more embodiments, the deposition source includes at least one of an effusion cell, an electron beam evaporator, a gas distribution unit (e.g., for gas precursors used in techniques such as molecular metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD)). Here, the fixture is manipulated by positioning the first facet opposite the deposition source to effectively contain the incoming group III atoms prior to exposing the first facet to an oxidizing agent from the oxidizing source.

[0051] In one or more embodiments, the system further comprises a monitoring instrument mounted within the second chamber. In particular, the system comprises a fifth port for mounting the monitoring instrument within the second chamber, and the fixture is further configured to be operated to expose a first facet of the cleaved semiconductor structure within the second chamber by positioning the first facet against the monitoring instrument to enable monitoring of the surface crystal structure by the monitoring instrument. Typically, to monitor and analyze the surface crystal structure, the system comprises a fifth port configured for mounting the monitoring instrument within the second chamber, and the fixture is operated to position the first facet of the cleaved semiconductor structure against the monitoring instrument for effective monitoring and analysis.

[0052] In one or more embodiments, the monitoring equipment comprises at least one of a high energy electron diffraction (RHEED) equipment, a low energy electron diffraction (LEED) equipment, an Auger electron spectroscopy (AES) equipment, and a residual gas analysis (RGA) equipment. In general, the method can use any suitable monitoring technique or device, such as an imaging equipment (e.g., a high resolution camera, a light detection and ranging equipment, a hyperspectral imaging equipment, etc.), a diffraction equipment (e.g., LEED), a spectroscopy equipment (e.g., AES), etc., to effectively monitor the surface crystal structure. Such monitoring equipment provides a detailed analysis of the facets, thereby enabling the system to derive meaningful observations therein for optimizing the system and method, for example, to monitor the effect of temperature on the performance of a cleaved semiconductor structure or an edge-emitting laser device.

[0053] The system further comprises a transfer arm configured to receive and transfer a cleaved semiconductor structure defining a first facet from the first chamber to the second chamber and a fixture adapted to mount the given structure thereon in the second chamber, the fixture being configured to be operated to: expose the first facet of the cleaved semiconductor structure in the second chamber to a cleaning beam from the cleaning source by placing the first facet against a cleaning source; expose the first facet of the cleaved semiconductor structure in the second chamber to a heating beam from the heating source by placing the first facet against a heating source; and expose the first facet of the cleaved semiconductor structure in the second chamber to an oxidizing agent from the oxidation source by placing the first facet against an oxidation source.

[0054] The system further comprises a gate valve for controlling a condition within the enclosure, and a controller configured to operate the fixture and control the movement and / or position of the transfer arm and fixture by sending command signals to each of the transfer arm and fixture i for transfer of the semiconductor structure from the first chamber to the second chamber. The controller may be operatively coupled to the gate valve, the transfer arm, and / or the fixture, where the gate valve is configured to maintain the state of the enclosure unless the controller sends a command signal to open the gate valve for transfer of the semiconductor structure from the first chamber to the second chamber.

[0055] The term "controller" as used herein refers to a structure and / or module that includes programmable and / or non-programmable components configured to store, process, and / or share information and / or signals to control the transfer arm and / or fixture. A controller may have elements such as a display, control buttons or joystick, a processor, memory, etc.

[0056] The present disclosure also provides an edge-emitting laser that utilizes a semiconductor structure passivated by the method and / or system described in the preceding paragraph. The edge-emitting laser includes a cleaved semiconductor structure having a multiple quantum well structure adapted to generate light at a specified wavelength and at least one facet defined by cleaving the semiconductor structure along a crystallographic direction thereof, the at least one facet including an ordered oxide layer formed thereon.

[0057] In one or more embodiments, the cleaved semiconductor structure comprises a III-V compound semiconductor material and the ordered oxide layer comprises group III and group V oxide bonds that form a structure with long-range order. In one or more embodiments, the ordered oxide layer has a thickness of less than 10 nm. DETAILED DESCRIPTION OF THE DRAWINGS

[0058] 1, there is shown a flow chart enumerating steps included in a method 100 of passivating a cleaved semiconductor structure for use as an edge-emitting laser device, according to an embodiment of the present disclosure. As shown, the method 100 includes steps 102, 104, 106, 108, and 110. The enumerated steps 102, 104, 106, 108, and 110 do not necessarily have to be performed in sequential order.

[0059] In step 102, the method 100 includes providing an enclosure having a first chamber and a second chamber, a transfer arm for receiving and transferring a given structure from the first chamber to the second chamber, and a fixture for mounting the given structure thereon in the second chamber, with each of the first and second chambers adapted to provide vacuum conditions therein, where vacuum conditions are provided (e.g., via a pump) within each of the first and second chambers to prevent external exposure of the cleaved semiconductor structure to the environment during processing to prevent damage thereto (e.g., due to COMD, corrosion, etc.).

[0060] At step 104, the method 100 further includes loading a cleaved semiconductor structure defining a first facet on a transfer arm therein in the first chamber.

[0061] At step 106, the method 100 further includes transferring the cleaved semiconductor structure from the first chamber to the second chamber using the transfer arm to mount the cleaved semiconductor structure on a fixture in the second chamber. Upon loading the cleaved semiconductor structure, the method 100 further includes transferring the cleaved semiconductor structure from the first chamber to the second chamber via the transfer arm, thereby mounting the cleaved semiconductor structure on a fixture in the second chamber for further processing steps.

[0062] At step 108, method 100 further includes exposing the first facet of the cleaved semiconductor structure in the second chamber to a cleaning beam from a cleaning source facing the first facet by manipulating a fixture therein to remove a native oxide layer that may have formed on the first facet of the cleaved semiconductor structure. Upon transferring the cleaved semiconductor structure into the second chamber, method 100 further includes cleaning the first facet of the cleaved semiconductor structure by manipulating a fixture over the first facet of the cleaved semiconductor structure and exposing the first facet to a cleaning beam to remove a native oxide layer that may have formed on the first facet of the cleaved semiconductor structure, the fixture being manipulated to position a cleaning source facing the first facet.

[0063] At step 110, method 100 further includes exposing the first facet of the cleaved semiconductor structure in the second chamber to a heat beam from a heating source facing the first facet by manipulating a fixture therein to heat the first facet of the cleaved semiconductor structure. As used herein, the first facet is exposed to a heat beam from a heating source during, during, or prior to cleaning the first facet of the cleaved semiconductor structure and during, during, or prior to exposing the first facet of the cleaved semiconductor structure to an oxidizing agent in the second chamber, e.g., to remove any residual contaminants, such as moisture, from the first facet prior to further processing and / or to supplement the oxidation process.

[0064] And, in step 112, method 100 further includes exposing the first facet of the cleaved semiconductor structure in the second chamber to an oxidant from an oxidation source facing the first facet by manipulating the fixture therein to form an ordered oxide layer on the first facet of the cleaved semiconductor structure. Upon heating the first facet of the cleaved semiconductor structure, method 100 further includes forming an ordered oxide layer that acts as a passivation layer on the first facet of the cleaved semiconductor structure to prevent potential damage from exposure to the ambient environment, such as COMD, corrosion, and the like, thereby improving the lifetime and reliability of the edge-emitting laser device.

[0065] 1B, a representative flow chart of a method 100 for passivating a cleaved semiconductor structure according to some embodiments of the present disclosure is shown. As shown, a heating step, i.e., step 110, can be performed at various stages (or steps) of the method 100. In particular, after transferring the loaded semiconductor structure 202 onto the second chamber 208, the heating step 110 can be performed simultaneously while cleaning the first facet 202A (i.e., during the cleaning step 108) or while forming the ordered oxide layer 236 thereon (oxidizing step 112), and / or the heating step 110 can be performed before or after cleaning the first facet 202A (i.e., after the cleaning step 108) and forming the ordered oxide layer 236.

[0066] Referring to FIG. 2A, a representative diagram of an exemplary semiconductor bar 201 including a plurality of cleaved semiconductor structures 202 according to an embodiment of the present disclosure is shown. As shown, the semiconductor bar 201 includes a plurality of cleaved semiconductor structures 202 arranged adjacent to each other. Further, as shown, each cleaved semiconductor structure 202 has a first facet 202A and a second facet 202B. Here, the semiconductor bar 201 is processed according to the method 100 (described above), and the cleaved semiconductor structures 202 are stacked to place the first facet 202A and / or the second facet 202B in the exposure process described above, allowing for uniform processing of the cleaved semiconductor structures 202. In other words, the exposed first facet 202A can be heated at any time, i.e., before, during, or after the cleaning step 208 and / or the oxidation step 212.

[0067] Referring to FIG. 2B, a representative diagram of one of the exemplary cleaved semiconductor structures 202 according to an embodiment of the present disclosure is shown. As shown, the cleaved semiconductor structure 202 provides a first facet 202A and a second facet 202B on either side thereof. Furthermore, the cleaved semiconductor structure 202 includes a deposited passivation layer 230 (e.g., a group III atomic layer) deposited on each of the first and second facets 202A, 202B to protect against potential damage from COMD, corrosion, and the like. Furthermore, the cleaved semiconductor structure 202 includes a first layer 232 deposited on each of the first and second facets 202A, 202B for further protection from ambient exposure, thereby effectively protecting the cleaved semiconductor structure 202 from damage. For example, the deposited first layer 232 is a metal coating. In another example, the deposited first layer 232 is a mirror coating.

[0068] Referring to FIG. 2C, an exemplary schematic diagram of a system 200 for passivating a cleaved semiconductor structure 202 (FIGS. 2A and 2B) for use as an edge-emitting laser device is shown, according to an embodiment of the present disclosure. As shown, the system 200 comprises an enclosure 204 having a first chamber 206, a second chamber 208, and a pump 210 configured to generate a vacuum condition (e.g., up to ultra-high vacuum (UHV) levels) within each of the first chamber 206 and the second chamber 208. The system 200 further comprises a stacking fixture 234 configured to hold a plurality of the cleaved semiconductor structures 202. The system 200 further comprises a first port 212 for mounting a cleaning source 214 within the second chamber 208, and a second port 216 for mounting an oxidation source 218 within the second chamber 208. The system 200 further comprises a gate valve 238 for isolating the first chamber 206 from the second chamber 208 to prevent loss of ultra-high vacuum (UHV) level in the second chamber 208 when the first chamber 206 is opened. Typically, the gate valve 238 is configured to isolate the first chamber 206 from the second chamber 208 when the first chamber 206 is opened to prevent loss of vacuum level or condition in the second chamber 208. The gate valve 238 is closed so that the second chamber 208 does not lose vacuum level or condition when the first chamber 206 can be opened to load the semiconductor bar 201 having the plurality of cleaved semiconductor structures 202 therein.

[0069] The system 200 further comprises a heating source 222 mounted within the second chamber 208. In particular, as shown, the system 200 comprises a third port 220 for mounting the heating source 222 within the second chamber 208, where the fixture 226 is configured to be operated to expose the first facet 202A of the cleaved semiconductor structure 202 within the second chamber 208 to a heat beam from the heating source 222 by positioning the first facet 202A facing the heating source 222, where the heat beam may be provided by the heating source 222 either during, before, or after the cleaning and / or oxidation process. As shown, the heating source 222 is a front-side illumination source, such as a laser mounted outside the second chamber 208. Accordingly, the system 200 comprises a transparent viewport 221 (shown in FIG. 5 ) to allow the heat beam from the heating source 222 to efficiently reach the cleaved semiconductor structure 202. Additionally, the system 200 includes a beam shaper 223 (shown in FIG. 5) for shaping the heat beam from the heat source 222 so that it is directed toward an exposed facet of the cleaved semiconductor structure 202 mounted in the second chamber 208.

[0070] 2C, the system 200 further comprises a transfer arm 224 configured to receive and transfer the cleaved semiconductor structure 202 from the first chamber 206 to the second chamber 208, and a fixture 226 adapted to mount the given structure 202 thereon in the second chamber 208, the fixture 226 being adapted to mount the cleaved semiconductor structure 202 in the second chamber 208 by positioning the first facet 202A against the cleaning source 214. The system 200 is configured to be operated to expose the first facet 202A (as shown in FIGS. 2A and 2B ) and / or the second facet 202B (as shown in FIGS. 2A and 2B ) of the semiconductor structure 202 to a cleaning beam from the cleaning source 214 and to expose the first facet 202A of the cleaved semiconductor structure 202 in the second chamber 208 to an oxidizing agent from the oxidation source 218 by positioning the first facet 202A facing the oxidation source 218. In some examples, the system 200 further comprises a mounting or stacking fixture 234 disposed in the first chamber 206 where the cleaved semiconductor structure 202 may be initially loaded into the system 200, from where the cleaved semiconductor structure 202 may be transported by the transfer arm 224 from the first chamber 206 to the second chamber 208 and loaded into the fixture 226 therein.

[0071] The system 200 further comprises a deposition source 242 mounted within the second chamber 208. In particular, as shown, the system 200 comprises a fourth port 240 for mounting the deposition source 242 within the second chamber 208, where the fixture 226 is configured to be operated to expose the first facet 202A of the cleaved semiconductor structure 202 within the second chamber 208 to group III atoms from the deposition source 242 by positioning the first facet 202A against the deposition source 242 prior to exposing the first facet 202A to an oxidizing agent from the oxidation source 218. The system 200 further comprises a monitoring device (not shown). The monitoring device is contoured to be utilized to provide visibility for observing and / or monitoring the surface of the cleaved semiconductor structure 202 within the second chamber 208. To this end, as shown in FIG. 5, the system 200 further comprises a fifth port 244 in the form of a transparent viewport so that the cleaved semiconductor structure 202 inside the second chamber 208 can be observed using externally mounted monitoring equipment.

[0072] 3A, a representative diagram of an exemplary cleaved semiconductor structure 202 prior to cleaning the first facet 202A is shown. As shown, the first facet 202A includes a crystalline layer 228 thereon, the crystalline layer 228 being formed through group III to group V atoms. Additionally, the first facet 202A has an amorphous oxide layer 302 that contaminates the first facet 202A of the cleaved semiconductor structure 202. Thus, upon transferring the cleaved semiconductor structure 202 to the second chamber 208, the first facet 202A of the cleaved semiconductor structure 202 is exposed to a cleaning beam from the cleaning source 214 by manipulating the fixture 226 to remove the amorphous oxide layer 302. Beneficially, such a cleaning step quickly, accurately, and efficiently removes the amorphous oxide layer 302 from the first facet 202A of the cleaved semiconductor structure 202 prior to further processing.

[0073] 3B, there is shown a representative diagram of the exemplary cleaved semiconductor structure 202 after cleaning the first facet 202A of the cleaved semiconductor structure 202. As shown, upon cleaning the first facet 202A of the cleaved semiconductor structure 202, the amorphous oxide layer 302 is removed from the first facet 202A of the cleaved semiconductor structure 202, which may then be processed with other deposition or cleaning techniques as desired.

[0074] 3C, a representative diagram of an exemplary cleaved semiconductor structure 202 after cleaning a first facet 202A of the cleaved semiconductor structure 202 is shown having an ordered oxide layer 236 formed thereon, where an oxidation source 218 is configured to form the ordered oxide layer 236 via controlled oxidation onto a crystalline layer 228 formed on the first facet 202A, and a fixture 226 is configured to be operated to expose an oxidizing agent from the oxidation source 218 to produce the ordered oxide layer 236.

[0075] Referring to FIG. 4A, a schematic diagram of an exemplary stacking fixture 234 is shown, in accordance with one or more embodiments of the present disclosure. As shown, the stacking fixture 234 is configured to hold or stack a plurality of cleaved semiconductor structures 202 therein. The stacking fixture 234 includes either a screw or a spring 400 configured to apply an appropriate pressure to press the clamps 402 together and keep the plurality of semiconductor structures 202 "sandwiched" between the clamps 402. Referring to FIG. 4B, a detailed view of an exemplary fixture 226 that holds the plurality of cleaved semiconductor structures 202 in the second chamber 208 is shown. As shown, each of the plurality of cleaved semiconductor structures 202 is spaced apart by a spacing element 404 to separate and protect the contacts of each of the cleaved semiconductor structures 202, such that the contacts of two adjacent cleaved semiconductor structures 202 do not directly contact each other, such that they may melt. Spacing element 404 may be GaAs, sapphire, or the like.

[0076] 5, a schematic diagram of an exemplary second chamber 208 for passivating a cleaved semiconductor structure 202 is shown, in accordance with one or more embodiments of the present disclosure. As shown, a plurality of cleaved semiconductor structures 202 are loaded onto a fixture 226 in the second chamber 208. Here, by operating the fixture 226, a cleaning source 214 is exposed to a given facet (such as the first facet 202A) to remove an amorphous oxide layer (such as the amorphous oxide layer 302 shown in FIG. 3A) from the exposed facet of the cleaved semiconductor structure 202. Further, by operating the fixture 226, a deposition source 242 is exposed to the given facet (such as the first facet 202A) to form a passivation layer (such as the passivation layer 230 shown in FIG. 2B) on the exposed facet of the cleaved semiconductor structure 202. Additionally, by manipulating the fixture 226, the heating source 222 is exposed to a given facet (such as the first facet 202A) to heat the exposed facet of the cleaved semiconductor structure 202 to aid in the processes described above. As used herein, the heating source 222 may be used either before, after, or during the cleaning and / or oxidation processes.

[0077] 6, a graphical representation 600 of temperature change in a cleaved semiconductor structure 202 as a measure of distance from a heat source is shown, according to one embodiment of the present disclosure. As shown, the x-axis and y-axis represent distance (in meters) and temperature (in degrees Celsius) from the heat source, respectively. Here, it is observed that temperature follows an inverse relationship with distance, as the temperature decreases with increasing distance.

[0078] Referring to FIG. 7, a graphical representation 700 of differential scanning tunneling spectroscopy IV curves versus voltage for an edge-emitting laser device formed using the cleaved semiconductor structure 202 according to one embodiment of the present disclosure is shown. As shown, the x-axis and y-axis represent differential IV (i.e., ΔI / ΔV) and voltage (in volts), respectively, where an energy band gap is observed during operation. The edge-emitting laser device or the cleaved semiconductor structure 202 includes an ordered native oxide layer 236. As discussed above, the introduction of an ordered native oxide layer (such as the ordered native oxide layer 236) causes an increase in the energy band gap in the semiconductor device. The higher energy gap gives the edge-emitting laser device the ability to operate at higher temperatures, and the energy band gap typically decreases with increasing temperature, which presents a problem during the use of conventional semiconductors. For example, wide band gap materials allow the edge-emitting laser device to switch larger voltages.

Claims

1. A method for passivating a cleaved semiconductor structure for use as an end-face emitting laser device, wherein the method is: - To provide an enclosure comprising a first chamber and a second chamber, a transfer arm for receiving and transferring a given structure from the first chamber to the second chamber, and a fastener for mounting the given structure on the second chamber, such that each of the first and second chambers is adapted to provide a vacuum inside it. - Loading the cleaved semiconductor structure defining the first facet onto the transfer arm within the first chamber, - To attach the cleaved semiconductor structure to the fixing device in the second chamber, the transfer arm is used to transfer the cleaved semiconductor structure from the first chamber to the second chamber, - To remove any native oxide layer that may have formed on the first facet of the cleaved semiconductor structure, the first facet of the cleaved semiconductor structure in the second chamber is exposed to a cleaning beam from a cleaning source facing the first facet by operating the fixing device therein, - To heat the first facet of the cleaved semiconductor structure, the fixing device inside is operated to expose the first facet of the cleaved semiconductor structure in the second chamber to thermal energy from a heating source facing the first facet, - In order to form an ordered oxide layer on the first facet of the cleaved semiconductor structure, the fixing device in the second chamber is operated to expose the first facet of the cleaved semiconductor structure in the second chamber to an oxidizing agent from an oxidation source facing the first facet, Methods that include...

2. The method according to claim 1, further comprising, before exposing the first facet to the oxidizing agent from the oxidation source, exposing the first facet of the cleaved semiconductor structure in the second chamber to group III atoms from a deposition source facing the first facet by manipulating the fixing device therein, thereby depositing the group III atoms onto the first facet of the cleaved semiconductor structure.

3. Si,a-Si:H,SiO2 on the ordered oxide layer formed on the first facet of the cleaved semiconductor structure ２ SiN ｘ The method according to claim 1, further comprising depositing at least one of the layers.

4. The method according to claim 1, wherein the cleaning beam comprises at least one of an atomic beam of hydrogen, argon, xenon, or a mixture thereof, or an ion beam containing an ionized noble gas and / or nitrogen.

5. The method according to claim 1, wherein the heat beam provided by the heat source is at least one of laser irradiation and infrared radiation.

6. The oxidizing agent is molecular oxygen, oxygen plasma, ozone, NO ｘ The method according to claim 1, comprising at least one of CO.

7. The method according to claim 1, wherein a plurality of cleaved semiconductor structures are loaded into the first chamber, stacked on top of each other in their respective lateral facets, the first facets being orthogonal to the corresponding lateral facets in each of the cleaved semiconductor structures, and the method further comprises manipulating the fixture in the second chamber to expose each of the first facets of the cleaved semiconductor structures among the plurality of cleaved semiconductor structures to one or more of the cleaning beam from the cleaning source, the heat beam from the heating source, and the oxidizing agent from the oxidation source.

8. The method according to claim 1, wherein the cleaved semiconductor structure further defines a second facet therein, and the method further comprises manipulating the fixture in the second chamber to expose the second facet of the cleaved semiconductor structure to one or more of the cleaning beam from the cleaning source in the second chamber, the heat beam from the heating source, and the oxidizing agent from the oxidation source, without removing the semiconductor structure from the enclosure.

9. A system for passivating a cleaved semiconductor structure for use as an end-face emitting laser, wherein the system is - An enclosure having a first chamber and a second chamber, A pump configured to generate a vacuum inside the first chamber and the second chamber, - A cleaning source installed inside the second chamber, - An oxidation source installed in the second chamber, - A heating source installed inside the second chamber, A transfer arm configured to receive the cleaved semiconductor structure defining a first facet and to transfer it from the first chamber to the second chamber, - A fastener adapted to mount the given structure above it within the second chamber, The fastener is equipped with, - By positioning the first facet facing the cleaning source, the first facet of the cleaved semiconductor structure in the second chamber is exposed to the cleaning beam from the cleaning source. - By positioning the first facet opposite the heat source, the first facet of the cleaved semiconductor structure in the second chamber is exposed to thermal energy from the heat source. - By positioning the first facet opposite the oxidation source, the first facet of the cleaved semiconductor structure in the second chamber is exposed to the oxidizing agent from the oxidation source. A system configured to be operated in a certain way.

10. The system according to claim 9, wherein the heating source includes at least one of a laser and an infrared lamp.

11. An end-face emitting laser device formed by the method of any one of claims 1 to 8, wherein the end-face emitting laser is - A cleaved semiconductor structure having a multiple quantum well structure adapted to generate light of a specified wavelength, - At least one facet defined by cleaving the semiconductor structure along its crystal direction, wherein the at least one facet comprises the ordered oxide layer formed thereon, An end-face emitting laser device comprising the above features.

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