Display device

Abstract

To provide a display device capable of randomly changing an output timing of a data voltage by gate line.SOLUTION: A display device according to the present invention comprises a display panel including a gate line and a data line, a control unit generating a source output enable signal for determining an output timing of a data voltage output to the data line, and a data driver including a signal change unit for generating a final source output enable signal by using the source output enable signal, and randomly changing the output timing of the data voltage by gate line by using the final source output enable signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present specification relates to a display device. [Background technology]

[0002] Recently, a display device to which spread spectrum clock generation (SSCG) is applied has been proposed.

[0003] In a display device to which spread spectrum clock generation (SSCG) is applied, the dispersion of the periodicity of digital data and the spreading effect of analog output can reduce electromagnetic interference (EMI).

[0004] However, as the trend for high-resolution display devices increases, the transmission speed of digital data increases, which places a limit on the level of applicable spread spectrum clock generation (SSCG).

[0005] In particular, even in a display device to which a spread spectrum clock generator (SSCG) is applied, the timing at which a data voltage is output to a horizontal line is fixed, so that the effect of reducing electromagnetic interference (EMI) is reduced. Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS In order to solve the above problems, an object of the present invention is to provide a display device capable of randomly changing the output timing of a data voltage for each gate line. [Means for solving the problem]

[0007] In order to achieve the above-mentioned technical objectives, a display device according to the present invention includes a display panel having gate lines and data lines, a control unit that generates a source output enable signal that determines an output timing of a data voltage that is output to the data lines, a signal modification unit that generates a final source output enable signal using the source output enable signal, and a data driver that randomly changes the output timing of the data voltage for each gate line using the final source output enable signal. Effect of the Invention

[0008] In the present invention, the timing at which the data voltage is output to the data line can be randomly changed for each gate line, thereby preventing or reducing electromagnetic interference that may occur due to the data voltage being output at a fixed timing. [Brief description of the drawings]

[0009] [Figure 1] 1 is an exemplary diagram showing a configuration of a display device according to the present invention; [Diagram 2] 1 is an exemplary diagram showing a pixel structure applied to a display device according to the present invention; [Diagram 3] FIG. 2 is an exemplary diagram showing a configuration of a control unit applied to the display device according to the present invention. [Figure 4] 1 is an exemplary diagram showing a configuration of a gate driver applied to a display device according to the present invention; [Diagram 5] 1 is an exemplary diagram showing a configuration of a data driver applied to a display device according to the present invention; [Figure 6] 4 is an exemplary diagram showing waveforms of gate signals and data voltages applied to a display device according to the present invention; [Figure 7] 4 is an exemplary diagram illustrating an output timing of a data voltage output by a display device according to the present invention; [Figure 8] 4 is an exemplary diagram illustrating an output timing of a data voltage output by a display device according to the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The advantages and features of the present invention, as well as the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and is provided to fully disclose the present invention and to inform those skilled in the art of the scope of the invention. The present invention is defined solely by the claims.

[0011] Please note that in this specification, when adding reference numbers to components in each figure, identical components will have the same numbers as much as possible, even if they appear in different figures.

[0012] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. The same components may be given the same reference numbers throughout this specification. In addition, in the description of the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When "including," "having," "consisting of," etc. are used in this specification, other parts may be added unless the expression "only" is used. When a component is expressed in the singular, it includes a plural unless otherwise explicitly stated.

[0013] When interpreting elements, they are to be interpreted as including an error range even if there is no explicit specification otherwise.

[0014] When describing a positional relationship, for example when the positional relationship of two parts is described using "above", "at the top", "below", "beside", etc., one or more other parts may be located between the two parts unless the words "immediately" or "directly" are used.

[0015] When describing a temporal relationship, for example when the temporal precedence is described using "after", "following", "next to", "before", etc., it can also include cases where the relationship is not consecutive, unless the words "immediately" or "directly" are used.

[0016] The term "at least one" should be understood to include all possible combinations of one or more of the associated items. For example, "at least one of the first, second, and third items" means each of the first, second, or third items, and all possible combinations of items that can be present from two or more of the first, second, and third items.

[0017] Although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of the present invention.

[0018] The features of the various embodiments of the present invention may be partially or fully combined or combined with each other, may be technically linked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in relation to each other.

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0020] FIG. 1 is an exemplary diagram showing a configuration of a display device according to the present invention, FIG. 2 is an exemplary diagram showing a pixel structure applied to the display device according to the present invention, FIG. 3 is an exemplary diagram showing a configuration of a control unit applied to the display device according to the present invention, and FIG. 4 is an exemplary diagram showing a configuration of a gate driver applied to the display device according to the present invention.

[0021] The display device according to the present invention can be used to configure various electronic devices, such as smartphones, tablet PCs, televisions, and monitors.

[0022] As shown in FIG. 1, the display device according to the present invention includes a display panel 100 including a display area 120 where an image is output and a non-display area 130 provided on the periphery of the display area, a gate driver 200 that supplies gate signals to gate lines (GL1 to GLg) provided in the display area 120 of the display panel, a data driver 300 that supplies data voltages to data lines (DL1 to DLd) provided on the display panel, a control unit 400 that controls the driving of the gate driver 200 and the data driver 300, and a power supply unit 500 that supplies power to the control unit, the gate driver, the data driver, and the display panel.

[0023] First, the display panel 100 includes a display area 120 and a non-display area 130. In the display area 120, gate lines (GL1 to GLg), data lines (DL1 to DLd), and pixels 110 are provided. Therefore, an image is output in the display area 120. g and d are natural numbers. The non-display area 130 surrounds the outer periphery of the display area 120.

[0024] 2, a pixel 110 provided in the display panel 100 includes a switching transistor (Tsw1), a storage capacitor (Cst), a driving transistor (Tdr) and a sensing transistor (Tsw2), and may include a light emitting unit including a pixel driving circuit (PDC) and a light emitting element (ED).

[0025] A first terminal of the driving transistor Tdr is connected to a high voltage supply line PLA through which a high voltage EVDD is supplied, and a second terminal of the driving transistor Tdr is connected to the light emitting element ED.

[0026] A first terminal of the switching transistor (Tsw1) is connected to the data line (DL), a second terminal of the switching transistor (Tsw1) is connected to the gate of the driving transistor (Tdr), and a gate of the switching transistor (Tsw1) is connected to the gate line (GL).

[0027] A data voltage (Vdata) is supplied to the data line (DL), and a gate signal (GS) is supplied to the gate line (GL).

[0028] A sensing transistor (Tsw2) may be provided to measure the threshold voltage or mobility of the driving transistor. A first terminal of the sensing transistor (Tsw2) is connected to the second terminal of the driving transistor (Tdr) and the light emitting element (ED), a second terminal of the sensing transistor (Tsw2) is connected to a sensing line (SL) to which a reference voltage (Vref) is supplied, and a gate of the sensing transistor (Tsw2) is connected to a sensing control line to which a sensing control signal is supplied.

[0029] The sensing line (SL) may be connected to the data driver 300, and may also be connected to the power supply unit 500 through the data driver 300. That is, a reference voltage (Vref) provided from the power supply unit 500 may be provided to the pixel through the sensing line (SL), and a sensing signal transmitted from the pixel may be processed by the data driver 300.

[0030] The structure of the pixel 110 applied to the present invention is not limited to the structure shown in Fig. 2. Therefore, the structure of the pixel 110 can be changed into various forms.

[0031] Furthermore, the present invention can be applied not only to a light-emitting display device including a light-emitting element as shown in Fig. 2, but also to a liquid crystal display device including a liquid crystal display panel. That is, the present invention can be applied to various types of display devices currently in use. However, for convenience of explanation, a light-emitting display device will be described below as an example of the present invention.

[0032] Next, the controller 400 can realign the input image data transmitted from the external system using a timing synchronization signal transmitted from the external system, and can generate a data control signal (DCS) and a gate control signal (GCS) to be supplied to the data driver 300 and the gate driver 200.

[0033] To this end, as shown in FIG. 3, the control unit 400 may include a data alignment unit 430 for realigning input image data to generate image data (DATA) and supplying the image data (DATA) to the data driver 300, a control signal generation unit 420 for generating a gate control signal (GCS) and a data control signal (DCS) using a timing synchronization signal, an input unit 410 for receiving the timing synchronization signal and input image data transmitted from an external system and transmitting the received data to the data alignment unit and the control signal generation unit, and an output unit 440 for supplying the image data (DATA) generated by the data alignment unit and the data control signal (DCS) generated by the control signal generation unit to the data driver 300 and outputting the gate control signal (GCS) generated by the control signal generation unit to the gate driver 200.

[0034] The control unit 400 can include a storage unit 450 that can store various types of information.

[0035] The data control signal (DCS) generated by the control signal generator 420 may include a source output enable signal (SOE) that controls the timing at which the data voltage is output to the data line.

[0036] The source output enable signal (SOE) generated by the control signal generating unit 420 is transmitted to the data driver 300 .

[0037] That is, the control unit 400 generates a source output enable signal (SOE) that determines the output timing of the data voltage (Vdata) that is output to the data line (DL), and the generated source output enable signal (SOE) is transmitted to the data driver 300.

[0038] The external system functions to drive the controller 400 and the electronic device. For example, if the electronic device is a television (TV), the external system can receive various audio information, video information, text information, etc. through a communication network and transmit the received video information to the controller 400. In this case, the video information can be input video data.

[0039] Next, the power supply unit 500 generates various power supplies and supplies the generated power supplies to the control unit 400, the gate driver 200, the data driver 300, and the display panel 100.

[0040] Next, the gate driver 200 is configured as an integrated circuit and then mounted in the non-display area 130. The gate driver 200 can also be directly built into the non-display area 130 using a gate in panel (GIP) method. When using the gate in panel method, the transistors constituting the gate driver 200 can be provided in the non-display area through the same process as the transistors provided in each pixel 110 in the display area.

[0041] The gate driver 200 supplies gate pulses (GP1 to GPg) to the gate lines (GL1 to GLg).

[0042] When a gate pulse generated by the gate driver 200 is supplied to the gate of a switching transistor (Tsw1) provided in the pixel 110, the switching transistor is turned on. When the switching transistor is turned on, the data voltage supplied via the data line is supplied to the pixel 110.

[0043] When a gate-off signal generated by the gate driver 200 is supplied to the switching transistor Tsw1, the switching transistor Tsw1 is turned off. When the switching transistor is turned off, the data voltage is no longer supplied to the pixel 110.

[0044] The gate signal (GS) supplied to the gate line (GL) includes a gate pulse (GP) and a gate off signal.

[0045] To this end, the gate driver 200 may include a stage 201, as shown in FIG.

[0046] Each of the stages 201 may be connected to at least one gate line (GL). Each of the stages 201 may be driven by a start signal transmitted from the control unit 400 or a start signal transmitted from a previous stage or a subsequent stage.

[0047] Each of the stages 201 can be constructed in a variety of forms including at least two transistors.

[0048] Finally, the data driver 300 can be provided on a chip-on-film that is attached to the display panel 100 or can be mounted directly to the display panel 100 .

[0049] The data driver 300 supplies a data voltage (Vdata) to the data lines (DL1 to DLd).

[0050] The data driver 300 generates a sampling signal by shifting a source start pulse transmitted from the controller 400 according to a source shift clock. The data driver 300 latches image data according to the sampling signal, converts the latched image data into a data voltage, and then supplies the data voltage corresponding to the gate line to the data lines (Dl1 to Dld) according to a final source output enable signal.

[0051] In particular, the data driver 300 randomly changes the output timing of the data voltage (Vdata) for each gate line using a source output enable signal (SOE) transmitted from the controller 400 .

[0052] The structure and function of the data driver 300 will now be described with reference to FIGS.

[0053] FIG. 5 is an exemplary diagram showing a configuration of a data driver applied to the display device according to the present invention.

[0054] As described above, the data driver 300 latches the image data transmitted from the control unit 400 according to the sampling signal, converts the latched image data into a data voltage, and then supplies the data voltage (Vdata) corresponding to the gate line to the data lines (DL1 to Dld) according to the final source output enable signal.

[0055] In particular, the data driver 300 applied to the present invention performs a function of randomly changing the output timing of the data voltage (Vdata) for each gate line using a source output enable signal (SOE) transmitted from the control unit 400.

[0056] The source output enable signal (SOE) may include at least four bits, each of which has a value of 0 or 1.

[0057] That is, the data driver 300 can determine the output timing of the data voltage according to a four-bit source output enable signal (SOE).

[0058] However, the data driver 300 does not use the source output enable signal (SOE) as it is. That is, the data driver 300 generates a final source output enable signal (SOEF) using the source output enable signal (SOE) and can randomly change the output timing of the data voltage (Vdata) for each gate line using the final source output enable signal (SOEF).

[0059] In this case, the data driver 300 generates a final source output enable signal (SOEF) by changing at least two bits of the at least four bits, and can randomly change the output timing of the data voltage for each gate line using the final source output enable signal (SOEF).

[0060] The timing at which the data voltage (Vdata) is output to the data line (DL) may be different from each other based on the falling timing of the gate pulses (GP1 to GPg) output to the gate lines (GL1 to GLg).

[0061] For this purpose, as shown in FIG. 5, the data driver 300 includes a shift register unit 310 for outputting a sampling signal, a latch unit 320 for latching image data (Data) received from the control unit 400, an analog-to-digital converter 330 for converting the image data (Data) transmitted from the latch unit 320 into a data voltage (Vdata) and outputting the data voltage, an output buffer 340 for outputting the data voltage transmitted from the analog-to-digital converter 330 to a data line (DL) in response to a final source output enable signal (SOEF), and a signal modifying unit 350 for generating a final source output enable signal (SOEF) using the source output enable signal (SOE) and for randomly modifying the output timing of the data voltage for each gate line using the final source output enable signal (SOEF).

[0062] First, the shift register unit 310 outputs a sampling signal using a data control signal (DCS) received from the control unit 400 .

[0063] Next, the latch unit 320 latches the image data sequentially received from the control unit 400, and then simultaneously outputs the image data to the analog-to-digital converter (DAC) 330 according to a sampling signal.

[0064] Next, the analog-to-digital converter 330 simultaneously converts the image data (Data) transmitted from the latch unit 320 into data voltages (Vdata1 to Vdatad) and outputs them.

[0065] Next, the output buffer 340 simultaneously outputs the data voltages (Vdata1 to Vdatad) transmitted from the analog-to-digital conversion unit 330 to the data lines (DL1 to DLd) of the display panel in accordance with the final source output enable signal (SOEF) transmitted from the signal modification unit 350.

[0066] To this end, the output buffer 340 includes a buffer 341 that stores the data voltage transmitted from the analog-to-digital converter 330, and a switch 342 that outputs the data voltage (Vdata) stored in the buffer 341 to the data line (DL) in response to a final source output enable signal (SOEF).

[0067] That is, the output buffer 340 includes switches 342 corresponding to the data lines (DL1 to DLd) and buffers 341. The buffers 341 and the switches 342 can be connected in a one-to-one relationship.

[0068] More specifically, when the switch 342 is turned on according to a final source output enable signal (SOEF) simultaneously supplied to the switch 342, the data voltage (Vdata) stored in the buffer 341 can be supplied to the data lines (DL1 to DLd) through the switch 342.

[0069] The data voltages (Vdata1 to Vdatad) supplied to the data lines (DL1 to DLd) are supplied to the pixels connected to the gate line (GL) to which the gate pulse (GP) is supplied.

[0070] Therefore, the timing at which the data voltages (Vdata1 to Vdatad) are output to the data lines (DL1 to DLd) can be determined by the final source output enable signal (SOEF).

[0071] Finally, the signal modifying unit 350 generates a final source output enable signal (SOEF) using the source output enable signal (SOE) and performs a function of randomly modifying the output timing of the data voltage (Vdata) for each gate line using the final source output enable signal (SOEF).

[0072] To this end, the signal modification unit 350 includes a random bit generator 351 that generates at least two random bits and a bit mixer 352 that replaces at least two of the at least four bits that constitute the source output enable signal (SOE) with at least two random bits to generate a final source output enable signal (SOEF).

[0073] That is, the source output enable signal (SOE) generated by the control unit 400 and supplied to the data driver 300 may include at least four bits, and the signal modification unit 350 modifies at least two of the at least four bits to generate the final source output enable signal (SOEF).

[0074] To this end, the random bit generator 351 is capable of generating at least two random bits.

[0075] For example, if the source output enable signal (SOEF) is composed of eight bits, each bit having a value of 0 or 1, the random bit generator 351 can generate two random bits. Each of the two random bits can have a value of 0 or 1.

[0076] In this case, the number of cases generated by the bit mixer 352 is four according to two random bits, so the timing at which the data voltage is output to the data line (DL) can be divided into four.

[0077] For example, if an 8-bit source output enable signal (SOE) has a value [10111010], the last two of the 8 bits can be changed to any of four values ​​that can be generated by two random bits, namely [00, 01, 10, 11].

[0078] Therefore, the source output enable signal (SOEF) finally generated by the bit mixer 352 can be any one of [10111000], [10111001], [10111010], and [10111011].

[0079] That is, the signal modifying unit 350 can generate one of four final source output enable signals (SOEF) using the source output enable signal (SOE) transmitted from the control unit 400.

[0080] In this case, the random bit generator 351 can randomly generate two random bits, so that the final source output enable signal (SOEF) generated by the bit mixer 352 can also be generated randomly.

[0081] Therefore, the timing at which the data voltage is output to the data line DL can be divided into four.

[0082] However, as mentioned above, the source output enable signal (SOE) can be formed of at least four bits, and the random bit generator 351 can generate at least two random bits.

[0083] Therefore, as the number of random bits generated by the random bit generator 351 increases, the timing at which the data voltage is output to the data line DL can be divided into more diverse ranges.

[0084] For example, when the number of random bits is three, the number of combinations that can be formed by the three random bits is eight, such as

[0000] ,

[0001] ,

[0010] ,

[0011] ,

[0100] ,

[0101] ,

[0110] , and

[0111] . Therefore, when the number of random bits is three, the timing at which the data voltage is output can be divided into eight.

[0085] More specifically, a switch 342 constituting the output buffer 340 is turned on by a final source output enable signal (SOEF) to output a data voltage to the data line.

[0086] In this case, the timing at which switch 342 is turned on is determined by the value of a bit that constitutes the final source output enable signal (SOEF).

[0087] Therefore, when the number of cases of the final source output enable signal (SOEF) is four, the timing at which the data voltage is output to the data line (DL) can be divided into four.

[0088] In this case, the timing at which the data voltage is output to the data line may be different from each other based on the falling timing of the gate pulse output to the gate line.

[0089] A specific example of this will be described below with reference to FIGS.

[0090] FIG. 6 is a diagram showing an example of waveforms of gate signals and data voltages applied to a display device according to the present invention.

[0091] In the following, a display device in which the source output enable signal (SOE) has 8 bits and two random bits are generated by the random bit generator 351 will be described as an example of the present invention.

[0092] That is, as described above, when the source output enable signal (SOE) generated by the control unit 400 and supplied to the data driver 300 is composed of 8 bits and two random bits are generated by the random bit generator 351, the number of final source output enable signals (SOEF) that can be generated using one source output enable signal (SOE) is four.

[0093] In this case, as shown in FIG. 6, the interval between the falling timing of the gate pulse output to the gate line and the final source output enable signal (SOEF) can be controlled by two random bits.

[0094] For example, as shown in Figures 1 and 6, five gate pulses (GPn to GPn+4) output to five consecutive gate lines (GLn to GLn+4) have the same pulse width and are spaced apart from one another. That is, the rising and falling timings of the gate pulses (GPn to GPn+4) are repeated at the same intervals.

[0095] In this case, at the timing when the gate pulse (GP) falls, the data voltage (Vdata) supplied via the data line is finally charged to the pixel 110, and light corresponding to the charged voltage can be output from the pixel 110.

[0096] Therefore, when the data voltage (Vdata) is superimposed on the falling timing of the gate pulse (GP), the superimposed data voltage (Vdata) can be supplied to the pixel.

[0097] In this case, the two random bits can control the polling timing of the gate pulses (GPn to GPn+4) and the interval between the final source output enable signals (SOEF), as shown in FIG. 6, and therefore the timing at which the data voltages are output to the data lines can be different from each other based on the polling timing of the gate pulses.

[0098] In particular, according to the above example, four final source output enable signals (SOEF) can be outputted by two random bits, and therefore the timing at which the data voltage is outputted can be divided into four.

[0099] For example, when the nth gate pulse (GPn) is output to the nth gate line (GLn), the nth data voltage (n) output to the data line is output by the nth final source output enable (SOEFn) signal. The final source output enable signal (SOEF) including the nth final source output enable signal (SOEFn) is a digital value, but for convenience of explanation, the final source output enable signal (SOEF) is shown as a waveform in FIG. 6. In this case, the nth final source output enable signal (SOEFn) can include random bits of

[00] .

[0100] That is, the nth data voltage (n) is output to the pixel connected to the nth gate line (GLn) by the nth final source output enable signal (SOEFn) including the random bit

[00] .

[0101] In this case, the timing when the nth gate pulse (GPn) falls and the timing when the nth data voltage (n) is output to the data line may have an interval of A, as shown in FIG.

[0102] Also, the point (n+1) at which the n+1th gate pulse (GPn+1) is output to the n+1th gate line (GLn+1) is output by the n+1th final source output enable signal (SOEFn+1). In this case, the n+1th final source output enable signal (SOEFn+1) may include a random bit of

[01] .

[0103] That is, the n+1th data voltage (n+1) is output to the pixel connected to the n+1th gate line (GLn+1) by the n+1th final source output enable signal (SOEFn+1) including the random bit

[01] .

[0104] In this case, the interval between the falling timing of the (n+1)th gate pulse (GPn+1) and the timing at which the (n+1)th data voltage (n+1) is output to the data line may be an interval B, as shown in FIG.

[0105] In addition, when the n+2th gate pulse (GPn+2) is output to the n+2th gate line (GLn+2), the n+2th data voltage (n+2) output to the data line is output by the n+2th final source output enable signal (SOEFn+2). In this case, the n+2th final source output enable signal (SOEFn+2) may include a random bit of

[10] .

[0106] That is, the n+2th data voltage (+2) is output to the pixel connected to the n+2th gate line (GLn+2) by the n+2th final source output enable signal (SOEFn+2) including the random bit

[10] .

[0107] In this case, the timing at which the (n+2)th gate pulse (GPn+2) falls and the timing at which the (n+2)th data voltage (n+2) is output to the data line may have an interval of C, as shown in FIG.

[0108] In addition, when the n+3 gate pulse (GPn+3) is output to the n+3 gate line (GLn+3), the n+3 data voltage (n+3) output to the data line is output by the n+3 final source output enable signal (SOEFn+3). In this case, the n+3 final source output enable signal (SOEFn+3) may include the random bit of

[11] .

[0109] That is, the n+3th data voltage (n+3) is output to the pixel connected to the n+3th gate line (GLn+3) by the n+3th final source output enable signal (SOEFn+3) including the random bit

[11] .

[0110] In this case, the interval between the falling timing of the (n+3)th gate pulse (GPn+3) and the timing when the (n+3)th data voltage (n+3) is output to the data line may be an interval D, as shown in FIG.

[0111] In this case, the intervals A, B, C, and D may all be different from each other, so that the data voltage outputted through one data line DL may be outputted at different timings for each gate line.

[0112] However, at least two of the A intervals, B intervals, C intervals and D intervals may be identical, and the A intervals, B intervals, C intervals and D intervals may not be repeated.

[0113] That is, in the present invention, two random bits are randomly selected by the random bit generator 351. Therefore, the random bit

[00] , the random bit

[01] , the random bit

[10] , and the random bit

[11] are not selected in that order, and the order in which the random bit

[00] , the random bit

[01] , the random bit

[10] , and the random bit

[11] are selected is not fixed.

[0114] For example, in the above example, the random bit of

[00] , the random bit of

[01] , the random bit of

[10] , and the random bit of

[11] were selected in order to generate the final source output enable signal (SOEFn, SOEFn+1, SOEFn+2, SOEFn+3), but the final source output enable signal (SOEFn, SOEFn+1, SOEFn+2, SOEFn+3) may be generated in the order of the random bit of

[00] , the random bit of

[11] , the random bit of

[10] , and the random bit of

[01] .

[0115] In addition, after a final source output enable signal (SOEFn, SOEFn+1) including a random bit of

[00] and a random bit of

[11] is generated, a final source output enable signal (SOEFn+2, SOEFn+3) including a random bit of

[01] and a random bit of

[10] can also be generated.

[0116] More specifically, when the n+4th gate pulse (GPn+4) is output to the n+4th gate line (GLn+4), the n+4th data voltage (n+4) output to the data line is output by the n+4th final source output enable signal (SOEFn+3). In this case, the n+4th final source output enable signal (SOEFn+3) can include any one of a random bit of

[00] , a random bit of

[01] , a random bit of

[10] , and a random bit of

[11] .

[0117] For example, Fig. 6 shows an example in which the n+4th final source output enable signal (SOEFn+3) is output by a random bit of

[01] . Therefore, the interval between the falling edge of the n+4th final source output enable signal (SOEFn+3) and the output of the n+4th data voltage (n+4) to the data line can have an interval B, as shown in Fig. 6.

[0118] Therefore, the timing at which the n+4th data voltage (n+4) is output to the data line by the n+4th final source output enable signal (SOEFn+4) may be the same as the timing at which the n+1st data voltage (n+1) is output to the data line by the n+1th final source output enable signal (SOEFn+1).

[0119] That is, the four pairs of random bits described above are not necessarily selected once every four times, and the order of the random bits may be changed in various ways.

[0120] Therefore, according to the present invention, the timing at which the data voltage is output to the gate line is not fixed, and therefore, according to the present invention, it is possible to prevent or minimize electromagnetic interference that may occur due to the data voltage being output at a fixed timing.

[0121] 7 and 8 are exemplary diagrams illustrating output timings of data voltages output by a display device according to the present invention, in particular, FIG 7 is an exemplary diagram for visually showing that the timings at which data voltages are output to gate lines are different.

[0122] That is, as described above, the timing at which the nth data voltage (Vdatan) is output to the pixel connected to the nth gate line (GLn) may be different from the timing at which the n+1th data voltage (Vdatan+1) is output to the pixel connected to the n+1th gate line (GLn+1).

[0123] Therefore, as shown in FIG. 7, the timing at which the data voltage is output may differ for each gate line, and in particular, the timing at which the data voltage is output to the data lines may differ from each other based on the falling timing of the gate pulse (GP) output to the gate lines.

[0124] More specifically, as shown in FIG. 7, the rising timing (R) and falling timing (F) of the gate pulse (GP) outputted to the nth gate line to the n+4th gate line (GLn+4) are constant.

[0125] However, based on the falling timing (F) of the gate pulse (GP), the nth data voltage (Vdatan) to the n+4th data voltage (Vdata n The timings at which the nth data voltage (Vdatan) to the n+4th data voltage (Vdatan+4) are output may be different from each other. However, the timings at which the nth data voltage (Vdatan) to the n+4th data voltage (Vdatan+4) are output may include the same timing. That is, in the example shown in FIG. 6 and FIG. 7, the timing (B) at which the n+4th data voltage (Vdatan+4) is output to the data line by the n+4th final source output enable signal (SOEFn+4) is the same as the timing at which the n+1th data voltage (Vdatan+1) is output to the data line by the n+1th final source output enable signal (SOEFn+1).

[0126] Therefore, as shown in FIG. 8, the intervals (K1 to K4) between the timings at which the data voltages (Vdatan to Vdatan+4) are output to the data lines can also be changed randomly.

[0127] As described above, according to the present invention, the timing at which the data voltage is output to the gate line is not fixed, and therefore, according to the present invention, it is possible to prevent or minimize electromagnetic interference that may occur due to the data voltage being output at a fixed timing.

[0128] Those skilled in the art to which the present invention pertains will understand that the present invention can be embodied in other specific forms without changing its technical concept or essential features. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. The scope of the present invention is indicated by the claims below, not by the above detailed description, and all modifications or alterations derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0129] 100: Display panel 200: Gate driver 300: Data driver 400: Control unit

Claims

1. A display panel equipped with gate lines and data lines, A control unit that generates at least four-bit source output enable signals to determine the initial output timing of the data voltage output to the data line, A gate driver that supplies gate pulses to the gate line, A data driver comprising a signal modification unit that generates a final source output enable signal by replacing at least two of the at least four bits of the source output enable signal with random bits, Includes, The initial output timing of the data voltage is randomly changed for each gate line by controlling the interval between the falling edge timing of the gate pulse and the rising edge timing of the final source output enable signal using the random bit. Display device.

2. The aforementioned data driver A latch unit that latches image data received from the control unit, An analog-to-digital conversion unit that converts the video data transmitted from the latch unit into the data voltage and outputs it, An output buffer that outputs the data voltage transmitted from the analog-to-digital conversion unit to the data line by the final source output enable signal, The signal modification unit and It further includes, The output timing of the data voltage is randomly changed for each gate line by the final source output enable signal. The display device according to claim 1.

3. The output buffer, A buffer for storing the data voltage transmitted from the analog-to-digital conversion unit, The final source output enable signal enables a switch that outputs the data voltage stored in the buffer to the data line. The display device according to claim 2, including the following:

4. The signal modification unit is, A random bit generator that generates at least two of the aforementioned random bits, A bit mixer that replaces at least two of the four bits with the random bits to generate the final source output enable signal, The display device according to claim 2, including the following:

5. The display device according to claim 4, wherein the timing at which the data voltage is output to the data line is divided into at least four stages.

6. The display device according to claim 5, wherein the timing at which the data voltage is output to the data line differs from that of the falling edge timing of the gate pulse output to the gate line provided on the display panel.

7. The display device according to claim 4, wherein the timing at which the nth data voltage is output to a pixel connected to the nth gate line among the gate lines provided on the display panel via the data line is different from the timing at which the (n+1)th data voltage is output to a pixel connected to the (n+1)th gate line via the data line.

8. The display device according to claim 1, wherein the timing at which the data voltage is output to the data line differs from that of the falling edge timing of the gate pulse output to the gate line provided on the display panel.

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