Semiconductor device
Patent Information
- Application Number
- JP2023022573
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-02-16
- Publication Date
- 2025-12-24
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to a semiconductor device. [Background technology]
[0002] Semiconductor devices such as operational amplifiers include analog circuits such as a reference voltage circuit, a current mirror circuit, etc. MOS transistors used in such analog circuits must have the same subthreshold characteristics, including threshold voltage, mutual conductance, and leakage current, if they have the same structure and layout.
[0003] A current mirror circuit is configured so that a current supply source MOS transistor and a current supply destination MOS transistor whose gates are connected to each other are paired. If the pair of MOS transistors has the same structure and layout, it has the function of passing the same current value as the current supply source MOS transistor to the current supply destination MOS transistor.
[0004] In a current mirror circuit, if a difference in characteristics occurs between paired MOS transistors, a current error may occur, which may degrade the performance of the semiconductor device and cause unintended malfunctions.
[0005] Differences in the characteristics of MOS transistors that form a pair in an analog circuit are caused by differences in leakage current between the MOS transistors.
[0006] To suppress this leakage current difference, for example, in the invention described in Patent Document 1, only one MOS transistor is placed inside one well region. If the leakage current remains low, the leakage current difference between individual MOS transistors does not become so large, so the performance of the analog circuit is less likely to degrade. [Prior art documents] [Patent documents]
[0007] [Patent Document 1] JP 2010-129645 A Summary of the Invention [Problem to be solved by the invention]
[0008] One aspect of the present invention aims to provide a semiconductor device that can suppress the occurrence of leakage current differences and suppress the occurrence of performance degradation in analog circuits even when multiple MOS transistors are arranged inside one well region. [Means for solving the problem]
[0009] The semiconductor device according to an embodiment of the present invention comprises: A semiconductor substrate; a rectangular first well region of a first conductivity type formed on a surface of the semiconductor substrate; a second well region of a second conductivity type that is in contact with the first well region and is formed in a region other than the first well region and has an impurity concentration higher than that of the first well region; a high concentration impurity region of a second conductivity type formed on a surface of the first well region; having When the short side of the first well region is less than a predetermined dimension, the distance between the long side of the first well region and the high concentration impurity region is large. Effect of the Invention
[0010] According to one aspect of the present invention, it is possible to provide a semiconductor device that can suppress the occurrence of leakage current differences and suppress the occurrence of performance degradation of analog circuits even when multiple MOS transistors are arranged inside one well region. [Brief description of the drawings]
[0011] [Figure 1] FIG. 1 is a schematic plan view showing a semiconductor device in which the dimension of the short side of a P-type well region is less than 10 μm in an embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along line II-II shown in FIG. [Diagram 3] FIG. 3 is a schematic plan view showing a semiconductor device in which the dimension of the short side of the P-type well region is 10 μm or more in the embodiment of the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line IV-IV shown in FIG. [Diagram 5] FIG. 5 is an explanatory diagram showing the distance from the long side of the P-type well region to the N-type high concentration impurity region and the characteristics of the leakage current. [Figure 6] FIG. 6 is a graph showing the relationship between the dimension of the short side of the P-type well region and the distance from the long side of the P-type well region to the N-type high concentration impurity region at which a leakage current of 1 nA occurs. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0012] The semiconductor device according to one embodiment of the present invention is based on the following findings.
[0013] A well region in a semiconductor device is formed by injecting impurities into a predetermined area on the surface of a semiconductor substrate and then thermally diffusing the impurities. The impurities in the well region injected into the surface of the semiconductor substrate diffuse from a region with a high impurity concentration to a region with a low impurity concentration due to this thermal diffusion. Therefore, the impurities in the well region diffuse based on the concentration difference between the center of the well region, which has a high impurity concentration, and the end of the well region, which has a low impurity concentration, and diffusion at the end of the well region is promoted.
[0014] When the size of the well region is equal to or larger than a certain value, the impurities continue to diffuse from the center to the edges of the well region, but when the size of the well region is smaller than a certain value, the impurities in the center of the well region that should be supplied to the edges of the well region tend to be depleted, resulting in a decrease in the impurity concentration in the center of the well region. In this case, the difference in impurity concentration between the center and edges of the well region decreases, and the amount of impurity diffusion decreases.
[0015] For the above reasons, when a well region is smaller than a certain size, the amount of impurities diffusing from the center to the edges of the well region decreases as the size of the well region decreases, and the leakage current of the MOS transistor at the edges of the well region tends to increase.
[0016] For this reason, a difference in leakage current occurs between MOS transistors that are located at different distances from the edge of the well region.
[0017] If the semiconductor device is a digital circuit, there is little possibility that a small difference in leakage current will cause a degradation in performance. However, in an analog circuit such as a current mirror circuit, a difference in leakage current will cause a degradation in performance, which may result in unintended malfunction.
[0018] Therefore, in one embodiment of the present invention, in a semiconductor device, when the short side of the well region in which the MOS transistor is formed is less than a specified dimension, the distance separating the high concentration impurity region of the MOS transistor from the long side of the well region is increased.
[0019] As a result, this semiconductor device can reduce the effects of fluctuations in impurity concentration at the ends of the well region, thereby suppressing the occurrence of leakage current differences between MOS transistors that form the analog circuit and suppressing performance degradation of the analog circuit.
[0020] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0021] In the drawings, the same components are denoted by the same reference numerals, and duplicate explanations may be omitted.
[0022] In addition, the X-axis, Y-axis, and Z-axis shown in the drawings are mutually perpendicular. The X-axis direction may be referred to as the "width direction", the Y-axis direction as the "depth direction", and the Z-axis direction as the "height direction" or "thickness direction". The surface of each film on the +Z direction side may be referred to as the "front surface" or "upper surface", and the surface on the -Z direction side as the "rear surface" or "lower surface".
[0023] Furthermore, the drawings are schematic, and the ratios of width, depth, and thickness are not as shown. The number, position, shape, structure, size, etc. of a plurality of films or layers, or a semiconductor element obtained by structurally combining them, are not limited to the embodiments shown below, and may be any number, position, shape, structure, size, etc. that is preferable for implementing the present invention.
[0024] Fig. 1 is a schematic plan view showing a semiconductor device in which the dimension Wx1 of the short sides M1 and M2 of the P-type well region is less than 10 um and the dimension Wy1 of the long sides L1 and L2 is 10 um or more in an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along line II-II shown in Fig. 1.
[0025] The semiconductor device 10 has an analog circuit using N-type MOS transistors 111, 112, 113, 114, 115, and 116. The analog circuit is, for example, an operational amplifier, a current mirror circuit, or the like.
[0026] The semiconductor device 10 includes an N-type semiconductor substrate 101, a P-type well region 102, an N-type well region 103, and N-type high concentration impurity regions 111a, 111b, 112a, 112b, 113a, 113b, 114a, 114b, 115a, 115b, 116a, and 116b.
[0027] The N-type semiconductor substrate 101 is a wafer-shaped N-type silicon semiconductor substrate.
[0028] P-type well region 102 as a first well region is formed by injecting P-type impurities into a predetermined range on the surface of N-type semiconductor substrate 101. The dimension Wx1 of the short side of P-type well region 102 is less than 10 um, and the dimension Wy1 of the long side is 10 um or more.
[0029] N-type well region 103 as a second well region is formed by injecting N-type impurities into a predetermined range on the surface of N-type semiconductor substrate 101, so as to be in contact with P-type well region 102. N-type well region 103 has a higher impurity concentration than the P-type well region.
[0030] The N-type MOS transistors 111-116 are part of an analog circuit and are designed to have the same channel length and width so as to have the same characteristics. The N-type MOS transistors 111-116 are connected to other MOS transistors via metal wiring (not shown).
[0031] The N-type MOS transistors 111-116 are formed on the surface of the P-type well region 102 and in its vicinity, and each include N-type high concentration impurity regions 111a, 111b, 112a, 112b, 113a, 113b, 114a, 114b, 115a, 115b, 116a, and 116b as high concentration impurity regions of the second conductivity type.
[0032] The N-type high concentration impurity regions 111a, 112b, 113a, 114b, 115a, and 116b are disposed at a distance Sx1 from the long sides L1 and L2 of the P-type well region 102. The N-type high concentration impurity regions 111a, 111b, 112a, 112b, 115a, 115b, 116a, and 116b are disposed at a distance Sy1 from the short sides M1 and M2 of the P-type well region 102. Here, Sx1 is greater than Sy1.
[0033] A method for manufacturing the semiconductor device 10 will now be described. A P-type impurity is implanted into a predetermined area on the surface of the semiconductor substrate 101 using photolithography and ion implantation.
[0034] Next, N-type impurities are implanted into a predetermined area on the surface of the semiconductor substrate 101 using photolithography and ion implantation.
[0035] Next, the P-type and N-type impurities on the surface of the semiconductor substrate 101 are diffused to a predetermined depth by thermal diffusion using a high-temperature heat treatment, thereby forming a P-type well region 102 and an N-type well region 103 .
[0036] Thereafter, an element isolation film is formed on the surface of the P-type well region 102 in an area where the N-type MOS transistors 111, 112, 113, 114, 115, and 116 are not to be formed.
[0037] Next, N-type impurities are injected into the regions where the N-type MOS transistors 111, 112, 113, 114, 115, and 116 are to be formed, using photolithography technology and ion implantation, to form N-type high concentration impurity regions 111a, 111b, 112a, 112b, 113a, 113b, 114a, 114b, 115a, 115b, 116a, and 116b.
[0038] 3 is a schematic plan view showing a semiconductor device in which the dimension Wx2 of the short sides M3 and M4 of the P-type well region and the dimension Wy2 of the long sides L3 and L4 of the P-type well region are both 10 um or more in an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view taken along line IV-IV shown in FIG.
[0039] The semiconductor device 20, like the semiconductor device 10, has an analog circuit.
[0040] This semiconductor device 20 includes an N-type semiconductor substrate 101, a P-type well region 202, an N-type well region 203, and N-type high concentration impurity regions 211a, 211b, 212a, 212b, 213a, 213b, 214a, 214b, 215a, 215b, 216a, 216b, 217a, 217b, 218a, 218b, 219a, and 219b.
[0041] The dimension Wx2 of the short side and the dimension Wy2 of the long side of the P-type well region 202 are 10 um or more.
[0042] The N-type high concentration impurity regions 211a, 213b, 214a, 216b, 217a, and 219b are disposed at a distance Sx2 from the short sides M3 and M4 of the P-type well region 202. Here, Sx2 is smaller than Sx1 of the semiconductor device 10 shown in Figures 1 and 2. The N-type high concentration impurity regions 211a, 211b, 212a, 212b, 213a, 213b, 217a, 217b, 218a, 218b, 219a, and 219b are disposed at a distance Sy2 from the long sides L3 and L4 of the P-type well region 202.
[0043] The rest is the same as in FIGS.
[0044] FIG. 5 is an explanatory diagram showing the distance Sx1 from the long side L1 of the P-type well region 102 to the N-type high concentration impurity region 111a in the semiconductor device 10 shown in FIGS. 1 and 2, and the leakage current characteristics of the N-type MOS transistor 111.
[0045] As shown in FIG. 5, when the dimension Wx1 of the short side of the P-type well region 102 is small, the distance Sx1 from the long side of the P-type well region 102 to the N-type high concentration impurity region at which a leakage current of 1 nA occurs becomes large.
[0046] This is because, when the dimension of the short side of the P-type well region 102 is large, the leakage current is determined by the reverse bias breakdown of the PN junction between the P-type well region 102 and the N-type high concentration impurity region 111a.
[0047] Furthermore, when the dimension of the short side of the P-type well region 102 is small, a leakage current occurs between the N-type high concentration impurity region 111a and the N-type well region 103 before breakdown occurs between the P-type well region 102 and the N-type high concentration impurity region 111a.
[0048] FIG. 6 is a graph showing the relationship between the dimension Wx1 of the short side of the P-type well region 102 in the semiconductor device 10 shown in FIGS. 1 and 2 and the distance Sx1 from the long side L1 of the P-type well region 102 to the N-type high concentration impurity region 111a at which a leakage current of 1 nA occurs in the N-type MOS transistor 111.
[0049] The dashed line in the graph in Fig. 6 represents the leakage current characteristic determined by the reverse bias breakdown of the PN junction between the P-type well region 102 and the N-type high concentration impurity region 111a. The solid line in the graph in Fig. 6 represents the leakage current characteristic determined by the leakage current between the N-type high concentration impurity region 111a and the N-type well region 103.
[0050] In the graph of FIG. 6, when the dimension Wx1 of the short side of the P-type well region 102 is 10 um or more, the distance Sx1 from the long side L1 of the P-type well region 102 to the N-type high concentration impurity region 111a, at which a leakage current of 1 nA occurs in the N-type MOS transistor 111, is constant at 3.0 um.
[0051] However, if the dimension Wx1 of the short side of the P-type well region 102 is less than 10 um, the distance Sx1 from the long side L1 of the P-type well region 102 to the N-type high concentration impurity region 111a, at which a leakage current of 1 nA occurs in the N-type MOS transistor 111, must be greater than 3.0 um. In this case, the impurity concentration of the P-type well region 102 is 1.1×10 16 / cm 3 The impurity concentration of the N-type well region 103 is 1.2×10 16 / cm 3 It is.
[0052] As a specific separation distance, when the dimension Wx1 of the short side of the P-type well region 102 is 9.5 um, Sx1 is 3.5 um, and when the dimension Wx1 of the short side of the P-type well region 102 is 9.3 um, Sx1 is 4.1 um. The approximation formula is the following exponential function of the base e. Sx=544exp(-0.5Wx)
[0053] The dimension Wy1 of the long side of the P-type well region 102 and the distance Sy1 from the short sides M1 and M2 of the P-type well region 102 to the N-type high concentration impurity regions 111a, 111b, 112a, 112b, 115a, 115b, 116a, and 116b have a similar relationship.
[0054] In this embodiment, when the dimension Wx1 of the short side of the P-type well region 102 is less than 10 μm, the distances between the long sides L1 and L2 of the P-type well region 102 and the N-type high concentration impurity regions 111a, 112b, 113a, 114b, 115a, and 116b are increased. This reduces the leakage current of the N-type MOS transistors 111-116 that form the analog circuit, suppressing the occurrence of a leakage current difference, and suppressing the occurrence of a deterioration in the performance of the analog circuit.
[0055] In this embodiment, the semiconductor substrate is an N-type, but may be another semiconductor substrate. The first conductivity type is a P-type and the second conductivity type is an N-type, but the first conductivity type may be an N-type and the second conductivity type may be a P-type.
[0056] Moreover, the high concentration impurity region formed in the first well region is an N-type MOS transistor, but may be a diode or the like. [Explanation of symbols]
[0057] 10, 20 Semiconductor device 101 N-type semiconductor substrate 102, 202 P-type well region (first well region) 103, 203 N-type well region (second well region) 111, 112, 113, 114, N-type MOS transistor 111a, 111b, 112a, 112b, 113a, 113b, 114a, 114b N-type high concentration impurity region 211, 212, 213, 214, 215, 216, 217, 218, 219 N-type MOS transistors 211a, 211b, 212a, 212b, 213a, 213b, 214a, 214b, 215a, 215b, 216a, 216b, 217a, 217b, 218a, 218b, 219a, 219b N-type high concentration impurity region L1, L2, L3, L4 Long side of P-type well area M1, M2, M3, M4 Short side of P-type well area Wx1, Wx2 Dimensions of the short side of the P-type well area Wy1, Wy2 Dimensions of the long side of the P-type well area Sx1, Sx2 Distance from the long side of the P-type well region to the N-type high concentration impurity region Sy1, Sy2 Distance from the short side of the P-type well region to the N-type high concentration impurity region
Claims
1. a semiconductor substrate; a first well region of a first conductivity type formed on a surface of the semiconductor substrate and having a rectangular shape with a short side of less than 10 μm and a long side of 10 μm or more; a second well region of a second conductivity type that is formed in contact with the first well region and in a region other than the first well region and has a higher impurity concentration than the first well region; a plurality of semiconductor elements each including a high concentration impurity region of a second conductivity type formed on a surface of the first well region; and a distance between the long side and each of the high concentration impurity regions of the plurality of semiconductor elements is equal to or greater than a predetermined value according to the dimension of the short side;
2. The impurity concentration of the first well region is 1.1×10 １６ / cm ３ The impurity concentration of the second well region is 1.2×10 １６ / cm ３ 2. The semiconductor device according to claim 1,
3. The predetermined value is defined as follows: Wx is the dimension of the short side of the first well region, and Sx is the distance between the long side of the first well region and the high-concentration impurity region. Sx=544exp(-0.5Wx) 3. The semiconductor device according to claim 1, wherein the Sx calculated by the following formula is equal to or greater than the Sx calculated by the following formula.