Semiconductor device

Abstract

To suppress modulation of an electric characteristic of a semiconductor device before and after a stress test.SOLUTION: A semiconductor device contains: a first gate electrode; a first insulation layer onto the first gate electrode; an oxide semiconductor layer onto the first insulation layer; a second insulation layer onto the oxide semiconductor layer; and a second gate electrode onto the second insulation layer. The first insulation layer contains: a first layer containing silicon and nitrogen; a second layer containing silicon and oxygen; and a third layer containing aluminum and oxygen. The thickness of the first layer is 10nm or more and 190nm or less. The thickness of the second layer is 10nm or more and 100nm or less. The total thickness of the first and second layers is 200nm or less. The thickness of the third layer is 1nm or more and 10nm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device that uses an oxide semiconductor as a channel. [Background technology]

[0002] In recent years, semiconductor devices using oxide semiconductors as channels instead of silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single crystal silicon have been developed (see, for example, Patent Documents 1 to 6). A semiconductor device using such an oxide semiconductor as a channel can be formed with a simple structure and a low-temperature process, similar to a semiconductor device using amorphous silicon as a channel. In addition, a semiconductor device using an oxide semiconductor as a channel is known to have a higher field-effect mobility than a semiconductor device using amorphous silicon as a channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device using an oxide semiconductor as a channel, the electrical characteristics may fluctuate due to electrons or holes being trapped in an insulating layer provided above or below the oxide semiconductor layer during a stress test. In particular, a phenomenon in which the electrical characteristics of a semiconductor device are shifted toward a negative voltage during a reliability test in which a negative stress voltage is applied to a gate electrode of the semiconductor device while the semiconductor device is irradiated with light has become a problem.

[0005] An object of one embodiment of the present invention is to suppress the variation in electrical characteristics of a semiconductor device before and after a stress test. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment of the present invention includes a first gate electrode, a first insulating layer on the first gate electrode, an oxide semiconductor layer on the first insulating layer, a second insulating layer on the oxide semiconductor layer, and a second gate electrode on the second insulating layer. The first insulating layer includes a first layer containing silicon and nitrogen, a second layer containing silicon and oxygen, and a third layer containing aluminum and oxygen. The first layer has a thickness of 10 nm to 190 nm. The second layer has a thickness of 10 nm to 100 nm. The total thickness of the first layer and the second layer is 200 nm or less. The third layer has a thickness of 1 nm to 10 nm. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; [Diagram 3] FIG. 4 is a diagram showing electrical characteristics of a semiconductor device according to an embodiment of the present invention. [Figure 4] FIG. 11 is a diagram showing a threshold voltage calculated from the electrical characteristics of a semiconductor device according to one embodiment of the present invention. [Diagram 5]FIG. 10 is a diagram showing the mobility calculated from the electrical characteristics of a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A and 1B are diagrams showing electrical characteristics before and after a stress test of a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A and 1B are diagrams showing electrical characteristics before and after a stress test of a semiconductor device according to an embodiment of the present invention. [Figure 8] 11 is a diagram showing a change in threshold voltage calculated from electrical characteristics before and after a stress test of a semiconductor device according to an embodiment of the present invention. FIG. [Figure 9] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 10] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 19] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 20] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 21]1 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [Figure 22] 2 is a plan view of a pixel electrode and a common electrode of the display device according to the embodiment of the present invention; [Diagram 23] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 24] 1 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". In this way, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the stacking order in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0010] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0011] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described by taking a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure in this embodiment can be applied to display devices including other electro-optical layers as described above.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0014] [1. First embodiment] A semiconductor device according to an embodiment of the present invention will be described with reference to Figures 1 to 17. The semiconductor device according to the embodiment described below may be used in an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU) or a memory circuit, in addition to a transistor used in a display device.

[0015] [1-1. Configuration of semiconductor device 10] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention. Figure 2 is a plan view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0016] 1, the semiconductor device 10 is provided above a substrate 100. The semiconductor device 10 includes a gate electrode 105, gate insulating layers 110, 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170, 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrode 200.

[0017] The gate electrode 105 is provided on the substrate 100. The gate insulating layers 110 and 120 are provided on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. The oxide semiconductor layer 140 is patterned. A part of the metal oxide layer 130 extends beyond the end of the oxide semiconductor layer 140 and outside the pattern of the oxide semiconductor layer 140. However, the metal oxide layer 130 may be patterned in the same planar shape as the oxide semiconductor layer 140.

[0018] The gate electrode 105 may be referred to as a "first gate electrode." The gate insulating layers 110, 120 and the metal oxide layer 130 may be collectively referred to as a "first insulating layer." In this case, the gate insulating layer 110 may be referred to as a "first layer," the gate insulating layer 120 may be referred to as a "second layer," and the metal oxide layer 130 may be referred to as a "third layer." As will be described in detail later, the gate insulating layer 110 is a layer containing silicon and nitrogen. The gate insulating layer 120 is a layer containing silicon and oxygen. The metal oxide layer 130 is a layer containing aluminum and oxygen.

[0019] The thickness of the gate insulating layer 110 is 10 nm to 190 nm, 10 nm to 150 nm, or 10 nm to 100 nm. The thickness of the gate insulating layer 120 is 10 nm to 100 nm, 10 nm to 75 nm, or 10 nm to 50 nm. The total thickness of the gate insulating layers 110 and 120 is 300 nm or less, 200 nm or less, or 150 nm or less. As will be described in detail later, by setting the thicknesses of the gate insulating layers 110 and 120 and the metal oxide layer 130 within the above ranges, the reliability of the semiconductor device 10 in stress testing is improved.

[0020] The thickness of the metal oxide layer 130 is 1 nm or more and 10 nm or less, 1 nm or more and 4 nm or less, or 1 nm or more and 3 nm or less. The ratio of the thickness of the metal oxide layer 130 to the thickness of the oxide semiconductor layer 140 is 1 / 30 or more and 2 / 3 or less, 1 / 30 or more and 4 / 30 or less, or 1 / 30 or more and 1 / 10 or less.

[0021] In other words, the gate insulating layer 120 is provided between the substrate 100 and the metal oxide layer 130. In further words, the metal oxide layer 130 is between the gate insulating layer 120 and the oxide semiconductor layer 140 and is in contact with each of the gate insulating layer 120 and the oxide semiconductor layer 140. As will be described in detail later, the gate insulating layer 120 is an insulating layer containing oxygen. Specifically, the gate insulating layer 120 is an insulating layer having a function of releasing oxygen by heat treatment at 600° C. or less. Oxygen released from the gate insulating layer 120 by heat treatment repairs oxygen vacancies formed in the oxide semiconductor layer 140.

[0022] In this embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100 .

[0023] In the present embodiment, a configuration in which the metal oxide layer 130 is in contact with the gate insulating layer 120 and the oxide semiconductor layer 140 is in contact with the metal oxide layer 130 is exemplified, but is not limited to this configuration. Another layer may be provided between the gate insulating layer 120 and the metal oxide layer 130. Another layer may be provided between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0024] The gate electrode 160 faces the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. Of the main surfaces of the oxide semiconductor layer 140, a surface in contact with the gate insulating layer 150 is referred to as an upper surface 141. Of the main surfaces of the oxide semiconductor layer 140, a surface in contact with the metal oxide layer 130 is referred to as a lower surface 142. A surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are provided on the gate insulating layer 150 and the gate electrode 160. The insulating layers 170 and 180 are provided with openings 171 and 173 that reach the oxide semiconductor layer 140. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0025] The gate electrode 160 may be referred to as a “second gate electrode.” The gate insulating layer 150 may be referred to as a “second insulating layer.”

[0026] The gate electrode 105 functions as a bottom gate of the semiconductor device 10 and as a light shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 functions as a barrier film that blocks impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 function as gate insulating layers for the bottom gate. The metal oxide layer 130 is a layer containing a metal oxide mainly composed of aluminum, and has a barrier property that blocks gases such as oxygen and hydrogen. Furthermore, the metal oxide layer 130 has a function of suppressing the movement of holes from the oxide semiconductor layer 140 to the gate insulating layer 120 during a stress test.

[0027] The semiconductor device 10 is divided into a first region A1, a second region A2, and a third region A3 based on the patterns of the gate electrode 160 and the oxide semiconductor layer 140. The first region A1 is a region that overlaps with the gate electrode 160 in a planar view. The second region A2 is a region that does not overlap with the gate electrode 160 in a planar view, but overlaps with the oxide semiconductor layer 140. The third region A3 is a region that does not overlap with either the gate electrode 160 or the oxide semiconductor layer 140 in a planar view.

[0028] 1 illustrates a configuration in which the thickness of the gate insulating layer 150 in the second region A2 and the third region A3 is the same as the thickness of the gate insulating layer 150 in the first region A1, but is not limited to this configuration. For example, the thickness of the gate insulating layer 150 in the second region A2 and the third region A3 may be smaller than the thickness of the gate insulating layer 150 in the first region A1. In other words, the thickness of the gate insulating layer 150 in a region that does not overlap with the gate electrode 160 in a plan view may be smaller than the thickness of the gate insulating layer 150 in a region that overlaps with the gate electrode 160.

[0029] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the pattern of the gate electrode 160. The source region S and the drain region D correspond to the second region A2. The channel region CH corresponds to the first region A1. In a plan view, an end of the channel region CH coincides with an end of the gate electrode 160. The oxide semiconductor layer 140 in the channel region CH has a semiconductor property. The oxide semiconductor layer 140 in each of the source region S and the drain region D has a conductor property. That is, the carrier concentration of the oxide semiconductor layer 140 in the source region S and the drain region D is higher than the carrier concentration of the oxide semiconductor layer 140 in the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the oxide semiconductor layer 140 in the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a multilayer structure.

[0030] The gate electrode 160 functions as a light-shielding film for the top gate of the semiconductor device 10 and the oxide semiconductor layer 140. The gate insulating layer 150 functions as a gate insulating layer for the top gate. The gate insulating layer 150 may have a function of releasing oxygen by heat treatment in the manufacturing process, similar to the gate insulating layer 120. The insulating layers 170 and 180 insulate the gate electrode 160 from the source-drain electrode 200 and reduce the parasitic capacitance between them. The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, when the gate electrode 105 is simply used as a light-shielding film, the gate electrode 105 may not be supplied with a specific voltage and the potential of the gate electrode 105 may be floating. In other words, the gate electrode 105 may simply be called a "light-shielding film". In that case, the light-shielding film may be an insulator.

[0031] In this embodiment, a configuration in which a dual-gate transistor in which a gate electrode is provided both above and below an oxide semiconductor layer is used as the semiconductor device 10 is illustrated, but the present invention is not limited to this configuration. For example, a bottom-gate transistor in which a gate electrode is provided only below the oxide semiconductor layer, or a top-gate transistor in which a gate electrode is provided only above the oxide semiconductor layer may be used as the semiconductor device 10. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0032] 1 and 2, the lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130. In particular, in this embodiment, the entire lower surface 142 of the oxide semiconductor layer 140 is covered with the metal oxide layer 130. In the D1 direction shown in FIG. 2, the width of the gate electrode 105 is larger than the width of the gate electrode 160. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and is a direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of a region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W.

[0033] In the present embodiment, the configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130 is illustrated, but the present invention is not limited to this configuration. For example, a part of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered by the metal oxide layer 130, and the entire or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered by the metal oxide layer 130. That is, the entire or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, a part of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered by the metal oxide layer 130, and the other part of the lower surface 142 may be in contact with the metal oxide layer 130.

[0034] In the present embodiment, the gate insulating layer 150 is formed on the entire surface, and the openings 171 and 173 are provided in the gate insulating layer 150. However, the present invention is not limited to this configuration. The gate insulating layer 150 may be patterned into a shape different from the shape in which the openings 171 and 173 are provided. For example, the gate insulating layer 150 may be patterned so as to expose all or part of the oxide semiconductor layer 140 in the source region S and the drain region D. In other words, the gate insulating layer 150 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 140 and the insulating layer 170 may be in contact with each other in these regions.

[0035] 2 illustrates a configuration in which the source-drain electrode 200 does not overlap the gate electrode 105 and the gate electrode 160 in a plan view, but the present invention is not limited to this configuration. For example, the source-drain electrode 200 may overlap at least one of the gate electrode 105 and the gate electrode 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0036] [1-2. Materials of each component of semiconductor device 10] As the substrate 100, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 100 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin in order to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top-emission display, the substrate 100 does not need to be transparent, and therefore impurities that deteriorate the transparency of the substrate 100 may be used. When the semiconductor device 10 is used in an integrated circuit that is not a display device, a substrate not having light-transmitting properties, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, is used as the substrate 100.

[0037] As the gate electrode 105, the gate electrode 160, and the source-drain electrodes 200, general metal materials are used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. As the gate electrode 105, the gate electrode 160, and the source-drain electrodes 200, the above materials may be used in a single layer or in a multilayer structure. When the gate electrode 105 does not need to be conductive, a material other than the above metal materials may be used as a light-shielding layer instead of the gate electrode 105. For example, a black matrix such as a black resin may be used as the light-shielding layer. The gate electrode 105 may have a single-layer structure or a multilayer structure. For example, the gate electrode 105 may have a multilayer structure of a red color filter, a green color filter, and a blue color filter.

[0038] A general insulating material is used for the gate insulating layers 110 and 120 and the insulating layers 170 and 180. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y The gate insulating layer 110 and the insulating layer 170 are made of an inorganic insulating layer such as silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), Aluminum Nitride (AlN x ), aluminum oxide nitride (AlN x O y However, the insulating layer 170 is preferably made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ) may be used as the insulating layer 180. x ), silicon oxynitride (SiN x O y ), Aluminum Nitride (AlN x ), aluminum oxide nitride (AlN x O y ) or other inorganic insulating layers may be used.

[0039] The gate insulating layer 150 is an insulating layer containing oxygen among the above insulating layers. For example, the gate insulating layer 150 is made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ) or other inorganic insulating layers are used.

[0040] An insulating layer having a function of releasing oxygen by heat treatment is used as the gate insulating layer 120. That is, an oxide insulating layer containing excess oxygen is used as the gate insulating layer 120. The temperature of the heat treatment at which the gate insulating layer 120 releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the gate insulating layer 120 releases oxygen at a heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 100. At least one of the insulating layers 170 and 180 may be an insulating layer having a function of releasing oxygen by heat treatment, similar to the gate insulating layer 120.

[0041] An insulating layer with few defects is used as the gate insulating layer 150. For example, when the oxygen composition ratio in the gate insulating layer 150 is compared with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the gate insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, silicon oxide (SiO x ), the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the insulating layer 180. For example, the gate insulating layer 150 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0042] The above SiO x N y and AlO x N y is a silicon and aluminum compound that contains a smaller ratio (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds that contain a smaller proportion of oxygen than nitrogen (x>y).

[0043] A metal oxide containing aluminum as a main component is used as the metal oxide layer 130. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) is used. "Metal oxide layer 130 containing aluminum as a main component" means that the ratio of aluminum contained in metal oxide layer 130 is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in metal oxide layer 130 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0044] The oxide semiconductor layer 140 may be a metal oxide having semiconductor properties. For example, the oxide semiconductor layer 140 may be an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). For example, the oxide semiconductor layer 140 may be an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and an oxide semiconductor having a composition different from the above may be used. For example, an oxide semiconductor layer having a ratio of In larger than the above may be used to improve mobility. On the other hand, an oxide semiconductor layer having a ratio of Ga larger than the above may be used to increase the band gap and reduce the influence of light irradiation.

[0045] For example, an oxide semiconductor containing two or more metals including indium (In) may be used as the oxide semiconductor layer 140 having a ratio of In larger than the above. In this case, the ratio of indium elements to all metal elements in the oxide semiconductor layer 140 may be 50% or more in atomic ratio. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoids may be used as the oxide semiconductor layer 140. Elements other than the above may be used as the oxide semiconductor layer 140.

[0046] As the oxide semiconductor layer 140, other elements may be added to an oxide semiconductor containing In, Ga, Zn, and O, and for example, a metal element such as Al or Sn may be added. In addition to the above oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), an oxide semiconductor containing In and W, or the like may be used as the oxide semiconductor layer 140.

[0047] When the ratio of the indium element is high, the oxide semiconductor layer 140 is likely to crystallize. As described above, by using a material in which the ratio of the indium element to all metal elements in the oxide semiconductor layer 140 is 50% or more, the oxide semiconductor layer 140 having a polycrystalline structure can be obtained. It is preferable that the oxide semiconductor layer 140 contains gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is not impaired by gallium, and the oxide semiconductor layer 140 has a polycrystalline structure.

[0048] Although a detailed manufacturing method of the oxide semiconductor layer 140 will be described later, the oxide semiconductor layer 140 can be formed by a sputtering method. The composition of the oxide semiconductor layer 140 formed by the sputtering method depends on the composition of a sputtering target. Even if the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer 140 are approximately the same. In this case, the composition of the metal elements of the oxide semiconductor layer 140 can be specified based on the composition of the metal elements of the sputtering target.

[0049] When the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor layer may be identified by X-ray diffraction (XRD). Specifically, the composition of the metal elements in the oxide semiconductor layer can be identified based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by XRD. Furthermore, the composition of the metal elements in the oxide semiconductor layer 140 can also be identified by fluorescent X-ray analysis or Electron Probe Micro Analyzer (EPMA) analysis. However, this is not limited because the oxygen element contained in the oxide semiconductor layer 140 changes depending on the process conditions of sputtering, etc.

[0050] As described above, the oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. An oxide semiconductor having a polycrystalline structure can be manufactured using a Poly-OS (Polycrystalline Oxide Semiconductor) technique. In the following, an oxide semiconductor having a polycrystalline structure may be described as a Poly-OS to distinguish it from an oxide semiconductor having an amorphous structure.

[0051] [1-3. Electrical Characteristics of Semiconductor Device 10] The electrical characteristics of the semiconductor device 10 will be described with reference to Figs. 3 to 5. Fig. 3 is a diagram showing the electrical characteristics of the semiconductor device according to one embodiment of the present invention. Fig. 4 is a diagram showing the threshold voltage calculated from the electrical characteristics of the semiconductor device according to one embodiment of the present invention. Fig. 5 is a diagram showing the mobility calculated from the electrical characteristics of the semiconductor device according to one embodiment of the present invention. Figs. 3 to 5 show the electrical characteristics of the semiconductor device 10 shown in Fig. 1, in which the thicknesses of the gate insulating layers 110, 120, and 150 are different. Under any condition, the amount of impurities implanted into the oxide semiconductor layer 140 is adjusted so that the resistance values ​​of the oxide semiconductor layers 140 in the source region S and the drain region D are approximately the same.

[0052] In the semiconductor device 10, a silicon nitride film is used as the gate insulating layer 110, a silicon oxide film is used as the gate insulating layer 120, and a silicon oxide film is used as the gate insulating layer 150. The gate insulating layer 110 is written as "UC-SiN". The gate insulating layer 120 is written as "SiO". The gate insulating layer 150 is written as "GI-SiO". Aluminum oxide is used as the metal oxide layer 130.

[0053] The thicknesses of the gate insulating layers 110 and 120 (UC-SiN\SiO thickness) are 100 nm\50 nm, 200 nm\100 nm, or 300 nm\200 nm. The thicknesses of the gate insulating layer 150 (GI-SiO thickness) for each UC-SiN\SiO thickness are 75 nm, 100 nm, 125 nm, or 150 nm.

[0054] The measurement conditions for the electrical characteristics shown in FIG. Channel region CH size: W / L=4.5μm / 3.0μm Source-drain voltage: 0.1V, 10V Gate voltage: -15V~+15V Measurement environment: Room temperature, dark room Number of measurement points: 26

[0055] The solid horizontal lines in each graph in Fig. 3 indicate the drain current ID of -7 [A] and the mobility is 100 [cm 2 / Vs]. The drain current ID changes by one digit per scale. The mobility changes by 20 [cm 2 / Vs]. The solid vertical line in each graph in FIG. 3 is shown at the scale position where the gate voltage is 0 [V]. The gate voltage changes in value by 5 [V] per scale. In each graph in FIG. 3, the electrical characteristics indicated with a left-pointing arrow indicate the Id-Vg characteristics of the semiconductor device 10. Two types of Id-Vg characteristics are displayed in each graph. Of the two types of Id-Vg characteristics, the Id-Vg characteristics with a relatively large current are characteristics when the source-drain voltage is 10 V, and the Id-Vg characteristics with a relatively small current are characteristics when the source-drain voltage is 0.1 V. In each graph in FIG. 3, the electrical characteristics indicated with a right-pointing arrow indicate the mobility of the semiconductor device 10. As shown in FIG. 3, good electrical characteristics without any particular abnormalities were obtained under most conditions, and the mobility was 50 [cm 2 / Vs] or higher.

[0056] FIG. 4 is a box plot of the threshold voltage calculated from the electrical characteristics in FIG. 3. FIG. 4 shows the maximum value (top of the whisker), minimum value (bottom of the whisker), distribution of the central 50% of the data (from the top to the bottom of the box), average value (x mark), and median value (boundary between the upper and lower boxes) of each calculated value. As shown in FIG. 4, for each UC-SiN\SiO film thickness, the smaller the film thickness of the gate insulating layer 150 (GI-SiO), the more the threshold voltage Vth shifts in the negative direction. When comparing under the same condition of the film thickness of the gate insulating layer 150 (GI-SiO), the smaller the UC-SiN\SiO film thickness, the more the threshold voltage Vth shifts in the negative direction.

[0057] Fig. 5 is a box plot of the mobility calculated from the electrical characteristics in Fig. 3. As shown in Fig. 5, for each UC-SiN\SiO thickness, the smaller the thickness of the gate insulating layer 150 (GI-SiO), the higher the mobility. When comparing under the same conditions of the thickness of the gate insulating layer 150 (GI-SiO), there is a tendency that the smaller the UC-SiN\SiO thickness, the slightly lower the mobility, but there is no large decrease in mobility, and good characteristics are obtained under all conditions.

[0058] [1-4. Reliability of semiconductor device 10] The reliability of the semiconductor device 10 will be described with reference to Figs. 6 to 8. Figs. 6 and 7 are diagrams showing electrical characteristics before and after a stress test of a semiconductor device according to one embodiment of the present invention. Fig. 8 is a diagram showing a change in threshold voltage calculated from the electrical characteristics before and after a stress test of a semiconductor device according to one embodiment of the present invention. Figs. 6 to 8 show the results of a reliability test on the semiconductor device 10 shown in Figs. 3 to 5.

[0059] Fig. 6 shows the results of a reliability test using Positive Bias Temperature Stress (PBTS). Fig. 7 shows the results of a reliability test using Negative Bias Temperature Illumination Stress (NBTIS). Fig. 8 shows the results of a reliability test calculated based on the electrical characteristics of the semiconductor device 10 shown in Figs. 6 and 7.

[0060] The conditions for the PBTS test are as follows: Channel region CH size: W / L=4.5μm / 3.0μm Light irradiation conditions: No irradiation (dark room) Gate voltage: +30V Source and drain voltage: 0V Stress application time: 1000 sec Stage temperature when stress is applied: 85℃

[0061] The conditions for the NBTIS test are as follows: Channel region CH size: W / L=4.5μm / 3.0μm Light irradiation conditions: With irradiation (7000 lux) Gate voltage: -20V Source and drain voltage: 0V Stress application time: 1000 sec Stage temperature when stress is applied: 85℃

[0062] In Fig. 8, the results of the PBTS test are shown in white bars, the results of the NBTIS test are shown in black bars, and the threshold voltage Vth before each test is shown with a cross.

[0063] 6 and 8, under all conditions, the threshold voltage Vth shifts positively before and after the PBTS test. The smaller the thickness (GI-SiO) of the gate insulating layer 150, the smaller the amount of the positive shift. When comparing under the same conditions of the thickness (GI-SiO) of the gate insulating layer 150, the smaller the UC-SiN\SiO thickness, the smaller the amount of the positive shift.

[0064] As shown in Fig. 7 and Fig. 8, the threshold voltage Vth shifts negatively before and after the NBTIS test under all conditions. Under the condition where the UC-SiN\SiO thickness is 300nm\200nm, the amount of the negative shift does not depend on the GI-SiO thickness. On the other hand, under the condition where the UC-SiN\SiO thickness is 200nm\100nm, the amount of the negative shift is smaller as the GI-SiO thickness is smaller. In particular, when the GI-SiO thickness is 75nm, the amount of the negative shift is significantly reduced compared to when the GI-SiO thickness is 100nm. Furthermore, under the condition where the UC-SiN\SiO thickness is 100nm\50nm, the amount of the negative shift is dramatically reduced compared to the above conditions. Even under the condition where the UC-SiN\SiO thickness is 100nm\50nm, the amount of the negative shift is smaller as the GI-SiO thickness is smaller.

[0065] In this embodiment, the thickness of the gate insulating layer 110 containing silicon and nitrogen is 10 nm or more and 190 nm or less, the thickness of the gate insulating layer 120 containing silicon and oxygen is 10 nm or more and 100 nm or less, the total thickness of the gate insulating layers 110, 120 is 200 nm or less, and the thickness of the metal oxide layer 130 containing aluminum and oxygen is 1 nm or more and 10 nm or less, and dramatic improvements were confirmed, especially in the NBTIS test.

[0066] In the NBTIS test, a gate voltage of −20 V is applied to the gate electrodes 105 and 160 as described above. Therefore, holes generated in the oxide semiconductor layer 140 by light irradiation are attracted to either the gate electrodes 105 or 160. Here, when the thicknesses of the gate insulating layers 110 and 120 are small, the effect of the electric field generated by the gate electrode 105 on the oxide semiconductor layer 140 becomes relatively strong. As a result, it is considered that many of the holes generated in the oxide semiconductor layer 140 are attracted to the gate electrode 105. In the conventional transistor, holes are trapped by the gate insulating layer on the bottom gate side, which causes a negative shift in the threshold voltage of the transistor characteristics in the NBTIS test. On the other hand, in this embodiment, the metal oxide layer 130 is provided below the oxide semiconductor layer 140, which makes it difficult for holes generated in the oxide semiconductor layer 140 to reach the gate insulating layer 120, and it is considered that the amount of holes trapped in the gate insulating layer 120 is reduced.

[0067] [1-5. Manufacturing Method of Semiconductor Device 10] A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 9 to Fig. 17. Fig. 9 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figs. 10 to 17 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0068] 9 and 10, a gate electrode 105 is formed on a substrate 100, and gate insulating layers 110 and 120 are formed on the gate electrode 105 (step S1001 "Insulating layer / GE formation" in FIG. 9). For example, silicon nitride is formed as the gate insulating layer 110. For example, silicon oxide is formed as the gate insulating layer 120. The gate insulating layer 110 and the gate insulating layer 120 are formed by a CVD (Chemical Vapor Deposition) method.

[0069] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block impurities diffusing from, for example, the substrate 100 side toward the oxide semiconductor layer 140. For example, silicon oxide used as the gate insulating layer 120 is silicon oxide that has the physical property of releasing oxygen by heat treatment.

[0070] 9 and 11, a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on a gate insulating layer 120 (step S1002 "OS / AlOx film formation" in FIG. 9). The metal oxide layer 130 and the oxide semiconductor layer 140 are formed by sputtering or atomic layer deposition (ALD).

[0071] The oxide semiconductor layer 140 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 15 nm to 40 nm. In this embodiment, the oxide semiconductor layer 140 has a thickness of 15 nm. The oxide semiconductor layer 140 is amorphous before a heat treatment (OS annealing) described later.

[0072] When the oxide semiconductor layer 140 is crystallized by OS annealing described later, the oxide semiconductor layer 140 after deposition and before OS annealing is preferably amorphous (a state in which the oxide semiconductor has few crystalline components). In other words, the deposition conditions for the oxide semiconductor layer 140 are preferably such that the oxide semiconductor layer 140 immediately after deposition is as little crystallized as possible. For example, when the oxide semiconductor layer 140 is deposited by a sputtering method, the oxide semiconductor layer 140 is deposited while controlling the temperature of the deposition target (the substrate 100 and a structure formed thereon).

[0073] When a film is formed on a target object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target object, and the temperature of the target object increases with the film formation process. If the temperature of the target object increases during the film formation process, the oxide semiconductor layer 140 may contain microcrystals immediately after the film formation, which may hinder crystallization by the subsequent OS annealing. In order to control the temperature of the target object as described above, for example, the target object may be cooled while the film is formed. For example, the target object may be cooled from the surface opposite to the surface to be formed so that the temperature of the surface to be formed of the target object (hereinafter referred to as the "film formation temperature") becomes 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, by forming the oxide semiconductor layer 140 while cooling the target object, the oxide semiconductor layer 140 having a small amount of crystalline components immediately after the film formation can be formed. The oxide semiconductor layer 140 is formed under a partial pressure of oxygen of 2% to 20%, 3% to 15%, or 3% to 10%.

[0074] As shown in FIG. 9 and FIG. 12, a pattern of the oxide semiconductor layer 140 is formed ("OS pattern formation" in step S1003 in FIG. 9). Although not shown, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. For etching the oxide semiconductor layer 140, wet etching or dry etching may be used. For wet etching, etching can be performed using an acidic etchant. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, or hydrofluoric acid can be used as the etchant. Since the oxide semiconductor layer 140 in step S1003 is amorphous, the oxide semiconductor layer 140 can be easily patterned into a predetermined shape by wet etching.

[0075] After the oxide semiconductor layer 140 is patterned, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 ("OS annealing" in step S1004 of FIG. 9). In the OS annealing, the oxide semiconductor layer 140 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300° C. or higher and 500° C. or lower, or 350° C. or higher and 450° C. or lower. The holding time at the target temperature is 15 minutes or higher and 120 minutes or lower, or 30 minutes or higher and 60 minutes or lower. In this embodiment, the oxide semiconductor layer 140 is crystallized by this OS annealing. However, the oxide semiconductor layer 140 does not necessarily have to be crystallized by the OS annealing.

[0076] As shown in FIG. 9 and FIG. 13, the gate insulating layer 150 is formed ("GI formation" in step S1005 in FIG. 9). For example, silicon oxide is formed as the gate insulating layer 150. The gate insulating layer 150 is formed by a CVD method. For example, in order to form an insulating layer with few defects as the gate insulating layer 150 as described above, the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is, for example, 75 nm or more and 150 nm or less. After the gate insulating layer 150 is formed, a process of implanting oxygen into the upper part of the gate insulating layer 150 may be performed. As the process of implanting oxygen, a configuration in which a metal oxide layer is formed on the gate insulating layer 150 by a sputtering method may be performed.

[0077] With the gate insulating layer 150 formed on the oxide semiconductor layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 ("oxidation annealing" in step S1006 in FIG. 9). In the process from when the oxide semiconductor layer 140 is formed to when the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen vacancies are generated on the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. By the above-mentioned oxidation annealing, oxygen released from the gate insulating layers 120 and 150 is supplied to the oxide semiconductor layer 140, and the oxygen vacancies are repaired. When the process of implanting oxygen into the gate insulating layer 150 is not performed, the oxidation annealing may be performed in a state where an insulating layer that releases oxygen by heat treatment is formed on the gate insulating layer 150.

[0078] In order to increase the amount of oxygen supplied from the gate insulating layer 150 to the oxide semiconductor layer 140, a metal oxide layer mainly composed of aluminum may be formed on the gate insulating layer 150 by a sputtering method, and oxidation annealing may be performed in this state. By using aluminum oxide, which has high gas barrier properties, as this metal oxide layer, it is possible to suppress outward diffusion of oxygen implanted into the gate insulating layer 150 during oxidation annealing. By forming the metal oxide layer and performing oxidation annealing, the oxygen implanted into the gate insulating layer 150 is efficiently supplied to the oxide semiconductor layer 140.

[0079] 9 and 14, the gate electrode 160 is formed ("GE formation" in step S1007 in FIG. 9). The gate electrode 160 is formed by sputtering or atomic layer deposition, and is patterned through a photolithography process. The gate insulating layer 150 provided outside the pattern of the gate electrode 160 may be thinned by etching to form the gate electrode 160.

[0080] 15, with the gate electrode 160 being patterned, impurity ions are implanted into the oxide semiconductor layer 140 ("implantation of impurity ions" in step S1008 in FIG. 9). Specifically, impurities are implanted into the gate insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150 using the gate electrode 160 as a mask. By the ion implantation, elements such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are implanted into the gate insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150.

[0081] In the oxide semiconductor layer 140 in the second region A2 that does not overlap with the gate electrode 160, oxygen defects are generated by ion implantation. Hydrogen is trapped in the generated oxygen defects, thereby decreasing the resistance of the oxide semiconductor layer 140 in the second region A2. On the other hand, in the oxide semiconductor layer 140 in the first region A1 that overlaps with the gate electrode 160, impurities are not implanted, so that no oxygen defects are generated and the resistance in the first region A1 does not decrease. Through the above process, a channel region CH is formed in the oxide semiconductor layer 140 in the first region A1, and a source region S and a drain region D are formed in the oxide semiconductor layer 140 in the second region A2.

[0082] The ion implantation generates dangling bond defects DB in the gate insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3. The positions and amount of the dangling bond defects DB can be controlled by adjusting the process parameters of the ion implantation (e.g., dose amount, acceleration voltage, plasma power, etc.). By adjusting the process parameters, the impurity concentration near the upper surface of the oxide semiconductor layer 140 can be adjusted to 1×10 19 / cm 3 On the other hand, when an insulating layer containing silicon and nitrogen is used as the gate insulating layer 110, if impurities are implanted into the gate insulating layer 110 at a high concentration, hydrogen generated in the gate insulating layer 110 reaches the oxide semiconductor layer 140 and adversely affects the electrical characteristics of the semiconductor device 10. Therefore, the impurity concentration near the top surface of the gate insulating layer 110 can be adjusted to 1×10 19 / cm 3 It can be adjusted as follows:

[0083] As shown in FIGS. 9 and 16, insulating layers 170, 180 are formed as interlayer films on the gate insulating layer 150 and the gate electrode 160 ("Interlayer film formation" in step S1009 in FIG. 9). The insulating layers 170, 180 are formed by a CVD method. For example, a silicon nitride layer is formed as the insulating layer 170, and a silicon oxide layer is formed as the insulating layer 180. The materials used for the insulating layers 170, 180 are not limited to the above. The thickness of the insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.

[0084] 9 and 17, openings 171, 173 are formed in the gate insulating layer 150 and the insulating layers 170, 180 ("contact opening" in step S1010 in FIG. 9). The opening 171 exposes the oxide semiconductor layer 140 in the source region S. The opening 173 exposes the oxide semiconductor layer 140 in the drain region D. By forming source-drain electrodes 200 on the oxide semiconductor layer 140 exposed by the openings 171, 173 and on the insulating layer 180 ("SD formation" in step S1011 in FIG. 9), the semiconductor device 10 shown in FIG. 1 is completed.

[0085] [2. Second embodiment] A display device using a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 18 to 22. In the embodiment shown below, a configuration in which the semiconductor device 10 described in the first embodiment above is applied to a circuit of a liquid crystal display device will be described.

[0086] [2-1. Overview of the display device 20] Fig. 18 is a plan view showing an overview of a display device according to an embodiment of the present invention. As shown in Fig. 18, the display device 20 has an array substrate 300, a seal portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the seal portion 310. In a liquid crystal region 22 surrounded by the seal portion 310, a plurality of pixel circuits 301 are arranged in a matrix. The liquid crystal region 22 is an area that overlaps with a liquid crystal element 311 described later in a plan view.

[0087] The seal area 24 in which the seal portion 310 is provided is the area surrounding the liquid crystal area 22. The FPC 330 is provided in the terminal area 26. The terminal area 26 is an area in which the array substrate 300 is exposed from the counter substrate 320, and is provided outside the seal area 24. The outside of the seal area 24 means the outside of the area in which the seal portion 310 is provided and the area surrounded by the seal portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0088] [2-2. Circuit configuration of display device 20] Fig. 19 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. As shown in Fig. 19, a source driver circuit 302 is provided at a position adjacent to the liquid crystal region 22 in which the pixel circuits 301 are arranged in the D1 direction (column direction), and a gate driver circuit 303 is provided at a position adjacent to the liquid crystal region 22 in the D2 direction (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the above-mentioned sealing region 24. However, the region in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the sealing region 24, and may be any region outside the region in which the pixel circuits 301 are provided.

[0089] A source line 304 extends from the source driver circuit 302 in the direction D1 and is connected to a plurality of pixel circuits 301 arranged in the direction D1. A gate line 305 extends from the gate driver circuit 303 in the direction D2 and is connected to a plurality of pixel circuits 301 arranged in the direction D2.

[0090] A terminal portion 306 is provided in the terminal region 26. The terminal portion 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal portion 306 and the gate driver circuit 303 are connected by a connection wiring 307. By connecting the FPC 330 to the terminal portion 306, an external device to which the FPC 330 is connected is connected to the display device 20, and each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device.

[0091] The semiconductor device 10 according to the first embodiment is used as a transistor included in a pixel circuit 301, a source driver circuit 302, and a gate driver circuit 303.

[0092] Pixel circuit 301 of display device 20 FIG. 20 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. As shown in FIG. 20, a pixel circuit 301 includes elements such as a semiconductor device 10, a storage capacitor 350, and a liquid crystal element 311. The semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to a gate wiring 305. The source electrode 201 is connected to a source wiring 304. The drain electrode 203 is connected to a storage capacitor 350 and a liquid crystal element 311. In this embodiment, for convenience of explanation, the electrode indicated by the symbol "201" is called a source electrode, and the electrode indicated by the symbol "203" is called a drain electrode, but the electrode indicated by the symbol "201" may function as a drain electrode, and the electrode indicated by the symbol "203" may function as a source electrode.

[0093] [2-4. Cross-sectional structure of the display device 20] Fig. 21 is a cross-sectional view of a display device according to one embodiment of the present invention. As shown in Fig. 21, a display device 20 is a display device using a semiconductor device 10. In this embodiment, a configuration in which the semiconductor device 10 is used in a pixel circuit 301 is illustrated, but the semiconductor device 10 may also be used in a peripheral circuit including a source driver circuit 302 and a gate driver circuit 303. In the following description, the configuration of the semiconductor device 10 is similar to that of the semiconductor device 10 shown in Fig. 1, and therefore description thereof will be omitted.

[0094] An insulating layer 360 is provided on the source electrode 201 and the drain electrode 203. A common electrode 370 that is provided in common to a plurality of pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. An opening 381 is provided in the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

[0095] Fig. 22 is a plan view of a pixel electrode and a common electrode of a display device according to one embodiment of the present invention. As shown in Fig. 22, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a lateral electric field is formed from the pixel electrode 390 in the overlapping region to the common electrode 370 in the non-overlapping region. This lateral electric field causes liquid crystal molecules contained in the liquid crystal element 311 to operate, thereby determining the grayscale of the pixel.

[0096] [3. Third embodiment] A display device using a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 23 and 24. In this embodiment, a configuration in which the semiconductor device 10 described in the first embodiment is applied to the circuit of an organic EL display device will be described. The outline and circuit configuration of the display device 20 are similar to those shown in Figures 18 and 19, and therefore will not be described.

[0097] 3-1. Pixel circuit 301 of display device 20 FIG. 23 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. As shown in FIG. 23, a pixel circuit 301 includes elements such as a driving transistor 11, a selection transistor 12, a storage capacitor 210, and a light-emitting element DO. The driving transistor 11 and the selection transistor 12 have the same configuration as the semiconductor device 10. The source electrode of the selection transistor 12 is connected to a signal line 211, and the gate electrode of the selection transistor 12 is connected to a gate line 212. The source electrode of the driving transistor 11 is connected to an anode power line 213, and the drain electrode of the driving transistor 11 is connected to one end of the light-emitting element DO. The gate electrode of the driving transistor 11 is connected to the drain electrode of the selection transistor 12. The other end of the light-emitting element DO is connected to a cathode power line 214. The storage capacitor 210 is connected to the gate electrode and drain electrode of the driving transistor 11. A grayscale signal that determines the light-emitting intensity of the light-emitting element DO is supplied to the signal line 211. A signal that selects a pixel row to which the above grayscale signal is written is supplied to the gate line 212.

[0098] [3-2. Cross-sectional structure of the display device 20] Fig. 24 is a cross-sectional view of a display device according to one embodiment of the present invention. The configuration of the display device 20 shown in Fig. 24 is similar to that of the display device 20 shown in Fig. 21, but the structure above the insulating layer 360 of the display device 20 in Fig. 24 is different from the structure above the insulating layer 360 of the display device 20 in Fig. 21. Hereinafter, a description of the configuration of the display device 20 in Fig. 24 that is similar to that of the display device 20 in Fig. 21 will be omitted, and the differences between the two will be described.

[0099] As shown in FIG. 24, the display device 20 has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 (light-emitting element DO) above an insulating layer 360. The pixel electrode 390 is provided on the insulating layer 360 and inside an opening 381. An insulating layer 362 is provided on the pixel electrode 390. An opening 363 is provided in the insulating layer 362. The opening 363 corresponds to a light-emitting region. In other words, the insulating layer 362 defines a pixel. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are provided individually for each pixel. On the other hand, the common electrode 394 is provided in common to a plurality of pixels. The light-emitting layer 392 is made of different materials depending on the display color of the pixel.

[0100] In the second and third embodiments, the semiconductor device described in the first embodiment is applied to a liquid crystal display device and an organic EL display device, but the semiconductor device may be applied to a display device other than these display devices (for example, a self-luminous display device other than an organic EL display device or an electronic paper display device). In addition, the semiconductor device can be applied to a variety of display devices, from small and medium-sized display devices to large display devices, without any particular limitations.

[0101] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0102] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those which are clear from the description in this specification or which can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0103] 10: semiconductor device, 11: driving transistor, 12: selection transistor, 20: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 100: substrate, 105, 160: gate electrode, 110, 120, 150: gate insulating layer, 130: metal oxide layer, 140: oxide semiconductor layer, 141: upper surface, 142: lower surface, 143: side surface, 170, 180: insulating layer, 171, 173: opening, 200: source drain electrode, 201: source electrode, 203: drain electrode, 210: storage capacitor, 211: signal line, 212: gate line, 213: anode power line, 214: cathode power line, 300: array substrate, 301: pixel circuit, 302: source driver circuit, 303: Gate driver circuit, 304: Source wiring, 305: Gate wiring, 306: Terminal portion, 307: Connection wiring, 310: Seal portion, 311: Liquid crystal element, 320: Counter substrate, 330: Flexible printed circuit board, 340: IC chip, 350: Storage capacitor, 360, 362, 380: Insulating layer, 363, 381: Opening, 370, 394: Common electrode, 390: Pixel electrode, 392: Light-emitting layer, A1: First region, A2: Second region, A3: Third region, CH: Channel region, D: Drain region, S: Source region, DO: Light-emitting element

Claims

1. a first gate electrode; a first insulating layer over the first gate electrode; an oxide semiconductor layer on the first insulating layer; a second insulating layer on the oxide semiconductor layer; a second gate electrode on the second insulating layer; the first insulating layer includes a first layer including silicon and nitrogen, a second layer including silicon and oxygen, and a third layer including aluminum and oxygen; the thickness of the first layer is 10 nm or more and 190 nm or less; the thickness of the second layer is 10 nm or more and 100 nm or less; a total thickness of the first layer and the second layer is 200 nm or less; The semiconductor device, wherein the third layer has a thickness of 1 nm or more and 10 nm or less.

2. the second layer is provided on the first layer, The semiconductor device according to claim 1 , wherein said third layer is provided on said second layer.

3. The impurity concentration near the top surface of the oxide semiconductor layer is 1×10 １９ / cm ３ 3. The semiconductor device according to claim 2, wherein:

4. The impurity concentration near the top surface of the first layer is 1×10 １９ / cm ３ 4. The semiconductor device according to claim 3, wherein:

5. 3. The semiconductor device according to claim 2, wherein the first layer has a thickness of 10 nm or more and 100 nm or less.

6. 3. The semiconductor device according to claim 2, wherein the total thickness of said first layer and said second layer is 150 nm or less.

7. The semiconductor device according to claim 1 , wherein the second insulating layer has a thickness of 10 nm to 75 nm.

8. the thickness of the first layer is 10 nm or more and 100 nm or less; the thickness of the second layer is 10 nm or more and 50 nm or less; 3. The semiconductor device according to claim 2, wherein the total thickness of said first layer and said second layer is 150 nm or less.

9. 9. The semiconductor device according to claim 8, wherein the second insulating layer has a thickness of 10 nm or more and 100 nm or less.

Images