Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device that can reduce forward voltage (VF).SOLUTION: A semiconductor device according to the embodiment comprises: a first electrode; a second electrode; a silicon carbide layer between the first and second electrodes and including an n-type first silicon carbide region; a titanium nitride layer between the first electrode and the first silicon carbide region; and an intermediate layer between the titanium nitride layer and the first silicon carbide region and containing silicon nitride.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has excellent physical properties, such as a band gap about three times larger, a breakdown electric field strength about ten times larger, and a thermal conductivity about three times larger. By utilizing these characteristics, it is possible to realize power semiconductor devices that can withstand high voltages, have low loss, and operate at high temperatures.

[0003] For example, in a Schottky barrier diode (SBD) using silicon carbide, a reduction in the forward voltage (VF) is required. By reducing the forward voltage (VF), for example, a low-loss SBD can be realized. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6242724 [Patent Document 2] JP 2022-140933 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of reducing a forward voltage (VF). [Means for solving the problem]

[0006] The semiconductor device of the embodiment comprises a first electrode, a second electrode, a silicon carbide layer provided between the first electrode and the second electrode and including an n-type first silicon carbide region, a titanium nitride layer provided between the first electrode and the first silicon carbide region, and an intermediate layer including silicon nitride provided between the titanium nitride layer and the first silicon carbide region. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a comparative example of the first embodiment. [Figure 4] FIG. 4 is an enlarged schematic cross-sectional view of a portion of a semiconductor device as a comparative example of the first embodiment. [Diagram 5] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are explanatory diagrams illustrating the operation and effect of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 9] FIG. 11 is an enlarged schematic cross-sectional view of a portion of a semiconductor device according to a third embodiment. [Figure 10] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described may be omitted as appropriate.

[0009] In the following description, n + , n, n - And, p +, p, p - When n is used, it indicates the relative impurity concentration of each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + shape, n - Simply put, n-type and p-type + shape, p - The shape is sometimes simply described as p-shape.

[0010] In this specification, the "p-type impurity concentration" of a p-type silicon carbide region means a net p-type impurity concentration obtained by subtracting the n-type impurity concentration of the region from the p-type impurity concentration of the region. Also, the "n-type impurity concentration" of an n-type silicon carbide region means a net n-type impurity concentration obtained by subtracting the p-type impurity concentration of the region from the n-type impurity concentration of the region.

[0011] Furthermore, unless otherwise specified in the specification, the impurity concentration in a particular region means the maximum impurity concentration in that region.

[0012] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, Scanning Capacitance Microscopy (SCM). The distances such as the width and depth of the impurity region can be obtained by, for example, SIMS. The distances such as the width and depth of the impurity region can be obtained from, for example, an image of an SCM or an image of a Scanning Electron Microscope (SEM). The thicknesses of the conductive layer and the insulating layer can be measured on, for example, an image of an SEM, a Transmission Electron Microscope (TEM), or a Scanning Transmission Electron Microscope (STEM). The qualitative and quantitative analysis of the chemical composition of the members constituting the semiconductor device can be performed by, for example, SIMS, Electron Energy Loss Spectroscopy (EELS), and Energy Dispersive X-ray Spectroscopy (EDX). Furthermore, the direction of the crystal axis of the crystal grains of the members constituting the semiconductor device can be determined from, for example, the atomic arrangement of the crystal grains observed in a STEM image.

[0013] (First embodiment) The semiconductor device of the first embodiment includes a first electrode, a second electrode, a silicon carbide layer provided between the first electrode and the second electrode and including an n-type first silicon carbide region, a titanium nitride layer provided between the first electrode and the first silicon carbide region, and an intermediate layer provided between the titanium nitride layer and the first silicon carbide region and including silicon nitride.

[0014] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention, which is an SBD 100 made of silicon carbide.

[0015] The SBD 100 includes a silicon carbide layer 10, an anode electrode 12, a cathode electrode 14, a titanium nitride layer 16, an intermediate layer 18, and an insulating layer 20. The silicon carbide layer 10 includes a drift region 10a and a cathode region 10b.

[0016] The anode electrode 12 is an example of a first electrode. The cathode electrode 14 is an example of a second electrode. The drift region 10a is an example of a first silicon carbide region. The cathode region 10b is an example of a second silicon carbide region.

[0017] The silicon carbide layer 10 is provided between an anode electrode 12 and a cathode electrode 14 .

[0018] The silicon carbide layer 10 is single crystal SiC. The silicon carbide layer 10 is, for example, 4H-SiC. The silicon carbide layer 10 includes a first face F1 and a second face F2. The second face F2 faces the first face F1.

[0019] The first face F1 is a front surface of the silicon carbide layer 10. The second face F2 is a back surface of the silicon carbide layer 10. The front surface of the silicon carbide layer 10 is a face inclined at an angle of, for example, 0 degree or more and 8 degrees or less with respect to the (0001) plane.

[0020] The silicon carbide layer 10 includes a drift region 10a and a cathode region 10b.

[0021] At least a portion of the drift region 10a is in contact with the first face F1. The drift region 10a is made of n-type silicon carbide. The drift region 10a contains n-type impurities.

[0022] The n-type impurity contained in the drift region 10a is, for example, nitrogen (N) or phosphorus (P). The n-type impurity concentration of the drift region 10a is, for example, 1×10 16 cm -3 5×10 or more 17 cm -3 The following is the result.

[0023] The cathode region 10b is provided between the drift region 10a and the second face F2. The cathode region 10b is in contact with, for example, the second face F2.

[0024] The cathode region 10b is made of n-type silicon carbide and contains n-type impurities.

[0025] The n-type impurity contained in the cathode region 10b is, for example, nitrogen (N) or phosphorus (P). The n-type impurity concentration of the cathode region 10b is higher than the n-type impurity concentration of the drift region 10a. The n-type impurity concentration of the cathode region 10b is, for example, 1×10 19 cm -3 5×10 or more 21 cm -3 The following is the result.

[0026] The anode electrode 12 is provided on the first face F1 side of the silicon carbide layer 10. The anode electrode 12 is provided on the silicon carbide layer 10.

[0027] The anode electrode 12 is a conductor. The anode electrode 12 includes, for example, a metal or a metal compound. The anode electrode 12 includes a material other than titanium nitride.

[0028] The anode electrode 12 includes, for example, aluminum (Al) The anode electrode 12 is, for example, an aluminum layer.

[0029] The cathode electrode 14 is provided on the second face F2 side of the silicon carbide layer 10. The cathode electrode 14 is provided under the silicon carbide layer 10.

[0030] The cathode electrode 14 is in contact with the second face F2. The cathode electrode 14 is in contact with the cathode region 10b.

[0031] The cathode electrode 14 is a conductor and includes, for example, a metal or a metal compound.

[0032] The cathode electrode 14 includes, for example, nickel silicide and titanium (Ti) and has, for example, a laminated structure of nickel silicide, titanium (Ti), nickel (Ni), and gold (Au).

[0033] The titanium nitride layer 16 is provided between the anode electrode 12 and the silicon carbide layer 10. The titanium nitride layer 16 is provided between the anode electrode 12 and the drift region 10a. The titanium nitride layer 16 is in contact with the anode electrode 12, for example.

[0034] The titanium nitride layer 16 is an electrical conductor. The titanium nitride layer 16 contains titanium nitride. The chemical composition of the titanium nitride contained in the titanium nitride layer 16 is, for example, TiNx(0.5 <x<2)である。

[0035] The thickness of titanium nitride layer 16 is, for example, not less than 10 nm and not more than 300 nm. The thickness of titanium nitride layer 16 is the thickness in the direction from anode electrode 12 to cathode electrode 14. In other words, the thickness of titanium nitride layer 16 is the thickness in the direction perpendicular to the surface of silicon carbide layer 10.

[0036] The intermediate layer 18 is provided between the titanium nitride layer 16 and the silicon carbide layer 10. The intermediate layer 18 is provided between the titanium nitride layer 16 and the drift region 10a.

[0037] The intermediate layer 18 contacts, for example, the drift region 10a. The intermediate layer 18 contacts, for example, the titanium nitride layer 16.

[0038] The intermediate layer 18 contains silicon nitride. The intermediate layer 18 is, for example, mainly composed of silicon nitride. That the intermediate layer 18 is mainly composed of silicon nitride means that, among the materials contained in the intermediate layer 18, the mole fraction of silicon nitride is the highest.

[0039] The thickness of intermediate layer 18 is, for example, not less than 0.5 nm and not more than 3 nm. The thickness of intermediate layer 18 is the thickness in the direction from anode electrode 12 to cathode electrode 14. In other words, the thickness of intermediate layer 18 is the thickness in the direction perpendicular to the surface of silicon carbide layer 10.

[0040] Fig. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device of the first embodiment. Fig. 2 is a schematic cross-sectional view of a portion surrounded by dotted line X in Fig. 1. Fig. 2 is a cross section perpendicular to the surface of silicon carbide layer 10.

[0041] The titanium nitride layer 16 is, for example, polycrystalline. The titanium nitride layer 16 includes, for example, a plurality of titanium nitride crystal grains in contact with the intermediate layer 18. The titanium nitride layer 16 includes, for example, a plurality of titanium nitride crystal grains 16a, 16b, 16c, and 16d in contact with the intermediate layer 18.

[0042] The crystal axes (indicated by arrows in FIG. 2) of the multiple titanium nitride crystal grains in contact with intermediate layer 18 are oblique to each other. In other words, the multiple titanium nitride crystal grains in contact with intermediate layer 18 are in contact with intermediate layer 18 at planes with different plane orientations.

[0043] For example, the crystal axes of the titanium nitride crystal grains 16a-16d are oblique to each other. For example, the crystal axes of the titanium nitride crystal grains 16a-16d are oriented in different directions. For example, the titanium nitride crystal grains 16a-16d contact the intermediate layer 18 at planes having different plane orientations.

[0044] Titanium nitride is a sodium chloride cubic crystal. The crystal axis indicated by the arrow in Fig. 2 is, for example, one of the a-axis, b-axis, and c-axis.

[0045] Whether or not the crystal axes of multiple titanium nitride crystal grains in contact with intermediate layer 18 are oblique to each other can be determined, for example, from the atomic arrangement of the crystal grains observed in a STEM image. For example, when the directions of the atomic arrangement of the crystal grains are oblique to adjacent crystal grains, it can be determined that the crystal axes of the crystal grains are oblique to each other.

[0046] The length (d in FIG. 2) of the portion where the intermediate layer 18 contacts one titanium nitride crystal grain is smaller than the thickness of the titanium nitride layer 16, for example.

[0047] The intermediate layer 18 includes, for example, a first portion 18a and a second portion 18b. The second portion 18b is provided between the first portion 18a and the drift region 10a.

[0048] The nitrogen atomic concentration in the first portion 18a is higher than the nitrogen atomic concentration in the second portion 18b. For example, the nitrogen atomic concentration in the intermediate layer 18 decreases continuously from the titanium nitride layer 16 toward the drift region 10a.

[0049] The insulating layer 20 is an insulator. The insulating layer 20 includes, for example, silicon oxide. The insulating layer 20 is, for example, a silicon oxide layer.

[0050] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0051] A manufacturing method for a semiconductor device according to the first embodiment includes preparing a plurality of semiconductor substrates each having a silicon carbide layer, forming a titanium nitride film on the silicon carbide layer, and performing heat treatment on the plurality of semiconductor substrates in an atmosphere containing nitrogen to form an intermediate layer containing silicon nitride between the silicon carbide layer and the titanium nitride film, forming a metal film on the titanium nitride film, and after forming the intermediate layer, extracting one semiconductor substrate from the plurality of semiconductor substrates and measuring the thickness of the intermediate layer in a cross section of the one semiconductor substrate.

[0052] First, a plurality of semiconductor wafers having a silicon carbide layer 10 including an n-type drift region 10a and an n-type cathode region 10b are prepared. The semiconductor wafer is an example of a semiconductor substrate. The drift region 10a is formed on the cathode region 10b by, for example, epitaxial growth.

[0053] Next, a silicon oxide film is formed on the surface of the silicon carbide layer 10. The silicon oxide film is formed by, for example, a vapor phase growth method or a thermal oxidation method. A part of the silicon oxide film will eventually become the insulating layer 20.

[0054] Next, an opening is formed in the insulating layer 20 using lithography and reactive ion etching (RIE).

[0055] Next, a titanium nitride film is formed on the surface of the silicon carbide layer 10 exposed in the opening. A part of the titanium nitride film will eventually become the titanium nitride layer 16. The titanium nitride film is formed by using, for example, a sputtering method.

[0056] Next, the titanium nitride film is patterned by using, for example, lithography and RIE.

[0057] Next, the plurality of semiconductor wafers are subjected to a heat treatment at a temperature of 500° C. to 700° C. The heat treatment is performed in an atmosphere containing nitrogen. The heat treatment is performed, for example, in an atmosphere containing nitrogen and hydrogen.

[0058] The heat treatment forms an intermediate layer 18 containing silicon nitride between the titanium nitride film and the silicon carbide layer 10. It is believed that the heat treatment causes nitrogen to diffuse between the titanium nitride film and the silicon carbide layer 10 from the surface of the titanium nitride film or from an area without the titanium nitride film, forming the intermediate layer 18 containing silicon nitride.

[0059] Next, one semiconductor wafer is extracted from the plurality of semiconductor wafers. The thickness of the intermediate layer 18 in the cross section of the extracted semiconductor wafer is measured. The thickness of the intermediate layer 18 is measured, for example, on a STEM image.

[0060] For example, if the thickness of the intermediate layer 18 differs from the desired thickness, the process conditions for the semiconductor wafers to be subsequently processed are adjusted, for example, the temperature of the heat treatment is adjusted.

[0061] Also, for example, if the thickness of the intermediate layer 18 is different from the desired thickness, it is determined that there is an abnormality in the processing, and processing of semiconductor wafers other than the one semiconductor wafer is stopped.

[0062] Next, an aluminum film is formed on the titanium nitride film of the semiconductor wafer other than the one semiconductor wafer. A part of the aluminum film will eventually become the anode electrode 12.

[0063] Next, the aluminum film is patterned using, for example, lithography and RIE.

[0064] Thereafter, a cathode electrode 14 is formed on the back surface of the silicon carbide layer 10 using a known process technology.

[0065] By the above-described method for manufacturing a semiconductor device, the SBD 100 of the first embodiment shown in FIG. 1 is manufactured.

[0066] The removal of the single semiconductor wafer may be performed, for example, after the aluminum film is formed.

[0067] In addition, the semiconductor wafer for measuring the thickness of the intermediate layer 18 may be a semiconductor wafer dedicated to thickness monitoring that is joined to the multiple semiconductor wafers just before the formation of the titanium nitride film and is extracted after heat treatment.

[0068] Furthermore, the thickness of the intermediate layer 18 may be measured after an aluminum film is formed on a semiconductor wafer other than the one semiconductor wafer described above.

[0069] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0070] In SBDs using silicon carbide, there is a demand for a reduction in the forward voltage (VF), which, for example, makes it possible to realize a low-loss SBD.

[0071] Fig. 3 is a schematic cross-sectional view of a semiconductor device of a comparative example to the first embodiment. The semiconductor device of the comparative example is an SBD 900. Fig. 3 is a view corresponding to Fig. 1 of the first embodiment.

[0072] Fig. 4 is an enlarged schematic cross-sectional view of a portion of a semiconductor device of a comparative example of the first embodiment. Fig. 4 is a schematic cross-sectional view of a portion surrounded by dotted line Y in Fig. 3. Fig. 4 is a view corresponding to Fig. 2 of the first embodiment.

[0073] The SBD 900 includes a silicon carbide layer 10, an anode electrode 12, a cathode electrode 14, a titanium nitride layer 16, and an insulating layer 20. The silicon carbide layer 10 includes a drift region 10a and a cathode region 10b.

[0074] The SBD 900 differs from the SBD 100 of the first embodiment in that it does not include an intermediate layer 18.

[0075] In the SBD 900, the titanium nitride layer 16 is in contact with the silicon carbide layer 10. In the SBD 900, the titanium nitride layer 16 is in contact with the drift region 10a.

[0076] The titanium nitride layer 16 is single crystalline. Therefore, the crystal axes (indicated by arrows in FIG. 4) of the titanium nitride in the titanium nitride layer 16 are aligned in one direction.

[0077] Next, an example of a method for manufacturing a semiconductor device according to a comparative example of the first embodiment will be described. The method for manufacturing a semiconductor device according to the comparative example of the first embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that an aluminum film and a titanium nitride film are patterned simultaneously, a heat treatment is performed after the aluminum film is formed, and the temperature of the heat treatment is low.

[0078] The process up to the formation of the titanium nitride film on the surface of the silicon carbide layer 10 is the same as the method for manufacturing the semiconductor device of the above-described first embodiment.

[0079] Next, an aluminum film is formed on the titanium nitride film. A part of the aluminum film will eventually become the anode electrode 12.

[0080] Next, the aluminum film and the titanium nitride film are simultaneously patterned using, for example, lithography and RIE.

[0081] Next, a heat treatment is performed at a temperature of, for example, 300° C. The heat treatment is performed in an atmosphere containing nitrogen. The heat treatment is performed in an atmosphere containing, for example, nitrogen and hydrogen.

[0082] Thereafter, a cathode electrode 14 is formed on the back surface of the silicon carbide layer 10 using a known process technology.

[0083] The SBD 900 of the comparative example shown in FIG. 3 is manufactured by the above-described method for manufacturing a semiconductor device.

[0084] 5 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, and is a diagram showing the voltage-current characteristics of the SBD 100 of the first embodiment and an SBD 900 of a comparative example.

[0085] 5, the SBD 100 of the first embodiment has a reduced forward voltage (VF) compared to the comparative example SBD 900. The reduced forward voltage (VF) of the SBD 100 makes it possible to realize, for example, a low-loss SBD.

[0086] In the SBD 100 of the first embodiment, it is believed that the forward voltage (VF) is reduced by reducing the Schottky barrier between the titanium nitride layer 16 and the drift region 10a. Although the reason why the Schottky barrier between the titanium nitride layer 16 and the drift region 10a in the SBD 100 is reduced is not necessarily clear, it is believed that the Schottky barrier is reduced due to the presence of the intermediate layer 18 containing silicon nitride.

[0087] For example, the presence of the intermediate layer 18 containing silicon nitride makes the titanium nitride layer 16 polycrystalline, as shown in Fig. 2. Therefore, the titanium nitride layer 16 comes into contact with the intermediate layer 18 at surfaces of a plurality of different plane orientations. For example, it is considered that the Schottky barrier is reduced by the titanium nitride work function having plane orientation dependence and the titanium nitride layer 16 having surfaces of a plurality of different plane orientations.

[0088] The thickness of titanium nitride layer 16 is preferably 10 nm or more and 300 nm or less, and more preferably 20 nm or more and 150 nm or less. When the thickness of titanium nitride layer 16 is equal to or more than the above-mentioned lower limit, the forward voltage (VF) of SBD 100 is stabilized. When the thickness of titanium nitride layer 16 is equal to or less than the above-mentioned upper limit, the stress of titanium nitride layer 16 is reduced, and wafer warpage during manufacture of SBD 100 is suppressed. Suppressing wafer warpage makes it easier to manufacture SBD 100, for example.

[0089] The length of the portion where the intermediate layer 18 and the titanium nitride crystal grains contact each other (d in FIG. 2) is preferably smaller than the thickness of the titanium nitride layer 16. This increases the number of titanium nitride crystal grains in contact with the intermediate layer 18, and further reduces the forward voltage (VF) of the SBD 100.

[0090] The thickness of the intermediate layer 18 is preferably 0.5 nm or more and 3 nm or less. When the thickness of the intermediate layer 18 is 0.5 nm or more, the forward voltage (VF) of the SBD 100 is further reduced. When the thickness of the intermediate layer 18 is 3 nm or less, the on-current of the SBD 100 is increased.

[0091] The intermediate layer 18 includes a first portion 18a and a second portion 18b, and the nitrogen atomic concentration of the first portion 18a is preferably higher than that of the second portion 18b. By lowering the nitrogen atomic concentration of the second portion 18b close to the drift region 10a, the forward voltage (VF) of the SBD 100 is prevented from decreasing too much.

[0092] 6 is an explanatory diagram of the operation and effect of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment, and is a diagram showing the relationship between the thickness of the intermediate layer and the reverse leakage current of the SBD 100 according to the first embodiment.

[0093] 6, the thinner the intermediate layer 18, the smaller the reverse leakage current. From the viewpoint of reducing the reverse leakage current of the SBD 100, it is preferable that the intermediate layer 18 is thinner. From the viewpoint of reducing the reverse leakage current of the SBD 100, it is preferable that the thickness of the intermediate layer 18 is 1.5 nm or less, and more preferably 1.3 nm or less.

[0094] In the method for manufacturing a semiconductor device according to the first embodiment, after intermediate layer 18 is formed, the semiconductor wafer is extracted and the thickness of intermediate layer 18 is measured. By measuring the thickness of intermediate layer 18, it is possible to predict the magnitude of the reverse leakage current of SBD 100 after the SBD 100 is manufactured based on the correlation shown in FIG.

[0095] For example, if the thickness of intermediate layer 18 is different from the desired thickness, the process conditions for the semiconductor wafers to be subsequently processed are adjusted, allowing early feedback to the process conditions, which may improve, for example, the manufacturing yield of SBD 100.

[0096] For example, if the thickness of intermediate layer 18 is different from the desired thickness, it is determined that there is an abnormality in the processing, and further processing of semiconductor wafers other than the one semiconductor wafer is halted. By halting the production of SBDs 100 that are predicted to be defective, it is possible to reduce manufacturing costs, for example.

[0097] As described above, the thinner the intermediate layer 18, the smaller the reverse leakage current. For example, the lower the temperature of the heat treatment for forming the intermediate layer 18, the thinner the thickness of the intermediate layer 18. From the viewpoint of reducing the thickness of the intermediate layer 18 and reducing the reverse leakage current of the SBD 100, the temperature of the heat treatment for forming the intermediate layer 18 is preferably 600° C. or less.

[0098] Furthermore, the thickness of intermediate layer 18 becomes thinner, for example, as the thickness of the titanium nitride film formed before forming intermediate layer 18 becomes thicker. From the viewpoint of reducing the thickness of intermediate layer 18 and reducing the reverse leakage current of SBD 100, the thickness of the titanium nitride film formed before forming intermediate layer 18 is preferably 250 nm or less, more preferably 100 nm or less, and even more preferably 50 nm or less.

[0099] As described above, according to the first embodiment, an SBD that can reduce the forward voltage (VF) can be realized. In addition, the manufacturing yield of the SBD can be improved, and the manufacturing cost can be reduced.

[0100] Second Embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the silicon carbide layer further includes a p-type third silicon carbide region provided between the first silicon carbide region and the first electrode, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first electrode, and the first silicon carbide region is provided between the third silicon carbide region and the fourth silicon carbide region. Hereinafter, description of contents that overlap with the first embodiment may be omitted.

[0101] 7 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is an SBD 200 that uses silicon carbide. The SBD 200 has a so-called Junction Barrier Schottky structure (JBS structure) that combines a pn junction and a Schottky junction.

[0102] The SBD 200 includes a silicon carbide layer 10, an anode electrode 12, a cathode electrode 14, a titanium nitride layer 16, an intermediate layer 18, and an insulating layer 20. The silicon carbide layer 10 includes a drift region 10a, a cathode region 10b, a first p-type region 10c, and a second p-type region 10d.

[0103] The anode electrode 12 is an example of a first electrode. The cathode electrode 14 is an example of a second electrode. The drift region 10a is an example of a first silicon carbide region. The cathode region 10b is an example of a second silicon carbide region. The first p-type region 10c is an example of a third silicon carbide region. The second p-type region 10d is an example of a fourth silicon carbide region.

[0104] The first p-type region 10c is provided between the drift region 10a and the anode electrode 12. The first p-type region 10c is provided between the drift region 10a and the first face F1. The first p-type region 10c is in contact with the first face F1.

[0105] The first p-type region 10c is made of p-type silicon carbide and contains p-type impurities.

[0106] The p-type impurity contained in the first p-type region 10c is, for example, aluminum (Al). The p-type impurity concentration of the first p-type region 10c is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0107] The second p-type region 10d is provided between the drift region 10a and the anode electrode 12. The second p-type region 10d is provided between the drift region 10a and the first face F1. The second p-type region 10d is in contact with the first face F1.

[0108] A portion of the drift region 10a is provided between the first p-type region 10c and the second p-type region 10d. A portion of the drift region 10a provided between the first p-type region 10c and the second p-type region 10d contacts the first face F1. A portion of the drift region 10a provided between the first p-type region 10c and the second p-type region 10d contacts the intermediate layer 18.

[0109] The second p-type region 10d is made of p-type silicon carbide. The second p-type region 10d contains p-type impurities.

[0110] The p-type impurity contained in the second p-type region 10d is, for example, aluminum (Al). The p-type impurity concentration of the second p-type region 10d is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0111] When a reverse bias is applied to the SBD 200, for example, a depletion layer extending from the first p-type region 10c and the second p-type region 10d to the drift region 10a covers the interface between the intermediate layer 18 and the drift region 10a. Therefore, the SBD 200 reduces leakage current when a reverse bias is applied compared to the SBD 100. In other words, the SBD 200 reduces off-leakage current compared to the SBD 100.

[0112] As described above, according to the second embodiment, an SBD capable of reducing the forward voltage (VF) can be realized. Also, an SBD capable of reducing the off-leakage current can be realized.

[0113] (Third embodiment) The semiconductor device of the third embodiment includes a first electrode, a second electrode, a silicon carbide layer provided between the first electrode and the second electrode and including an n-type first silicon carbide region, a vanadium nitride layer provided between the first electrode and the first silicon carbide region, and an intermediate layer including silicon nitride provided between the vanadium nitride layer and the first silicon carbide region. The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that it includes a vanadium nitride layer instead of a titanium nitride layer. Hereinafter, some of the contents that overlap with the first embodiment may be omitted.

[0114] 8 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. The semiconductor device according to the third embodiment is an SBD 300 that uses silicon carbide.

[0115] The SBD 300 includes a silicon carbide layer 10, an anode electrode 12, a cathode electrode 14, a vanadium nitride layer 17, an intermediate layer 18, and an insulating layer 20. The silicon carbide layer 10 includes a drift region 10a and a cathode region 10b.

[0116] The vanadium nitride layer 17 is provided between the anode electrode 12 and the silicon carbide layer 10. The vanadium nitride layer 17 is provided between the anode electrode 12 and the drift region 10a. The vanadium nitride layer 17 is in contact with the anode electrode 12, for example.

[0117] The vanadium nitride layer 17 is an electrical conductor. The vanadium nitride layer 17 contains vanadium nitride. The chemical composition of the vanadium nitride contained in the vanadium nitride layer 17 is, for example, VNx (0.5≦x<2).

[0118] The thickness of the vanadium nitride layer 17 is, for example, not less than 10 nm and not more than 300 nm. The thickness of the vanadium nitride layer 17 is the thickness in the direction from the anode electrode 12 to the cathode electrode 14. In other words, the thickness of the vanadium nitride layer 17 is the thickness in the direction perpendicular to the surface of the silicon carbide layer 10.

[0119] The intermediate layer 18 is provided between the vanadium nitride layer 17 and the silicon carbide layer 10. The intermediate layer 18 is provided between the vanadium nitride layer 17 and the drift region 10a.

[0120] The intermediate layer 18 is in contact with, for example, the drift region 10a. The intermediate layer 18 is in contact with, for example, the vanadium nitride layer 17.

[0121] The intermediate layer 18 contains silicon nitride. The intermediate layer 18 is, for example, mainly composed of silicon nitride. That the intermediate layer 18 is mainly composed of silicon nitride means that, among the materials contained in the intermediate layer 18, the mole fraction of silicon nitride is the highest.

[0122] The thickness of intermediate layer 18 is, for example, not less than 0.5 nm and not more than 3 nm. The thickness of intermediate layer 18 is the thickness in the direction from anode electrode 12 to cathode electrode 14. In other words, the thickness of intermediate layer 18 is the thickness in the direction perpendicular to the surface of silicon carbide layer 10.

[0123] Fig. 9 is an enlarged schematic cross-sectional view of a portion of the semiconductor device of the third embodiment. Fig. 9 is a schematic cross-sectional view of a portion surrounded by dotted line X in Fig. 8. Fig. 9 is a cross section perpendicular to the surface of silicon carbide layer 10.

[0124] The vanadium nitride layer 17 is, for example, polycrystalline. The vanadium nitride layer 17 includes, for example, a plurality of vanadium nitride crystal grains in contact with the intermediate layer 18. The vanadium nitride layer 17 includes, for example, a plurality of vanadium nitride crystal grains 17a, 17b, 17c, and 17d in contact with the intermediate layer 18.

[0125] The crystal axes (indicated by arrows in FIG. 9) of the multiple vanadium nitride crystal grains in contact with intermediate layer 18 are oblique to each other. In other words, the multiple vanadium nitride crystal grains in contact with intermediate layer 18 are in contact with intermediate layer 18 at planes with different plane orientations.

[0126] For example, the crystal axes of the vanadium nitride crystal grains 17a-17d are oblique to each other. For example, the crystal axes of the vanadium nitride crystal grains 17a-17d are oriented in different directions. For example, the vanadium nitride crystal grains 17a-17d contact the intermediate layer 18 at planes having different plane orientations.

[0127] Vanadium nitride is a sodium chloride cubic crystal. The crystal axis indicated by the arrow in Fig. 9 is, for example, one of the a-axis, b-axis, and c-axis.

[0128] Whether or not the crystal axes of multiple vanadium nitride crystal grains in contact with intermediate layer 18 are oblique to each other can be determined, for example, from the atomic arrangement of the crystal grains observed in a STEM image. For example, when the directions of the atomic arrangement of the crystal grains are oblique to adjacent crystal grains, it can be determined that the crystal axes of the crystal grains are oblique to each other.

[0129] The length of the portion where the intermediate layer 18 contacts one crystal grain of the vanadium nitride (d in FIG. 9) is smaller than the thickness of the vanadium nitride layer 17, for example.

[0130] The intermediate layer 18 includes, for example, a first portion 18a and a second portion 18b. The second portion 18b is provided between the first portion 18a and the drift region 10a.

[0131] The nitrogen atomic concentration in the first portion 18a is higher than the nitrogen atomic concentration in the second portion 18b. For example, the nitrogen atomic concentration in the intermediate layer 18 decreases continuously from the vanadium nitride layer 17 toward the drift region 10a.

[0132] The insulating layer 20 is an insulator. The insulating layer 20 includes, for example, silicon oxide. The insulating layer 20 is, for example, a silicon oxide layer.

[0133] Next, the semiconductor device of the third embodiment can be manufactured by, for example, replacing the titanium nitride film with a vanadium nitride film in the manufacturing method of the first embodiment.

[0134] As described above, according to the third embodiment, an SBD capable of reducing the forward voltage (VF) can be realized, as in the first embodiment, and also, an improvement in the manufacturing yield of SBDs and a reduction in manufacturing costs can be realized.

[0135] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the third embodiment in that the silicon carbide layer further includes a p-type third silicon carbide region provided between the first silicon carbide region and the first electrode, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first electrode, and the first silicon carbide region is provided between the third silicon carbide region and the fourth silicon carbide region. The semiconductor device of the fourth embodiment also differs from the semiconductor device of the second embodiment in that the semiconductor device of the fourth embodiment includes a vanadium nitride layer instead of a titanium nitride layer. Hereinafter, the description of the contents overlapping with the third embodiment or the second embodiment may be omitted.

[0136] 10 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment. The semiconductor device according to the fourth embodiment is an SBD 400 that uses silicon carbide. The SBD 400 has a so-called Junction Barrier Schottky structure (JBS structure) that combines a pn junction and a Schottky junction.

[0137] The SBD 400 includes a silicon carbide layer 10, an anode electrode 12, a cathode electrode 14, a vanadium nitride layer 17, an intermediate layer 18, and an insulating layer 20. The silicon carbide layer 10 includes a drift region 10a, a cathode region 10b, a first p-type region 10c, and a second p-type region 10d.

[0138] As described above, according to the fourth embodiment, an SBD capable of reducing the forward voltage (VF) can be realized, similarly to the second embodiment, and also an SBD with reduced off-leakage current can be realized.

[0139] In the first to fourth embodiments, the crystal structure of SiC is 4H-SiC, but the present invention can be applied to devices using SiC with other crystal structures such as 6H-SiC, 3C-SiC, etc. Also, a plane other than the (0001) plane can be applied to the surface of the silicon carbide layer 10.

[0140] In the first to fourth embodiments, aluminum (Al) is exemplified as the p-type impurity, but boron (B) can also be used. In addition, nitrogen (N) and phosphorus (P) are exemplified as the n-type impurity, but arsenic (As), antimony (Sb), etc. can also be used.

[0141] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0142] 10 Silicon carbide layer 10a drift region (first silicon carbide region) 10b Cathode region (second silicon carbide region) 10c first p-type region (third silicon carbide region) 10d second p-type region (fourth silicon carbide region) 12 Anode electrode (first electrode) 14 Cathode electrode (second electrode) 16 Titanium nitride layer 16a Grain 16b Grain 16c grain 16d grain 17 Vanadium nitride layer 18 Middle Class 18a First Part 18b Second Part 20 Insulating layer 100 SBD (semiconductor device) 200 SBD (semiconductor device) 300 SBD (semiconductor device) 400 SBD (semiconductor device)

Claims

1. The first electrode and The second electrode and A silicon carbide layer is provided between the first electrode and the second electrode, and includes an n-type first silicon carbide region. A titanium nitride layer is provided between the first electrode and the first silicon carbide region, An intermediate layer containing silicon nitride is provided between the titanium nitride layer and the first silicon carbide region, A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein the intermediate layer and the first silicon carbide region are in contact, and the intermediate layer and the titanium nitride layer are in contact.

3. The semiconductor device according to claim 1, wherein the titanium nitride layer is polycrystalline.

4. The semiconductor device according to claim 3, wherein the titanium nitride layer includes a plurality of crystal grains in contact with the intermediate layer, and the crystal axes of the plurality of crystal grains are oblique to each other.

5. The semiconductor device according to claim 1, wherein the intermediate layer includes a first portion and a second portion provided between the first portion and the first silicon carbide region, and the nitrogen atom concentration of the first portion is higher than the nitrogen atom concentration of the second portion.

6. The semiconductor device according to claim 1, wherein the thickness of the intermediate layer is 0.5 nm or more and 3 nm or less.

7. The semiconductor device according to claim 1, wherein the silicon carbide layer is provided between the first silicon carbide region and the second electrode, is in contact with the second electrode, and further includes a second n-type silicon carbide region having a higher n-type impurity concentration than the n-type impurity concentration of the first silicon carbide region.

8. The aforementioned silicon carbide layer is A p-shaped third silicon carbide region is provided between the first silicon carbide region and the first electrode, The present invention further includes a p-shaped fourth silicon carbide region provided between the first silicon carbide region and the first electrode, The semiconductor device according to claim 7, wherein a portion of the first silicon carbide region is provided between the third silicon carbide region and the fourth silicon carbide region.

9. Prepare multiple semiconductor substrates having a silicon carbide layer, A titanium nitride film is formed on the silicon carbide layer. By performing heat treatment on the plurality of semiconductor substrates in a nitrogen-containing atmosphere, an intermediate layer containing silicon nitride is formed between the silicon carbide layer and the titanium nitride film. A metal film is formed on the titanium nitride film, After forming the intermediate layer, one semiconductor substrate is removed from the plurality of semiconductor substrates. A method for manufacturing a semiconductor device, comprising measuring the thickness of the intermediate layer in a cross-section of the aforementioned semiconductor substrate.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the single semiconductor substrate is removed before the metal film is formed.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the temperature of the heat treatment is 500°C or more and 700°C or less.

12. The method for manufacturing a semiconductor device according to claim 9, wherein the metal film contains aluminum.

13. The first electrode and The second electrode and A silicon carbide layer is provided between the first electrode and the second electrode, and includes an n-type first silicon carbide region. A vanadium nitride layer is provided between the first electrode and the first silicon carbide region, An intermediate layer containing silicon nitride is provided between the vanadium nitride layer and the first silicon carbide region, A semiconductor device equipped with a semiconductor device.

14. The semiconductor device according to claim 13, wherein the intermediate layer and the first silicon carbide region are in contact, and the intermediate layer and the vanadium nitride layer are in contact.

15. The semiconductor device according to claim 13, wherein the vanadium nitride layer is polycrystalline.

16. The semiconductor device according to claim 15, wherein the vanadium nitride layer includes a plurality of crystal grains in contact with the intermediate layer, and the crystal axes of the plurality of crystal grains are oblique to each other.

17. The semiconductor device according to claim 13, wherein the intermediate layer includes a first portion and a second portion provided between the first portion and the first silicon carbide region, and the nitrogen atom concentration of the first portion is higher than the nitrogen atom concentration of the second portion.

18. The semiconductor device according to claim 13, wherein the thickness of the intermediate layer is 0.5 nm or more and 3 nm or less.

19. The semiconductor device according to claim 13, wherein the silicon carbide layer is provided between the first silicon carbide region and the second electrode, is in contact with the second electrode, and further includes a second n-type silicon carbide region having a higher n-type impurity concentration than the n-type impurity concentration of the first silicon carbide region.

20. The aforementioned silicon carbide layer is A p-shaped third silicon carbide region is provided between the first silicon carbide region and the first electrode, The present invention further includes a p-shaped fourth silicon carbide region provided between the first silicon carbide region and the first electrode, The semiconductor device according to claim 19, wherein a portion of the first silicon carbide region is provided between the third silicon carbide region and the fourth silicon carbide region.

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