Voltage regulator
Patent Information
- Application Number
- JP2023213500
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-03-23
- Filing Date
- 2023-12-19
- Publication Date
- 2026-10-06
AI Technical Summary
Conventional voltage regulators experience delays in responding to sudden changes in load current due to the use of delay compensation with Miller capacitance in the control loop.
A voltage regulator design incorporating a common source amplifier circuit with phase lead compensation using a resistor and capacitor, and an output transistor with a gate connected to a control signal, which reduces impedance and ensures rapid response to load current fluctuations without relying on Miller capacitance.
The design enables faster output voltage response to sudden load current changes, ensuring quicker phase margin and overcurrent protection through reduced gain and impedance, outperforming traditional regulators with Miller capacitance-based delay compensation.
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Abstract
Description
[Technical field]
[0001] The present invention relates to a voltage regulator. [Background technology]
[0002] In general, it is desirable for a voltage regulator to generate a constant output voltage by receiving a power supply voltage and maintain the output voltage at a constant value even if the power supply voltage or the load current fluctuates. One example is a voltage regulator that includes a reference voltage source, an error amplifier circuit, an output transistor, and a phase compensation circuit using a mirror capacitance (see, for example, Patent Document 1). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2013-149147 A Summary of the Invention [Problem to be solved by the invention]
[0004] However, in conventional voltage regulators, delay compensation by a Miller capacitance is used for phase compensation of the control loop, so there is room for improvement in that a delay occurs in the response of the output voltage to a sudden change in the load current.
[0005] SUMMARY OF THE PRESENT EMBODIMENT In consideration of the above-mentioned circumstances, an object of the present invention is to provide a voltage regulator in which the response of the output voltage to a sudden change in load current is faster than in the past. [Means for solving the problem]
[0006] A voltage regulator according to an embodiment of the present invention includes an error amplifier circuit that outputs a signal obtained by amplifying the difference between a reference voltage and a feedback voltage, a source-grounded amplifier circuit that amplifies the signal supplied from the error amplifier circuit and outputs it as a control signal, and an output transistor that includes a gate to which the control signal is supplied and outputs an output voltage, wherein the source-grounded amplifier circuit has a phase-lead compensation circuit including a resistor and a capacitor, a load including an offset generation element that generates an offset voltage and a resistor, a gate to which the signal output from the error amplifier circuit is supplied, and a transistor including a drain connected to one end of the resistor and one end of the capacitor included in the phase-lead compensation circuit, and a source connected to the load. Effect of the Invention
[0007] According to the present invention, it is possible to provide a voltage regulator in which the response of the output voltage to a sudden change in load current is faster than in the past. [Brief description of the drawings]
[0008] [Figure 1] 1 is a circuit diagram showing an example of the configuration of a voltage regulator according to a first embodiment of the present invention. [Diagram 2] FIG. 5 is a circuit diagram illustrating an example of the configuration of a voltage regulator according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A voltage regulator according to an embodiment of the present invention will now be described with reference to the drawings.
[0010] [First embodiment] FIG. 1 is a circuit diagram of a voltage regulator 100, which is an example of a voltage regulator according to a first embodiment of the present invention.
[0011] The voltage regulator 100 includes a power supply terminal 101, a ground terminal 102, a reference voltage source 120, an error amplifier circuit 121, a resistor 122, a PMOS transistor 123, an NMOS transistor 124, a resistor 125, a capacitor 126, a PMOS transistor 127, a resistor 128, a resistor 129, and an output terminal 110. The ground terminal 102 is a power supply terminal that supplies a power supply voltage of 0V (zero volts) (hereinafter referred to as "ground voltage") as an example of a power supply voltage that is a reference for circuit operation. The resistor 122, the PMOS transistor 123, the NMOS transistor 124, the resistor 125, and the capacitor 126 configure a source-grounded amplifier circuit 103.
[0012] The grounded-source amplifier circuit 103 has a load including a resistor 122 and a PMOS transistor 123, a phase-lead compensation circuit including a resistor 125 and a capacitor 126, and an NMOS transistor 124. The grounded-source amplifier circuit 103 also has an input terminal 103a and an output terminal 103b. Here, the input terminal 103a is a connection point between the output terminal of the error amplifier circuit 121 and the gate of the NMOS transistor 124, and is a node that receives a signal supplied from the error amplifier circuit 121. The output terminal 103b is a connection point between the drain of the NMOS transistor 124, the gate and drain of the PMOS transistor 123, and the gate of the PMOS transistor 127, and is a node that outputs a control voltage to the gate of the PMOS transistor 127.
[0013] One end of the reference voltage source 120 is connected to the non-inverting input terminal (+) of the error amplifier circuit 121 , and the other end is connected to the ground terminal 102 . The NMOS transistor 124 has a gate connected to the output terminal of the error amplifier circuit 121, a source connected to one end of the resistor 125 and one end of the capacitor 126, and a drain connected to the gate and drain of the PMOS transistor 123 and the gate of the PMOS transistor 127. The resistor 122 has one end connected to the power supply terminal 101 and the other end connected to the source of the PMOS transistor 123 . The other end of the resistor 125 is connected to the ground terminal 102. The other end of the capacitor 126 is connected to the ground terminal 102. A PMOS transistor 127 serving as an output transistor has a source connected to the power supply terminal 101 and a drain connected to the output terminal 110 and one end of a resistor 128. The other end of the resistor 128 is connected to one end of a resistor 129 and the inverting input terminal (-) of the error amplifier circuit 121. The other end of the resistor 129 is connected to the ground terminal 102.
[0014] Next, the operation of the voltage regulator 100 will be described. A power supply terminal 101 supplies a predetermined power supply voltage, and a ground terminal 102 supplies a ground voltage.
[0015] The output terminal 110 is the output terminal of the voltage regulator 100, and the voltage at the output terminal 110 is the output voltage VOUT. Resistors 128 and 129 divide the output voltage VOUT to generate a feedback voltage VFB. The error amplifier circuit 121 compares the magnitude of the reference voltage VREF output from the reference voltage source 120 with the feedback voltage VFB, and outputs an error voltage VERR from the output terminal. The error voltage VERR is supplied to the source-grounded amplifier circuit 103 (more specifically, the gate of the NMOS transistor 124).
[0016] In the common-source amplifier circuit 103, a lead compensation is generated by an NMOS transistor 124, a resistor 125, and a capacitor 126. In addition, a PMOS transistor 123 as an offset generating element generates an offset voltage across both ends, i.e., between the source and drain. Since the common-source amplifier circuit 103 generates an offset voltage between the source and drain of the PMOS transistor 123, the impedance of the load is reduced and the gain is reduced. The signal amplified by the common-source amplifier circuit 103 is supplied as a control signal from an output terminal 103b to the gate of a PMOS transistor 127. The PMOS transistor 127 receives a voltage VGATE as a control signal at its gate and outputs an output voltage VOUT to its drain. The output voltage VOUT is supplied to an output terminal 110 connected to the drain of the PMOS transistor 127.
[0017] Next, the reason why the impedance of the load of the common-source amplifier circuit 103 including the resistor 122 and the PMOS transistor 123 is reduced will be described.
[0018] Since the gate and drain of the PMOS transistor 123 are connected, the impedance between the source and drain is small, and the PMOS transistor 123 operates as an offset generating element that generates an offset voltage between the source and drain. A control signal for making the PMOS transistor 127 conductive, i.e., the gate-source voltage of the PMOS transistor 127, is generated by the offset voltage and the voltage across the resistor 122. As such, since the offset voltage exists in the load, the voltage drop (voltage across the resistor 122) is reduced compared to when the offset voltage does not exist. As a result, the impedance of the load of the source-grounded amplifier circuit 103 is reduced.
[0019] According to voltage regulator 100, by adding lead compensation to the control loop in common-source amplifier circuit 103 and further reducing the gain, it is possible to ensure the phase margin of voltage regulator 100. Furthermore, according to voltage regulator 100, since lag compensation by Miller capacitance is not used in the control loop, it is possible to speed up the response speed of the output voltage to abrupt fluctuations in the load current compared to a voltage regulator that uses lag compensation by Miller capacitance in the control loop. In other words, it is possible to make the response of the output voltage to abrupt fluctuations in the load current faster than in the past.
[0020] [Second embodiment] FIG. 2 is a circuit diagram of a voltage regulator 200, which is an example of a voltage regulator according to a second embodiment of the present invention.
[0021] Voltage regulator 200 differs from voltage regulator 100 in that it further includes overcurrent protection circuit 106, but is not substantially different in other respects. Therefore, in the description of this embodiment, the different overcurrent protection circuit 106 will be mainly described, and components that overlap with voltage regulator 100 will be denoted by the same reference numerals and description thereof will be omitted.
[0022] The voltage regulator 200 includes a power supply terminal 101, a ground terminal 102, a reference voltage source 120, an error amplifier circuit 121, a resistor 122, a PMOS transistor 123, an NMOS transistor 124, a resistor 125, a capacitance 126, a PMOS transistor 127, a resistor 128, a resistor 129, an overcurrent protection circuit 106, and an output terminal 110.
[0023] The overcurrent protection circuit 106 includes a PMOS transistor 131, a resistor 132, and an NMOS transistor 133. The PMOS transistor 131 and the resistor 132 form a voltage generating circuit that generates a voltage VN1 at a node N1 which is a connection point between the PMOS transistor 131 and the resistor 132.
[0024] The overcurrent protection circuit 106 has connection terminals 106a to 106d for connection to the outside of the overcurrent protection circuit 106. The connection terminal 106a is connected to the output terminal of the error amplifier circuit 121 and the gate of the NMOS transistor 124. The connection terminal 106b is connected to the ground terminal 102. The connection terminal 106c is connected to the gate and drain of the PMOS transistor 123, the drain of the NMOS transistor 124, and the gate of the PMOS transistor 127, and receives a voltage VGATE. The connection terminal 106d is connected to the power supply terminal 101.
[0025] The PMOS transistor 131 has a source connected to the power supply terminal 101, a gate connected to a connection point between the drain of the NMOS transistor 124, the gate and drain of the PMOS transistor 123, and the gate of the PMOS transistor 127, and a drain connected to one end of the resistor 132. The other end of the resistor 132 is connected to the ground terminal 102. The NMOS transistor 133 has a drain connected to a connection point between the output terminal of the error amplifier circuit 121 and the gate of the NMOS transistor 124, a source connected to the ground terminal 102, and a gate connected to a node N1. That is, the NMOS transistor 133 as a switch switches the path connecting the output terminal of the error amplifier circuit 121 and the ground terminal 102 between a conductive (on) state and an open (off) state in response to a voltage VN1, which is an example of a voltage based on a control signal.
[0026] Next, a description will be given of the operation of the voltage regulator 200. Note that, in describing the operation of the voltage regulator 200, the description will be centered on the case where the output terminal 110 is shorted to the ground terminal 102 and the overcurrent protection circuit 106 is operating.
[0027] The same voltage VGATE is applied to the gate of the PMOS transistor 131 and the gate of the PMOS transistor 127, which are the same node. Proportional drain currents flow through the PMOS transistor 131 and the PMOS transistor 127. The drain current of the PMOS transistor 127 flows through the resistor 132, generating a voltage VN1 at the node N1.
[0028] If the drain currents of the PMOS transistors 127 and 131 are large and the voltage VN1 exceeds the threshold voltage of the NMOS transistor 133, the NMOS transistor 133 turns on and the gate voltage of the NMOS transistor 124 drops. When the gate voltage of the NMOS transistor 124 drops, the voltage VGATE rises, so that the drain currents of the PMOS transistor 127 and the PMOS transistor 131 drop. In this way, a negative feedback loop is formed in the voltage regulator 200, and the overcurrent protection circuit 106 performs overcurrent protection operation by the negative feedback of the negative feedback loop formed in the voltage regulator 200.
[0029] According to the voltage regulator 200, similarly to the voltage regulator 100, the response of the output voltage to a sudden change in the load current can be made faster than in the past. Moreover, in the voltage regulator 200, the drain currents of the PMOS transistors 127 and 131 are large, and when the voltage VN1 exceeds the threshold voltage of the NMOS transistor 133, a negative feedback loop is formed to turn on the PMOS transistor 133 and reduce the drain currents of the PMOS transistors 127 and 131, so that overcurrent protection is possible. According to the voltage regulator 200, the negative feedback loop formed includes the common source circuit 103, so that the response speed of the overcurrent protection function to a sudden change in the load current can be made faster. That is, the response of the overcurrent protection function to a sudden change in the load current can be made faster than in the past.
[0030] The present invention is not limited to the above-described embodiment, and can be implemented in various forms other than the above-described examples at the implementation stage, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. These embodiments and modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]
[0031] 100 Voltage Regulator 101 Power terminal 102 Ground terminal 103 Source grounded amplifier circuit 106 Overcurrent protection circuit 120 Reference Voltage Source 121 Error Amplifier Circuit 124 NMOS transistor 123 PMOS transistor (offset generating element) 122, 125, 128, 129 Resistor 126 capacity 127 PMOS transistor (output transistor) 133 NMOS transistor (switch) 110 Output terminal
Claims
1. an error amplifier circuit that outputs a signal obtained by amplifying the difference between a reference voltage and a feedback voltage; a source ground amplifier circuit that amplifies the signal supplied from the error amplifier circuit and outputs the amplified signal as a control signal; an output transistor including a gate to which the control signal is supplied and which outputs an output voltage; The source ground amplifier circuit includes a phase lead compensation circuit including a resistor and a capacitor; a load including an offset generating element that generates an offset voltage and a resistor; a transistor including: a gate to which the signal output from the error amplifier circuit is supplied; a source connected to one end of the resistor and one end of the capacitor included in the phase lead compensation circuit; and a drain connected to the load; A voltage regulator comprising:
2. 2. The voltage regulator according to claim 1, further comprising an overcurrent protection circuit having a switch that switches a path connecting an output terminal of the error amplifier circuit and a power supply terminal that supplies a power supply voltage that is a reference for circuit operation between a conductive state and an open state in response to a voltage based on the control signal.
3. 2. The voltage regulator according to claim 1, further comprising an overcurrent protection circuit including: a voltage generation circuit connected between a first power supply terminal supplying a first power supply voltage and a second power supply terminal supplying a second power supply voltage, the voltage generation circuit generating a voltage based on the control signal; and a switch switching a path connecting an output terminal of the error amplifier circuit and the first power supply terminal between a conductive state and an open state depending on the voltage generated by the voltage generation circuit.
4. 2. The voltage regulator according to claim 1, wherein the offset generating element is a transistor having a gate and a drain connected together.