Semiconductor device and display device

Abstract

To improve the electrical characteristic of a semiconductor device including an oxide semiconductor.SOLUTION: A semiconductor device includes a first insulating layer, a metal oxide layer mainly containing aluminum on the first insulating layer, an oxide semiconductor layer having a polycrystal structure on the metal oxide layer, a gate insulating layer on the oxide semiconductor layer, a gate electrode on the gate insulating layer, and a second insulating layer on the gate electrode. The metal oxide layer has a pattern shape. The oxide semiconductor layer includes a first region in contact with the gate insulating layer, and a second region continuing to the first region in a first direction and in contact with the gate insulating layer and the second insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a display device, particularly to a semiconductor device including an oxide semiconductor and a display device using the semiconductor device including the oxide semiconductor. [Background technology]

[0002] In recent years, oxide semiconductors have been attracting attention as materials constituting semiconductor devices, replacing amorphous silicon, polysilicon, and single crystal silicon. In particular, thin film transistors using oxide semiconductors as channels have been developed as semiconductor devices including oxide semiconductors (for example, Patent Documents 1 to 6). Thin film transistors using oxide semiconductors as channels can be formed with a simple structure and low-temperature process, similar to semiconductor devices using amorphous silicon as channels. Thin film transistors using oxide semiconductors as channels are known to have higher field-effect mobility than thin film transistors using amorphous silicon as channels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a conventional thin film transistor including an oxide semiconductor, the threshold voltage indicating switching characteristics may shift in the negative direction or the variation in the threshold voltage may become large when the channel length is reduced. Therefore, the conventional thin film transistor including an oxide semiconductor has a low degree of freedom in designing the channel length when reducing the size, and the applications may be limited.

[0005] An object of the present invention is to improve the electrical characteristics of a semiconductor device including an oxide semiconductor. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a first insulating layer, a metal oxide layer mainly composed of aluminum on the first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the metal oxide layer, a gate insulating layer on the oxide semiconductor layer, a gate electrode on the gate insulating layer, and a second insulating layer on the gate electrode, wherein the metal oxide layer has a pattern shape, and the oxide semiconductor layer has a first region in contact with the gate insulating layer and a second region that is continuous with the first region in a first direction and in contact with the gate insulating layer and the second insulating layer. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic plan view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 4 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 6]1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 13] 4 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 15] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 16] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 17] 1 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [Figure 18] 2 is a plan view of a pixel electrode and a common electrode of the display device according to the embodiment of the present invention. FIG. [Figure 19] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. [Figure 20] 1 is a cross-sectional view showing an overview of a display device according to an embodiment of the present invention. [Figure 21A] FIG. 4 is a diagram showing electrical characteristics of a semiconductor device according to an embodiment of the present invention. [Figure 21B] FIG. 13 is a diagram showing electrical characteristics of a semiconductor device in a comparative example. [Figure 22]1 is a diagram illustrating an example of the relationship between the design channel length (channel length on the layout) (Lg) of a transistor and the channel resistance (R) for different gate voltages (Vg). [Figure 23A] FIG. 11 is a diagram showing the dependency of the threshold voltage on the channel length in a semiconductor device according to one embodiment of the present invention. [Figure 23B] FIG. 13 is a diagram showing the dependency of the threshold voltage on the channel length in a semiconductor device of the comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". In this way, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the order of stacking in a structure in which multiple layers are stacked, and when it is expressed as "a pixel electrode above a transistor", it may be a positional relationship in which the transistor and the pixel electrode do not overlap in a planar view. On the other hand, when it is expressed as "a pixel electrode vertically above a transistor", it means a positional relationship in which the transistor and the pixel electrode overlap in a planar view.

[0010] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described by taking a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure in this embodiment can be applied to display devices including other electro-optical layers as described above.

[0011] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0012] In this specification, "the same" includes not only completely the same, but also substantially the same. "Substantially the same" refers to a case where the difference is not completely the same but is within a slight range that can be considered to be the same, for example, within an error range of ±5% (preferably ±3%).

[0013] First Embodiment A semiconductor device according to an embodiment of the present invention will be described by taking a thin film transistor as an example with reference to Figures 1 to 12. The semiconductor device according to the embodiment described below may be a thin film transistor used in a display device, or may be a thin film transistor used in an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU) or a memory circuit.

[0014] [Configuration of semiconductor device] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a schematic cross-sectional view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. Figure 2 is a schematic plan view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. Specifically, Figure 1 corresponds to a cross-sectional view taken along the dashed line indicated by A-A' in Figure 2.

[0015] 1, the semiconductor device 10 is provided above a substrate 100. The semiconductor device 10 includes a conductive layer 105, insulating layers 110 and 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrode 200.

[0016] The conductive layer 105 is provided over the substrate 100. The conductive layer 105 functions as a light-shielding film for the oxide semiconductor layer 140.

[0017] The insulating layers 110 and 120 are provided on the substrate 100 and the conductive layer 105. The insulating layer 110 functions as a barrier film that blocks impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140.

[0018] The metal oxide layer 130 is provided on the insulating layer 120. The metal oxide layer 130 is in contact with the insulating layer 120. The metal oxide layer 130 is a layer containing a metal oxide containing aluminum as a main component, and functions as a gas barrier film that blocks gases such as oxygen and hydrogen.

[0019] The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. The surface of the main surface of the oxide semiconductor layer 140 that is in contact with the metal oxide layer 130 is referred to as the lower surface 142. In this embodiment, the metal oxide layer 130 and the oxide semiconductor layer 140 have the same pattern shape. That is, in a cross-sectional view, the end of the metal oxide layer 130 and the end of the oxide semiconductor layer 140 are approximately aligned. In this embodiment, a configuration in which the metal oxide layer 130 is in contact with the insulating layer 120 and the oxide semiconductor layer 140 is in contact with the metal oxide layer 130 is illustrated, but is not limited to this configuration. Another layer may be provided between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0020] 1, the side surface of the metal oxide layer 130 and the side surface of the oxide semiconductor layer 140 are aligned in a substantially straight line, but the present invention is not limited to this configuration. The angle of the side surface of the metal oxide layer 130 with respect to the main surface of the substrate 100 may be different from the angle of the side surface 143 of the oxide semiconductor layer 140. The cross-sectional shape of the side surface of at least one of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

[0021] The gate insulating layer 150 is provided on the oxide semiconductor layer 140. The gate insulating layer 150 is patterned to have the same shape as the gate electrode 160. That is, the gate insulating layer 150 and the gate electrode 160 have the same pattern shape. Therefore, a part of the oxide semiconductor layer 140 (a region not overlapping with the gate electrode 160) is not covered with the gate insulating layer 150. In other words, a part of the oxide semiconductor layer 140 is exposed from the gate insulating layer 150. The gate insulating layer 150 functions as a gate insulating layer for the top gate (gate electrode 160). In addition, the gate insulating layer 150 has a function of releasing oxygen by heat treatment in the manufacturing process.

[0022] The gate electrode 160 faces the oxide semiconductor layer 140 via the gate insulating layer 150. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. Of the main surfaces of the oxide semiconductor layer 140, a surface in contact with the gate insulating layer 150 is referred to as an upper surface 141. A surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The gate electrode 160 functions as a top gate of the semiconductor device 10 and a light shielding film for the oxide semiconductor layer 140.

[0023] The insulating layers 170 and 180 are provided on the gate insulating layer 150 and the gate electrode 160. In this embodiment, the laminated structure formed by the insulating layers 170 and 180 may be called a passivation layer. The insulating layers 170 and 180 insulate the gate electrode 160 from the source-drain electrodes 200. By providing the insulating layers 170 and 180, the parasitic capacitance between the gate electrode 160 and the source-drain electrodes 200 can be reduced.

[0024] In this embodiment, a silicon oxide layer is used as the insulating layer 170, and a silicon nitride layer is used as the insulating layer 180. The material constituting the insulating layers 170 and 180 is not limited to this example, but it is preferable to have at least one insulating layer containing hydrogen, as described later. As shown in FIG. 1, the insulating layer 170 constituting a part of the passivation layer contacts the gate electrode 160, the gate insulating layer 150 (specifically, the side surface of the gate insulating layer 150), and the oxide semiconductor layer 140. The insulating layers 170 and 180 are provided with openings 171 and 173 that reach the oxide semiconductor layer 140.

[0025] The source electrode 201 is provided inside an opening 171 provided in the insulating layers 170 and 180. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside an opening 173 provided in the insulating layers 170 and 180. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0026] The operation of the semiconductor device 10 is mainly controlled by a gate voltage supplied to the gate electrode 160. An auxiliary voltage may be supplied to the conductive layer 105. That is, the conductive layer 105 may function as a gate electrode by supplying an auxiliary voltage. However, this is not the only example, and the conductive layer 105 may be used simply as a light-shielding film. When the conductive layer 105 is used simply as a light-shielding film, the conductive layer 105 may be in a floating state without being supplied with a specific voltage.

[0027] In this embodiment, the semiconductor device 10 is exemplified as a top-gate transistor in which a gate electrode 160 is provided above the oxide semiconductor layer 140, but is not limited to this configuration. For example, the semiconductor device 10 may be a dual-gate transistor in which the conductive layer 105 is used as a gate electrode in addition to the gate electrode 160. When the conductive layer 105 is used as the gate electrode, the insulating layers 110 and 120 function as gate insulating layers. However, the above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0028] As shown in FIG. 2, in a plan view, the pattern shape of the metal oxide layer 130 is the same as the pattern shape of the oxide semiconductor layer 140. With reference to FIGS. 1 and 2, the lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130. In particular, in this embodiment, the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130. In the D1 direction, the width of the conductive layer 105 is larger than the width of the gate electrode 160. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and corresponds to the direction in which carriers move. The length of the channel region CH of the oxide semiconductor layer 140 in the D1 direction is the channel length (L), and the width of the channel region CH in the D2 direction is the channel width (W).

[0029] In the present embodiment, the configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130 is illustrated, but the present invention is not limited to this configuration. For example, a part of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered by the metal oxide layer 130, and the entire or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered by the metal oxide layer 130. That is, the entire or part of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, a part of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered by the metal oxide layer 130, and the other part of the lower surface 142 may be in contact with the metal oxide layer 130.

[0030] 2 illustrates a configuration in which the source-drain electrode 200 does not overlap the conductive layer 105 and the gate electrode 160 in a plan view, but the present invention is not limited to this configuration. For example, the source-drain electrode 200 may overlap at least one of the conductive layer 105 and the gate electrode 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0031] [Materials of each layer of semiconductor device] The substrate 100 can support each layer constituting the semiconductor device 10. For example, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate, can be used as the substrate 100. A rigid substrate having no light-transmitting properties, such as a silicon substrate, can also be used as the substrate. Furthermore, a flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, can also be used as the substrate. In order to improve the heat resistance of the substrate 100, impurities may be introduced into the above-mentioned resin substrate. Note that a substrate in which a silicon oxide film or a silicon nitride film is formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0032] The conductive layer 105 can reflect or absorb external light. As described above, the conductive layer 105 has an area larger than the channel region CH of the oxide semiconductor layer 140, and therefore can block external light incident on the channel region CH. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy or compound thereof can be used as the conductive layer 105. In addition, when conductivity is not required, a resin layer made of black resin or the like can be used instead of the conductive layer 105. The conductive layer 105 may have a single-layer structure or a multilayer structure.

[0033] The insulating layers 110, 120, 170, and 180 serve to prevent diffusion of impurities into the oxide semiconductor layer 140. The insulating layers 110, 120, 170, and 180 may have a single-layer structure or a multilayer structure. For example, silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), aluminum nitride (AlNx), and the like can be used as the insulating layers 110, 120, 170, and 180. Here, silicon oxynitride (SiOxNy) and aluminum oxynitride (AlOxNy) are silicon compounds and aluminum compounds, respectively, containing nitrogen (N) at a ratio (x>y) smaller than that of oxygen (O). Silicon nitride oxide (SiNxOy) and aluminum nitride oxide (AlNxOy) are silicon compounds and aluminum compounds that contain oxygen at a ratio (x>y) smaller than that of nitrogen. In this embodiment, silicon nitride (SiNx) is used for the insulating layers 110 and 180, and silicon oxide (SiOx) is used for the insulating layers 120 and 170.

[0034] Metal oxide containing aluminum as a main component is used as the metal oxide layer 130. For example, the metal oxide layer 130 may be made of aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), aluminum nitride (AlN x ) is used. "A metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer 130 is 1% or more of the entire metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

[0035] In this embodiment, the oxide semiconductor layer 140 has a polycrystalline structure. That is, the oxide semiconductor layer 140 in this embodiment is composed of an oxide semiconductor formed by using a Poly-OS technique. The Poly-OS technique refers to a technique for forming an oxide semiconductor layer having a polycrystalline structure. A metal oxide having semiconductor properties can be used as the oxide semiconductor layer 140. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer 140. The ratio of indium to the entire oxide semiconductor layer 140 is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoids are used as the oxide semiconductor layer 140. An element other than the above may be used as the oxide semiconductor layer 140.

[0036] In the oxide semiconductor layer 140 of this embodiment, the ratio of indium is 50% or more, and therefore oxygen vacancies are easily formed. On the other hand, oxygen vacancies are less likely to form in a crystalline oxide semiconductor than in an amorphous oxide semiconductor. Therefore, the oxide semiconductor layer 140 has the advantage that oxygen vacancies are less likely to form, even though the ratio of indium is 50% or more.

[0037] The gate insulating layer 150 includes an oxide having insulating properties. Specifically, silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), or the like can be used as the gate insulating layer 150. The gate insulating layer 150 preferably has a composition close to a stoichiometric ratio. In addition, the gate insulating layer 150 preferably has few defects. For example, the gate insulating layer 150 may be made of an oxide in which no defects are observed when evaluated by electron spin resonance (ESR).

[0038] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof, can be used for each of the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a multilayer structure.

[0039] (Structure of oxide semiconductor layer) The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region of the oxide semiconductor layer 140 located vertically below the gate electrode 160 and in contact with the gate insulating layer 150. The source region S is a region of the oxide semiconductor layer 140 in contact with the insulating layer 170, and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 140 in contact with the insulating layer 170, and is closer to the drain electrode 203 than the channel region CH. The source region S and the drain region D are formed by reducing the resistance of a part of a pattern made of an oxide semiconductor layer. That is, in the first direction (D1 direction) shown in FIG. 2, the channel region CH, the source region S, and the drain region D are continuous with each other.

[0040] The oxide semiconductor layer 140 in the channel region CH has properties as a semiconductor. The oxide semiconductor layer 140 in the source region S and the drain region D has properties as a conductor. That is, the source region S and the drain region D can be said to be regions having a lower resistance than the channel region CH. In other words, the electrical conductivity of the source region S and the drain region D is higher than the electrical conductivity of the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a multilayer structure.

[0041] As shown in FIG. 1, in the semiconductor device 10 of this embodiment, a part of the source region S and the drain region D overlap with the gate electrode 160. Specifically, an end of the source region S close to the channel region CH and an end of the drain region D close to the channel region CH overlap with the gate electrode 160. In other words, an end of the source region S close to the channel region CH and an end of the drain region D close to the channel region CH are in contact with the gate insulating layer 150, respectively. That is, the source region S and the drain region D are in contact with both the gate insulating layer 150 and the insulating layer 170. Here, the region where the source region S (or the drain region D) and the gate electrode 160 overlap is called an "overlap region OL". As shown in FIG. 1, the width of the overlap region OL in the first direction is represented by ΔL / 2.

[0042] The semiconductor device 10 of this embodiment has a symmetrical structure in the first direction (D1 direction), and both the source region S and the drain region D extend below the gate wiring 160. Therefore, the end of the channel region CH in the first direction does not coincide with the end of the gate electrode 160. Specifically, the end of the channel region CH in contact with the source region S and the end of the channel region CH in contact with the drain region D are located directly below the gate electrode 160. That is, in the first direction, the width of the channel region CH is narrower than the width of the gate electrode 160. This means that the designed channel length (hereinafter referred to as the "designed channel length") is narrower than the designed value by the amount of the overlapping region OL.

[0043] Generally, the design channel length in a top-gate transistor is determined by the width of the gate electrode overlapping the semiconductor layer. That is, in the case of the semiconductor device 10 of this embodiment, the width of the gate electrode 160 in the first direction corresponds to the design channel length. However, as shown in FIG. 1, the width of the channel region CH is narrower than the width of the gate electrode 160. That is, the effective channel length (hereinafter referred to as the "effective channel length") corresponding to the width of the channel region CH is shorter than the design channel length corresponding to the width of the gate electrode 160. Specifically, the design channel length (Lg) and the effective channel length (L eff ) between the L eff =Lg-ΔL.

[0044] In this embodiment, the source region S and the drain region D are formed by utilizing the diffusion of hydrogen from the insulating layers 170 and 180 to the oxide semiconductor layer 140. In this case, due to the structure, hydrogen also diffuses into the oxide semiconductor layer 140 directly below the gate electrode 160, so that the overlap region OL is formed. The overlap region OL is a region formed by hydrogen penetrating into the oxide semiconductor layer 140 located directly below the gate electrode 160. However, in this embodiment, the amount of hydrogen diffusing directly below the gate electrode 160 can be reduced to suppress the range in which the overlap region OL is formed. Specifically, in the semiconductor device 10 of this embodiment, the width (ΔL / 2) of the overlap region OL is controlled to be 1 μm or less.

[0045] The width of the overlap region OL being 1 μm or less means that, for example, even if the design channel length is 4 μm, an effective channel length of at least 2 μm can be ensured. According to this embodiment, the design channel length (the width of the gate electrode in the first direction) of the semiconductor device 10 can be set to 4 μm or less (preferably 3 μm or less). However, in order to ensure an effective channel length of at least 1 μm or more, it is preferable that the design channel length of the semiconductor device 10 is 1 μm or more greater than twice the width of the overlap region OL (2×ΔL / 2=ΔL).

[0046] As described above, in the semiconductor device 10 of this embodiment, the gate insulating layer 150 has the same pattern shape as the gate electrode 160, and therefore a part of the oxide semiconductor layer 140 is in contact with the insulating layer 170. Therefore, in the semiconductor device 10, due to the influence of hydrogen diffused from the insulating layers 170 and 180, a part of the source region S and the drain region D extends below the gate electrode 160. However, according to this embodiment, the width of the overlap region OL where the source region S and the drain region D overlap with the gate electrode 160 can be suppressed to 1 μm or less, and therefore the deviation between the designed channel length and the effective channel length can be suppressed.

[0047] [Method of manufacturing semiconductor device] A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 3 to Fig. 12. Fig. 3 is a sequence diagram showing the method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Fig. 4 to Fig. 12 are cross-sectional views showing the method for manufacturing the semiconductor device 10 according to one embodiment of the present invention.

[0048] As shown in Figures 3 and 4, a conductive layer 105 is formed on a substrate 100 as a light-shielding layer, and insulating layers 110 and 120 are formed on the conductive layer 105 (step S1001 in Figure 3). For example, silicon nitride is formed as the insulating layer 110. For example, silicon oxide is formed as the insulating layer 120. The insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method. In this specification, forming a film on a substrate by a method such as a sputtering method or a CVD method is expressed as "forming a thin film", but is used in the same sense as the expression "forming a thin film".

[0049] By using silicon nitride as the insulating layer 110, the insulating layer 110 can block impurities diffusing, for example, from the substrate 100 side toward the oxide semiconductor layer 140. The silicon oxide used as the insulating layer 120 is silicon oxide having the physical property of releasing oxygen by heat treatment.

[0050] In this embodiment, the film formation temperature is set to 350° C. when forming the insulating layers 110 and 120. In particular, the amount of oxygen contained in the insulating layer 120 (i.e., the silicon oxide layer) can be increased by setting the film formation temperature relatively low. As will be described later, the amount of hydrogen diffusing into the oxide semiconductor layer 140 can be reduced by increasing the amount of oxygen contained in the insulating layer 120. The film formation temperature for the insulating layers 110 and 120 may be set to 250° C. or higher and 500° C. or lower (preferably 300° C. or higher and 450° C. or lower, and more preferably 325° C. or higher and 400° C. or lower).

[0051] 3 and 5, the metal oxide layer 130 and the oxide semiconductor layer 140 are formed on the insulating layer 120 (step S1002 in FIG. 3). In this embodiment, the metal oxide layer 130 and the oxide semiconductor layer 140 are formed by a sputtering method. In particular, the oxide semiconductor layer 140 is formed by sputtering using a target formed of a crystalline oxide semiconductor.

[0052] The thickness of the metal oxide layer 130 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, the thickness of the metal oxide layer 130 is 3 nm. In this embodiment, an oxide containing aluminum as a main component (specifically, aluminum oxide) is used as the metal oxide layer 130. Aluminum oxide has high barrier properties against gases.

[0053] In this embodiment, the aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the insulating layer 120 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.

[0054] Since the oxide semiconductor layer 140 of the present embodiment has an indium ratio of 50% or more as described above, the semiconductor device 10 with high mobility can be realized, but oxygen is easily reduced and oxygen vacancies are easily formed in the layer. Therefore, blocking hydrogen released from the insulating layer 120 by the metal oxide layer 130 is preferable in terms of suppressing the reduction of the oxide semiconductor layer 140.

[0055] In addition, after the oxide semiconductor layer 140 is formed, in the process of going through various manufacturing processes (patterning process or etching process), more oxygen vacancies are formed on the upper layer side of the oxide semiconductor layer 140 than on the lower layer side. That is, the oxygen vacancies in the oxide semiconductor layer 140 are distributed unevenly in the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen vacancies formed on the upper layer side of the oxide semiconductor layer 140, excessive oxygen is supplied to the lower layer side of the oxide semiconductor layer 140. As a result, the excessive supply of oxygen forms a defect level different from the oxygen vacancies, which may lead to phenomena such as characteristic fluctuations in reliability tests or a decrease in field effect mobility. Therefore, it can be said that blocking oxygen released from the insulating layer 120 by the metal oxide layer 130 is also preferable in terms of suppressing the excessive supply of oxygen to the lower layer side of the oxide semiconductor layer 140.

[0056] The oxide semiconductor layer 140 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 15 nm to 40 nm. The oxide semiconductor layer 140 is amorphous before a heat treatment (OS annealing) described later.

[0057] When the oxide semiconductor layer 140 is crystallized by OS annealing, which will be described later, the oxide semiconductor layer 140 is preferably amorphous (a state in which the oxide semiconductor has few crystalline components) after being formed by a sputtering method and before performing OS annealing. In other words, the formation conditions of the oxide semiconductor layer 140 are preferably such that the oxide semiconductor layer 140 immediately after being formed is not crystallized as much as possible. For example, when the oxide semiconductor layer 140 is formed by a sputtering method, it is desirable to form the oxide semiconductor layer 140 while controlling the temperature of the object to be formed (including the substrate 100 and the structure formed thereon). Note that, although the object to be formed is actually the object to be temperature-controlled, the structure formed on the substrate 100 is very thin, and therefore it may be considered that the temperature of the substrate 100 is substantially controlled. Therefore, in the following description, the object to be formed may be simply called a "substrate".

[0058] When a thin film is formed on a substrate by sputtering, ions generated in plasma and atoms recoiled from the sputtering target collide with an object to be formed (specifically, a structure formed on the substrate 100), causing the temperature of the substrate to rise during the thin film formation process. If the temperature of the substrate rises during the thin film formation process, the oxide semiconductor layer 140 contains microcrystals immediately after formation, which inhibits crystallization by subsequent OS annealing.

[0059] In order to control the temperature of the substrate (i.e., the film formation temperature) when the oxide semiconductor layer 140 is formed, for example, the thin film may be formed while cooling the substrate. For example, the substrate can be cooled from the surface opposite to the surface to be formed so that the film formation temperature becomes 100° C. or less, 70° C. or less, 50° C. or less, or 30° C. or less. In particular, the film formation temperature of the oxide semiconductor layer 140 in this embodiment is preferably 50° C. or less. In this embodiment, the oxide semiconductor layer 140 is formed at a film formation temperature of 50° C. or less, and the OS annealing described later is performed at a heating temperature of 400° C. or more. Thus, in this embodiment, the difference between the temperature when the oxide semiconductor layer 140 is formed and the temperature when the OS annealing is performed on the oxide semiconductor layer 140 is preferably 350° C. or more. By forming the oxide semiconductor layer 140 while cooling the substrate, the oxide semiconductor layer 140 having a small amount of crystalline components immediately after the formation can be obtained.

[0060] Next, as shown in FIGS. 3 and 6, a pattern (OS pattern) composed of the oxide semiconductor layer 140 is formed (step S1003 in FIG. 3). Although not shown, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask patterned by photolithography. The oxide semiconductor layer 140 may be etched by wet etching or dry etching. In the wet etching, for example, an acidic etchant may be used. Specifically, oxalic acid or hydrofluoric acid may be used as the etchant.

[0061] After the oxide semiconductor layer 140 is patterned, the oxide semiconductor layer 140 is subjected to a heat treatment (OS annealing) (step S1004 in FIG. 3). In the OS annealing, the oxide semiconductor layer 140 is subjected to a heat treatment in an air atmosphere at a temperature of 250° C. to 500° C. (preferably 300° C. to 500° C., more preferably 350° C. to 450° C.), thereby crystallizing the amorphous oxide semiconductor layer 140. The heating atmosphere is not limited to the air atmosphere, but is preferably an oxidizing atmosphere (an atmosphere containing oxygen). In addition, the oxidizing atmosphere is more preferably a moist atmosphere (specifically, a moist air atmosphere). In addition, the processing time of the heat treatment is 15 minutes to 120 minutes, or 30 minutes to 60 minutes, after the predetermined temperature is reached. In this embodiment, the temperature of the OS annealing is set to 350° C.

[0062] In this embodiment, the substrate on which the patterned oxide semiconductor layer 140 is formed is placed in a heating furnace having a heating medium (e.g., a support plate) maintained at a preset temperature (250° C. or more and 500° C. or less, 350° C. in this embodiment). The support plate as a heating medium has a role of supporting the substrate and a role of heating the substrate and the coating (including the oxide semiconductor layer 140) formed on the substrate. When the substrate on which the oxide semiconductor layer 140 is formed is placed on the support plate, the oxide semiconductor layer 140 is rapidly heated. When the substrate is placed in the heating furnace, it is desirable to suppress the temperature drop of the support plate to within 15%, 10%, or 5% of the set temperature. In other words, it is desirable to control the temperature of the support plate so that the oxide semiconductor layer 140 reaches the set temperature in as short a time as possible.

[0063] Note that, although the example in which OS annealing is performed after the OS pattern is formed has been described in this embodiment, the present invention is not limited to this example, and OS annealing may be performed on the oxide semiconductor layer 140 before the OS pattern is formed. In this case, since the OS pattern is formed by etching the crystallized oxide semiconductor layer 140, it is preferable to use dry etching for the etching process.

[0064] Next, as shown in FIG. 3 and FIG. 7, a pattern (AlOx pattern) composed of the metal oxide layer 130 is formed (step S1005 in FIG. 3). The crystallized oxide semiconductor layer 140 has etching resistance to hydrofluoric acid. Therefore, the metal oxide layer 130 of this embodiment is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. The etching of the metal oxide layer 130 may be performed by wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used in the wet etching. By etching the metal oxide layer 130 using the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted. In addition, since the metal oxide layer 130 is etched using the oxide semiconductor layer 140 as a mask, the metal oxide layer 130 and the oxide semiconductor layer 140 have the same pattern shape.

[0065] In this embodiment, the OS pattern is formed, and then the AlOx pattern is formed using the OS pattern as a mask, but the OS pattern and the AlOx pattern can be formed at the same time. In this case, the oxide semiconductor layer 140 and the metal oxide layer 130 may be etched at the same time using the same resist mask in step S1003 of FIG.

[0066] Next, as shown in FIG. 3 and FIG. 8, the gate insulating layer 150 is formed (step S1006 in FIG. 3). For example, a silicon oxide layer is formed as the gate insulating layer 150. The gate insulating layer 150 is formed by a CVD method. It is desirable to form an insulating layer with as few defects as possible as the gate insulating layer 150. In this embodiment, the deposition temperature of the gate insulating layer 150 is 350° C. The thickness of the gate insulating layer 150 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0067] Next, in this embodiment, after the gate insulating layer 150 is formed, the metal oxide layer 190 is formed on the gate insulating layer 150 (step S1007 in FIG. 3). The metal oxide layer 190 is formed by a sputtering method. By using the sputtering method to form the metal oxide layer 190, oxygen is implanted into the gate insulating layer 150 when the metal oxide layer 190 is formed. Therefore, the gate insulating layer 150 after the metal oxide layer 190 is formed contains a large amount of oxygen.

[0068] The thickness of the metal oxide layer 190 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 190. As described above, aluminum oxide has high barrier properties against gas, and therefore can suppress the upward diffusion of oxygen implanted into the gate insulating layer 150 during the heat treatment described below.

[0069] When the metal oxide layer 190 is formed by a sputtering method, the process gas used in the sputtering remains in the film of the metal oxide layer 190. For example, when Ar is used as the process gas for the sputtering, Ar may remain in the film of the metal oxide layer 190. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 190 or the like.

[0070] Next, in a state where the metal oxide layer 190 is formed on the gate insulating layer 150, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 (step S1008 in FIG. 3). In other words, a heat treatment (oxidation annealing) is performed on the patterned metal oxide layer 130 and the oxide semiconductor layer 140. In a process between the formation of the oxide semiconductor layer 140 and the formation of the gate insulating layer 150 on the oxide semiconductor layer 140, oxygen vacancies may occur on the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. By the oxidation annealing, oxygen released from the insulating layer 120 and the gate insulating layer 150 is supplied to the oxide semiconductor layer 140, and the oxygen vacancies are repaired. The oxidation annealing may be performed at a temperature of 250° C. or higher and 500° C. or lower (preferably 300° C. or higher and 500° C. or lower, more preferably 350° C. or higher and 450° C. or lower). In this embodiment, the oxidation annealing is performed at a temperature of 350° C.

[0071] Oxygen released from the insulating layer 120 by the oxidation annealing is blocked by the metal oxide layer 130, so that oxygen is not easily supplied to the lower surface 142 of the oxide semiconductor layer 140. Oxygen released from the insulating layer 120 diffuses from an area where the metal oxide layer 130 is not formed to the gate insulating layer 150, and reaches the oxide semiconductor layer 140 via the gate insulating layer 150. As a result, oxygen released from the insulating layer 120 is not easily supplied to the lower surface 142 of the oxide semiconductor layer 140, and is mainly supplied to the side surface 143 and the upper surface 141 of the oxide semiconductor layer 140. Furthermore, oxygen released from the gate insulating layer 150 is supplied to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 by the oxidation annealing. Hydrogen may be released from the insulating layer 110 by the above oxidation annealing. However, the hydrogen is captured by oxygen contained in the insulating layer 120 or blocked by the metal oxide layer 130 before reaching the oxide semiconductor layer 140.

[0072] As described above, the oxidation annealing can supply oxygen to the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140, which have a relatively large amount of oxygen vacancies, while suppressing the supply of oxygen to the lower surface 142 of the oxide semiconductor layer 140, which has a small amount of oxygen vacancies. Similarly, during the oxidation annealing, the upward diffusion of oxygen implanted into the gate insulating layer 150 is blocked by the metal oxide layer 190, and thus the oxygen is prevented from being released into the atmosphere. Therefore, during the oxidation annealing, oxygen can be efficiently supplied to the oxide semiconductor layer 140.

[0073] 3 and 9, after the oxidation annealing, the metal oxide layer 190 is etched and removed (step S1009 in FIG. 3). The etching of the metal oxide layer 190 may be wet etching or dry etching. In the wet etching, for example, diluted hydrofluoric acid (DHF) is used. The entire metal oxide layer 190 is removed by the etching process in step S1009.

[0074] Next, as shown in FIG. 3 and FIG. 10, a gate electrode 160 is formed on the gate insulating layer 150, and then the gate insulating layer 150 is etched (step S1010 in FIG. 3). The gate electrode 160 is formed by patterning a metal layer formed by a sputtering method or an atomic layer deposition method, and then performing dry etching. The gate insulating layer 150 is etched by further continuing dry etching after the gate electrode 160 is formed. That is, the gate insulating layer 150 is etched using the gate electrode 160 as a mask. Thus, in this embodiment, the metal layer and the gate insulating layer 150 are etched together to form the patterned gate insulating layer 150 and gate electrode 160.

[0075] In this embodiment, the gate insulating layer 150 is etched using the gate electrode 160 as a mask, thereby exposing a part of the oxide semiconductor layer 140 (regions that become a source region S and a drain region D described later). In addition, since the etching process is performed using the gate electrode 160 as a mask, the gate insulating layer 150 and the gate electrode 160 have the same pattern shape.

[0076] 10, when the gate insulating layer 150 is etched until the oxide semiconductor layer 140 is exposed, not only the upper surface 141 of the oxide semiconductor layer 140 but also the side surface 143 of the oxide semiconductor layer 140 are exposed. Furthermore, the side surface of the metal oxide layer 130 and the upper surface of the insulating layer 120 are also exposed. At this time, since the insulating layer 120 is composed of a silicon oxide layer like the gate insulating layer 150, it is desirable to not excessively prolong the etching time and to promptly stop the etching process when the upper surface of the oxide semiconductor layer 140 is exposed.

[0077] If the etching time is excessively long, the insulating layer 120 is etched deeply, and there is a risk of a large step being generated between the end of the metal oxide layer 130 and the upper surface of the insulating layer 120. Such a step may adversely affect the electrical characteristics of the semiconductor device 10 (for example, an increase in leakage current, etc.). Conversely, if the etching time is insufficient, the gate insulating layer 150 remains on the oxide semiconductor layer 140, and may adversely affect the electrical characteristics of the semiconductor device 10 (for example, a shift in the threshold voltage in the negative direction, etc.). Therefore, in this embodiment, a slight overetching is performed (for example, the above-mentioned etching time is extended by 10%) with respect to the etching time required until the upper surface of the oxide semiconductor layer 140 is exposed, thereby preventing deterioration of the electrical characteristics.

[0078] Next, as shown in FIG. 3 and FIG. 11, insulating layers 170 and 180 are formed as passivation layers on the gate insulating layer 150 and the gate electrode 160 (step S1011 in FIG. 3). The insulating layers 170 and 180 are formed by a CVD method. In this embodiment, a silicon oxide layer is formed as the insulating layer 170, and a silicon nitride layer is formed as the insulating layer 180. The film formation temperature of the insulating layers 170 and 180 is preferably set to 250° C. or more and 500° C. or less (preferably 300° C. or more and 450° C. or less, more preferably 325° C. or more and 400° C. or less). In this embodiment, the film formation temperature of the insulating layers 170 and 180 is set to 350° C. In addition, the thickness of the insulating layers 170 and 180 may be set to 50 nm or more and 500 nm or less. In this embodiment, the thickness of the insulating layer 170 is set to 100 nm, and the thickness of the insulating layer 180 is set to 300 nm.

[0079] The insulating layers 170 and 180 function as passivation layers (protective layers) to prevent the intrusion of gas and moisture from the outside. As described above, they also serve to insulate and separate the gate electrode 160 from the source / drain electrodes 200. Furthermore, in this embodiment, the insulating layers 170 and 180 (particularly the insulating layer 180) are formed, thereby forming a source region S and a drain region D in the oxide semiconductor layer 140.

[0080] The insulating layer 180 of this embodiment is made of silicon nitride. When the insulating layer 180 is formed by the CVD method, ammonia is used as a raw material gas, so that the insulating layer 180 contains a large amount of hydrogen. Therefore, when the insulating layer 180 is formed and after the insulating layer 180 is formed, the insulating layer 180 is heated, so that hydrogen diffuses from the insulating layer 180. The diffused hydrogen reaches the oxide semiconductor layer 140 through the insulating layer 170. At this time, oxygen contained in the region of the oxide semiconductor layer 140 that contacts the insulating layer 170 is reduced, and oxygen vacancies are formed. Hydrogen is trapped in the formed oxygen vacancies, and a donor level is formed. As a result, the part of the oxide semiconductor layer 140 to which hydrogen is supplied is made to have a low resistance and functions as a source region S and a drain region D. In contrast, the oxide semiconductor layer 140 located directly under the gate electrode 160 is not made to have a low resistance because hydrogen does not reach it, and functions as a channel region CH.

[0081] In the semiconductor device 10 of this embodiment, the gate insulating layer 150 has the same pattern shape as the gate electrode 160, so that the oxide semiconductor layer 140 exposed from the gate insulating layer 150 is in direct contact with the insulating layer 170. Therefore, compared with a structure in which the oxide semiconductor layer 140 is covered with the gate insulating layer 150, this structure allows hydrogen to easily diffuse below the gate electrode 160. Therefore, as shown in FIG. 11, the hydrogen diffused below the gate electrode 160 also reduces the resistance of the region that should be the channel region CH. That is, the source region S and the drain region D are extended toward the channel region CH, and an overlap region OL is formed.

[0082] As described above, in this embodiment, the width (ΔL) of the overlap region OL in the first direction (channel length direction) can be suppressed to 1 μm or less. By suppressing the width of the overlap region OL to 1 μm or less, the deviation between the design channel length and the effective channel length can be suppressed. As a result, the semiconductor device 10 of this embodiment can obtain stable electrical characteristics even if the channel length is 4 μm or less.

[0083] The width (ΔL) of the overlap region OL can be suppressed to 1 μm or less because the insulating layer 120 (in this embodiment, a silicon oxide layer) provided below the oxide semiconductor layer 140 contains a large amount of oxygen.

[0084] In a plan view, the insulating layer 120 containing a large amount of oxygen and the insulating layer 170 are in direct contact with each other around the oxide semiconductor layer 140. Therefore, most of the hydrogen diffused from the insulating layers 170 and 180 is captured by the insulating layer 120, and the amount of hydrogen diffusing toward the oxide semiconductor layer 140 is suppressed. At this time, since the source region S and the drain region D of the oxide semiconductor layer 140 are in direct contact with the insulating layer 170, the resistance is sufficiently reduced even if the amount of hydrogen diffused is small, but the amount of hydrogen diffusing toward the lower side of the gate electrode 160 is reduced. As a result, in this embodiment, it is considered that the width of the overlap region OL (i.e., the diffusion length of hydrogen) is shortened.

[0085] In order to increase the amount of oxygen contained in the insulating layer 120, for example, it is preferable to set the deposition temperature of the insulating layer 120 relatively low. In this embodiment, it is set to 350° C., but it may be within the range of 250° C. to 500° C. (preferably 300° C. to 450° C., and more preferably 325° C. to 400° C.).

[0086] Furthermore, this embodiment includes a process of forming the metal oxide layer 130 on the insulating layer 120, and this process also contributes to increasing the amount of oxygen contained in the insulating layer 120. Specifically, when aluminum oxide is formed by sputtering as the metal oxide layer 130, oxygen is implanted into the insulating layer 120. As a result, more oxygen is implanted into the insulating layer 120, which already contains a large amount of oxygen at the above-mentioned film formation temperature, so that the total amount of oxygen in the insulating layer 120 can be increased.

[0087] As described above, in the semiconductor device 10 of the present embodiment, the gate insulating layer 150 is processed into the same pattern shape as the gate electrode 160, so that the oxide semiconductor layer 140 and the insulating layer 170 are in direct contact with each other. This allows the source region S and the drain region D to be formed by reducing the resistance of a part of the oxide semiconductor layer 140 using hydrogen diffusing from the insulating layers 170 and 180. In addition, since the insulating layer 120 underlying the oxide semiconductor layer 140 contains a large amount of oxygen, the amount of hydrogen used to reduce the resistance of the oxide semiconductor layer 140 can be reduced. As a result, the diffusion of hydrogen directly below the gate electrode 160 can be suppressed, and the width of the overlap region OL can be shortened.

[0088] 3 and 12, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 (Step S1012 in FIG. 3). The opening 171 exposes the oxide semiconductor layer 140 in the source region S. The opening 173 exposes the oxide semiconductor layer 140 in the drain region D. By forming source-drain electrodes 200 on the oxide semiconductor layer 140 exposed by the openings 171 and 173 and on the insulating layer 180 (Step S1013 in FIG. 3), the semiconductor device 10 shown in FIG. 1 is completed.

[0089] In the semiconductor device 10 manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region CH is in the range of 2 μm to 4 μm and the channel width of the channel region CH is in the range of 2 μm to 25 μm, the field effect mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 In this embodiment, the "field effect mobility" refers to the field effect mobility in the saturation region of the semiconductor device 10, and means the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the voltage (Vg) supplied to the gate electrode minus the threshold voltage (Vth) of the semiconductor device 10 (Vg-Vth).

[0090] Second Embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the first embodiment will be described. The structure of the semiconductor device 10 of this embodiment is identical in appearance to the semiconductor device 10 described in the first embodiment. In this embodiment, the differences from the first embodiment will be described.

[0091] Fig. 13 is a sequence diagram showing a method for manufacturing the semiconductor device 10 in one embodiment of the present invention. As shown in Fig. 13, in this embodiment, two steps, namely, step S1007 (AlOx formation) and step S1009 (AlOx removal) shown in Fig. 3 are omitted. That is, in this embodiment, after the gate insulating layer 150 is formed, oxidation annealing is performed in this state. By this oxidation annealing, oxygen released from the gate insulating layer 150 is supplied to the oxide semiconductor layer 140, and oxygen vacancies contained in the oxide semiconductor layer 140 are repaired. The role of the metal oxide layer 130 in this case is the same as in the first embodiment, and therefore a description thereof will be omitted here.

[0092] In the semiconductor device 10 manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region CH is in the range of 2 μm to 4 μm and the channel width W of the channel region CH is in the range of 2 μm to 25 μm, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 In this embodiment, the field-effect mobility is defined in the same manner as in the first embodiment.

[0093] Third embodiment A display device using the semiconductor device of one embodiment of the present invention will be described with reference to Figures 14 to 18. In the following embodiment, a configuration in which the semiconductor devices described in the first and second embodiments are applied to a circuit of a liquid crystal display device will be described.

[0094] [Display device overview] Fig. 14 is a plan view showing an overview of a display device 20 according to an embodiment of the present invention. As shown in Fig. 14, the display device 20 has an array substrate 300, a seal portion 310, a counter substrate 320, a flexible printed circuit board 330 (FPC 330), and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the seal portion 310. In a liquid crystal region 22 surrounded by the seal portion 310, a plurality of pixel circuits 301 are arranged in a matrix. The liquid crystal region 22 is an area that overlaps with a liquid crystal element 311, which will be described later, in a plan view.

[0095] The seal area 24 in which the seal portion 310 is provided is the area surrounding the liquid crystal area 22. The FPC 330 is provided in the terminal area 26. The terminal area 26 is an area of ​​the array substrate 300 exposed from the counter substrate 320, and is provided outside the seal area 24. The outside of the seal area 24 means the outside of the area in which the seal portion 310 is provided and the area surrounded by the seal portion 310. The IC chip 340 is provided on the FPC 330. The IC chip 340 supplies signals for driving each pixel circuit 301.

[0096] [Circuit configuration of display device] Fig. 15 is a block diagram showing a circuit configuration of a display device 20 according to an embodiment of the present invention. As shown in Fig. 15, a source driver circuit 302 is provided at a position adjacent in the Y direction (column direction) to the liquid crystal region 22 in which the pixel circuits 301 are arranged. Also, a gate driver circuit 303 is provided at a position adjacent in the X direction (row direction) to the liquid crystal region 22. The source driver circuit 302 and the gate driver circuit 303 are provided in the above-mentioned sealing region 24. However, the region in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the sealing region 24, and may be any region outside the region in which the pixel circuits 301 are provided.

[0097] A source line 304 extends from the source driver circuit 302 in the Y direction and is connected to a plurality of pixel circuits 301 arranged in the Y direction. A gate line 305 extends from the gate driver circuit 303 in the X direction and is connected to a plurality of pixel circuits 301 arranged in the X direction.

[0098] A terminal section 306 is provided in the terminal region 26. The terminal section 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal section 306 and the gate driver circuit 303 are connected by a connection wiring 308. The FPC 330 is connected to the terminal section 306, thereby connecting an external device to the display device 20 via the FPC 330. Each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device input via the FPC 330.

[0099] The semiconductor device 10 shown in the first and second embodiments is used as a transistor included in a pixel circuit 301, a source driver circuit 302, and a gate driver circuit 303.

[0100] [Pixel circuit of display device] 16 is a circuit diagram showing a pixel circuit 301 of a display device 20 according to one embodiment of the present invention. As shown in FIG. 16, the pixel circuit 301 includes elements such as a semiconductor device 10, a storage capacitor 350, and a liquid crystal element 311.

[0101] The semiconductor device 10 has a gate electrode 160, a source electrode 201, and a drain electrode 203. The gate electrode 160 is connected to a gate wiring 305. The source electrode 201 is connected to a source wiring 304. The drain electrode 203 is connected to a storage capacitor 350 and a liquid crystal element 311. The roles of the source electrode 201 and the drain electrode 203 may be interchanged depending on the relationship between the voltage supplied to the source wiring 304 and the voltage stored in the storage capacitor 350. That is, the source electrode 201 may function as a drain electrode, and the drain electrode 203 may function as a source electrode.

[0102] [Cross-sectional structure of display device] Fig. 17 is a cross-sectional view showing an overview of a display device 20 in one embodiment of the present invention. As shown in Fig. 17, the display device 20 is a display device using a semiconductor device 10. In this embodiment, a configuration in which the semiconductor device 10 is used in a pixel circuit 301 is illustrated, but the semiconductor device 10 may also be used in a peripheral circuit including a source driver circuit 302 and a gate driver circuit 303. In the following description, the configuration of the semiconductor device 10 is similar to that of the semiconductor device 10 shown in Fig. 1, and therefore a detailed description thereof will be omitted.

[0103] An insulating layer 360 is provided on the source electrode 201 and the drain electrode 203. A common electrode 370 that is provided in common to a plurality of pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. An opening 381 is provided in the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and inside the opening 381. The pixel electrode 390 is connected to the drain electrode 203.

[0104] Fig. 18 is a plan view of a pixel electrode 390 and a common electrode 370 of a display device 20 according to an embodiment of the present invention. As shown in Fig. 18, the common electrode 370 is composed of a flat conductive layer. The pixel electrode 390 is composed of a comb-shaped conductive layer that combines a portion extending in the X direction and a portion extending in the Y direction. The portion extending in the Y direction is composed of a plurality of linear electrodes, each of which is connected to a portion extending in the X direction.

[0105] The common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 in a plan view, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a horizontal electric field is formed from the pixel electrode 390 in the overlapping region to the common electrode 370 in the non-overlapping region. This horizontal electric field causes the liquid crystal molecules contained in the liquid crystal element 311 to operate, thereby determining the grayscale of the pixel.

[0106] Fourth embodiment A display device using a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 19 and 20. In the following embodiment, a configuration in which each of the semiconductor devices described in the first and second embodiments is applied to a circuit of an organic EL display device will be described. The outline and circuit configuration of the display device 20a are similar to those shown in Figures 14 and 15, and therefore will not be described here.

[0107] [Pixel circuit of display device] Fig. 19 is a circuit diagram showing a pixel circuit 301a of a display device 20a according to one embodiment of the present invention. As shown in Fig. 19, the pixel circuit 301a includes elements such as a drive transistor 11, a selection transistor 12, a storage capacitor 210, and a light-emitting element DO.

[0108] The driving transistor 11 and the selection transistor 12 have the same configuration as the semiconductor device 10. The source electrode of the selection transistor 12 is connected to a signal line 211, and the gate electrode of the selection transistor 12 is connected to a gate line 212. The source electrode of the driving transistor 11 is connected to an anode power line 213, and the drain electrode of the driving transistor 11 is connected to one end of the light-emitting element DO. The other end of the light-emitting element DO is connected to a cathode power line 214. The gate electrode of the driving transistor 11 is connected to the drain electrode of the selection transistor 12. The storage capacitor 210 is connected to the gate electrode and drain electrode of the driving transistor 11. A grayscale signal that determines the light emission intensity of the light-emitting element DO is supplied to the signal line 211. A signal that selects a pixel row to which the above grayscale signal is written is supplied to the gate line 212.

[0109] [Cross-sectional structure of display device] Fig. 20 is a cross-sectional view showing an overview of a display device 20a according to one embodiment of the present invention. The configuration of the display device 20a shown in Fig. 20 is similar to that of the display device 20 shown in Fig. 17, but the display device 20 and the display device 20a differ in structure above the insulating layer 360. Hereinafter, a description of the configuration of the display device 20a shown in Fig. 20 that is similar to that of the display device 20 shown in Fig. 17 will be omitted, and only the differences between the two will be described.

[0110] As shown in FIG. 20, the display device 20a has a pixel electrode 390, a light-emitting layer 392, and a common electrode 394 above an insulating layer 360. The light-emitting element DO is composed of the pixel electrode 390, the light-emitting layer 392, and the common electrode 394. The pixel electrode 390 is provided on the insulating layer 360 and inside the opening 381. Here, the insulating layer 362 is called a bank, a rib, or the like, and plays a role of defining a light-emitting region. The insulating layer 362 is provided on the pixel electrode 390. The insulating layer 362 is provided with an opening 363. The opening 363 corresponds to the light-emitting region. The light-emitting layer 392 and the common electrode 394 are provided on the pixel electrode 390 exposed by the opening 363. The pixel electrode 390 and the light-emitting layer 392 are provided individually for each pixel. On the other hand, the common electrode 394 is provided in common to a plurality of pixels. The light-emitting layer 392 is made of different materials depending on the display color of the pixel.

[0111] In the third and fourth embodiments, the semiconductor devices described in the first and second embodiments are respectively applied to a liquid crystal display device and an organic EL display device. However, the semiconductor devices described in the first and second embodiments may be applied to display devices other than these display devices (for example, a self-luminous display device other than an organic EL display device or an electronic paper display device). In addition, the semiconductor devices can be applied to a variety of display devices, from small and medium-sized display devices to large display devices, without any particular limitations.

[0112] Example [Electrical characteristics of semiconductor device] Fig. 21A is a diagram showing electrical characteristics of the semiconductor device 10 according to one embodiment of the present invention. Fig. 21B is a diagram showing electrical characteristics of a semiconductor device according to a comparative example. Specifically, Fig. 21B corresponds to the electrical characteristics of a semiconductor device having a structure in which the metal oxide layer 130 is omitted from the semiconductor device 10 shown in Fig. 1. Figs. 21A and 21B each show a number of electrical characteristics obtained by measuring a number of semiconductor devices.

[0113] The measurement conditions for the electrical characteristics shown in FIGS. 21A and 21B are as follows. Channel region CH size: W / L=4.5μm / 3.0μm Source-drain voltage: 0.1V, 10V Gate voltage: -15V~+15V Measurement environment: Room temperature, dark room

[0114] In Figures 21A and 21B, the Id-Vg characteristics and the field effect mobility (μsat) in the saturation region are shown as the electrical characteristics of the semiconductor device. As indicated by the arrows in the graphs of Figures 21A and 21B, the vertical axis showing the drain current (Id) is shown on the left side of the graph. Also, the vertical axis showing the field effect mobility calculated from the drain current is shown on the right side of the graph. The horizontal axis is the gate voltage supplied to each semiconductor device.

[0115] As shown in FIG. 21A, the Id-Vg characteristics of the semiconductor device 10 of the first embodiment show so-called normally-off characteristics in which the drain current Id starts to flow when the gate voltage Vg is approximately 0 V. The drain current has little variation whether the source-drain voltage is 0.1 V or 10 V, and is very stable. The average value of the threshold voltage (Vth) obtained from multiple Id-Vg characteristics was 0.30 V. The average value of the intrinsic mobility obtained from multiple Id-Vg characteristics was 23.7 cm 2 / Vs, and the average field-effect mobility is 37.6 cm 2 / Vs.

[0116] In contrast, as shown in FIG. 21B, the Id-Vg characteristics of the semiconductor device of the comparative example showed that the threshold voltage was shifted in the negative direction, and the drain current Id began to flow when the gate voltage Vg was 0 V or less, indicating a so-called normally-on characteristic. The average value of the threshold voltage obtained from the multiple Id-Vg characteristics was -3.59 V. The drain current showed a high value on average, although there was some variation, and no major problems were observed with the switching characteristics. The average value of the intrinsic mobility obtained from the multiple Id-Vg characteristics was 19.5 cm 2 / Vs, and the average field-effect mobility is 30.8 cm 2 / Vs.

[0117] Here, the average width (ΔL / 2) of the overlap region OL in the semiconductor device 10 of the first embodiment was 0.82 μm, and the average width of the overlap region OL in the semiconductor device of the comparative example was 1.50 μm. In other words, it was found that the presence or absence of the metal oxide layer 130 shown in FIG. 1 caused a difference in the width of the overlap region OL of nearly two times. In other words, it was found that providing the metal oxide layer 130 was very effective in reducing the width of the overlap region OL.

[0118] In the comparative example, the design channel length is 3.0 μm and the width of the overlap region OL is 1.5 μm, so that the channel region CH does not appear to exist in terms of calculation. However, in reality, the design channel length has an error, and the width of the overlap region OL is merely an average value, so that the channel region CH does not actually disappear completely.

[0119] The width of the overlap region OL can be obtained by various methods. In this embodiment, an example is shown in which the width of the overlap region OL is obtained from the relationship between the design channel length and the channel resistance R of the transistor when different gate voltages are applied.

[0120] FIG. 22 is a diagram illustrating the relationship of channel resistance (R) to the design channel length (channel length on layout) (Lg) of a transistor for different gate voltages (Vg). Specifically, in FIG. 22, the horizontal axis is the design channel length (Lg) and the vertical axis is the channel resistance (R). FIG. 22 shows each channel resistance (R) when a gate voltage (Vg) of 1V, 2V, or 3V is applied to each transistor having a design channel length (Lg) of L1, L2, or L3. As shown in FIG. 22, there is a linear relationship between the design channel length (Lg) and the channel resistance (R) at each gate voltage (Vg).

[0121] If the straight lines showing each linear relationship are extrapolated in the direction in which Lg decreases, a point appears where the extrapolated lines intersect. This intersection point is the effective channel length (L eff ) is zero. At this time, if the X coordinate of the intersection is ΔL and the Y coordinate is R0, ΔL corresponds to the width of the overlap region OL, and R0 corresponds to the series resistance generated by the overlap region OL. The effective channel length (L eff ) and the design channel length (Lg), eff As shown in FIG. 1, when the transistor is symmetrical in the first direction (direction D1), the overlapping region OL S and the overlapping region OL on the drain side D The sum of these is ΔL. In other words, the overlapping area OL S and the overlapping region OL on the drain side D Between them, OL S =OL D =ΔL / 2.

[0122] Next, Fig. 23A is a diagram showing the dependency of threshold voltage on channel length in the semiconductor device 10 of one embodiment of the present invention. Fig. 23B is a diagram showing the dependency of threshold voltage on channel length in the semiconductor device of the above-mentioned comparative example. Here, the channel width (W) of each semiconductor device was set to 4.5 μm.

[0123] As shown in FIG. 23A, the semiconductor device 10 of this embodiment shows stable switching characteristics with the threshold voltage hardly changing when the channel length is in the range of 4 μm or more and 20 μm or less. It was also found that a threshold voltage of −0.4 V or more can be ensured even when the channel length is in the range of 4 μm or less (for example, 2.5 μm or more and 4 μm or less). That is, the semiconductor device 10 of this embodiment can obtain a stable threshold voltage independent of the channel length, and the threshold voltage does not shift significantly in the negative direction even when the channel length is 4 μm or less. In contrast, as shown in FIG. 23B, the semiconductor device of the comparative example shows a shift in the threshold voltage in the negative direction when the channel length is in the range of 10 μm or less.

[0124] The difference in electrical characteristics seen in Figures 23A and 23B is believed to be due to the width (ΔL / 2) of the overlap region OL. That is, in the semiconductor device 10 of this embodiment, the width of the overlap region OL can be suppressed to 1 μm or less, so that the design channel length (Lg) and the effective channel length (L eff ) is small. Therefore, the dependency of the threshold voltage on the channel length shows a tendency to be close to the dependency of the threshold voltage on the design channel length. On the other hand, in the semiconductor device of the comparative example, the width of the overlap region OL is longer than that of the present embodiment, and therefore the shorter the design channel length, the more noticeable the effect of the width of the overlap region OL becomes.

[0125] As described above, it can be said that it is important to set the width of the overlap region OL to 1 μm or less in order to suppress deterioration of the electrical characteristics of the semiconductor device, particularly the shift of the threshold voltage in the negative direction. In order to suppress the width of the overlap region OL to 1 μm or less, it is effective to increase the oxygen content of the layer that serves as the base of the oxide semiconductor layer 140, that is, the insulating layer 120. In addition to increasing the oxygen content of the insulating layer 120, it is desirable to further provide a metal oxide layer 130 between the insulating layer 120 and the oxide semiconductor layer 140.

[0126] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions, based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0127] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0128] 10, 10a...semiconductor device, 11...driving transistor, 12...selection transistor, 20, 20a...display device, 22...liquid crystal region, 24...sealing region, 26...terminal region, 100...substrate, 105...conductive layer, 110...insulating layer, 120...insulating layer, 130...metal oxide layer, 140...oxide semiconductor layer, 141...upper surface, 142...lower surface, 143...side surface, 150...gate insulating layer, 160...gate electrode, 170...insulating layer, 171, 173...opening, 180...insulating layer, 190...metal oxide layer, 200...source-drain electrode, 201...source electrode, 203...drain electrode, 210...storage capacitance, 211...signal line, 212...gate line, 213...anode power line, 214...cathode power line, 300...array substrate, 301, 301a...pixel circuit, 302...source driver circuit, 303...gate driver circuit, 304...source wiring, 305...gate wiring, 306...terminal portion, 307, 308...connection wiring, 310...seal portion, 311...liquid crystal element, 320...opposite substrate, 330...flexible printed circuit board, 340...chip, 350...storage capacitance, 360...insulating layer, 362...insulating layer, 363...opening, 370...common electrode, 380...insulating layer, 381...opening, 390...pixel electrode, 392...luminescent layer, 394...common electrode

Claims

1. The first insulating layer and A metal oxide layer mainly composed of aluminum on the first insulating layer, An oxide semiconductor layer on the aforementioned metal oxide layer, A gate insulating layer on the oxide semiconductor layer, The gate electrode on the aforementioned gate insulating layer, The second insulating layer on the gate electrode, Includes, The metal oxide layer has a pattern shape, The oxide semiconductor layer has a first region in contact with the gate insulating layer and a second region that is continuous with the first region in a first direction and is in contact with the gate insulating layer and the second insulating layer, respectively, in a semiconductor device.

2. The semiconductor device according to claim 1, wherein the second insulating layer is in contact with the gate electrode, the gate insulating layer, and the oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein the second insulating layer has a laminated structure including a silicon nitride layer and a silicon oxide layer.

4. The first region is the channel region, The semiconductor device according to claim 1, wherein the second region is a region with lower resistance than the channel region.

5. The semiconductor device according to claim 1, wherein the metal oxide layer and the oxide semiconductor layer have the same pattern shape.

6. The semiconductor device according to claim 1, wherein the gate insulating layer and the gate electrode have the same pattern shape.

7. The semiconductor device according to claim 1, wherein the width in the first direction of the portion of the second region that is in contact with the gate insulating layer is 1 μm or less.

8. The semiconductor device according to claim 7, wherein the width of the gate electrode in the first direction is 4 μm or less.

9. The semiconductor device according to claim 7, wherein the width of the gate electrode in the first direction is 1 μm or more greater than twice the width of the portion of the second region in contact with the gate insulating layer in the first direction.

10. A display device comprising a semiconductor device according to any one of claims 1 to 9 for each pixel.

Images