Processing for generating physical implementation guidance during synthesis of networks-on-chip

Abstract

To provide a system and method for augmenting a synthesized network-on-chip (NoC) with data that guides the physical implementation of a NoC topology to match topology synthesis results and reducing timing violations in a final physical design.SOLUTION: A NoC, during the physical implementation of a synthesized NoC, generates physical implementation guidance, inserts a link as a pipeline placeholder, and assigns a minimal set of created module regions to a particular link in a topology. Each route has a new link and a corresponding module region inserted into a physical path.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] Technical Field The present technology is in the field of electronic systems design, and more specifically, relates to physical implementation guidance during the generation of network-on-chip (NoC). [Background technology]

[0002] background Multiprocessor systems are implemented in systems-on-chip (SoCs) that communicate through a NoC. The SoC contains instances of initiator intellectual property (IP) and target IP. Transactions in the form of packets are sent from the initiator to one or more targets using industry standard protocols. An initiator connected to the NoC sends a request transaction to the target, using an address to select the target. The NoC decodes the address and transports the request from the initiator to the target. The target handles the transaction and sends a response transaction, which is transported back to the initiator by the NoC.

[0003] For a given set of performance requirements, such as connectivity and latency between sources and destinations, frequencies of various elements, maximum area available for the NoC logic and its associated routing (wiring), minimum throughput between sources and destinations, power consumption requirements for the NoC, and location on the floorplan of the elements attached to the NoC, it is a complex task to create an optimal NoC that meets all the requirements with the minimum amount of logic and wires. It is typically the job of a chip engineer or chip designer to create this optimal NoC, which is a difficult and time-consuming task. In addition to this being a difficult challenge, the design of the NoC is revised every time one of the requirements changes, such as a change in the chip floorplan, an IP component is added or removed, or the expected performance changes. As a result, this task needs to be re-done frequently over the design time of the chip. This process is time-consuming and results in production delays. Therefore, what is needed is a system and method for efficiently generating a NoC from a set of constraints enumerated as requirements and a set of inputs. The system needs to produce a NoC with all its elements placed on the chip's floorplan.

[0004] A current technical problem in creating a NoC is the lack of availability of physical floorplan information. For example, if two components are logically plugged into a network in an adjacent configuration or are logically adjacent to each other, they may go through a single switch to implement communication between the two components. However, in the physical floorplan, the two components may be far away from each other. As a result, it may be difficult and / or even impossible to meet the timing requirements when the NoC is implemented in the body of the actual floorplan. Timing requirements are passed to downstream tools. Timing requirements indicate, for example, parameters between component A and component B. For example, the timing between component A and component B must be within a certain range of values. It is now known that if the value measured from component A to component B exceeds the range of values ​​of the timing requirement, then it cannot essentially be met, as downstream tools will be overworked when trying to meet the time requirement when component A is too far from component B. It would therefore be more desirable to create a NoC that downstream tools can successfully implement while meeting all timing, power, area, and congestion design constraints. Summary of the Invention [Problem to be solved by the invention]

[0005] overview According to various embodiments and aspects of the present invention, a process for generating implementation guidance during synthesis of a NoC is described. A system and method are disclosed for generating a NoC using constraints and steps with inputs to create or generate a NoC with all its elements. The elements of the NoC are placed on a chip's floorplan. An advantage of the present invention is the simplification of the design process and the work of the chip engineer or designer. Furthermore, the technical solution provides a technical effect of allowing a NoC to be created such that by having physical floorplan instructions, it is easier to automate mechanisms such as, but not limited to, adding distance pipe components, compared to current techniques. [Means for solving the problem]

[0006] In one embodiment, creating the synthesized NoC is configured to augment the NoC with information to ensure that the NoC meets performance criteria provided in the specification for the NoC when implemented in downstream tools, and provide floorplan instructions so that timing estimates can be implemented to determine how far a first component is from a second component. The timing estimate may provide data indicating, for example, that a first component of the NoC is too far from a second component of the NoC and exceeds a timing requirement. As a result of exceeding the timing requirement, at least one distance pipeline or link may be inserted into the floorplan. The addition of distance pipes to the floorplan solves many of the problems associated with two components of the NoC exceeding their timing requirements. However, the addition of distance pipes to the floorplan of the NoC contributes to added latency in that it adds clock cycles for data to pass through the distance pipe. It is more desirable to simultaneously add distance pipes and create a NoC topology that requires as few distance pipes as possible. As a result, overall performance, bandwidth, and latency may be optimized given the floorplan constraints. [Brief description of the drawings]

[0007] [Figure 1A] 1 is a logical diagram of a NoC including the various elements that create the NoC. [Figure 1B] FIG. 1 shows a NoC in which elements are arranged on a network floorplan. [Figure 2A] FIG. 1 illustrates a method for generating an NoC description based on a set of constraints according to various aspects and embodiments of the present invention. [Figure 2B] FIG. 2 is a block diagram of a NoC synthesis tool in accordance with various aspects and embodiments of the present invention. [Diagram 3] FIG. 2 is a graphical representation of a chip floor plan with occlusion areas and locations of interfaces with a NoC in accordance with various aspects and embodiments of the present invention. [Figure 4] FIG. 2 illustrates a connectivity table for a NoC according to various aspects and embodiments of the present invention. [Diagram 5] FIG. 1 illustrates a scenario table with throughput definitions for read and write transactions in accordance with various aspects and embodiments of the present invention. [Figure 6] FIG. 1 illustrates the creation of a network with three traffic classes in accordance with various aspects and embodiments of the present invention. [Figure 7] 7 illustrates a decomposition of the network of FIG. 6 using mergers and splitters in accordance with various aspects and embodiments of the present invention. [Figure 8] FIG. 7 illustrates a roadmap in a floor plan for one initiator of the network of FIG. 6 in accordance with various aspects and embodiments of the present invention. [Figure 9] FIG. 7 illustrates a roadmap for one target floor plan of the network of FIG. 6 in accordance with various aspects and embodiments of the present invention. [Figure 10] FIG. 9 illustrates the decomposition of a main node splitter into a cascade of splitters physically distributed along the roadmap of FIG. 8 in accordance with various aspects and embodiments of the present invention. [Figure 11]FIG. 10 illustrates the decomposition of a main node merger into a cascade of physically distributed mergers along the roadmap of FIG. 9 in accordance with various aspects and embodiments of the present invention. [Figure 12] FIG. 2 illustrates an example of two closely merged nodes in accordance with various aspects and embodiments of the present invention. [Figure 13] 1 is a flowchart illustrating a method for creating a synthetic NoC using data that indicates potential guidance for a physical implementation. [Figure 14] 11 is a flowchart illustrating an alternative method for creating a synthetic NoC using data that provides potential guidance for a physical implementation. [Figure 15A] 15 is a flowchart of the method of FIG. 14 for synthesizing a topology of a chip in accordance with various aspects of the present invention. [Figure 15B] FIG. 15B is an illustrative diagram of the process of FIG. 15A for synthesizing a topology of a chip according to various embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Detailed Description In the following, various examples of the present technology are described, illustrating various aspects and embodiments of the present invention. In general, the examples can use the described aspects in any combination. All statements herein that recite principles, aspects, and embodiments, as well as specific examples thereof, are intended to encompass both their structural and functional equivalents. Moreover, such equivalents are intended to include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0009] It should be noted that, as used herein, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Throughout this specification, reference to "one aspect," "aspect," "particular aspect," "various aspects," or similar language means that the particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment of the invention.

[0010] Throughout this specification, the appearance of "in one embodiment," "in at least one embodiment," "in an embodiment," "in a particular embodiment," and similar phrases may, but do not necessarily, all refer to the same or similar embodiments. Furthermore, the aspects and embodiments of the invention described herein are merely exemplary and should not be construed as limiting the scope or spirit of the invention as understood by those of ordinary skill in the art. The disclosed invention may be effectively made or used in any embodiment, including any novel aspects described herein. All statements herein reciting principles, aspects, and embodiments of the invention are intended to encompass both structural and functional equivalents thereof. Such equivalents are intended to include both currently known equivalents and equivalents developed in the future.

[0011] As used herein, a transaction may be a request transaction or a response transaction. Examples of request transactions include write requests and read requests.

[0012] As used herein, a node is defined as a distribution point or communication endpoint that can create, receive, and / or transmit information over a communication path or channel. A node may refer to any one of a switch, a splitter, a merger, a buffer, and an adapter. As used herein, splitters and mergers are switches, but not all switches are splitters or mergers. As used herein, in accordance with various aspects and embodiments of the invention, the term "splitter" refers to a switch having a single ingress port and multiple egress ports. As used herein, in accordance with various aspects and embodiments of the invention, the term "merger" refers to a switch having a single egress port and multiple ingress ports.

[0013] 1A, a NoC 100 according to various aspects and embodiments of the present invention is shown. The NoC 100 is an example of a network. According to various aspects and embodiments of the present invention, the network includes a set of nodes and a set of edges, each of which has a model and can be used at a synthesis center to perform and implement transformations on the network and converge to the best solution that meets the specified requirements. The NoC 100 includes nodes and endpoints and uses assembled basic network functions such as network interface units (NIUs, also called AIUs or agent interface units) 102, 104, 106, 108, 110, 112, 130, 132, and 134, nodes / switches 114, 116, 118, 120, and 122, adapters such as adapter 126, and buffers such as buffer 124. The NoC basic network functions use an internal transport protocol specific to the NoC 100 to communicate with each other, typically based on the transmission of packets. The NIU translates the protocol used by the attached SoC unit (not shown) to the transport protocol used within the NoC 100. The switches are configured to route the flow of traffic between the source and destination. The buffers 124 are used to store packets to insert pipeline elements to span long distances or to handle rate adaptation between high speed transmitters and low speed receivers or vice versa. The adapters 126 handle various transitions between data widths, clocks, and power domains. It is within the scope of the present invention, but is not limited to, that the transport protocols include proprietary and / or industry standard protocols.

[0014] 1B, NoC 150 is shown having various elements such as NIUs, switches, and occlusion areas in a floorplan. NoC 150 includes various connectivity elements through various switches. According to an aspect of the invention, a set of constraints is used as input to a tool, which will be described in more detail below. According to some aspects of the invention, the tool executes a set of sub-steps to produce a description (synthesis) of the resulting NoC, such as NoC 150, with its configured elements and the location of each element on the floorplan. The generated description is used to actually implement the NoC hardware, using the physical information produced to provide guidance to the back-end implementation flow. It is within the scope of the invention that NoC components are abstractions of what will become a much larger number of semiconductor gates in a SoC. It is also an important aspect that components have locations, such as the centroids of individual gates. Individual gates may comprise components that are placed and routed by downstream tools.

[0015] 2A, in accordance with some aspects of the present invention, a set of constraints (210, 212, 214, 216, and scenarios) are provided to a synthesis tool 220. In accordance with some embodiments and aspects of the present invention, the capabilities and capabilities of the tool 220 may include third-party ASIC implementation tools such as logic synthesis, place and route back-end tools. A designer and / or user constructs a set of constraints that are provided to the tool 220. The constraints are captured in a machine-readable format, such as a computer file that uses a defined format to capture information that is understood and processed by the tool. In accordance with one aspect of the present invention, the format is XML. In accordance with another aspect of the present invention, the format is JSON. The scope of the present invention is not limited by the particular format used.

[0016] 2B, the tool reads a file containing a description of the constraints and executes a synthesis process. According to some aspects of the invention, the synthesis process is subdivided into multiple steps. A sequencer 250 is responsible for executing each step of the process. According to some aspects of the invention, a set of steps are executed by the sequencer 250 of the tool 220 in light of the constraints indicated by the user / designer. The scope of the invention is not limited by the number and type of steps that the sequencer 250 can call and execute.

[0017] Referring again to FIG. 2A in conjunction with FIG. 2B, according to various aspects of the present invention, a network designer provides and defines a set of constraints, such as constraints 210, 212, 214, and 216. The sequencer 250 receives various inputs including: an input 251 including a global unified roadmap with connectivity between initiators and targets, including roadmap creation and information between each initiator and target; an input 252 including traffic classification and main switch creation; an input 254 including main switch decomposition into mergers and splitters; an input 258 including information regarding physical distribution of splitters and mergers in the roadmap; an input 259 including information regarding edge clustering; and an input 260 including information regarding performance aware node clustering. According to one aspect of the present invention, the sequencer 250 also receives an input 262 including information regarding optimization and network restructuring. According to one aspect of the present invention, the sequencer 250 receives an input 264 including information regarding routing and legalization. According to various aspects and embodiments of the present invention, the sequencer 250 uses all the inputs 251-264 to generate the network. According to various aspects and embodiments of the invention, sequencer 250 uses a combination of inputs 251-264 to generate a network.

[0018] According to various aspects of the invention, the input 251 includes input for a global integration roadmap. The global integration roadmap includes an integration model that captures a global physical view of the connectivity of the free space of the floorplan as well as the connectivity between initiators and targets. The global integration roadmap is modeled by a graph of physical nodes and standard segments that are used to locate the nodes (splitters, mergers, switches, adapters) of the network being built. The global integration roadmap is used to speed up computation. According to various aspects of the invention, the global integration roadmap is persistent, meaning that it is data that the system exports and re-consumes in incremental synthesis and subsequent runs.

[0019] According to some aspects of the invention, the input 259 includes information regarding edge clustering. Edge clustering aims to minimize resources and improve performance objectives through appropriate algorithms and techniques. According to some aspects of the invention, the edge clustering is applied in conjunction and cooperation with the node clustering of the input 260. Edge clustering and node clustering can be used in combination by mixing, by applying in parallel, or by applying in sequence. The advantage and goal is to expand the scope of synthesis and span a larger solution space for the network.

[0020] According to various aspects of the invention, the input 262 includes information regarding the restructuring. The restructuring includes various transformations and capabilities. According to some aspects of the invention, the transformation is logical in that there is a change in the structure of the network. According to some aspects of the invention, the transformation is physical because there is a physical change in the network, such as moving a node to a new location. Other examples of restructuring include subdividing a node into smaller nodes, changing parents between nodes, duplication of network subparts to avoid deadlocks and address congestion, and physically rerouting links to avoid congested areas or to meet timing constraints.

[0021] According to various aspects of the invention, other constraints may be provided, including the extension of clock domains, as well as power domains 212. Domains 212 include areas of the chip where logic belonging to a particular domain may be placed.

[0022] 3, a floorplan 300 of a chip on which a NoC is implemented is shown, having the locations of various initiator and target interfaces, in accordance with various aspects of the present invention. Physical constraints 210 provide physical information about the design, including the size of the chip on which the NoC is implemented, various occlusion areas on the floorplan, which are rectangles representing areas of the chip where NoC logic cannot or cannot be placed, free space, which is areas of the chip where NoC logic can reside and is defined by areas not covered by occlusion, and the locations of interfaces between SoC units and the NoC, which are the locations of initiator and target interfaces, such as NIUs. The occlusion may be represented at the top level of the floorplan, or may be included in a hierarchical representation of the physical / logical blocks in the design, and then used at the top level in the same manner.

[0023] According to various aspects of the present invention, functionality of a logic library used to implement a NoC is provided, including the size of a reference logic gate and the time it takes a signal to cover a distance of 1 mm.

[0024] Referring again to FIG. 2A, in accordance with various aspects of the present invention, an SoC includes multiple clock domains and multiple power domains. A clock domain is defined by all logic fed by a given clock input. The clock input is characterized by its most critical parameter, the frequency of the clock. A power domain is defined by all logic powered from the same power supply. In accordance with various aspects of the present invention, the power supplies are gated, thus power domains can be turned on or off or isolated from other power domains. Thus, the designer provides a set of clock and power domain constraints 212 as part of the initial design.

[0025] According to various aspects of the invention, initiators and targets are communicatively connected to the NoC. An initiator is a unit that sends a request. An initiator is typically configured to read and write commands. A target is a unit that serves or responds to a request. A target is typically configured to read and write commands. Each initiator is attached or connected to the NoC through an NIU. An NIU attached to an initiator is called an Initiator Network Interface Unit (INIU). Furthermore, each target is attached to the NoC through an NIU. An NIU attached to a target is called a Target Network Interface Unit (TNIU). The main function of the NoC is to transport each request from an initiator to a desired destination target, and if the request asks for or requires a response, the NoC transports each target's response to the corresponding requesting initiator. Initiators and targets have many different parameters that characterize them. According to various aspects of the present invention, for each initiator and target, the clock domain and power domain to which they belong are defined. The width of the data bus they use to transmit and receive write and read payloads is several bits. According to various aspects of the present invention, the width of the data bus for the connection (communication path to and from the target) used to transmit the write request and receive the write response is also defined. Furthermore, the clock and power domain definitions are references to the aforementioned clock and power domains present in the SoC, as described herein.

[0026] With continued reference to Figures 2A and 2B, and also with reference to Figure 4, a connectivity table 400 is shown. According to various aspects of the present invention, the table 400 allows traffic to be defined by classification. The tool allows the use of a traffic class label for each connection between an initiator and a target. As shown in the table 400, there are three traffic classes: L1, L2, and L3. The traffic class labels are any label selected by the user or designer. Any number of labels can be defined, and the scope of the present invention is not limited by the number of labels. Each label represents an independent network resource need. Each label is given a separate sub-network by the present invention, which can be physically distinct or use a virtual network if supported by the underlying NoC technology.

[0027] According to various aspects of the present invention, an initiator does not need to be able to send requests to all targets or targets connected to the NoC. The exact definition of targets that can receive requests from an initiator is outlined or described in a connectivity table, such as table 400. The connectivity and traffic class labeling information can be represented as an explicit or conceptual matrix. Each initiator has a row and each target has a column. If an initiator must be able to send traffic to a target, a traffic class label must be present at the intersection of the initiator row and the target column. If no label is present at the intersection, the tool does not require connectivity between that initiator and that target. For example, initiator 1 (M1) is connected and communicating with target 1 (S1) using a defined label 1 (L1), but M1 does not communicate with S2, and therefore there is no label at the intersection of M1 and S2. According to various aspects of the invention, the actual format used to represent connectivity may vary, so long as each pair of initiator-target combinations has a precise definition of its traffic class, or in the absence of a connection, no classification label. It is within the scope of the invention for an initiator / target connection to support multiple traffic classes.

[0028] Referring now to FIG. 5, a table 500 is shown according to various aspects of the present invention, including various scenarios of read (RD) and write (WR) transactions (as shown in FIG. 2A). The table 500 includes information that defines various throughput rates provided to the tool. The scenarios define the expected performance in terms of throughput of data between initiators and targets. Each scenario describes the expected required read bandwidth and the expected required write bandwidth between each initiator and each target. The throughput is defined in Bytes per second (B / s). A typical SoC has multiple operating modes. As an example, an SoC for a smartphone may have a gaming operating mode, an audio call operating mode, an idle operating mode, etc. These define scenarios that depend on different throughput rates. Thus, the set of scenarios represents the different operating modes that the SoC supports, and correspondingly, the expected NoC minimum performance in terms of throughput between initiators and targets.

[0029] A scenario can be represented as two matrices, one defining the read throughput and one defining the write throughput. According to various aspects of the invention, the read throughput requirement is used to size the response network, which handles data returning from the target to the initiator. The write throughput requirement is used to size the request network, which is data moving from the initiator to the target, according to various aspects of the invention. An example of throughput requirements for various scenarios, according to various aspects of the invention, is shown in table 500. The actual format used to represent the scenarios can vary, as long as each (initiator, target) pair has a precise definition of the minimum throughput required for reads and writes. In table 500, a read transaction from M1 to S1 has a minimum performance throughput of 100MB / s. In table 500, a write transaction from M1 to S1 has a minimum throughput of 50MB / s.

[0030] It is within the scope of the present invention that latency refers to the number of clock cycles it takes for data to traverse the network. Latency causes problems in transport networks, despite having high bandwidth (frequency). An example of a "real-time traffic class" is video data from a camera in an autonomous vehicle. It is not acceptable to have long latency in the propagation of data. If some data is lost, the vehicle becomes unsafe. A traffic class that is still real-time but less critical is for audio and / or video in an entertainment system. It is undesirable to have gaps in that data, but it is not dangerous. An example of non-real-time data is data from a gas gauge sensor in a car. If the data is delayed for a few seconds, it is not an issue because the rate of change of the data is very slow compared to the speed at which the SoC operates.

[0031] According to some aspects of the invention, a tool scenario is not defined, where the tool optimizes the NoC synthesis process for physical cost, such as lowest gate cost and / or lowest wire cost.

[0032] 6 in conjunction with FIG 2B, an initial network 600 is created in accordance with various aspects of the present invention. Network 600 implements a connectivity matrix having the following defined parameters or components:

[0033] One Network Interface Unit per initiator, 1 network interface unit per target, One switch is created for each defined traffic class, called the main switch for the class. One switch that splits the traffic for each initiator / after the initiator NIU to the different main switches this initiator needs to reach, One switch in front of each target / target NIU that merges traffic from the different main switches sending traffic to that target The data width of each switch and the clock domain it belongs to are calculated using the data width of each attached interface and their clock domains as input to the tool. According to various aspects of the invention, each step of transforming a network that is part of a NoC also performs a calculation of the data width and clock domain of the newly created network element.

[0034] 7 and 2B, the network 600 of FIG. 6 is shown and a tool process transforms the network 600 according to various aspects of the invention. The sequencer 250 has an input 254 representing a main switch decomposition into mergers and splitters. The tool decomposes each main switch of the network 600 into an equivalent implementation with splitters and mergers. According to various aspects of the invention, some switches have a single ingress port and multiple egress ports. According to various aspects of the invention, some switches have multiple ingress ports and a single egress port. Each main switch ingress port is connected to a splitter and each main switch egress port is connected to a merger. To the main switches, splitters and mergers are connected together according to the connectivity table.

[0035] 8, a floor plan 800 according to various aspects of the present invention is shown. The sequencer 250 has an input 256 representing the creation of a roadmap between each initiator and target. The floor plan 800 includes physical paths 802 calculated between an initiator interface (M0) on the floor plan and each of its connected targets, such as targets S0, S1, S2, and S3. The path 802 is called the splitter roadmap of initiator M0, and although not shown, every initiator has a splitter roadmap. The tool uses any algorithm suitable for finding paths between a source point and multiple destination points, including an algorithm that minimizes the length of the path.

[0036] 9, the floor plan 800 is shown with calculated physical paths 902 between the target interfaces of target S0 on the floor plan and each of its connected initiators. The paths 902 are the merger roadmap of target S0. As is evident, every target has a merger roadmap. The tool uses any suitable algorithm to find paths between multiple source and destination points, including algorithms that minimize the length of the paths. In accordance with various aspects of the present invention, the tool transforms the network to maintain its functionality and add location information to the network elements.

[0037] 10, a floorplan 800 is shown with a path 1002 in accordance with various aspects of the present invention. The sequencer 250 has an input 258 that provides the physical distribution of splitters and mergers on the roadmap. Using this tool, each switch is decomposed into mergers and splitters. Using the tool, each splitter in the main switch is further decomposed into a cascade of splitters, and each splitter in the cascade is placed at a branch point in the splitter roadmap of the attached initiator. A branch point in the roadmap is defined by the fact that a path is split into two or more branches.

[0038] Referring now to FIG. 11, a floor plan 800 is shown with a path 1102 according to various aspects of the invention. Using a tool, each switch of each merger in the main switch is further decomposed into a cascade of mergers, with each merger of the cascade being placed at a branch point of the attached target's merger roadmap. A branch point of the roadmap is defined by the fact that the path is split into two or more branches. The process of decomposing a splitter within a cascade of splitters maintains the original splitter functionality since the number of inputs to the cascade is still one and the number of outputs of the cascade is identical to the number of outputs of the original splitter. The process of decomposing a merger within a cascade of mergers maintains the original merger functionality since the number of outputs of the cascade is still one and the number of inputs to the cascade is identical to the number of inputs to the original merger. According to various aspects of the invention, the effect of the process is to obtain a set of basic switches, represented by mergers and splitters, physically located near where the actual connections between the switches are required.

[0039] According to various aspects of the invention, the tool transforms the network to reduce the number of wires used between achievable switches while maintaining the scenario-defined performance, which is a set of required minimum throughput between initiators and targets. According to various aspects of the invention, switches are clustered for performance-aware switching, and mergers and splitters distributed on the roadmap are treated similarly to normal switches.

[0040] According to one aspect of the invention, the tool uses an iterative process to merge switches under conditions where performance is still met until no further switch merging can occur. The tool uses a process that is described as follows.

[0041] 1) While further switch fusion is not possible, do the following: a) Select a candidate switch to merge with one of its neighbors. The selection process ensures that all switches in the network are eventually candidates.

[0042] b) Once a candidate is selected, search for neighbors to fuse. The neighbor criterion is based on the evaluation of a cost function. The cost function shall return the switch that is "best suited" to fuse with the candidate. The definition of "best suited" is implementation dependent, but the cost function shall be such that the potential fusion of two switches maximizes the gain in terms of at least one metric, including congestion, wire length, logic area, power, and performance.

[0043] c) If a merge occurs, test whether the performance scenarios still all meet the minimum throughput requirements. If not, these two switches cannot be merged. The process performed by the tool explores another neighbor until no more neighbors can be found, in which case all switches are left as they are, or until one neighbor is found that can be merged with the candidate without violating the minimum throughput requirements of all scenarios, in which case the network is modified by merging the candidate switch with its neighbor.

[0044] According to various aspects of the invention, a process can prevent a switch from growing beyond a certain size (maximum ingress ports, maximum egress ports). If the combined switch exceeds a set threshold, a merge is prevented.

[0045] Now referring to FIG. 12, a candidate switch SW3 is shown next to switch SW4 for a merger according to various aspects of the present invention. A sequencer 250 has an input 260 that provides performance aware switching clustering. The tool executes a process to merge two switches. When the switches are merged, the wires that were coming out of different switches are simplified to one wire from each connected switch to the combined switch. According to various aspects of the present invention, switches SW3 and SW4 are merged. The connections between SW1, SW4 and SW3 are combined and replaced with a single connection between SW1 and SW3_4. Thus, long connections between distant switches are eliminated and reduced to a minimum, while connections between close switches are eliminated and made inside the switches themselves.

[0046] 2B, inputs 262 to sequencer 250 include various optimizations that may be performed to further reduce the number of wires used by the network, the area of ​​the network elements, and the power consumed by the network elements. Examples of such optimizations include detecting links that may be removed because they are not being used or because their traffic may be rerouted, reducing the width of links if they are wider than required in the scenario, and performing wire length optimization by finding the optimal placement of all switch elements that minimizes the total wire length of the network, which is the sum of the products of the distance spanned by each connection between network elements and the width of that connection.

[0047] 2B, inputs 264 to sequencer 250 include producing a legal NoC by modifying the locations of network elements such that they fit into the allocated free space, do not overlap, and are within the limitations of the corresponding clock and power domains. According to various aspects of the invention, the area occupied on the die by each network element is calculated using information provided regarding the capabilities of the technology, such as the area of ​​a reference logic gate. Each element is then tested for the correctness of its placement (there is enough free space for the element and other elements do not overlap). If the test fails, the element is moved until a suitable location is found that passes the test.

[0048] According to another aspect of the invention, there is provided an extension of clock and power domains on the floorplan, where each element is tested to ensure that it is located within the boundaries of the specified clock and power domains. If the test fails, the element is moved until a suitable location is found where the test passes. Once a suitable placement is found for each element, each connection between the elements is routed. The routing process finds suitable paths for the sets of wires that make the connections between the elements. After routing is done, distance-spanning pipeline elements are inserted into the links as necessary using information provided about the capabilities of the technology based on the time it takes a signal to cover a distance of 1 mm.

[0049] According to some aspects and embodiments of the invention, the tool generates one or more computer files that describe the generated NoC, which include:

[0050] A list of network elements and their configuration: data width, clock domain. The location of each generated network element on the floor plan.

[0051] A set of routes through the network elements that implement a connection. According to an aspect of the invention, a route is an ordered list of network elements, one for each pair of (initiator, target) and one for each pair of (target, initiator). The route describes how traffic between the pairs flows and through which elements.

[0052] According to various aspects of the invention, a tool is used to generate metrics for the generated NoC, such as a histogram of wire length distribution, number of switches, and a histogram of switches by size.

[0053] According to another aspect of the invention, the tool automatically inserts various adapters and buffers into the network. The tool inserts adapters based on the accommodation required between two elements having different data widths, different clock and power domains. The tool inserts buffers based on the scenario and the detected rate mismatch.

[0054] According to some aspects and embodiments, the tool can be used to ensure that multiple iterations of synthesis are performed for incremental optimization of the NoC, including situations where one constraint provided to the tool is information about a previous run.

[0055] After the software performs the synthesis process, the results are generated in a machine-readable form, such as a computer file, using a well-defined format to capture the information. An example of such a format is XML, and another example of such a format is JSON. The scope of the invention is not limited by any particular format.

[0056] FIG. 13 illustrates a method 1300 performed by a tool to augment the synthetic NoC with data that serves as guidance for the physical implementation of the synthetic NoC. At step 1302, constraint parameters for the network are received at the tool, the constraint parameters being selected from a group of constraints including at least physical constraints and performance constraints. At step 1304, the physical floorplan of the NoC is augmented with additional information that helps guide the physical implementation. For example, the information may relate to placeholders for potential pipelines in the physical floorplan. At step 1306, the tool constrains the physical implementation of the connections to locations on the physical floorplan within the constraint parameters based on the augmentation information added to or for the physical floorplan. At step 1308, using the tool, the gates of the connections are directed to the shortest routing distance from the connections compared to a list of routing distances between the gates and the connections detected by the tool. At step 1310, using the tool, the portions of the logical interconnect are calibrated to the size of the tool by splitting the logical interconnect into portions.

[0057] FIG. 14 shows a flow chart illustrating an alternative method 1400 used by a tool to create a synthetic NoC using data indicating potential guidance for physical implementation. At step 1402, the tool receives timing requirements for the NoC. At step 1404, the tool receives performance constraints for the NoC. At step 1406, the tool augments a physical floorplan of the NoC with information that can be used to guide implementation of the synthesized NoC. At step 1408, the tool implements a timing estimation configured to determine whether a length between a first component and a second component placed on the physical floorplan exceeds a timing requirement. At step 1410, the tool identifies a physical insertion point for at least one link to the physical floorplan in response to exceeding the time requirement. At step 1412, the at least one link is inserted into the floorplan using wire delay technology specific parameters according to some aspects and embodiments of the present invention. At step 1414, the tool identifies a minimum set of module regions that can be assigned to a particular link of the at least one link of the NoC topology.

[0058] 15A and 15B illustrate a process used by the tools of FIGS. 13 and 14 to physically implement the topology of a composite NoC according to various aspects of the present invention. Any physical implementation tool, including but not limited to Synopsys SNPS Design Compiler, having NoC topology information 1502, including but not limited to physical floorplan, component locations, and / or specification inputs, is provided. Routes are created by topology synthesis (also called NoC generation) 1504 and configured to follow a set of floorplan regions or checkpoints. Mechanisms 1506 include but are not limited to timing realizations such as distance pipe insertion configured to improve timing between two components. Distance pipeline placeholder insertion 1510 may insert placeholders for potential pipelines using wire delay technology specific parameters. Using this method, many segments in the network fall within the legal length range for timing closure. In other words, the length between the two components is within the parameters established in the timing constraints. The placeholders are regular components of the topology known as links.

[0059] 15A and 15B, automatic module region creation 1512 facilitates the creation of a minimum set of module regions that are assigned specific links of the topology. Links inserted as pipeline placeholders may be reused as checkpoints. For each route generated by topology synthesis 1504, new links and corresponding module regions are inserted into the physical path when placement guidance calculation 1508 detects a problem to be avoided based on information 1502. In one example, when a predetermined wire distance is traced between two hops along both X and Y, new links and corresponding module regions are inserted into the physical topology 1510 and 1512. In other words, the distance between two components is too large to exceed timing requirements. This process ensures that downstream tools route topology wires approximately following the path of topology synthesis. Furthermore, because the routing is similar, the pipeline placeholders generated by the generated topology synthesis process have a high probability of reducing timing violations in the final design.

[0060] It would be more desirable to guide the physical implementation tool to lay out the NoC topology in a new way similar to the topology synthesis results, while still allowing the physical implementation tool enough flexibility to move logical elements around as needed.Rather than forcing exact locations of switches, routes follow a set of floorplan regions or checkpoints.

[0061] In one embodiment, mechanisms for accommodating timing implementation between a first component and a second component in a NoC include, but are not limited to, distance pipe insertion, adding a buffer stage, switching a buffer to a higher driving buffer or a faster buffer, adjusting wire widths, and / or indicating which wire layers are being used.

[0062] It is within the scope of the present invention that different mechanisms are physically implemented to overcome timing issues in the composite topology and resolve timing issues before their occurrence by communicating constraints and / or guidance for physical implementation. It is within the scope of the present invention for the physical implementation of connections, including, but not limited to, the physical placement of objects, components, and / or gates around the NoC topology, so that downstream tools do not place a first connection at a distance far enough away from a second connection such that a time limit is exceeded. It is more desirable to synthesize networks for all connections that can meet the connectivity requirements and minimize the number of gates in the composite network. It is important to minimize the number of gates in the composite network to include, but not limited to, allow the NoC to fit within the topology parameters, ensure that timing requirements can be met, be built more efficiently with smaller networks, and minimize the overall power used for interconnects between signals.

[0063] In other embodiments, the driving side components are replaced with components that have a larger drive strength to increase speed. For example, when a signal is transferred from a first switch to a second switch, timing requirements are exceeded because the distance between the first switch and the second switch is too large, a distance pipe may be placed between the first switch and the second switch, or the drive strength may be increased to make the signal faster by using a larger wire with a lower resistance to reduce parasitic elements on a particular line.

[0064] In one embodiment, a floorplan region is a mechanism that can include, but is not limited to, constraining components, such as switches and / or distance pipe stages, to physical locations and / or approximate physical locations and / or splitting logical interconnects into multiple parts that are scaled to the size of downstream tools for proper synthesis. The physical and logical configurations of interconnects are configured together to form logical interconnects. Floorplan regions are used to constrain components to specific locations. The need for floorplan regions is a response to the increase in size of the networks or interconnects of SoCs being developed. In other words, the networks or interconnects of SoCs are growing larger than the capacity of downstream implementation tools, including, but not limited to, the addition of wider interconnects and / or more interconnected components.

[0065] In a first aspect, because performance of the switch may be adversely affected if the switch is moved to a location outside of the constrained location, it may be more desirable to have the switch in a particular constrained location based on data associated with signals received and transmitted by the switch.

[0066] In a second aspect, additional constraints may be utilized to place component gates, for example for a switch or pipe stage, as close together as possible within each individual component. A current problem with existing placement programs is that they tend to place components too far from each other. It is within the scope of this invention that a switch is a single component with multiple gates, and each gate needs to be placed. The netlist facilitates the interconnection of these components, but downstream tools physically place the components and create routes to connect the specified logical connectivity.

[0067] In the third aspect, two separate constraints of the first and second aspects may be used simultaneously. For example, if the components of a switch specified to have a certain performance are distributed over a larger area than specified, the switch will have a lower performance than originally specified. Therefore, it is more desirable to keep the components of this switch close to each other. Furthermore, based on the larger network, it is more desirable to keep the components within a certain region or area of ​​free space in the floor plan so that the entire network functions as specified or analyzed.

[0068] In one embodiment, to an approximation in a given semiconductor process, a maximum length of a single wire is established to ensure that the overall timing of that particular path can be met. Furthermore, moving from a first component to a second component within a given time is a critical aspect. There are cases where moving a signal from a first component to a second component within a given time cannot be achieved due to excess length between the first and second components. As a result, the need for a technical solution of inserting a distance pipe stage, compared to current technology, would solve this technical problem.

[0069] In one embodiment, area estimates for the first component and the second component are received and timing and other performance requirements are balanced in optimizing the NoC to ensure that the resulting NoC gates can be placed, i.e., fit within the available floorplan space allocated to the NoC.

[0070] In one embodiment, power requirements for the NoC are further received and timing and other performance requirements are balanced in optimizing the NoC to ensure that the resulting NoC does not exceed the power requirements specified in the constraints.

[0071] In one embodiment, physical routing congestion data, obtained as an estimate based on the NoC netlist structure or as feedback from downstream implementation tools, is further incorporated to balance timing and other performance requirements in optimizing the NoC, thereby ensuring that the resulting NoC is routable in the free floorplan space allocated to the NoC.

[0072] According to certain aspects and embodiments of the invention, a method is disclosed for guiding a physical generation of a NoC from a synthesized representation, the method including receiving at least one constraint parameter for the NoC at a tool, the at least one constraint parameter selected from a group of constraint parameters including at least one physical constraint and at least one performance constraint, using the tool to augment a physical floorplan for the NoC with information that guides a physical implementation of the NoC, and using the physical floorplan to constrain the physical implementation of connections to locations on the physical floorplan based on the at least one constraint parameter.

[0073] According to some aspects and embodiments of the present invention, a method is disclosed in which, using a tool, a gate of a connection is directed to the one with the shortest routing distance from the connection compared to a list of routing distances between the gate and connections detected by the tool.

[0074] In accordance with certain aspects and embodiments of the present invention, a method is disclosed that includes dividing, using a tool, a logical interconnect into multiple portions, whereby the multiple portions of the logical interconnect are calibrated to a size of the tool.

[0075] According to certain aspects and embodiments of the invention, a method is disclosed for guiding a physical implementation of a synthesized topology of a NoC, the method including receiving at least one timing requirement for the NoC at a tool, receiving at least one performance constraint for the NoC at the tool, augmenting a physical floorplan for the NoC using the tool with information to guide the physical implementation, implementing a timing estimation configured to determine whether a length between a first component and a second component placed on the physical floorplan exceeds the at least one timing requirement, and inserting at least one link in the physical floorplan in response to exceeding the at least one timing requirement.

[0076] According to some aspects and embodiments of the present invention, a method is disclosed in which the at least one link is inserted using wire delay technology specific parameters. According to some aspects and embodiments of the present invention, a method is disclosed further comprising creating, in a tool, at least one modular region, and the at least one link of the NoC is assigned to the at least one modular region.

[0077] According to some aspects and embodiments of the invention, a method is disclosed that includes receiving an area estimate for a first component and a second component.

[0078] According to certain aspects and embodiments of the present invention, a method is disclosed that includes performing balancing against at least one timing requirement in optimizing a NoC to identify that at least one gate of the NoC may be placeable on at least a portion of a physical floorplan.

[0079] According to certain aspects and embodiments of the present invention, a method is disclosed that includes performing balancing against at least one performance constraint in optimizing a NoC to identify that at least one gate of the NoC may be placeable on at least a portion of a physical floorplan.

[0080] According to certain aspects and embodiments of the present invention, a method is disclosed that includes receiving a power requirement for an NoC.

[0081] According to certain aspects and embodiments of the present invention, a method is disclosed that includes performing balancing against at least one timing requirement in optimizing an NoC to identify that the NoC does not exceed a power requirement specified by the at least one timing requirement.

[0082] According to certain aspects and embodiments of the present invention, a method is disclosed that includes performing balancing against at least one performance constraint in optimizing a NoC to identify that the NoC does not exceed a power requirement specified in the at least one performance constraint. According to certain aspects and embodiments of the present invention, a method is disclosed that includes providing physical routing congestion data.

[0083] According to certain aspects and embodiments of the present invention, a method is disclosed that includes performing balancing against at least one timing requirement in optimizing a NoC to identify that the NoC may be routable to at least a portion of a physical floorplan.

[0084] According to certain aspects and embodiments of the present invention, a method is disclosed that includes performing balancing against at least one performance constraint in optimizing a NoC to identify that at least one gate of the NoC may be routable to at least a portion of a physical floorplan.

[0085] Certain methods according to various aspects of the present invention may be performed by instructions stored on a non-transitory computer-readable medium. The non-transitory computer-readable medium stores code including instructions that, when executed by one or more processors, cause a system or computer to perform steps of the methods described herein. Non-transitory computer-readable media include rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanically moving or solid-state storage media. Any type of computer-readable medium is suitable for storing code including instructions according to various examples.

[0086] It should be noted that although specific examples have been described herein, different combinations of different components from different examples may be possible. Salient features are presented to better explain the examples, but it will be apparent that certain features can be added, modified, and / or omitted without changing the functional aspects of these examples as described.

[0087] Various examples are methods that use any or a combination of machine behaviors. The method examples are completed wherever most of the constituent steps are performed. For example, according to various aspects and embodiments of the present invention, an IP element or unit includes a processor (e.g., CPU or GPU), RAM, e.g., off-chip dynamic RAM or DRAM, network interfaces for wired or wireless connections such as Ethernet, Wi-Fi, 3G, 4G long-term evolution (LTE), 5G, and other wireless interface standard radios. The IP may also include various I / O interface devices for various peripheral devices such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices (such as keyboards and mice, among others), as needed. By executing instructions stored in the RAM device, the processor performs the steps of the methods described herein.

[0088] Some examples are one or more non-transitory computer-readable media configured to store such instructions for the methods described herein. Any machine that holds a non-transitory computer-readable medium containing any of the necessary code may implement an example. Some examples may be implemented as a physical device such as a semiconductor chip, a hardware description language representation of the logical or functional behavior of such a device, and one or more non-transitory computer-readable media configured to store such hardware description language representation. All statements herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements coupled herein have an operative relationship that can be realized by direct connection or indirectly with one or more other intervening elements.

[0089] Those skilled in the art will recognize many modifications and variations. Modifications and variations include any relevant combination of the disclosed features. All statements herein reciting principles, aspects, and embodiments encompass both structural and functional equivalents thereof. Elements described herein as "coupled" or "communicatively coupled" have an effective relationship that can be achieved by a direct connection or an indirect connection using one or more other intervening elements. Embodiments described herein as "communicating" or "in communication" with other devices, modules, or elements include any form of communication or link and include an effective relationship. For example, the communication link can be established using a wired connection, a wireless protocol, a near-field protocol, or RFID.

[0090] Wherever the terms "including," "includes," "having," "has," "with," or variations thereof are used in any of the detailed description and claims, such terms are intended to be inclusive in the same manner as the term "comprising."

[0091] The scope of the present invention, therefore, is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the present invention is embodied in the appended claims.

Claims

1. A method for guiding the physical generation of NoC from a synthesized representation, The tool receives at least one constraint parameter for the NoC, wherein the at least one constraint parameter is selected from a group of constraint parameters including at least one physical constraint and at least one performance constraint. The process involves using the aforementioned tools to enhance a physical floor plan for the NoC that meets the supplied performance criteria, using information that guides the physical implementation of the NoC, wherein the information includes placeholders for potential pipelines in the physical floor plan. Using the physical floor plan, the physical implementation of the connection guided by the information is constrained to a location on the physical floor plan based on the at least one constraint parameter, Methods that include...

2. The method according to claim 1, wherein, using the tool, the gate of the connection is directed to the shortest routing distance from the connection by comparing it with a list of routing distances between the gate and the connection detected by the tool.

3. The method according to claim 1, further comprising dividing a logical interconnection into a plurality of parts using the tool, wherein the plurality of parts of the logical interconnection are calibrated to the size of the tool.

4. A method for guiding the physical implementation of a synthesized topology of a NoC, The tool receives at least one timing requirement for the aforementioned NoC, The tool receives at least one performance constraint for the NoC, The means of using the aforementioned tools to enhance the physical floor plan for the NoC to meet performance criteria, using information to guide the physical implementation, wherein the information includes placeholders for potential pipelines in the physical floor plan. Implementing a timing estimation configured to determine whether the length between a first component and a second component arranged on the physical floor plan exceeds at least one timing requirement, In response to exceeding at least one of the aforementioned timing requirements, at least one link is inserted into the physical floor plan, Methods that include...

5. The method according to claim 4, wherein the at least one link is inserted using parameters specific to the wire delay technique.

6. The method according to claim 4, further comprising creating at least one module region in the tool, wherein the at least one link of the NoC is assigned to the at least one module region.

7. The method according to claim 4, further comprising receiving area estimates for the first component and the second component.

8. The method according to claim 7, further comprising performing an equilibration for the at least one timing requirement in the optimization of the NoC in order to identify that at least one gate of the NoC may be located in at least a portion of the physical floor plan.

9. The method of claim 7, further comprising performing an equilibration for the at least one performance constraint in the optimization of the NoC in order to identify that at least one gate of the NoC may be located in at least a portion of the physical floor plan.

10. The method according to claim 4, further comprising receiving the power requirements for the NoC.

11. The method according to claim 10, further comprising performing an equilibration with respect to the at least one timing requirement in the optimization of the NoC in order to identify that the NoC does not exceed the power requirement specified by the at least one timing requirement.

12. The method according to claim 10, further comprising performing a balancer with respect to the at least one performance constraint in optimizing the NoC in order to identify that the NoC does not exceed the power requirement specified by the at least one performance constraint.

13. The method according to claim 4, further comprising providing physical routing congestion data.

14. The method of claim 13, further comprising performing a balancer for the at least one timing requirement in the optimization of the NoC in order to identify that the NoC may be routable to at least a portion of the physical floor plan.

15. The method according to claim 13, further comprising performing a balancer for the at least one performance constraint in the optimization of the NoC in order to identify that at least one gate of the NoC may be routeable to at least a portion of the physical floor plan.

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