Silicon carbide semiconductor device

Abstract

To provide a SiC semiconductor device in which switching tolerance can be improved irrespective of a rate controlling place of tolerance dose.SOLUTION: In a SiC semiconductor device in which a trench gate structure semiconductor element is formed, an n-type JFET layer 14 and a p-type first deep layer 15 are formed in a cell region 1. And, in a connecting part 2b positioned on an outer periphery of the cell region 1, an outer periphery end position Po that is an outer peripheral side end position of the cell region 1 in the JFET layer 14 is arranged to be positioned on a side of the cell region 1 compared to an inner periphery end position Pi that is an end position on a side of the cell region 1 in gate wiring 26.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a silicon carbide (hereinafter also referred to as SiC) semiconductor device having a semiconductor element with a trench gate structure. [Background technology]

[0002] In a SiC semiconductor device having a MOSFET with a trench gate structure, a gate insulating film is extended to the periphery of a cell region in which the MOSFET is formed, and a field oxide film is disposed thereon. The gate electrode of the MOSFET provided in the cell region is extended onto the gate insulating film and field insulating film disposed to the periphery of the cell region, and is connected to the gate wiring. In a SiC semiconductor device configured in this way, thin insulating films such as the gate insulating film are easily destroyed by the flow of displacement current during high-speed switching. For this reason, in Patent Document 1, the distance from the source contact in the cell region to the step portion that is the boundary between the gate insulating film and the field insulating film is set short to shorten the distance of the current path. This reduces the current path resistance, suppresses the destruction of the gate insulating film caused by the displacement current, and improves the switching resistance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-57850 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the structure of Patent Document 1, when the withstand voltage of the SiC semiconductor device is limited at a location other than the step portion of the field oxide film, the effect of reducing the current path resistance cannot be obtained even with the configuration of Patent Document 1, and the switching withstand voltage cannot be improved.

[0005] An object of the present disclosure is to provide a SiC semiconductor device that can improve switching withstand capability regardless of the location that determines the withstand capability. [Means for solving the problem]

[0006] One aspect of the present disclosure is a SiC semiconductor device having a cell region (1) in which a semiconductor element of a trench gate structure is formed, and a peripheral region (2) surrounding the cell region and provided with a peripheral breakdown-withstanding structure part (2a) constituting a peripheral breakdown-withstanding structure (16) and a connecting part (2b) located between the peripheral breakdown-withstanding structure part and the cell region, the device having a substrate (11) made of SiC of a first conductivity type or a second conductivity type, and a first impurity region (13) of the first conductivity type formed on the surface of the substrate and having a lower impurity concentration than the substrate. The cell region includes a JFET layer (14) made of a first conductivity type SiC formed in a surface layer portion of the first impurity region and having a higher impurity concentration than the first impurity region, a deep layer (15) made of a second conductivity type SiC formed in a surface layer portion of the first impurity region and arranged alternately with the JFET layer in the surface direction of the substrate, a base layer (18) made of the second conductivity type SiC formed on the JFET layer and the deep layer, and a gate trench (21) formed on the inner wall surface of a plurality of gate trenches (21) arranged in one direction deeper than the base layer. The semiconductor element includes a gate insulating film (22), a trench gate structure having a gate electrode (23) formed on the gate insulating film in the gate trench, a second impurity region (19) made of SiC of a first conductivity type having a higher impurity concentration than the first impurity region, formed in contact with the trench gate structure in the surface layer portion of the base layer, a first electrode (25) electrically connected to the second impurity region and the base layer, and a second electrode (28) disposed on the back side of the substrate and electrically connected to the substrate. The connecting portion includes a gate insulating film extending from the cell region and formed on the first impurity region, a gate electrode extending from the cell region and disposed on the gate insulating film, and a gate wiring (26) connected to the gate electrode. The outer periphery end position (Po), which is the end position on the outer periphery side of the cell region in the JFET layer, is located closer to the cell region than the inner periphery end position (Pi), which is the end position on the cell region side of the gate wiring.

[0007] In this way, the electric field applied to the gate insulating film is likely to be large especially below the gate wiring, but the JFET layer is not formed in that portion, and the outer peripheral end position of the JFET layer is closer to the cell region than the inner peripheral end position of the gate wiring. Because of this structure, the impurity concentration of the p-type layer and n-type layer constituting the pn junction is reduced, and the displacement current generated when the voltage suddenly increases during switching can be reduced. Therefore, the electric field concentration caused by the displacement current is mitigated, the breakdown of the gate insulating film can be suppressed, and the switching resistance can be improved. And this effect can be obtained regardless of the rate-determining location of the resistance. Therefore, it is possible to obtain a SiC semiconductor device that can improve the switching resistance regardless of the rate-determining location of the resistance.

[0008] In a second aspect of the present disclosure, the JFET layer is formed only on the cell region side of the cell region and the connecting portion.

[0009] In this way, the JFET layer is formed on the cell region side of the connecting portion, but the JFET layer is not formed on the outside. Therefore, the pn junction on the outer edge side of the connecting portion is composed of a low concentration layer and a deep layer. Therefore, the effect of the first aspect can be obtained.

[0010] In a third aspect of the present disclosure, the JFET layer is also formed in the connecting portion, and a portion of the JFET layer that is outside an inner peripheral end position, which is an end position on the cell region side of the gate wiring, has a first conductivity type impurity concentration that is equal to or lower than that of the first impurity region.

[0011] In this way, even if a JFET layer is formed in the junction, if the first conductivity type impurity concentration is lowered outside the inner circumference end position of the gate wiring, the impurity concentration of the p-type layer and n-type layer constituting the pn junction in the outer circumference region will be lowered. Therefore, the time change dV / dt is reduced and the displacement current can be reduced, so that the switching resistance can be improved, and it is possible to obtain a SiC semiconductor device in which the switching resistance can be improved regardless of the rate-determining location of the resistance.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view of a SiC semiconductor device according to a first embodiment. [Diagram 2] 2 is a perspective cross-sectional view of an area RA in FIG. 1 as viewed from a direction II. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along line IV-IV in FIG. [Diagram 5] FIG. 11 is a cross-sectional view illustrating a displacement current generated in the outer circumferential region. [Figure 6A] 2A to 2C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 6B] FIG. 6B is a cross-sectional view showing a manufacturing process subsequent to FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view showing a manufacturing process subsequent to FIG. 6B. [Figure 6D] FIG. 6D is a cross-sectional view showing a manufacturing process following FIG. 6C. [Figure 6E] FIG. 6B is a cross-sectional view showing a manufacturing process subsequent to FIG. 6D. [Figure 7] FIG. 11 is a cross-sectional view of a SiC semiconductor device according to a second embodiment. [Figure 8A] 2A to 2C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 8B] FIG. 8B is a cross-sectional view showing a manufacturing process following FIG. 8A. [Figure 8C] FIG. 8C is a cross-sectional view showing a manufacturing process subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a cross-sectional view showing a manufacturing process subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a cross-sectional view showing a manufacturing process subsequent to FIG. 8D. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First embodiment) The first embodiment will be described with reference to the drawings. As shown in Fig. 1, the SiC semiconductor device of the present embodiment has a cell region 1 which is an active region that operates as an element, and a peripheral region 2 which surrounds the cell region 1.

[0016] In addition, below the cell region 1 in FIG. 1, various pads 3 for controlling elements provided in the cell region 1 of the SiC semiconductor device, for temperature detection, etc. are formed.

[0017] 2, the peripheral region 2 has a guard ring portion 2a corresponding to a peripheral breakdown withstand structure portion in which a peripheral breakdown withstand structure is configured, and a connecting portion 2b arranged inside the guard ring portion 2a. In other words, the peripheral region 2 has a guard ring portion 2a and a connecting portion 2b arranged between the cell region 1 and the guard ring portion 2a.

[0018] Hereinafter, a SiC semiconductor device in which an n-channel vertical MOSFET is provided as a semiconductor element having a trench gate structure in a cell region 1 will be described with reference to FIGS. 2 to 4. In addition, in the following, one direction in the surface direction of a semiconductor substrate 10 described later is defined as an X-axis direction, a direction intersecting with the one direction in the surface direction of the semiconductor substrate 10 is defined as a Y-axis direction, and a direction intersecting with the X-axis direction and the Y-axis direction is defined as a Z-axis direction. Here, the X-axis direction, the Y-axis direction, and the Z direction are defined as axes perpendicular to each other. In addition, the Z-axis direction in this embodiment corresponds to the thickness direction of the semiconductor substrate 10 described later, and also corresponds to the stacking direction of a substrate 11 and a low concentration layer 13 described later. The Y-axis direction is, for example, a <11-20> direction.

[0019] The SiC semiconductor device is constructed using a semiconductor substrate 10 on which a vertical MOSFET element is formed. + In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si surface and an n-type impurity concentration of 1.0×10 19 / cm 3 and has a thickness of about 300 μm. In the case of a vertical MOSFET, the substrate 11 constitutes the drain region.

[0020] If necessary, an n-type buffer layer 12 made of SiC is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration between that of the substrate 11 and a low concentration layer 13 described later, and has a thickness of about 1 μm.

[0021] On the surface of the buffer layer 12, for example, an n-type impurity concentration of 5.0×10 15 ~2.0×10 16 / cm 3 The thickness of the n-type SiC substrate is about 7 to 15 μm. - A low concentration layer 13 of a mold is formed. The impurity concentration of this low concentration layer 13 may be constant in the Z-axis direction, but it is preferable that the concentration distribution is gradient so that the low concentration layer 13 on the substrate 11 side has a higher concentration than the low concentration layer 13 on the side away from the substrate 11. In this embodiment, the low concentration layer 13 corresponds to a first impurity region.

[0022] A JFET layer 14 and a first deep layer 15 are formed in the surface layer of the low concentration layer 13 in the cell region 1. In this embodiment, the JFET layer 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. That is, the JFET layer 14 and the first deep layer 15 are each formed in a stripe shape extending along the X-axis direction in the normal direction (hereinafter simply referred to as the normal direction) to the surface of the substrate 11, and are arranged alternately along the Y-axis direction. In addition, in the normal direction to the surface of the substrate 11, it can also be said that when viewed from the normal direction to the surface of the substrate 11. The normal direction to the surface of the substrate 11 is also the direction along the stacking direction of the drift layer 17 and the base layer 18 described later, and is the direction along the Z-axis direction.

[0023] The JFET layer 14 is of n-type with a higher impurity concentration than the low concentration layer 13, and has a thickness of 0.3 to 1.5 μm. In this embodiment, the JFET layer 14 has an n-type impurity concentration of 5.0×10 16 ~1.0×10 17 / cm 3 The first deep layer 15 has a p-type impurity concentration of about 2.0×10 17 ~2.0×10 18 / cm 3 It is said to be about that level.

[0024] The first deep layer 15 may be at the same depth as the JFET layer 14, or may be deeper or shallower than the JFET layer 14. In this embodiment, the first deep layer 15 is formed shallower than the JFET layer 14. That is, the first deep layer 15 is formed so that its bottom is located in the JFET layer 14. In other words, the first deep layer 15 is formed so that the JFET layer 14 is located between the first deep layer 15 and the low concentration layer 13. This suppresses the spread of the depletion layer into the JFET layer 14 between the first deep layers 15, thereby reducing the on-resistance. The JFET layer 14 and the first deep layer 15 are formed by appropriately ion-implanting impurities into the surface layer of the low concentration layer 13.

[0025] Meanwhile, a surface layer of the low concentration layer 13 in the guard ring portion 2a of the peripheral region 2 is provided with a plurality of p-type guard rings 16 as a peripheral voltage-resistant structure so as to surround the cell region 1. In this embodiment, the top surface layout of the guard rings 16 is a square or a circle with rounded corners in the normal direction.

[0026] Furthermore, a p-type connecting layer 15a is provided on the surface layer of the low concentration layer 13 in the connecting portion 2b of the peripheral region 2. The connecting layer 15a is disposed so that its inner edge side surrounds the cell region 1, and its outer edge side is disposed up to the boundary position with the guard ring portion 2a. The connecting layer 15a is formed by extending the first deep layer 15 up to the connecting portion 2b, and has the same depth and p-type impurity concentration as the first deep layer 15.

[0027] Note that the JFET layer 14 is formed in a part of the connecting portion 2b in the outer peripheral region 2, specifically, on the cell region 1 side of the connecting portion 2b, but the JFET layer 14 is not formed outside of that. Therefore, at a position where the JFET layer 14 is formed deeper than the first deep layer 15, the JFET layer 14 exists below the cell region 1 side of the connecting layer 15a, but the JFET layer 14 does not exist on the outer edge side of the connecting portion 2b or on the guard ring portion 2a side.

[0028] Moreover, on the JFET layer 14 and the first deep layer 15 in the cell region 1, a base layer 18, a source region 19, a contact region 20, etc. are formed.

[0029] The base layer 18 is of p-type and is formed on the JFET layer 14 and the first deep layer 15. Therefore, the first deep layer 15 is in a state of being connected to the base layer 18. The base layer 18 has a p-type impurity concentration of, for example, 5.0×10 16 ~2.0×10 19 / cm 3 The thickness is said to be about 2.0 μm.

[0030] The source region 19 is + The contact region 20 is a p + The source region 19 is formed in a surface layer portion of the base layer 18. Specifically, the source region 19 is formed so as to contact a side surface of a trench 21, which will be described later, and the contact region 20 is formed on the opposite side of the source region 19 to the trench 21, which will be described later. In this embodiment, the source region 19 has an n-type impurity concentration in the surface layer portion, i.e., a surface concentration, of, for example, 1.0×10 18 / cm 3 The contact region 20 has a p-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0×10 21 / cm 3 The thickness is set to about 0.3 μm. In this embodiment, the source region 19 corresponds to the second impurity region.

[0031] The base layer 18, the contact region 20, and the surface portion of the low concentration layer 13 are formed on the low concentration layer 13, the JFET layer 14, the first deep layer 15, and the connecting layer 15a in the connecting portion 2b of the outer peripheral region 2. On the inner edge side of the connecting portion 2b, the base layer 18 and the contact region 20 are formed on the connecting layer 15a and extend from the cell region 1. On the outer edge side of the connecting portion 2b, the base layer 18 and the contact region 20 are not formed, and the surface portion of the low concentration layer 13 is formed. That is, in this embodiment, the base layer 18 and the contact region 20 in the outer peripheral region 2 are extended from the cell region 1 and formed halfway in the connecting portion 2b, and are not formed in the connecting portion 2b and the guard ring portion 2a on the outer side. In addition, from the boundary position between the cell region 1 and the peripheral region 2 to halfway through the connecting portion 2b, the entire surface layer of the connecting portion 2b is made into a contact region 20, and outside of that, the entire surface layers of the connecting portion 2b and the guard ring portion 2a are made into a low concentration layer 13.

[0032] In this embodiment, the semiconductor substrate 10 is configured to include the substrate 11, the buffer layer 12, the low concentration layer 13, the JFET layer 14, the first deep layer 15, the base layer 18, the source region 19, the contact region 20, etc., as described above. Since each layer constituting the semiconductor substrate 10 is made of SiC, it can be said that the semiconductor substrate 10 is made of SiC. In this embodiment, on the inner edge side of the cell region 1 and the connecting portion 2b, one surface 10a of the semiconductor substrate 10 is made of the source region 19, the contact region 20, etc., and the other surface 10b of the semiconductor substrate 10 is made of the substrate 11.

[0033] In this embodiment, the JFET layer 14, the first deep layer 15, the connecting layer 15a, the guard ring 16, the base layer 18, the source region 19, and the contact region 20 are composed of ion-implanted layers formed by ion implantation.

[0034] In the cell region 1, a trench 21 is formed in the semiconductor substrate 10, penetrating the source region 19, the base layer 18, etc., and reaching the JFET layer 14 and the first deep layer 15 from the one surface 10a side. The trench 21 corresponds to a gate trench, has a depth such that its bottom surface is located within the JFET layer 14 and the first deep layer 15, and has a width of, for example, 0.4 to 0.8 μm.

[0035] 3, the trenches 21 are formed so that a plurality of trenches 21 extend along the Y-axis direction and are arranged at equal intervals of B1 in the X-axis direction to form a stripe shape. That is, in this embodiment, the trenches 21 are formed so that the longitudinal direction thereof is perpendicular to the longitudinal direction of the first deep layer 15.

[0036] A second deep layer 30 serving as an electric field relaxation layer is formed at the bottom of the trench 21 so as to contact the bottom surface of the trench 21. In this embodiment, the second deep layer 30 is composed of a p-type layer having a lower impurity concentration than the first deep layer 15. Specifically, the second deep layer 30 is formed along the longitudinal direction of the trench 21. That is, the second deep layer 30 extends along the Y-axis direction intersecting with the first deep layer 15. Moreover, the second deep layer 30 of this embodiment is formed so that the bottom surface thereof reaches the low concentration layer 13 by penetrating the JFET layer 14 and the first deep layer 15.

[0037] By forming the second deep layer 30 along the bottom surface of the trench 21, it is possible to suppress the penetration of the electric field into the gate insulating film 22 located at the bottom of the trench 21, and to suppress the breakdown of the oxide film. In addition, by forming the second deep layer 30 so as to be in contact with the bottom surface of the trench 21, it is possible to reduce the electrostatic capacitance between the gate electrode 23 and the lower electrode 28, i.e., the feedback capacitance, and to improve the switching speed. Furthermore, since the second deep layer 30 is formed so as to penetrate the JFET layer 14 and the first deep layer 15 and the bottom surface reaches the low concentration layer 13, the creeping up of the electric field to the JFET layer 14 disposed between the second deep layers 30 is suppressed, and the breakdown voltage can be improved. In addition, since a breakdown is likely to occur in the second deep layer 30 that protrudes downward when an overvoltage is applied, it is possible to easily cause a breakdown in the cell region 1, and the avalanche breakdown can be improved.

[0038] The second deep layer 30 may be divided into a plurality of layers along the Y-axis direction. However, the second deep layer 30 is formed so as to be electrically connected to the base layer 18 via the first deep layer 15.

[0039] Further, a gate insulating film 22 is formed on the inner wall surface of the trench 21, and a gate electrode 23 made of doped poly-Si or the like is formed on the gate insulating film 22. This constitutes a trench gate structure. Although not particularly limited, the gate insulating film 22 is formed by thermally oxidizing the inner wall surface of the trench 21 or by forming an insulating film by a CVD (short for chemical vapor deposition) method. The gate insulating film 22 has a thickness of about 100 nm on both the side and bottom sides of the trench 21.

[0040] The gate insulating film 22 is formed on the inner wall surface of the trench 21 as well as on one surface 10a of the semiconductor substrate 10. In the cell region 1, a contact hole 22a is formed in the gate insulating film 22, and the source region 19 and the contact region 20 are exposed.

[0041] A field oxide film 241 is formed on one surface 10a of the semiconductor substrate 10 so as to surround the outer edge of the cell region 1, and an interlayer insulating film 242 is further formed so as to cover the gate electrode 23, the gate insulating film 22, the field oxide film 241, etc. The interlayer insulating film 242 is made of BPSG (abbreviation of borophosphosilicate glass) or the like. Note that in FIG. 2, the field oxide film 241, the interlayer insulating film 242, etc. located above the one surface 10a of the semiconductor substrate 10 are omitted.

[0042] 3, the interlayer insulating film 242 has a contact hole 242a formed therein, which communicates with the contact hole 22a in the cell region 1 to expose the source region 19 and the contact region 20. Also, as shown in FIG. 4, the interlayer insulating film 242 has a contact hole 242b formed therein to expose a portion of the gate electrode 23 that extends to the connecting portion 2b.

[0043] An upper electrode 25 is formed on the interlayer insulating film 242, and is electrically connected to the source region 19 and the contact region 20 through the contact hole 22a and the contact hole 242a. The upper electrode 25 is adapted to be electrically connected to the outside. In this embodiment, the upper electrode 25 corresponds to a first electrode. Also, a gate wiring 26 is formed on the interlayer insulating film 242, and is electrically connected to the gate electrode 23 through the contact hole 242b. Although not shown in FIG. 1, the gate wiring 26 is formed along the outer edge of the cell region 1, and is formed along the right, left, and lower sides of the SiC semiconductor device that is a rectangular chip shown in FIG. 1, for example.

[0044] As described above, the JFET layer 14 is formed only on the cell region 1 side of the cell region 1 and the connecting portion 2b, but is not arranged below the gate wiring 26. That is, the outer periphery termination position Po located on the outer periphery side of the cell region 1 of the JFET layer 14 shown in Fig. 4 is arranged to be closer to the cell region 1 than the inner periphery termination position Pi located on the cell region 1 side of the gate wiring 26. Further, outside the inner periphery termination position Pi, a connecting layer 15a is formed or the low concentration layer 13 is arranged.

[0045] The upper electrode 25 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the n-type SiC, i.e., the portion that constitutes the source region 19, is made of a metal that can make ohmic contact with the n-type SiC. At least the portion of the plurality of metals that contacts the p-type SiC, i.e., the contact region 20, is made of a metal that can make ohmic contact with the p-type SiC. The gate wiring 26 may have the same structure as the upper electrode 25, or may be made of Al-Si or the like.

[0046] Furthermore, a protective film 27 made of polyimide or the like is formed so as to cover the connecting portion 2b and the guard ring portion 2a. In this embodiment, the protective film 27 is formed from the outer periphery region 2 to the outer edge of the cell region 1 in order to suppress the occurrence of creeping discharge between the upper electrode 25 and a lower electrode 28 described later. Specifically, the protective film 27 is formed in the cell region 1 so as to cover the portion of the upper electrode 25 on the outer periphery region 2 side while exposing the portion of the upper electrode 25 on the inner edge side.

[0047] A lower electrode 28 electrically connected to the substrate 11 is formed on the other surface 10b side of the semiconductor substrate 10. In this embodiment, the lower electrode 28 corresponds to the second electrode.

[0048] In the SiC semiconductor device of this embodiment, an n-channel type inversion type trench gate structure MOSFET is formed by such a structure.

[0049] The above is the configuration of the SiC semiconductor device in this embodiment. - type, n type, n + The first conductivity type corresponds to p-type, p + The type corresponds to the second conductivity type. Next, the operation of the above-mentioned SiC semiconductor device will be described.

[0050] First, in the above-described SiC semiconductor device, in the off state before a gate voltage is applied to the gate electrode 23, no inversion layer is formed in the base layer 18. For this reason, even if a positive voltage, for example, 1600 V, is applied to the lower electrode 28, electrons do not flow from the source region 19 into the base layer 18, and no current flows between the upper electrode 25 and the lower electrode 28.

[0051] Moreover, before the gate voltage is applied to the gate electrode 23, an electric field is applied between the drain and gate, and electric field concentration may occur at the bottom of the gate insulating film 22. However, in the above-mentioned SiC semiconductor device, the first deep layer 15 and the JFET layer 14 are provided at a position deeper than the trench 21. Therefore, the depletion layer formed between the first deep layer 15 and the JFET layer 14 suppresses the rise of the equipotential line due to the influence of the drain voltage, and the high electric field is less likely to penetrate into the gate insulating film 22. Furthermore, since the second deep layer 30 serving as an electric field relaxation layer is provided at the bottom of the trench 21, the high electric field is less likely to penetrate into the gate insulating film 22. Therefore, in this embodiment, it is possible to suppress the gate insulating film 22 from being destroyed.

[0052] Furthermore, when a predetermined gate voltage is applied to the gate electrode 23, a channel is formed on the surface of the base layer 18 that is in contact with the trench 21. Therefore, electrons injected from the upper electrode 25 pass through the channel formed in the base layer 18 from the source region 19, then pass through the JFET layer 14 and flow into the low concentration layer 13, and then pass through the substrate 11 as the drain layer and flow into the lower electrode 28. As a result, a current flows between the upper electrode 25 and the lower electrode 28, and the SiC semiconductor device is turned on. In this embodiment, since the electrons that have passed through the channel pass through the JFET layer 14 and the low concentration layer 13 and flow into the substrate 11, it can be said that a drift layer 17 having the JFET layer 14 and the low concentration layer 13 is configured.

[0053] As described above, the JFET layer 14 is arranged only on the cell region 1 side of the cell region 1 and the connecting portion 2b, and is not arranged on the outer side. This configuration improves the switching tolerance when the vertical MOSFET is turned on and off based on the application of a gate voltage. This switching tolerance will be described below.

[0054] Fig. 5 shows a comparative example assuming that the JFET layer 14 is formed not only in the cell region 1 but also in the connecting portion 2b etc. Fig. 5 shows the state of the displacement current A1 in a cross section of the SiC semiconductor device cut along the Y direction, which is the longitudinal direction of the trench gate structure, between adjacent trench gate structures, i.e., at a position other than the trench gate structure.

[0055] During high-speed switching of the vertical MOSFET, a displacement current A1 flows as shown by the dashed arrow in FIG. 5. That is, in the peripheral region 2, the displacement current A1 flows from the lower electrode 28 through the substrate 11, the low-concentration layer 13, and the JFET layer 14 to the connecting layer 15a, then reaches the base layer 18 and the contact region 20, and flows to the upper electrode 25 while moving in the surface direction of the semiconductor substrate 10 in the contact region 20. The displacement current A1 at this time is proportional to the time change dV / dt of the high voltage generated during switching. The higher the impurity concentration of the p-type layer and the n-type layer constituting the pn junction in the peripheral region 2, the larger the source-drain capacitance becomes, so the time change dV / dt becomes larger, and the displacement current A1 becomes larger. When the JFET layer 14 is formed in the connecting portion 2b as in the comparative example shown in FIG. 5, the pn junction is constituted by the JFET layer 14 and the connecting layer 15a, and the impurity concentration becomes larger. As a result, when the displacement current A1 becomes large and electric field concentration occurs, the thin gate insulating film 22 is destroyed, and switching withstand capability cannot be obtained. In particular, dielectric breakdown occurs at the boundary position RB between the gate insulating film 22 and the field oxide film 241 shown in the figure.

[0056] In contrast, if the JFET layer 14 is not provided at least on the outer edge side of the junction 2b as in this embodiment, the pn junction in that portion is composed of the low concentration layer 13 and the first deep layer 15. Because of this structure, in this embodiment, the impurity concentrations of the p-type layer and n-type layer that constitute the pn junction are lower than in the comparative example, and the displacement current A1 that occurs when the voltage suddenly increases during switching can be reduced. Therefore, the electric field concentration caused by the displacement current A1 is alleviated, the breakdown of the gate insulating film 22 can be suppressed, and the switching resistance can be improved.

[0057] In particular, the electric field applied to the gate insulating film 22 is likely to be large below the gate wiring 26. For this reason, it is preferable to prevent the JFET layer 14 from being formed below the gate wiring 26 and to arrange the outer periphery termination position Po, which is the termination position of the JFET layer 14 on the outer periphery side of the cell region 1, to be closer to the cell region 1 than the inner periphery termination position Pi of the gate wiring 26. With such a structure, it is possible to further suppress the breakdown of the gate insulating film 22 and improve the switching resistance.

[0058] Next, a method for manufacturing the SiC semiconductor device of this embodiment will be described with reference to Figures 6A to 6E. Figures 6A to 6E show manufacturing steps corresponding to a cross section of the cell region 1 and the connecting portion 2b in Figure 4.

[0059] 6A, a substrate 11 is prepared, and then a buffer layer 12 and a low-concentration layer 13 are epitaxially grown on one surface of the substrate 11. Then, a mask (not shown) having an opening corresponding to the JFET layer 14 is placed on the surface of the low-concentration layer 13, and then n-type impurities are ion-implanted to form the JFET layer 14.

[0060] Next, a mask (not shown) having an opening in a portion corresponding to the first deep layer 15 is formed again, and then p-type impurities are ion-implanted to form the first deep layer 15 as shown in FIG. 6B. At this time, the JFET layer 14 is formed up to the portion that will become the first deep layer 15, but by increasing the dose of the p-type impurities, the first deep layer 15 can be formed by turning back to p-type. In addition, a mask (not shown) having an opening in a portion corresponding to the base layer 18 is formed, and then p-type impurities are ion-implanted to form the base layer 18. Furthermore, p-type impurities are further ion-implanted using a mask having an opening in a portion corresponding to the contact region 20 to form the contact region 20 on the base layer 18.

[0061] Thereafter, a mask (not shown) having an opening corresponding to the source region 19 is formed, and then n-type impurities are ion-implanted to form the source region 19 as shown in Fig. 6C. At this time, the contact region 20 is formed up to the portion that will become the source region 19, but by increasing the dose of the n-type impurity, it is possible to convert it back to n-type and form the source region 19.

[0062] 6D, a mask 50 having an opening corresponding to the trench 21 is placed, and then the trench 21 is formed by dry etching. In addition, the same mask 50 is used to ion-implant p-type impurities to form a second deep layer 30 at the bottom of the trench 21.

[0063] 6E, after forming the gate insulating film 22 by thermal oxidation or CVD, the gate electrode 23 is formed by forming and patterning doped polysilicon. Furthermore, after performing the steps of forming the field oxide film 241 and the interlayer insulating film 242, contact holes 242a and 242b are formed in the interlayer insulating film 242. Thereafter, the steps of forming the upper electrode 25 and the gate wiring 26, the step of forming the protective film 27, and the step of forming the lower electrode 28 on the back side of the substrate 11 are performed by the conventional steps. In this way, the SiC semiconductor device according to this embodiment is completed.

[0064] The SiC semiconductor device thus formed has a structure in which the JFET layer 14 is formed on the cell region 1 side of the connecting portion 2b, but the JFET layer 14 is not formed on the outside thereof. Also, the JFET layer 14 is not disposed below the gate wiring 26 of the connecting portion 2b, but is disposed only on the cell region 1 side of the gate wiring 26.

[0065] As described above, in the SiC semiconductor device of this embodiment, the JFET layer 14 is formed on the cell region 1 side of the connecting portion 2b, but the JFET layer 14 is not formed on the outside of the connecting portion 2b. Therefore, the pn junction of the outer edge side of the connecting portion 2b is composed of the low concentration layer 13 and the first deep layer 15. Because of this structure, the impurity concentration of the p-type layer and the n-type layer constituting the pn junction is reduced, and the displacement current A1 generated when the voltage suddenly increases during switching can be reduced. Therefore, the electric field concentration caused by the displacement current A1 is alleviated, the destruction of the gate insulating film 22 can be suppressed, and the switching resistance can be improved. And this effect can be obtained regardless of the rate-determining location of the resistance. Therefore, it is possible to obtain a SiC semiconductor device that can improve the switching resistance regardless of the rate-determining location of the resistance. In addition, since the switching resistance can be improved, the switching speed of the vertical MOSFET can be increased.

[0066] In particular, the electric field applied to the gate insulating film 22 is likely to be large below the gate wiring 26, but the JFET layer 14 is not formed in that portion, and the outer periphery termination position Po of the JFET layer 14 is made closer to the cell region 1 than the inner periphery termination position Pi of the gate wiring 26. This makes it possible to further suppress breakdown of the gate insulating film 22 and improve switching resistance.

[0067] Furthermore, when the distance of the current path is shortened as in Patent Document 1, the ends of structures such as source contacts, field oxide films, and trenches are crowded together, making it difficult to manufacture each component with precision, which makes the manufacturing process unstable and reduces yields. In contrast, the configuration of this embodiment can improve switching tolerance regardless of the distance of the current path, thereby suppressing a decrease in yields.

[0068] Furthermore, since the switching tolerance can be improved by simply limiting the formation position of the JFET layer 14 to the cell region 1 side of the connecting portion 2b and the cell region 1 side, it is only necessary to change the mask for forming the JFET layer 14 from the conventional manufacturing method. This makes it possible to simplify the manufacturing process.

[0069] Second embodiment The second embodiment will be described. This embodiment is different from the first embodiment in that the range in which the JFET layer 14 is formed is changed, and other aspects are the same as those of the first embodiment, so only the differences from the first embodiment will be described.

[0070] In the first embodiment, the JFET layer 14 is formed on the cell region 1 and on the cell region 1 side of the connecting portion 2b. In this embodiment, however, the JFET layer 14 is formed only on the cell region 1.

[0071] In addition, in the first embodiment, the formation ranges of the ion implantation layers for forming the JFET layer 14 and the source region 19 were set separately, but in the present embodiment, the formation ranges of the ion implantation layers for forming the JFET layer 14 and the source region 19 are aligned in the normal direction to the surface of the substrate 11.

[0072] 7, the JFET layer 14 is formed only in the cell region 1, and is not formed in the peripheral region 2 including the junction portion 2b. The range in which the ion-implanted layer is formed when the JFET layer 14 is formed is limited to the cell region 1. In addition, the range in which the n-type impurity ions are implanted when the source region 19 is formed is set to the same as the range in which the JFET layer 14 is formed, as shown in FIG. 8B described later.

[0073] The formation range of the ion implantation layer for forming the JFET layer 14 means the entire range where the n-type impurity ions are implanted when the JFET layer 14 is formed as viewed from the normal direction of the substrate 11. This range also includes the part that becomes the p-type first deep layer 15 by the return of the p-type impurity. The formation range of the ion implantation layer for forming the source region 19 means the entire range where the n-type impurity ions are implanted when the source region 19 is formed as viewed from the normal direction of the substrate 11. This range also includes the part that becomes the p-type contact region 20 by the return of the p-type impurity. The formation range of the ion implantation layer is preferably the same, but means that it is manufactured with the aim of becoming the same formation range, and may include manufacturing errors. The dashed line shown in FIG. 7 indicates the ion implantation range of the n-type impurity when forming the source region 19.

[0074] In this way, by aligning the formation ranges of the ion implantation layers when forming the JFET layer 14 and the source region 19, a common ion implantation mask can be used when forming the JFET layer 14 and the source region 19 by ion implantation. A method for manufacturing a SiC semiconductor device according to this embodiment will be described with reference to Figures 8A to 8E. Figures 8A to 8E show manufacturing steps corresponding to the cross section of the cell region 1 and the connecting portion 2b in Figure 4.

[0075] First, in the process shown in FIG. 8A, a buffer layer 12 and a low concentration layer 13 are formed on a substrate 11 in the same manner as in FIG. 6A, and then a JFET layer 14 is formed. At this time, a mask 51 having an opening corresponding to the JFET layer 14 is placed on the surface of the low concentration layer 13, and then n-type impurities are ion-implanted to form the JFET layer 14, so that ion implantation is performed only in the cell region 1. Next, as shown in FIG. 8B, the mask 51 used in forming the JFET layer 14 is used as it is to ion-implant n-type impurities to form a source region 19. Note that the implantation depths of the JFET layer 14 and the source region 19 are made different by changing the ion implantation energy.

[0076] 8C, the first deep layer 15, the base layer 18, and the contact region 20 are formed by performing the same process as in FIG. 6C. When the contact region 20 is formed, the source region 19 is formed up to the portion that will become the contact region 20, but the dose of the p-type impurity can be increased to drive it back to p-type and form the contact region 20.

[0077] 8D, a process similar to that shown in FIG. 6D is performed to form a trench 21, and then a second deep layer 30 is formed. Furthermore, a process similar to that shown in FIG. 6E is performed to form a gate insulating film 22, a gate electrode 23, a field oxide film 241 and an interlayer insulating film 242, and contact holes 242a and 242b in the interlayer insulating film 242. Thereafter, a process of forming an upper electrode 25 and a gate wiring 26, a process of forming a protective film 27, and a process of forming a lower electrode 28 on the back side of the substrate 11 are performed. This completes the SiC semiconductor device according to this embodiment.

[0078] As described above, in this embodiment, the formation ranges of the ion implantation layers for forming the JFET layer 14 and the source region 19 are aligned. This allows the ion implantation masks for the JFET layer 14 and the source region 19 to be shared, making it possible to simplify the manufacturing process and reduce manufacturing costs.

[0079] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0080] For example, in each of the above embodiments, the connecting portion 2b is structured to include the base layer 18 and the contact region 20 in the surface layer of the low concentration layer 13, but one or both of these may not be included in the connecting portion 2b. When the base layer 18 is formed only in the cell region 1, the base layer 18 can also be formed using the ion implantation mask for the JFET layer 14 and the source region 19 as in the second embodiment. In this way, the ion implantation mask for the base layer 18 in addition to the JFET layer 14 and the source region 19 can be shared, which further simplifies the manufacturing process and reduces manufacturing costs.

[0081] In the first embodiment, the outer peripheral end position Po of the JFET layer 14 of the connecting portion 2b is located closer to the cell region 1 than the inner peripheral end position Pi of the gate wiring 26, and the outer side is either formed with the connecting layer 15a or is the low concentration layer 13. In other words, the JFET layer 14 is not formed outside the inner peripheral end position Pi of the gate wiring 26. In contrast, the JFET layer 14 may be formed outside the inner peripheral end position Pi of the gate wiring 26, while the n-type impurity concentration of that portion may be equal to or lower than the low concentration layer 13. In this way, even if the JFET layer 14 is formed, if the n-type impurity concentration is lowered outside the inner peripheral end position Pi of the gate wiring 26, the impurity concentration of the p-type layer and n-type layer constituting the pn junction in the outer peripheral region 2 is lowered, and the source-drain capacitance can be reduced. Therefore, the same effect as in the first embodiment can be obtained.

[0082] In the above embodiment, the bottom surface of the second deep layer 30 may be shallowed and positioned within the JFET layer 14 and the first deep layer 15. In other words, the second deep layer 30 may be formed so as not to reach the low concentration layer 13. This makes it difficult for a depletion layer to extend from the second deep layer 30, thereby reducing the on-resistance.

[0083] In the first embodiment, the JFET layer 14, the first deep layer 15, the base layer 18, the contact region 20, and the source region 19 are formed by ion implantation. A part or all of these may be composed of an epitaxial layer formed by epitaxial growth.

[0084] In the above embodiment, the base layer 18 is formed on the surfaces of the JFET layer 14 and the first deep layer 15, but an n-type current spreading layer having a higher n-type impurity concentration than the low concentration layer 13 may be formed between them. In that case, in addition to the current spreading layer, a p-type coupling layer may be formed on both sides of the trench 21, and the base layer 18 may be formed on these current spreading layers and coupling layers. In this case, the first deep layer 15 and the base layer 18 are connected through the coupling layer. In addition, the low concentration layer 13, the JFET layer 14, and the current spreading layer are connected, and the drift layer 17 is formed by these. Even in such a structure, the second deep layer 30 may be formed deeper than the first deep layer 15, or may be formed to a depth within the thickness of the first deep layer 15.

[0085] In the above embodiment, a vertical MOSFET with an n-channel type trench gate structure in which the first conductivity type is n-type and the second conductivity type is p-type is taken as an example of the semiconductor element provided in the cell region 1. However, this is merely an example, and a vertical MOSFET with a p-channel type trench gate structure in which the conductivity types of each component are inverted from the n-channel type may be used. Furthermore, instead of a vertical MOSFET, a vertical IGBT with a similar structure may be used. In the case of an IGBT, it is the same as the vertical MOSFET described in the above embodiment, except that the conductivity type of the substrate 11 in each of the above embodiments is changed from n-type to p-type.

[0086] When indicating a crystal orientation, a bar (-) should normally be placed above the desired number. However, due to limitations on expression based on electronic filing, a bar is placed before the desired number in this specification. [Explanation of symbols]

[0087] 1... cell region, 2... outer peripheral region, 2a... guard ring portion, 2b... connecting portion, 11... substrate 13...Low concentration layer (first impurity region), 14...JFET layer, 15...First deep layer 16: guard ring, 17: drift layer, 18: base layer, 19: source region 20: contact region, 21: trench, 22: gate insulating film, 23: gate electrode 24...interlayer insulating film, 25...upper electrode (first electrode), 26...gate wiring 27: protective film, 28: lower electrode (second electrode), 30: second deep layer Pi: inner circumference end position, Po: outer circumference end position

Claims

1. A silicon carbide semiconductor device having a cell region (1) in which a semiconductor element having a trench gate structure is formed, and an outer periphery region (2) provided on an outer periphery surrounding the cell region with a peripheral breakdown withstanding structure part (2a) constituting a peripheral breakdown withstanding structure (16) and a connecting part (2b) located between the peripheral breakdown withstanding structure part and the cell region, A substrate (11) made of silicon carbide of a first conductivity type or a second conductivity type; A first impurity region (13) of a first conductivity type is formed on the substrate and has a lower impurity concentration than the substrate, The cell region includes: a JFET layer (14) made of silicon carbide of a first conductivity type formed in a surface layer portion of the first impurity region and having a higher impurity concentration than the first impurity region; deep layers (15) made of second conductivity type silicon carbide formed in a surface layer portion of the first impurity region and arranged alternately with the JFET layers in a surface direction of the substrate; a base layer (18) made of second conductivity type silicon carbide formed on the JFET layer and the deep layer; a trench gate structure including a gate insulating film (22) formed on an inner wall surface of a plurality of gate trenches (21) arranged in one direction deeper than the base layer and with a longitudinal direction in one direction, and a gate electrode (23) formed on the gate insulating film in the gate trench; a second impurity region (19) formed in a surface layer portion of the base layer in contact with the trench gate structure and made of silicon carbide of the first conductivity type having a higher impurity concentration than the first impurity region; a first electrode (25) electrically connected to the second impurity region and the base layer; The semiconductor element is configured to have a second electrode (28) disposed on the back side of the substrate and electrically connected to the substrate, The connecting portion has a gate insulating film extending from the cell region and formed on the first impurity region; a gate electrode extending from the cell region and disposed on the gate insulating film; a gate wiring (26) connected to the gate electrode; A silicon carbide semiconductor device, wherein an outer periphery termination position (Po), which is a termination position on the outer periphery side of the cell region in the JFET layer, is located closer to the cell region than an inner periphery termination position (Pi), which is a termination position on the cell region side of the gate wiring.

2. The silicon carbide semiconductor device according to claim 1 , wherein said JFET layer is formed only in said cell region.

3. 3. The silicon carbide semiconductor device according to claim 1, wherein a formation range of an ion implantation layer for forming the JFET layer and a formation range of an ion implantation layer for forming the second impurity region are aligned in a normal direction to a surface of the substrate.

4. 3. The silicon carbide semiconductor device according to claim 1, wherein a formation range of an ion implantation layer for forming said JFET layer, a formation range of an ion implantation layer for forming said second impurity region, and a formation range of an ion implantation layer for forming said base layer are aligned in a normal direction to a surface of said substrate.

5. A silicon carbide semiconductor device having a cell region (1) in which a semiconductor element having a trench gate structure is formed, and an outer periphery region (2) provided on an outer periphery surrounding the cell region with a peripheral breakdown withstanding structure part (2a) constituting a peripheral breakdown withstanding structure (16) and a connecting part (2b) located between the peripheral breakdown withstanding structure part and the cell region, A substrate (11) made of silicon carbide of a first conductivity type or a second conductivity type; A first impurity region (13) of a first conductivity type is formed on the substrate and has a lower impurity concentration than the substrate, The cell region includes: a JFET layer (14) made of silicon carbide of a first conductivity type formed in a surface layer portion of the first impurity region and having a higher impurity concentration than the first impurity region; deep layers (15) made of second conductivity type silicon carbide formed in a surface layer portion of the first impurity region and arranged alternately with the JFET layers in a surface direction of the substrate; a base layer (18) made of second conductivity type silicon carbide formed on the JFET layer and the deep layer; a trench gate structure including a gate insulating film (22) formed on an inner wall surface of a plurality of gate trenches (21) arranged in one direction deeper than the base layer and with a longitudinal direction in one direction, and a gate electrode (23) formed on the gate insulating film in the gate trench; a second impurity region (19) formed in a surface layer portion of the base layer in contact with the trench gate structure and made of silicon carbide of the first conductivity type having a higher impurity concentration than the first impurity region; a first electrode (25) electrically connected to the second impurity region and the base layer; The semiconductor element is configured to have a second electrode (28) disposed on the back side of the substrate and electrically connected to the substrate, The connecting portion has a gate insulating film extending from the cell region and formed on the first impurity region; a gate electrode extending from the cell region and disposed on the gate insulating film; a gate wiring (26) connected to the gate electrode; the JFET layer is also formed in the connecting portion, and a portion of the JFET layer that is outside an inner circumference termination position (Pi), which is an termination position of the gate wiring on the cell region side, has a first conductivity type impurity concentration that is equal to or lower than the first impurity region.

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