Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of maintaining assemblability and improving stress tolerance.SOLUTION: A semiconductor device includes a plurality of trenches, a plurality of trench electrodes, an insulation film, and a first electrode. Each of the plurality of trench electrodes is provided inside the plurality of trenches. The insulation film covers two or more trench electrodes of the plurality of trench electrodes. The first electrode is provided on the insulation film. The insulation film includes an opening provided between two or more trench electrodes covered by the insulation film. The first electrode is provided on a semiconductor substrate so as to block the opening. The upper surface of each of the plurality of trench electrodes includes a first recess. The upper surface of the insulation film includes a second recess directly above the first recess. The upper surface of the first electrode includes a third recess directly above the opening.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] The semiconductor device has a structure in which semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and diodes are provided on a semiconductor substrate. The semiconductor device described in Patent Document 1 has contact plugs that connect the semiconductor substrate and a wiring layer. The contact plugs flatten the electrodes formed thereon, improving the ease of assembly in the subsequent manufacturing process of the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-29581 A Summary of the Invention [Problem to be solved by the invention]

[0004] When wiring or electrodes provided on a semiconductor substrate are planarized, the interfaces of the layers formed on the upper surface of the semiconductor substrate are also planarized, making the layer structure vulnerable to lateral stress.

[0005] In order to solve the above problems, an object of the present disclosure is to provide a semiconductor device that maintains ease of assembly and has improved stress resistance. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a plurality of trenches, a plurality of trench electrodes, an insulating film, and a first electrode. The plurality of trenches are provided on an upper surface of a semiconductor substrate. The plurality of trench electrodes are provided inside the plurality of trenches, respectively. The insulating film covers two or more of the plurality of trench electrodes. The first electrode is provided on the insulating film. The insulating film includes an opening provided between the two or more trench electrodes covered by the insulating film. The first electrode is provided on the semiconductor substrate so as to close the opening. An upper surface of each of the plurality of trench electrodes includes a first recess. An upper surface of the insulating film includes a second recess directly above the first recess. An upper surface of the first electrode includes a third recess directly above the opening. Effect of the Invention

[0007] According to the present disclosure, a semiconductor device is provided that maintains ease of assembly and improves stress resistance.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to an embodiment; [Diagram 2] 1 is a plan view showing a configuration of a semiconductor device according to an embodiment; [Diagram 3] 2 is a partial enlarged plan view showing the configuration of an IGBT region of the semiconductor device. FIG. [Figure 4] 2 is a cross-sectional view showing a configuration of an IGBT region of the semiconductor device. [Diagram 5] FIG. 2 is a partially enlarged cross-sectional view showing the configuration of an IGBT region. [Figure 6] FIG. 2 is a partially enlarged cross-sectional view showing the configuration of an IGBT region. [Figure 7] FIG. 2 is a partially enlarged cross-sectional view showing the configuration of an IGBT region. [Figure 8] 2 is a cross-sectional view showing a configuration of an IGBT region of the semiconductor device. [Figure 9]2 is a partial enlarged plan view showing a configuration of a diode region of the semiconductor device; [Figure 10] 2 is a cross-sectional view showing a configuration of a diode region of the semiconductor device; [Figure 11] 2 is a cross-sectional view showing a configuration of a diode region of the semiconductor device; [Figure 12] 4 is a cross-sectional view showing a configuration of a boundary portion between an IGBT region and a diode region. [Figure 13] 4 is a cross-sectional view showing the configuration of a boundary portion between an IGBT region and a termination region. [Figure 14] 4 is a cross-sectional view showing a configuration of a boundary portion between a diode region and a termination region. FIG. [Figure 15] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 16] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 17] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 18] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 20] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 21] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 22] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 23] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 24] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 26] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, n and p indicate the conductivity type of the semiconductor. - indicates that the impurity concentration is lower than n.+ indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p. + indicates that the impurity concentration is higher than p. The p-type and n-type of each layer shown below may be interchanged.

[0011] (1) Overall planar structure of the semiconductor device Fig. 1 is a plan view showing the configuration of a semiconductor device 100 according to an embodiment. Fig. 2 is a plan view showing the configuration of a semiconductor device 101 according to an embodiment. The semiconductor devices 100 and 101 are RC-IGBTs (Reverse Conducting IGBTs) in which an IGBT (Insulated Gate Bipolar Transistor) region 10 and a diode region 20 are provided in one semiconductor substrate. The semiconductor substrate is formed of a semiconductor such as Si, for example. The semiconductor is preferably formed of a so-called wide band gap semiconductor such as SiC, GaN, or gallium oxide.

[0012] 1, in the semiconductor device 100, an IGBT region 10 and a diode region 20 extend in a direction from one end of the semiconductor device 100 to the other end. The IGBT regions 10 and the diode regions 20 are alternately provided in a direction perpendicular to the extension direction. The semiconductor device 100 has a stripe-type structure in which the IGBT regions 10 and the diode regions 20 are arranged side by side in stripes.

[0013] The semiconductor device 100 includes three IGBT regions 10 and two diode regions 20. The numbers of the IGBT regions 10 and the diode regions 20 are not limited to these. The number of the IGBT regions 10 may be three or more, or three or less. The number of the diode regions 20 may be two or more, or two or less.

[0014] The diode region 20 of the semiconductor device 100 is sandwiched between two IGBT regions 10. The arrangement of the IGBT regions 10 and the diode regions 20 is not limited to this. The arrangement may be such that the IGBT regions 10 and the diode regions 20 are interchanged. In other words, the IGBT region 10 may be sandwiched between two diode regions 20. It is sufficient that the IGBT regions 10 and the diode regions 20 are provided alternately adjacent to each other.

[0015] 2, in the semiconductor device 101, a plurality of diode regions 20 are provided discretely in the vertical and horizontal directions. That is, the diode regions 20 are provided in a matrix shape. The IGBT region 10 is provided around the diode regions 20. The semiconductor device 101 has such an island-type structure.

[0016] In the semiconductor device 101, four diode regions 20 are arranged in the horizontal direction, and two diode regions 20 are arranged in the vertical direction. The number and arrangement of the diode regions 20 are not limited to this. It is sufficient that one or a plurality of diode regions 20 are provided interspersed within the IGBT region 10. In other words, it is sufficient that each diode region 20 is surrounded by the IGBT region 10.

[0017] A plurality of IGBT cells (not shown) are formed in the IGBT region 10 of the semiconductor devices 100 and 101. Each of the plurality of IGBT cells includes an IGBT as a semiconductor element. A plurality of diode cells (not shown) are formed in the diode region 20. Each of the plurality of diode cells includes a free wheel diode as a semiconductor element. Furthermore, one cell structure is a structure corresponding to the minimum unit of an element. The region including the IGBT region 10 and the diode region 20 is called a cell region.

[0018] As shown in FIGS. 1 and 2, semiconductor devices 100, 101 include a pad region 40 and a termination region 30 in addition to an IGBT region 10 and a diode region 20. As shown in FIG.

[0019] The pad region 40 is provided outside the cell region, i.e., outside the IGBT region 10 and the diode region 20. Here, the pad region 40 is provided adjacent to at least a part of the IGBT region 10. The pad region 40 is a region where control pads 41 for controlling the semiconductor devices 100, 101 are provided. The control pads 41 include, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d, 41e.

[0020] The current sense pad 41a is a control pad for detecting the current flowing through the cell region. The current sense pad 41a is electrically connected to a portion of the IGBT cells or diode cells in the cell region so that a current that is a fraction to a few ten-thousandth of the current flowing through the entire cell region flows through the current sense pad 41a.

[0021] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for controlling the on / off of the semiconductor devices 100 and 101. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 41b and the p-type base layer are electrically connected to the p-type source layer (both not shown). + They may be electrically connected to each other via a mold contact layer (not shown). The gate pad 41c is electrically connected to a gate trench electrode (not shown) of the IGBT cell.

[0022] The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region. The temperature sensing diode pads 41d and 41e measure the voltage between the anode and cathode of the temperature sensing diode to measure the temperature of the semiconductor device 100 and 101.

[0023] The termination region 30 is provided around the combined region of the cell region and the pad region 40. The termination region 30 has a structure for maintaining the breakdown voltage of the semiconductor device 100, 101. Various structures are appropriately selected for the breakdown voltage structure. The breakdown voltage structure is, for example, a field limiting ring (FLR) or variation of lateral doping (VLD) formed on the surface layer of the first main surface side (upper surface side) of the semiconductor substrate. The FLR has a p-type termination well layer (not shown) surrounding the cell region. The VLD has a p-type well layer (not shown) surrounding the cell region and having a concentration gradient. The number of ring-shaped p-type termination well layers constituting the FLR and the concentration distribution of the p-type well layer constituting the VLD are appropriately selected according to the breakdown voltage design of the semiconductor device 100, 101. In addition, the pad region 40 may be provided with a p-type termination well layer over almost the entire region. Alternatively, the pad region 40 may be provided with an IGBT cell or a diode cell.

[0024] (2) Structure of IGBT region 10 3 is a partial enlarged plan view showing the configuration of the IGBT region 10 of the semiconductor devices 100 and 101. FIG 3 shows an enlarged view of the configuration in a region 82 shown in FIG 1 or FIG 2.

[0025] The semiconductor device 100 and the semiconductor device 101 each include an active trench 11 and a dummy trench 12 provided in an IGBT region 10 .

[0026] In the semiconductor device 100, the active trenches 11 and the dummy trenches 12 extend in the longitudinal direction of the IGBT region 10. The active trenches 11 and the dummy trenches 12 have their longitudinal direction in the extension direction of the IGBT region 10. The longitudinal direction of the IGBT region 10 corresponds to the left-right direction in FIG.

[0027] In the semiconductor device 101, the active trenches 11 and the dummy trenches 12 extend in one direction. For example, the active trenches 11 and the dummy trenches 12 extend in either the up-down direction or the left-right direction in FIG.

[0028] The active trench 11 includes a gate trench electrode 11a and a gate trench insulating film 11b. Although the cross-sectional structure of the active trench 11 will be described in detail later, the gate trench insulating film 11b is formed along the inner wall of a trench structure formed in the depth direction from the first main surface, i.e., the upper surface, of the semiconductor substrate. The gate trench electrode 11a is formed inside the trench structure via the gate trench insulating film 11b. The gate trench electrode 11a is electrically connected to a gate pad 41c (not shown).

[0029] The dummy trench 12 includes a dummy trench electrode 12a and a dummy trench insulating film 12b. The cross-sectional structure of the dummy trench 12 will be described in detail later, but the dummy trench insulating film 12b is formed along the inner wall of a trench structure formed in the depth direction from the first main surface of the semiconductor substrate. The dummy trench electrode 12a is formed inside the trench structure via the dummy trench insulating film 12b. The dummy trench electrode 12a is electrically connected to an emitter electrode 6 (see FIG. 4) provided above the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0030] In the IGBT region 10, in the region where the active trench 11 is provided, the surface layer on the first main surface side of the semiconductor substrate is + Type source layer 13 and p + A contact layer 14 is optionally provided. + The source layer 13 and the p + The contact layers 14 are alternately provided along the extension direction of the active trenches 11. + Type source layer 13 and p +The gate trench insulating film 11b of the active trench 11 is provided so as to cross the n-type contact layer 14. + It is in contact with the mold source layer 13 .

[0031] In the IGBT region 10, in the region where the dummy trench 12 is provided, the surface layer on the first main surface side of the semiconductor substrate is made of p + A contact layer 14 is provided. + The mold contact layer 14 is provided between two adjacent dummy trenches 12 .

[0032] In FIG. 3, three dummy trenches 12 are arranged next to three active trenches 11. Furthermore, another three active trenches 11 are arranged next to the three dummy trenches 12. That is, a set of active trench groups including three active trenches 11 and a set of dummy trench groups including three dummy trenches 12 are arranged alternately. The number of active trenches 11 included in one set of active trench groups is not limited to three, and may be one or more. Moreover, the number of dummy trenches 12 included in one set of dummy trench groups is not limited to three, and may be one or more. However, the dummy trenches 12 are not necessarily required in the semiconductor devices 100 and 101. That is, all trenches provided in the IGBT region 10 may be active trenches 11.

[0033] 4 is a cross-sectional view showing the configuration of the IGBT region 10 of the semiconductor devices 100 and 101. Fig. 4 shows a cross section taken along dashed line AA shown in Fig. 3.

[0034] The semiconductor devices 100 and 101 have an IGBT region 10, + Type source layer 13, p + a p-type contact layer 14, a p-type base layer 15, an n-type carrier accumulation layer 2, -The semiconductor device includes a first drift layer 1, an n-type buffer layer 3, a p-type collector layer 16, an active trench 11, a dummy trench 12, an interlayer insulating film 4, a barrier metal 5, an emitter electrode 6, and a collector electrode .

[0035] One IGBT cell corresponds to an area divided by, for example, the active trench 11. The IGBT cell is + 1, p-type source layer 13, p-type base layer 15, n-type carrier accumulation layer 2, - The semiconductor device includes a n-type drift layer 1, an n-type buffer layer 3, a p-type collector layer 16, an active trench 11, an interlayer insulating film 4, a barrier metal 5, an emitter electrode 6, and a collector electrode .

[0036] The first main surface of the semiconductor substrate in the IGBT region 10 is n + The source layer 13 and the p + The first main surface corresponds to the surface (upper surface) of the p-type contact layer 14. The first main surface is the upper surface of the semiconductor substrate. The second main surface of the semiconductor substrate in the IGBT region 10 corresponds to the surface (lower surface) of the p-type collector layer 16. The second main surface is the surface opposite to the first main surface, which is the lower surface of the semiconductor substrate. In FIG. 4, the semiconductor substrate is + The source layer 13 and the p + This corresponds to the range from the upper surface of p-type contact layer 14 to the lower surface of p-type collector layer 16 .

[0037] n - The n-type drift layer 1 is made of a semiconductor substrate. - The n-type drift layer 1 is provided between a first main surface and a second main surface of a semiconductor substrate. - The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic (As) or phosphorus (P) as an n-type impurity. - The concentration of n-type impurities in the drift layer 1 is preferably 1.0E+12 / cm 3 More than 1.0E+15 / cm 3 The following is the result.

[0038] The n-type carrier accumulation layer 2 is -The n-type carrier accumulation layer 2 is provided on the first main surface side of the semiconductor substrate with respect to the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. - The n-type impurity concentration in the n-type carrier accumulation layer 2 is higher than that in the n-type drift layer 1. The n-type impurity concentration in the n-type carrier accumulation layer 2 is preferably 1.0E+13 / cm 3 More than 1.0E+17 / cm 3 The n-type carrier accumulation layer 2 reduces the current loss when a current flows through the IGBT region 10. - The n-type drift layer 1 and the n-type drift layer 2 may be defined as one n-type drift layer. The n-type carrier accumulation layer 2 is not necessarily required, and an n-type - A type drift layer 1 may be provided.

[0039] The p-type base layer 15 is provided on the first main surface side of the semiconductor substrate with respect to the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the p-type base layer 15 is preferably 1.0E+12 / cm 3 More than 1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench 11. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15.

[0040] n + The n-type source layer 13 is provided on the first main surface side of the semiconductor substrate with respect to the p-type base layer 15. + The n-type source layer 13 is selectively provided above the p-type base layer 15 as a surface layer of the semiconductor substrate. + The n-type source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. + The concentration of n-type impurities in the n-type source layer 13 is preferably 1.0E+17 / cm 3 More than 1.0E+20 / cm 3 The following is true: +The n-type source layer 13 is + This may be called the type emitter layer.

[0041] p + The p-type contact layer 14 is provided on the first main surface side of the semiconductor substrate with respect to the p-type base layer 15. + The p-type contact layer 14 is selectively provided above the p-type base layer 15 as a surface layer of the semiconductor substrate. + The n-type contact layer 14 is disposed above the p-type base layer 15. + The p-type source layer 13 is not provided in the region. + The p-type contact layer 14 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. + The concentration of the p-type impurity in the p-type contact layer 14 is higher than the concentration of the p-type impurity in the p-type base layer 15. + The concentration of the p-type impurity in the contact layer 14 is preferably 1.0E+15 / cm 3 More than 1.0E+20 / cm 3 The following is the result. + The p-type contact layer 14 and the p-type base layer 15 may be defined together as one p-type base layer.

[0042] The n-type buffer layer 3 is - The n-type buffer layer 3 is provided on the second main surface side of the semiconductor substrate with respect to the n-type drift layer 1. The n-type buffer layer 3 contains n-type impurities such as phosphorus and protons (H + The n-type buffer layer 3 is a semiconductor layer including at least one of the following: - The n-type buffer layer 3 has a higher n-type impurity concentration than the n-type drift layer 1. The n-type impurity concentration in the n-type buffer layer 3 is preferably 1.0E+12 / cm 3 More than 1.0E+18 / cm 3 The n-type buffer layer 3 prevents a depletion layer from extending from the p-type base layer 15 to the second main surface side and causing punch-through when the semiconductor device 100 is in an off state. -The n-type drift layer 1 may be defined as a single n-type drift layer. - The n-type drift layer 1 and the n-type drift layer 2 may be defined as one n-type drift layer. The n-type buffer layer 3 is not necessarily required, and an n-type - A type drift layer 1 may be provided.

[0043] The p-type collector layer 16 is provided on the second main surface side of the semiconductor substrate with respect to the n-type buffer layer 3. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type collector layer 16 is preferably 1.0E+16 / cm 3 More than 1.0E+20 / cm 3 The following is the result.

[0044] The active trench 11 is provided on the first main surface of the semiconductor substrate, i.e., the upper surface of the semiconductor substrate. The active trench 11 is formed at n + The n-type source layer 13, the p-type base layer 15, and the n-type carrier accumulation layer 2 are penetrated. - The drift layer 1 has been reached.

[0045] The gate trench insulating film 11b is formed along the inner wall of a trench structure formed in the depth direction from the first main surface of the semiconductor substrate. + The gate trench insulating film 11b is in contact with the p-type source layer 13 and the p-type base layer 15. The gate trench insulating film 11b is, for example, an oxide film.

[0046] The gate trench electrode 11a is formed inside the trench structure via the gate trench insulating film 11b. The bottom of the gate trench electrode 11a is connected to the n-type semiconductor layer 11 via the gate trench insulating film 11b. -The gate trench electrode 11a faces the p-type drift layer 1. The gate trench electrode 11a is made of, for example, conductive polysilicon. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b.

[0047] The dummy trench 12 is provided on the first main surface of the semiconductor substrate, i.e., the upper surface of the semiconductor substrate. The dummy trench 12 is formed at a depth of p + The n-type contact layer 14, the p-type base layer 15, and the n-type carrier accumulation layer 2 are penetrated. - The drift layer 1 has been reached.

[0048] The dummy trench insulating film 12b is formed along the inner wall of a trench structure formed in the depth direction from the first main surface of the semiconductor substrate. The dummy trench insulating film 12b is, for example, an oxide film.

[0049] The dummy trench electrode 12a is formed inside the trench structure via the dummy trench insulating film 12b. The bottom of the dummy trench electrode 12a is connected to the n-type - The dummy trench electrode 12a faces the type drift layer 1. The dummy trench electrode 12a is made of, for example, conductive polysilicon.

[0050] The interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench 11.

[0051] The barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 is formed of a metal containing titanium, such as Ti, TiN, or TiSi. Examples of the metal containing titanium include titanium nitride and TiSi. TiSi is an alloy of titanium and silicon (Si). The barrier metal 5 is a n + Type source layer 13, p + The barrier metal 5 is in ohmic contact with the n-type contact layer 14 and the dummy trench electrode 12a. +Type source layer 13, p + The contact layer 14 is electrically connected to the dummy trench electrode 12a.

[0052] The emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 is formed of, for example, an aluminum silicon alloy (Al-Si alloy). The emitter electrode 6 is connected to the n + Type source layer 13, p + The emitter electrode 6 is electrically connected to the die contact layer 14 and the dummy trench electrode 12a. The emitter electrode 6 may be composed of a plurality of metal films made of an aluminum alloy film and other metal films. For example, the emitter electrode 6 may be composed of an aluminum alloy film and a plating film. The plating film is formed by, for example, electroless plating or electrolytic plating. The plating film is, for example, a nickel (Ni) film. A tungsten film may be formed in the fine region between the adjacent interlayer insulating films 4. The emitter electrode 6 is formed on the tungsten film. The tungsten film has better embedding properties than the plating film, so a good emitter electrode 6 is formed.

[0053] The barrier metal 5 and the emitter electrode 6 may be defined as one emitter electrode. The barrier metal 5 is not necessarily required. When the barrier metal 5 is not provided, the emitter electrode 6 is n + On type source layer 13, p + The barrier metal 5 is provided on the n-type contact layer 14 and the dummy trench electrode 12a and is in ohmic contact with them. + The emitter electrode 6 may be provided only on an n-type semiconductor layer such as an n-type source layer 13. An interlayer insulating film 4 may be provided on a part of the dummy trench electrode 12a. In this case, the emitter electrode 6 is electrically connected to the dummy trench electrode 12a in any region on the dummy trench electrode 12a.

[0054] The collector electrode 7 is provided on the p-type collector layer 16. The collector electrode 7 is made of, for example, an aluminum alloy, similar to the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16. The collector electrode 7 may be made of an aluminum alloy and a plating film. The collector electrode 7 may have a different structure from the emitter electrode 6.

[0055] As shown in FIG. 4, the semiconductor device 100 and the semiconductor device 101 include a plurality of active trenches 11 and a plurality of dummy trenches 12 as a plurality of trenches. Inside the active trench 11, a gate trench electrode 11a is provided as a first trench electrode. Inside the dummy trench 12, a dummy trench electrode 12a is provided as a second trench electrode. The gate trench electrode 11a and the dummy trench electrode 12a are collectively referred to as a plurality of trench electrodes. The interlayer insulating film 4 covers two or more first trench electrodes of the plurality of trench electrodes, that is, two or more gate trench electrodes 11a.

[0056] 5 is a partially enlarged cross-sectional view showing the configuration of the IGBT region 10. FIG 5 shows the configuration in a region P shown in FIG 4.

[0057] The upper surface of the gate trench electrode 11a includes a first recess 51. The first recess 51 is provided in the center of the upper end in the short side direction of the gate trench electrode 11a. The short side direction is a direction perpendicular to the extension direction of the gate trench electrode 11a. The bottom of the first recess 51 is provided at a position lower than the upper surface of the semiconductor substrate. The upper end of the gate trench electrode 11a is provided at a position lower than the upper surface of the semiconductor substrate.

[0058] The upper surface of the interlayer insulating film 4 includes a second recess 52 directly above the first recess 51. The second recess 52 is formed to follow the first recess 51. The second recess 52 is located in the center of the upper surface of the interlayer insulating film 4.

[0059] The interlayer insulating film 4 includes an opening 4a. The opening 4a is provided between a plurality of gate trench electrodes 11a covered with the interlayer insulating film 4. The width of the bottom of the opening 4a is preferably larger than the height of the interlayer insulating film 4 forming the sidewall of the opening 4a.

[0060] The interlayer insulating film 4 has, for example, a single-layer structure including an oxide film. The oxide film of the single-layer structure is formed, for example, of TEOS (Tetraethoxysilane). The interlayer insulating film 4 may have a laminated structure including a plurality of oxide films. When the interlayer insulating film 4 has a laminated structure, the plurality of oxide films are composed of two or more types of oxide films having different dopant concentrations. Of the two or more types of oxide films, one oxide film is formed of TEOS (BPTEOS) containing boron and phosphorus, and another oxide film is formed of TEOS.

[0061] The emitter electrode 6 includes a first emitter electrode 6b and a second emitter electrode 6c. The first emitter electrode 6b is provided on the semiconductor substrate so as to cover the opening 4a of the interlayer insulating film 4 via the barrier metal 5. In other words, the barrier metal 5 and the emitter electrode 6 are formed in the space of the opening 4a. However, the barrier metal 5 is not necessarily required. If the barrier metal 5 is not provided, the first emitter electrode 6b contacts the upper surface of the semiconductor substrate at the bottom of the opening 4a.

[0062] The upper surface of the first emitter electrode 6b includes a third recess 53 immediately above the second recess 52 and the opening 4a. The third recess 53 is formed to follow the second recess 52 or the opening 4a. The third recess 53 shown in FIG. 5 is formed immediately above both the second recess 52 and the opening 4a, but it is not necessarily required that it is formed immediately above the second recess 52.

[0063] The second emitter electrode 6c is provided on the first emitter electrode 6b. For example, the second emitter electrode 6c has a laminated structure including two or more types of metal layers. The laminated structure includes, for example, a Ni film, a Pd film, and an Au film in this order from the first main surface side of the semiconductor substrate.

[0064] The upper surface of the second emitter electrode 6c may include a fourth recess 54 directly above the third recess 53. The fourth recess 54 is formed to follow the third recess 53. The depth of the fourth recess 54 is preferably shallower than the depth of the third recess 53. The depth of the fourth recess 54 is preferably shallower than the depth of the second recess 52 and the depth of the opening 4a. The depth of the fourth recess 54 is preferably shallower than the depth of the first recess 51.

[0065] The thickness of the first emitter electrode 6b may be thicker than the thickness of the second emitter electrode 6c, or conversely, the thickness of the second emitter electrode 6c may be thicker than the thickness of the first emitter electrode 6b. When the thickness of the first emitter electrode 6b is thicker than the thickness of the second emitter electrode 6c, the stress resistance is improved. When the thickness of the second emitter electrode 6c is thicker than the thickness of the first emitter electrode 6b, the wettability of the surface of the second emitter electrode 6c is improved, and high assembly properties are achieved.

[0066] 6 and 7 are partially enlarged cross-sectional views showing the configuration of the IGBT region 10. Fig. 6 shows the configuration in a region Q shown in Fig. 4. Fig. 7 shows the configuration in a region R shown in Fig. 6.

[0067] As shown in Figures 3 and 4, the dummy trench electrode 12a is provided between two gate trench electrodes 11a covered with the interlayer insulating film 4. In other words, three dummy trench electrodes 12a are provided inside the opening 4a of the interlayer insulating film 4. The dummy trench electrodes 12a are not covered with the interlayer insulating film 4 and are electrically connected to the emitter electrode 6. Although three dummy trench electrodes 12a are shown in Figures 4 and 6, the number of dummy trench electrodes 12a provided inside the opening 4a is one or more.

[0068] As shown in Figures 6 and 7, the upper surface of the dummy trench electrode 12a includes a first recess 51. The first recess 51 is provided in the center of the upper end in the short direction of the dummy trench electrode 12a. The bottom of the first recess 51 is provided at a position lower than the upper surface of the semiconductor substrate. The upper end of the dummy trench electrode 12a is provided at a position lower than the upper surface of the semiconductor substrate. The first recess 51 forms the bottom of the opening 4a.

[0069] The upper surface of the dummy trench insulating film 12b in contact with the dummy trench electrode 12a includes a fifth recess 55. The fifth recess 55 is located below the upper surface of the semiconductor substrate. The fifth recess 55 forms the bottom of the opening 4a.

[0070] The first emitter electrode 6b is provided on the semiconductor substrate so as to cover the opening 4a of the interlayer insulating film 4 via the barrier metal 5. The barrier metal 5 is formed on the first recess 51 and the fifth recess 55, but if the barrier metal 5 is not provided, the first emitter electrode 6b is formed in the first recess 51 and the fifth recess 55.

[0071] 6, the upper surface of the first emitter electrode 6b includes a third recess 53 directly above the opening 4a. The third recess 53 may further include a recess (not shown in FIG. 6) directly above the first recess 51 located inside the opening 4a. The third recess 53 is formed to follow the first recess 51 or the opening 4a.

[0072] The second emitter electrode 6c is provided on the first emitter electrode 6b. The upper surface of the second emitter electrode 6c may include a fourth recess 54 directly above the third recess 53. The fourth recess 54 is formed to follow the third recess 53.

[0073] 8 is a cross-sectional view showing the configuration of the IGBT region 10 of the semiconductor devices 100 and 101. Fig. 8 shows a cross section taken along dashed line BB shown in Fig. 3.

[0074] The cross section shown in FIG. 8 is a surface layer on the first main surface side of a semiconductor substrate. +4 in that the n-type source layer 13 is not provided. + The n-type source layer 13 is selectively provided as a surface layer on the first main surface side of the semiconductor substrate. + The mold source layer 13 is not present.

[0075] Although not shown, in the structure shown in FIG. 8, similarly to the configurations shown in FIGS. 5 to 7, the semiconductor device 100 and the semiconductor device 101 include the first recess 51 to the fifth recess 55 and the opening 4a.

[0076] (3) Structure of the diode region 20 9 is a partial enlarged plan view showing the configuration of the diode region 20 of the semiconductor devices 100 and 101. FIG 9 shows an enlarged view of the configuration in the region 83 shown in FIG 1 or FIG 2.

[0077] The semiconductor device 100 and the semiconductor device 101 include a diode trench 21 provided in the diode region 20 .

[0078] The diode trench 21 extends in one direction. In the embodiment, the diode trench 21 extends in the same direction as the active trench 11 and the dummy trench 12.

[0079] The diode trench 21 includes a diode trench insulating film 21b and a diode trench electrode 21a. The cross-sectional structure of the diode trench 21 will be described in detail later, but the diode trench insulating film 21b is formed along the inner wall of a trench structure formed in the depth direction from the first main surface of the semiconductor substrate. The diode trench electrode 21a is formed inside the trench structure via the diode trench insulating film 21b.

[0080] In the diode region 20, the surface layer on the first main surface side of the semiconductor substrate is p + A p-type contact layer 24 and a p-type anode layer 25 are selectively provided. +The p-type contact layers 24 and the p-type anode layers 25 are alternately provided along the extension direction (longitudinal direction) of the diode trench 21. + The p-type contact layer 24 and the p-type anode layer 25 are intersected. + The p-type contact layer 24 and the p-type anode layer 25 are provided between two adjacent diode trenches 21.

[0081] 10 is a cross-sectional view showing the configuration of the diode region 20 of the semiconductor devices 100 and 101. Fig. 10 shows a cross section taken along dashed line CC shown in Fig. 9.

[0082] The semiconductor device 100 and the semiconductor device 101 have a p + a p-type contact layer 24, a p-type anode layer 25, an n-type carrier accumulation layer 2, - n-type drift layer 1, n-type buffer layer 3, + The diode includes a cathode layer 26 , a diode trench 21 , a barrier metal 5 , an emitter electrode 6 and a collector electrode 7 .

[0083] One diode cell corresponds to an area divided by, for example, the diode trench 21. The diode cell has p + a p-type contact layer 24, a p-type anode layer 25, an n-type carrier accumulation layer 2, - n-type drift layer 1, n-type buffer layer 3, + The diode includes a cathode layer 26 , a diode trench 21 , a barrier metal 5 , an emitter electrode 6 and a collector electrode 7 .

[0084] The first main surface of the semiconductor substrate in the diode region 20 is p + The first main surface of the diode region 20 corresponds to the surface (upper surface) of the n-type contact layer 24. The first main surface of the diode region 20 is continuous with the first main surface of the IGBT region 10, and they are flush with each other. The second main surface of the semiconductor substrate in the diode region 20 corresponds to the surface (upper surface) of the n-type contact layer 24. +10, the second main surface of the diode region 20 corresponds to the surface (lower surface) of the first type cathode layer 26. The second main surface of the diode region 20 is continuous with the second main surface of the IGBT region 10, and they are flush with each other. + From the top surface of the contact layer 24, + This corresponds to the area extending to the lower surface of the mold cathode layer 26.

[0085] n - The n-type drift layer 1 is made of a semiconductor substrate. - The n-type drift layer 1 is a - Similar to the n-type drift layer 1, the n-type drift layer 20 is provided between the first and second major surfaces of the semiconductor substrate. - The n-type drift layer 1 is a - The n-type drift layer 1 is formed continuously and integrally with the diode region 20 and the IGBT region 10. - The drift layer 1 is formed on the same semiconductor substrate.

[0086] The n-type carrier accumulation layer 2 is - The n-type carrier accumulation layer 2 in the diode region 20 is provided on the first main surface side of the semiconductor substrate with respect to the n-type drift layer 1. The n-type carrier accumulation layer 2 in the diode region 20 has the same configuration as the n-type carrier accumulation layer 2 in the IGBT region 10. For example, the thickness and impurity concentration of the n-type carrier accumulation layer 2 in the diode region 20 are the same as those of the n-type carrier accumulation layer 2 in the IGBT region 10.

[0087] The p-type anode layer 25 is provided on the first main surface side of the semiconductor substrate with respect to the n-type carrier accumulation layer 2. The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type anode layer 25 is preferably 1.0E+12 / cm 3 More than 1.0E+19 / cm 3The concentration of p-type impurities in the p-type anode layer 25 is, for example, the same as the concentration of p-type impurities in the p-type base layer 15 in the IGBT region 10. When the concentrations of p-type impurities are the same, the p-type anode layer 25 may be formed simultaneously with the p-type base layer 15. Or, for example, the concentration of p-type impurities in the p-type anode layer 25 may be lower than the concentration of p-type impurities in the p-type base layer 15 in the IGBT region 10. When the concentration of p-type impurities in the p-type anode layer 25 is low, the amount of holes injected into the diode region 20 during diode operation is reduced. Therefore, the recovery loss during diode operation is reduced.

[0088] p + The p-type contact layer 24 is provided on the first main surface side of the semiconductor substrate with respect to the p-type anode layer 25. As shown in FIG. + The p-type contact layer 24 is selectively provided above the p-type anode layer 25 as a surface layer on the first main surface side of the semiconductor substrate. + The p-type contact layer 24 covers the entire surface of the p-type anode layer 25. + The p-type contact layer 24 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. + The concentration of p-type impurities in the contact layer 24 is preferably 1.0E+15 / cm 3 More than 1.0E+20 / cm 3 The following is the result. + The concentration of the p-type impurity in the p-type contact layer 24 is + The p-type impurity of the p-type contact layer 14 may be the same as or different from the p-type impurity of the p-type contact layer 14. + The p-type contact layer 24 and the p-type anode layer 25 may be defined together as one p-type anode layer.

[0089] The n-type buffer layer 3 is -The n-type buffer layer 3 in the diode region 20 is disposed on the second main surface side of the semiconductor substrate with respect to the n-type drift layer 1. The n-type buffer layer 3 in the diode region 20 extends in the same plane as the n-type buffer layer 3 in the IGBT region 10, and has the same configuration. For example, the thickness and impurity concentration of the n-type buffer layer 3 in the diode region 20 are the same as those of the n-type buffer layer 3 in the IGBT region 10. - The n-type drift layer 1 may be defined as a single n-type drift layer. - The n-type drift layer 1 and the n-type drift layer 2 may be defined as one n-type drift layer. The n-type buffer layer 3 is not necessarily required, and an n-type - A type drift layer 1 may be provided.

[0090] n + The n-type cathode layer 26 is provided on the second main surface side of the semiconductor substrate with respect to the n-type buffer layer 3. + The n-type cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. + The concentration of n-type impurities in the cathode layer 26 is preferably 1.0E+16 / cm 3 More than 1.0E+21 / cm 3 The following is the result.

[0091] n + The type cathode layer 26 may be provided in the entirety of the diode region 20 or in a part thereof. Although not shown in the drawings, the semiconductor device 100 and the semiconductor device 101 each include an n-type cathode layer as a semiconductor layer constituting the second main surface of the semiconductor substrate in the diode region 20. + The cathode layer 26 and the p + Such a structure may include, for example, a semiconductor layer alternating with an n-type cathode layer. + The n-type cathode layer 26 is formed by selectively implanting p-type impurities into a portion of the region where the n-type cathode layer 26 is formed. + The cathode layer 26 and the p +A diode including semiconductor layers and alternating cathode layers is called a Relaxed Field of Cathode (RFC) diode.

[0092] The diode trench 21 is provided on the first main surface of the semiconductor substrate, i.e., the upper surface of the semiconductor substrate. The diode trench 21 is formed at a p + The n-type contact layer 24, the p-type anode layer 25, and the n-type carrier accumulation layer 2 are penetrated. - The drift layer 1 has been reached.

[0093] The diode trench insulating film 21b is formed along the inner wall of a trench structure formed in the depth direction from the first main surface of the semiconductor substrate. The diode trench insulating film 21b is, for example, an oxide film.

[0094] The diode trench electrode 21a is formed inside the trench structure via the diode trench insulating film 21b. The bottom of the diode trench electrode 21a is connected to the n-type - The diode trench electrode 21a faces the type drift layer 1. The diode trench electrode 21a is made of, for example, conductive polysilicon.

[0095] The barrier metal 5 is p + The barrier metal 5 is provided on the type contact layer 24 and the diode trench electrode 21a. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. The barrier metal 5 is made of a metal containing titanium, such as Ti, TiN, or TiSi. + The semiconductor layer 21 is in ohmic contact with the contact layer 24 and the diode trench electrode 21a.

[0096] The emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 is continuous with the emitter electrode 6 in the IGBT region 10. The emitter electrode 6 is preferably made of, for example, an aluminum alloy (Al-Si alloy). The emitter electrode 6 is connected to the diode trench electrodes 21a and p + The metal contact layer 24 is electrically connected to the metal contact layer 24 .

[0097] The barrier metal 5 and the emitter electrode 6 may be defined as one emitter electrode. The barrier metal 5 is not necessarily required. When the barrier metal 5 is not provided, the emitter electrode 6 is formed on the p-type anode layer 25 and the p + The emitter electrode 6 is provided on the type contact layer 24 and the diode trench electrode 21a and is in ohmic contact with them. An interlayer insulating film 4 may be provided on a part of the diode trench electrode 21a. In that case, the emitter electrode 6 is electrically connected to the diode trench electrode 21a in any region on the diode trench electrode 21a.

[0098] The collector electrode 7 is + The collector electrode 7 is provided on the n-type cathode layer 26. The collector electrode 7 is continuous with the collector electrode 7 in the IGBT region 10. The collector electrode 7 is preferably made of an aluminum alloy. The collector electrode 7 is + The cathode layer 26 is in ohmic contact with the cathode layer 26 .

[0099] Although not shown, the semiconductor device 100 and the semiconductor device 101 also include a first recess 51, a third recess 53, a fourth recess 54 and a fifth recess 55 in the diode region 20 shown in FIG.

[0100] The semiconductor device 100 and the semiconductor device 101 include a plurality of active trenches 11 shown in FIG. 4 and a plurality of diode trenches 21 shown in FIG. 10 as a plurality of trenches. Inside the active trench 11, a gate trench electrode 11a is provided as a first trench electrode. Inside the diode trench 21, a diode trench electrode 21a is provided as a second trench electrode. The gate trench electrode 11a and the diode trench electrode 21a are collectively referred to as a plurality of trench electrodes. The interlayer insulating film 4 covers two or more first trench electrodes of the plurality of trench electrodes, that is, two or more gate trench electrodes 11a.

[0101] The openings 4a of the interlayer insulating film 4 in the diode region 20 are provided between a plurality of gate trench electrodes 11a covered with the interlayer insulating film 4. For example, as shown in FIG. 1 or FIG. 2, when both ends of one diode region 20 are sandwiched between two IGBT regions 10, the openings 4a are formed between the gate trench electrodes 11a of one IGBT region 10 and the gate trench electrodes 11a of the other IGBT region 10. + The upper surfaces of the mold contact layer 24 and the diode trench 21 correspond to the bottom of the opening 4a.

[0102] In other words, the diode trench electrode 21a is provided inside the opening 4a of the interlayer insulating film 4. The diode trench electrode 21a in the diode region 20 is not covered with the interlayer insulating film 4 and is electrically connected to the emitter electrode 6. The number of the diode trench electrodes 21a is one or more.

[0103] Similar to the dummy trench electrode 12a shown in FIG. 6, the upper surface of the diode trench electrode 21a includes a first recess 51. The first recess 51 is provided in the center of the upper end in the short direction of the diode trench electrode 21a. The bottom of the first recess 51 is provided at a position lower than the upper surface of the semiconductor substrate. The upper end of the diode trench electrode 21a is provided at a position lower than the upper surface of the semiconductor substrate. The first recess 51 forms the bottom of the opening 4a.

[0104] 6 and 7, the upper surface of the diode trench insulating film 21b includes a fifth recess 55. The fifth recess 55 is located below the upper surface of the semiconductor substrate. The fifth recess 55 forms the bottom of the opening 4a.

[0105] 6, the first emitter electrode 6b is provided on the semiconductor substrate so as to close the opening 4a of the interlayer insulating film 4 via the barrier metal 5. The barrier metal 5 is formed on the first recess 51 and the fifth recess 55. When the barrier metal 5 is not provided, the first emitter electrode 6b is formed in the first recess 51 and the fifth recess 55.

[0106] The upper surface of the first emitter electrode 6b includes a third recess 53 directly above the opening 4a. The third recess 53 may further include a recess (not shown) directly above the first recess 51 located inside the opening 4a. The third recess 53 is formed to follow the first recess 51 or the opening 4a.

[0107] The second emitter electrode 6c is provided on the first emitter electrode 6b. The upper surface of the second emitter electrode 6c may include a fourth recess 54 directly above the third recess 53. The fourth recess 54 is formed to follow the third recess 53.

[0108] 11 is a cross-sectional view showing the configuration of the diode region 20 of the semiconductor devices 100 and 101. Fig. 11 shows a cross section taken along the dashed line DD shown in Fig. 9.

[0109] The cross section shown in FIG. 11 is a cross section of the first main surface side of the semiconductor substrate. + 10 in that the contact layer 24 is not provided. + The contact layer 24 is selectively provided as a surface layer on the first main surface side of the semiconductor substrate. +The p-type contact layer 24 is not present. + In the region where the p-type contact layer 24 is not provided, the first main surface of the semiconductor substrate corresponds to the surface (upper surface) of the p-type anode layer 25. In the cross section shown in FIG. 11, one diode cell is made up of the p-type anode layer 25, the n-type carrier accumulation layer 2, the n - n-type drift layer 1, n-type buffer layer 3, + The cathode layer 26 , the barrier metal 5 , the emitter electrode 6 and the collector electrode 7 .

[0110] Although not shown, the semiconductor device 100 and the semiconductor device 101 also include a first recess 51, a third recess 53, a fourth recess 54 and a fifth recess 55 in the structure shown in FIG.

[0111] Moreover, the configuration in which the first recess 51, the third recess 53, the fourth recess 54, and the fifth recess 55 are formed in the diode region 20 is not limited to the above. The first recess 51, the third recess 53, the fourth recess 54, and the fifth recess 55 are also formed in a semiconductor device in which some of the diode trenches 21 (not shown) are covered by the interlayer insulating film 4. In that case, the first diode trench electrode of the plurality of diode trenches 21 covered by the interlayer insulating film 4 is the first trench electrode, and the second diode trench electrode not covered by the interlayer insulating film 4 is the second trench electrode. The first diode trench electrode is electrically connected to the emitter electrode 6 in any region on the first diode trench electrode. The opening 4a in the diode region 20 is provided between two first diode trench electrodes covered by the interlayer insulating film 4. At least one second diode trench electrode is provided inside the opening 4a of the interlayer insulating film 4. Even with this configuration, the first recess 51, the third recess 53, the fourth recess 54 and the fifth recess 55 are formed in the diode region 20.

[0112] (4) Structure of the Boundary Between the IGBT Region 10 and the Diode Region 20 12 is a cross-sectional view showing the configuration of the boundary portion between the IGBT region 10 and the diode region 20. FIG 12 shows a cross section taken along dashed line GG shown in FIG 1 or FIG 2.

[0113] The p-type collector layer 16 provided on the second main surface side of the IGBT region 10 protrudes into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. Compared to a structure in which the p-type collector layer 16 does not protrude into the diode region 20, + The distance between the type cathode layer 26 and the active trench 11 is increased. In this structure, even when a gate drive voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, n-type cathode layer 26 is not generated from the channel formed adjacent to the active trench 11. + This reduces the current flowing to the type cathode layer 26. The distance U1 is, for example, 100 μm. However, depending on the application of the semiconductor device 100 or the semiconductor device 101, the distance U1 may be 0 μm or a distance smaller than 100 μm.

[0114] (5) Structure of the termination region 30 Fig. 13 is a cross-sectional view showing the configuration of the boundary portion between the IGBT region 10 and the termination region 30. Fig. 13 shows a cross-section taken along dashed line EE shown in Fig. 1 or 2. Fig. 14 is a cross-sectional view showing the configuration of the boundary portion between the diode region 20 and the termination region 30. Fig. 14 shows a cross-section taken along dashed line FF shown in Fig. 1.

[0115] The semiconductor device 100 and the semiconductor device 101 have a p-type termination well layer 31, a n-type termination well layer 32, and a n-type termination well layer 33 in the termination region 30. + n-type channel stopper layer 32, - The semiconductor device includes a n-type drift layer 1, an n-type buffer layer 3, a p-type termination collector layer 16a, an interlayer insulating film 4, a barrier metal 5, an emitter electrode 6, a termination electrode 6a, a semi-insulating film 33, a termination protective film 34 and a collector electrode 7.

[0116] In the above structure, the p-type termination well layer 31, + n-type channel stopper layer 32, -The n-type drift layer 1, the n-type buffer layer 3 and the p-type termination collector layer 16a are provided between the first and second main surfaces of the semiconductor substrate.

[0117] The first main surface of the semiconductor substrate in the termination region 30 is n - The p-type drift layer 1, the p-type termination well layer 31 and the n + The first main surface in the termination region 30 corresponds to the surface (upper surface) of the p-type channel stopper layer 32. The first main surface in the termination region 30 is continuous with the first main surface in the IGBT region 10 or the diode region 20, and they are flush with each other. The second main surface of the semiconductor substrate in the termination region 30 corresponds to the surface (lower surface) of the p-type termination collector layer 16a. The second main surface in the termination region 30 is continuous with the second main surface in the IGBT region 10 or the diode region 20, and they are flush with each other.

[0118] n - The n-type drift layer 1 is a n-type - Similar to the n-type drift layer 1, the n-type drift layer 2 is provided between the first and second main surfaces of the semiconductor substrate. - A portion of the n-type drift layer 1 is exposed on the first main surface as a surface layer of the semiconductor substrate. - The n-type drift layer 1 is a n-type - It is formed continuously and integrally with the drift layer 1.

[0119] The p-type termination well layer 31 is -The p-type termination well layer 31 is provided on the first main surface side of the semiconductor substrate with respect to the type drift layer 1. The p-type termination well layer 31 surrounds the cell region in plan view. In the embodiment, the three p-type termination well layers 31 form a triple ring in plan view to surround the cell region. The three p-type termination well layers 31 form the FLR. The number of the p-type termination well layers 31 is not limited to three. The number of the p-type termination well layers 31 is appropriately selected depending on the breakdown voltage design of the semiconductor device 100 or the semiconductor device 101. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type termination well layer 31 is 1.0E+14 / cm 3 More than 1.0E+19 / cm 3 The following is the result.

[0120] n + The n-type channel stopper layer 32 - The n-type drift layer 1 is provided on the first main surface side of the semiconductor substrate. + The n-type channel stopper layer 32 is provided outside the p-type termination well layer 31 in plan view. + The p-type channel stopper layer 32 is provided to surround the p-type termination well layer 31 .

[0121] The n-type buffer layer 3 is - The n-type buffer layer 3 in the termination region 30 is provided on the second main surface side of the semiconductor substrate with respect to the n-type drift layer 1. The n-type buffer layer 3 in the termination region 30 has a similar configuration to the n-type buffer layer 3 in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 in the termination region 30 is formed continuously and integrally with the n-type buffer layer 3 in the IGBT region 10 or the diode region 20.

[0122] The p-type termination collector layer 16a is provided on the second main surface side of the semiconductor substrate with respect to the n-type buffer layer 3. The p-type termination collector layer 16a is formed continuously and integrally with the p-type collector layer 16 provided in the IGBT region 10. The p-type termination collector layer 16a in the termination region 30 and the p-type collector layer 16 in the IGBT region 10 may be defined together as one p-type collector layer.

[0123] 14, the p-type termination collector layer 16a protrudes into the diode region 20 by a distance U2 from the boundary between the diode region 20 and the termination region 30. Compared to a structure in which the p-type termination collector layer 16a does not protrude into the diode region 20, + In this case, the distance between the p-type cathode layer 26 and the p-type termination well layer 31 is increased. Such a structure prevents the p-type termination well layer 31 from acting as the anode of a freewheeling diode. The distance U2 is, for example, 100 μm.

[0124] The interlayer insulating film 4 is provided on the first main surface of the semiconductor substrate. The interlayer insulating film 4 has a contact hole. The contact hole is provided on the p-type termination well layer 31 and the n-type termination well layer 32. + The contact hole is provided on the p-type channel stopper layer 32. The p-type termination well layer 31 or the n-type + The surface of the type channel stopper layer 32 is exposed.

[0125] The barrier metal 5 is formed on the p-type termination well layer 31 and on the n + The semiconductor layer 32 is provided on the channel stopper layer 32 .

[0126] The emitter electrode 6 is electrically connected to a p-type termination well layer 31 near the IGBT region 10 or the diode region 20 via a barrier metal 5. The emitter electrode 6 in the termination region 30 is formed continuously and integrally with the emitter electrode 6 in the IGBT region 10 or the diode region 20.

[0127] The termination electrode 6a is separated from the emitter electrode 6 and is provided on the outer side of the emitter electrode 6. The termination electrode 6a is connected to the p-type termination well layer 31 and the n-type termination well layer 32 via the barrier metal 5 in the contact hole. + The insulating layer 32 is electrically connected to the channel stopper layer 32 .

[0128] The semi-insulating film 33 electrically connects the emitter electrode 6 and the termination electrode 6a. The semi-insulating film 33 is, for example, a semi-insulating silicon nitride film (sin SiN).

[0129] The terminal protective film 34 covers the emitter electrode 6, the terminal electrode 6a and the semi-insulating film 33. The terminal protective film 34 is made of, for example, polyimide.

[0130] The collector electrode 7 is provided on the p-type termination collector layer 16a, that is, on the second main surface of the semiconductor substrate. The collector electrode 7 in the termination region 30 is formed continuously and integrally with the collector electrode 7 in the IGBT region 10 and the diode region 20.

[0131] (6) Manufacturing Method of Semiconductor Devices 100 and 101 Figures 15 to 26 are diagrams showing a manufacturing method of the semiconductor devices 100, 101. Figures 15 to 22 show steps of forming a structure on the first main surface side of the semiconductor devices 100, 101. Figures 23 to 26 show steps of forming a structure on the second main surface side of the semiconductor devices 100, 101. Each figure shows a cross section of the boundary between the IGBT region 10 and the diode region 20, that is, a cross section along the dashed line GG shown in Figure 1 or 2.

[0132] FIG. 15 is a diagram showing a process of preparing a semiconductor substrate. In the embodiment, an n-type wafer containing n-type impurities is prepared as the semiconductor substrate. The semiconductor substrate may be a so-called FZ wafer produced by the FZ (Floating Zone) method, or a so-called MCZ wafer produced by the MCZ (Magnetic field applied CZochralki) method. Alternatively, the semiconductor substrate may be a wafer produced by sublimation or chemical vapor deposition (CVD). In this process, the entire semiconductor substrate is n-type. - The n-type drift layer 1 corresponds to the n-type impurity concentration. The concentration of the n-type impurity is appropriately selected depending on the withstand voltage specification of the semiconductor device 100 or the semiconductor device 101. For example, when the withstand voltage specification of the semiconductor device 100 or 101 is 1200 V, the concentration of the n-type impurity is n - The resistivity of the drift layer 1 is adjusted to be about 40 to 120 Ω·cm. - Although the step of preparing an n-type wafer as the n-type drift layer 1 is shown, the step of preparing a semiconductor substrate is not limited thereto. For example, a step of ion-implanting an n-type impurity from a first main surface or a second main surface of a semiconductor substrate and a step of diffusing the n-type impurity by heat treatment can be used to prepare an n-type drift layer 1. - A semiconductor substrate including a type drift layer 1 may be provided.

[0133] An IGBT region 10 in which the IGBT cells are to be arranged and a diode region 20 in which the diode cells are to be arranged are defined in the semiconductor substrate. Although not shown in Fig. 15, a termination region 30 in which a breakdown voltage holding structure is to be formed is defined around the IGBT region 10 and the diode region 20. Below, a method for manufacturing each structure in the IGBT region 10 and the diode region 20 will be mainly described.

[0134] 16 is a diagram showing a process of forming the n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25. The n-type impurities for forming the n-type carrier accumulation layer 2 are introduced into the n-type semiconductor substrate from the first main surface side. -Ions are implanted into the surface layer of n-type drift layer 1. The n-type impurity is, for example, phosphorus. A p-type impurity for forming p-type base layer 15 and p-type anode layer 25 is ion-implanted into the first main surface of the semiconductor substrate. The p-type impurity is, for example, boron. After the ion implantation, a heat treatment is performed. The n-type impurity and p-type impurity are diffused by the heat treatment, and n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed.

[0135] During the above ion implantation, a mask having openings in predetermined regions is formed on the first main surface of the semiconductor substrate. The n-type impurities and the p-type impurities are implanted in regions corresponding to the openings of the mask. The mask is formed by a process of applying a resist to the first main surface of the semiconductor substrate and a process of forming openings in the resist in predetermined regions by photolithography (photoengraving) technology. Hereinafter, the process of forming a mask having openings in such predetermined regions is referred to as a mask process. The n-type impurities and the p-type impurities are implanted in the predetermined regions by the mask process. As a result, the n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are selectively formed in the plane of the first main surface of the semiconductor substrate.

[0136] The p-type base layer 15 and the p-type anode layer 25 may be formed by simultaneously implanting p-type impurities. In this case, the depths and the concentrations of the p-type impurities of the p-type base layer 15 and the p-type anode layer 25 have the same configuration. On the other hand, the p-type base layer 15 and the p-type anode layer 25 may be formed by separately implanting p-type impurities by mask processing. In this case, the depths or the concentrations of the p-type impurities of the p-type base layer 15 and the p-type anode layer 25 have different configurations. For example, the p-type impurities for the p-type base layer 15 are implanted through an opening provided in the IGBT region 10. The p-type impurities for the p-type anode layer 25 are implanted through an opening provided in the diode region 20.

[0137] Although not shown, the p-type termination well layer 31 in the termination region 30 and the p-type anode layer 25 in the diode region 20 may be formed by ion-implanting p-type impurities at the same time. In this case, the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 are the same. Even if the concentrations of p-type impurities of the p-type termination well layer 31 and the p-type anode layer 25 are different from each other, the p-type impurities may be ion-implanted at the same time. However, in this case, a mask having a mesh shape is provided in at least one of the region where the p-type termination well layer 31 is formed and the region where the p-type anode layer 25 is formed. The amount of p-type impurities injected is controlled according to the aperture ratio of the mesh.

[0138] The p-type termination well layer 31 and the p-type anode layer 25 may be formed by ion implantation of p-type impurities separately using a mask process. In this case, the depths or p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 are different from each other.

[0139] The p-type termination well layer 31, the p-type base layer 15 and the p-type anode layer 25 may be formed by simultaneously implanting p-type impurities. The p-type termination well layer 31 may be formed by implanting p-type impurities before processing the IGBT region 10 and the diode region 20.

[0140] Figure 17 shows the + Type source layer 13, p + The p-type contact layer 14 and + 1 is a diagram showing a process of forming a p-type contact layer 24. An n-type impurity is ion-implanted from the first main surface side of the semiconductor substrate into the surface layer of the p-type base layer 15. At this time, the n-type impurity is implanted into the IGBT region 10 by a mask process. + An n-type source layer 13 is selectively formed on a surface layer of a p-type base layer 15 in the IGBT region 10. The n-type impurity is, for example, arsenic or phosphorus.

[0141] In addition, p-type impurities are ion-implanted from the first main surface side of the semiconductor substrate. At this time, openings in the mask are arranged so that the p-type impurities are implanted into predetermined regions in the IGBT region 10 and predetermined regions in the diode region 20. By this masking process, p + The p-type contact layer 14 and + A p-type contact layer 24 is selectively formed on the surface of the p-type base layer 15 in the IGBT region 10 and the diode region 20. The p-type impurity is, for example, boron or aluminum.

[0142] 18 is a diagram showing a process for forming a trench structure 8. The trench structure 8 is formed by a process of depositing a material for a hard mask on a first main surface of a semiconductor substrate, a process of forming a hard mask including an opening in a portion corresponding to the trench structure 8 by photolithography, and a process of etching the semiconductor substrate through the hard mask. The hard mask is, for example, a thin film such as SiO2.

[0143] The trench structure 8 in the IGBT region 10 penetrates from the first main surface of the semiconductor substrate through the p-type base layer 15 and the n-type carrier accumulation layer 2, and - The n-type drift layer 1 is reached. Among the multiple trench structures 8 formed in the IGBT region 10, some of the trenches are + The trench structure 8 also penetrates the p-type source layer 13. + The trench structure 8 in the diode region 20 penetrates from the first main surface of the semiconductor substrate through the p-type anode layer 25 and the n-type carrier accumulation layer 2, and - The surface layer of the semiconductor substrate is p + In the region where the contact layer 24 is provided, the trench structure 8 has its p + The mold contact layer 24 is also penetrated.

[0144] 18, the pitch of the trench structures 8 in the IGBT region 10 is the same as the pitch of the trench structures 8 in the diode region 20. However, the pitch of the trench structures 8 in the IGBT region 10 may be different from the pitch of the trench structures 8 in the diode region 20. The pitch of the trench structures 8 is changed as appropriate by a mask pattern in mask processing.

[0145] 19 is a diagram showing a step of forming an oxide film 9. The semiconductor substrate is heated in an atmosphere containing oxygen. The oxide film 9 is formed on the inner wall of the trench structure 8 and on the first main surface of the semiconductor substrate. In the IGBT region 10, n + The oxide film 9 formed on the inner wall of the trench structure 8 penetrating the p-type source layer 13 corresponds to the gate trench insulating film 11b. + The oxide film 9 formed on the inner wall of the trench structure 8 penetrating the type contact layer 14 corresponds to the dummy trench insulating film 12b. In the diode region 20, the oxide film 9 formed in the trench structure 8 corresponds to the diode trench insulating film 21b. Note that the oxide film 9 formed on the first main surface of the semiconductor substrate will be removed in a later process.

[0146] 20 is a diagram showing a process of forming a gate trench electrode 11a, a dummy trench electrode 12a, and a diode trench electrode 21a. Polysilicon doped with n-type or p-type impurities is deposited inside a trench structure 8 by CVD (chemical vapor deposition) or the like. As a result, a gate trench electrode 11a is formed inside the trench structure 8 via a gate trench insulating film 11b. A dummy trench electrode 12a is formed inside the trench structure 8 via a dummy trench insulating film 12b. A diode trench electrode 21a is formed inside the trench structure 8 via a diode trench insulating film 21b.

[0147] FIG. 21 is a diagram showing a process of forming an interlayer insulating film 4. The interlayer insulating film 4 is formed on the gate trench electrode 11a among the multiple trench electrodes. In this process, first, the interlayer insulating film 4 is formed on the upper surface of the semiconductor substrate. The interlayer insulating film 4 contains, for example, SiO2 as an oxide film. The interlayer insulating film 4 has, for example, a single-layer structure containing an oxide film. The oxide film of the single-layer structure is formed, for example, by TEOS (Tetraethoxysilane). The interlayer insulating film 4 may have a stacked structure containing multiple oxide films. When the interlayer insulating film 4 has a stacked structure, the multiple oxide films are composed of two or more types of oxide films having different dopant concentrations from each other. Of the two or more types of oxide films, the first oxide film is formed by TEOS (BPTEOS) containing boron and phosphorus, and the second oxide film is formed by TEOS.

[0148] Thereafter, the interlayer insulating film 4 is masked, and the interlayer insulating film 4 and the oxide film 9 at predetermined positions are etched. Specifically, the interlayer insulating film 4 and the oxide film 9 on the dummy trench electrodes 12a and the diode trench electrodes 21a are removed. As a result, an opening 4a in the interlayer insulating film 4 is formed. The opening 4a is located between the gate trench electrodes 11a covered with the interlayer insulating film 4. From the opening 4a, n + Type source layer 13, p + Type contact layer 14, p + The upper surfaces of the mold contact layer 24, the dummy trench 12, and the diode trench 21 are exposed. The first recesses 51 in the upper surfaces of the diode trench electrode 21a and the dummy trench electrode 12a form part of the bottom of the opening 4a.

[0149] During the formation of the opening 4a, the upper portion of the dummy trench insulating film 12b in contact with the dummy trench electrode 12a and the upper portion of the diode trench insulating film 21b in contact with the diode trench electrode 21a are also removed. As a result, a fifth recess 55 is formed on the upper surface of the dummy trench insulating film 12b and the upper surface of the diode trench insulating film 21b as shown in FIG.

[0150] 22 is a diagram showing a process for forming a barrier metal 5 and an emitter electrode 6. The barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4. The barrier metal 5 is preferably a metal containing titanium, such as Ti, TiN, or TiSi. The barrier metal 5 is formed by physical vapor deposition (PVD) or CVD.

[0151] The emitter electrode 6 is formed on the barrier metal 5. As shown in FIG. 5 and FIG. 6, the emitter electrode 6 includes a first emitter electrode 6b and a second emitter electrode 6c. The first emitter electrode 6b is formed by a PVD method such as sputtering or vapor deposition. The first emitter electrode 6b includes, for example, an aluminum silicon alloy (Al-Si alloy). The second emitter electrode 6c is formed on the first emitter electrode 6b by an electroless plating method or an electrolytic plating method. The second emitter electrode 6c includes, for example, nickel or a nickel alloy. The second emitter electrode 6c may have, for example, a laminated structure including two or more kinds of metal layers. The laminated structure is, for example, composed of a Ni film, a Pd film, and an Au film, and is formed by a plating method.

[0152] The plating method makes it possible to easily form a thick metal film. In the thick emitter electrode 6, the heat capacity increases, and therefore the heat resistance of the emitter electrode 6 improves. When a nickel alloy is further formed on the aluminum silicon alloy by plating, the plating may be performed after the second main surface of the semiconductor substrate is processed.

[0153] 23 is a diagram showing a process of thinning the semiconductor substrate. The second main surface of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined thickness according to the design of the semiconductor devices 100 and 101. The thickness of the semiconductor substrate after grinding is, for example, 80 μm or more and 200 μm or less.

[0154] 24 is a diagram showing a process of forming the n-type buffer layer 3 and the p-type collector layer 16. The n-type impurity for forming the n-type buffer layer 3 is introduced from the second main surface side of the semiconductor substrate. -Ions are implanted into the surface layer of n-type drift layer 1. As the n-type impurity, for example, phosphorus may be implanted or protons may be implanted. Alternatively, for example, both phosphorus and protons may be implanted.

[0155] Protons are implanted deep into the second main surface of the semiconductor substrate with a relatively low acceleration energy. The proton implantation depth can be controlled relatively easily by changing the acceleration energy. Therefore, when protons are ion-implanted multiple times while changing the acceleration energy, an n-type buffer layer 3 is formed that is wider in the thickness direction of the semiconductor substrate than the n-type buffer layer 3 containing phosphorus.

[0156] Phosphorus has a higher activation rate as an n-type impurity than protons. Even in a thinned semiconductor substrate, an n-type buffer layer 3 containing phosphorus more reliably reduces the occurrence of punch-through caused by the expansion of the depletion layer. In order to further thin the semiconductor substrate, it is preferable to form an n-type buffer layer 3 containing both protons and phosphorus. In this case, protons are implanted deeper from the second main surface of the semiconductor substrate than phosphorus.

[0157] A p-type impurity for forming a p-type collector layer 16 is ion-implanted from the second main surface side of the semiconductor substrate. For example, boron is implanted as the p-type impurity. After the ion implantation, a laser is irradiated onto the second main surface of the semiconductor substrate. The implanted boron is activated by the laser annealing, and the p-type collector layer 16 is formed.

[0158] During this laser annealing, the n-type impurity phosphorus implanted at a position relatively shallow from the second main surface of the semiconductor substrate is also activated at the same time. Protons are activated at a relatively low annealing temperature of about 350°C to 500°C. Therefore, after the protons are implanted, it is preferable that the semiconductor substrate is not heated to a temperature higher than 350°C to 500°C except in the step of activating the protons. Laser annealing heats only the vicinity of the second main surface of the semiconductor substrate to a high temperature. Therefore, laser annealing is effective in activating n-type or p-type impurities after the protons are implanted.

[0159] The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20 and the termination region 30, or may be formed only in the IGBT region 10 or the diode region 20. The p-type collector layer 16 is also formed in the termination region 30. Here, the p-type collector layer 16 in the termination region 30 corresponds to a p-type termination collector layer 16a.

[0160] Figure 25 shows the + FIG. 1 is a diagram showing a process for forming a cathode layer 26. + An n-type impurity for forming the n-type cathode layer 26 is ion-implanted into the second main surface of the semiconductor substrate in the diode region 20. Phosphorus is implanted as the n-type impurity. At this time, the p-type collector layer 16 and the n + The n-type impurity is selectively implanted by mask processing so that the boundary with the n-type cathode layer 26 extends into the diode region 20 from the boundary between the IGBT region 10 and the diode region 20 by a distance U1.

[0161] n + The amount of n-type impurities implanted to form the n-type cathode layer 26 is greater than the amount of p-type impurities implanted in the p-type collector layer 16. + The n-type impurities of the cathode layer 26 are implanted into the region where the p-type collector layer 16 is formed. That is, the p-type semiconductor needs to be changed to an n-type semiconductor by implanting the n-type impurities. + In all of the regions where the type cathode layer 26 is to be formed, n-type impurities are implanted such that the concentration of the n-type impurities is higher than the concentration of the p-type impurities.

[0162] In FIG. 25, the depth of the p-type collector layer 16 from the second main surface and the n + In the illustrated example, the depths of the p-type collector layer 16 and the n-type cathode layer 26 are the same. + The relationship of the depth of the mold cathode layer 26 is not limited thereto. + The depth of the p-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16 .

[0163] 26 is a diagram showing a step of forming the collector electrode 7. The collector electrode 7 is formed on the second main surface in the IGBT region 10, the diode region 20 and the termination region 30. The collector electrode 7 may be formed over the entire surface of the second main surface of the semiconductor substrate.

[0164] The collector electrode 7 includes an aluminum silicon alloy, titanium, or the like. The collector electrode 7 is formed by PVD such as sputtering or vapor deposition. The collector electrode 7 may be formed of a plurality of metal layers each including an aluminum silicon alloy, titanium, nickel, gold, or the like. Alternatively, the collector electrode 7 may have a structure in which another metal film is formed by electroless plating or electrolytic plating on a metal film formed by PVD.

[0165] In the embodiment, a plurality of semiconductor devices 100 or a plurality of semiconductor devices 101 are fabricated in a matrix on one semiconductor substrate by the above-mentioned manufacturing process. The plurality of semiconductor devices 100, 101 are cut into individual semiconductor devices by laser dicing or blade dicing. As a result, the semiconductor device 100 or the semiconductor device 101 is completed.

[0166] In summary, the semiconductor device 100, 101 in the embodiment includes a plurality of trenches, a plurality of trench electrodes, an interlayer insulating film 4, and a first emitter electrode 6b. The plurality of trenches are provided on the upper surface of a semiconductor substrate. The plurality of trenches are any of the active trench 11, the dummy trench 12, and the diode trench 21. The plurality of trench electrodes are provided inside the plurality of trenches, respectively. The plurality of trench electrodes are any of the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a. The interlayer insulating film 4 covers two or more of the plurality of trench electrodes. The two or more trench electrodes correspond to the gate trench electrode 11a or a part of the diode trench electrode 21a. The first emitter electrode 6b is provided on the interlayer insulating film 4. The interlayer insulating film 4 includes an opening 4a. The opening 4a is provided between two or more trench electrodes covered by the interlayer insulating film 4. The first emitter electrode 6b is provided on the semiconductor substrate so as to cover the opening 4a. The upper surface of each of the plurality of trench electrodes includes a first recess 51. The upper surface of the interlayer insulating film 4 includes a second recess 52 directly above the first recess 51. The upper surface of the first emitter electrode 6b includes a third recess 53 directly above the opening 4a.

[0167] Moreover, the semiconductor devices 100 and 101 further include a second emitter electrode 6c provided on the first emitter electrode 6b. The upper surface of the second emitter electrode 6c includes a fourth recess 54 directly above the third recess 53. Furthermore, the third recess 53 is also provided directly above the second recess 52 on the upper surface of the first emitter electrode 6b.

[0168] In such semiconductor device 100, 101, the contact area at each interface between the gate trench electrode 11a, the dummy trench electrode 12a, the diode trench electrode 21a, the interlayer insulating film 4, the first emitter electrode 6b, and the second emitter electrode 6c increases. Therefore, the adhesion is improved. The uneven structure generates an anchor effect, and the stress resistance is improved. The depth of the fourth recess 54 is shallower than the depth of the third recess 53, the depth of the second recess 52, the depth of the opening 4a, and the depth of the first recess 51. Since the upper surface of the second emitter electrode 6c is flat, the assembly is improved, for example, in wire bonding or solder bonding. In this way, the semiconductor device 100, 101 improves the assembly and stress resistance.

[0169] The bottom of the first recess 51 is located lower than the upper surface of the semiconductor substrate. The upper ends of the trench electrodes are located lower than the upper surface of the semiconductor substrate. This configuration increases the depression of the second recess 52. This improves the contact area and the anchor effect.

[0170] The interlayer insulating film 4 has a single-layer structure including an oxide film. When the oxide film of the single-layer structure is formed of TEOS, the degree of unevenness becomes large. Therefore, the contact area and the anchor effect are improved.

[0171] The interlayer insulating film 4 may have a laminated structure including two or more oxide films having different dopant concentrations. Of the two or more oxide films, one oxide film is formed of TEOS (BPTEOS) containing boron and phosphorus, and the other oxide film is formed of TEOS. The degree of unevenness can be controlled by the difference in dopant concentration.

[0172] The thickness of the first emitter electrode 6b may be greater than the thickness of the second emitter electrode 6c. In this case, the stress resistance is improved. Conversely, the thickness of the second emitter electrode 6c may be greater than the thickness of the first emitter electrode 6b. In this case, the wettability is improved, and high assembly efficiency is achieved.

[0173] The width of the bottom of opening 4a is greater than the height of interlayer insulating film 4 forming the sidewall of opening 4a, which improves the embedding property of first emitter electrode 6b or barrier metal 5.

[0174] The first recess 51 on the upper surface of the dummy trench electrode 12a and the diode trench electrode 21a forms part of the bottom of the opening 4a, thereby expanding the contact area between the first emitter electrode 6b or the barrier metal 5 and the semiconductor substrate.

[0175] The above configuration is applied to both the IGBT region 10 and the diode region 20 of the RC-IGBT, but may be applied to only one of the IGBT region 10 and the diode region 20. The above configuration is not limited to only RC-IGBTs. It may also be applied to a semiconductor device including a single IGBT or a single diode, and the above effects can be obtained in such cases.

[0176] In the present disclosure, the embodiments can be modified or omitted as appropriate.

[0177] Various aspects of the present disclosure are summarized below as appendices.

[0178] (Appendix 1) A plurality of trenches provided on an upper surface of a semiconductor substrate; a plurality of trench electrodes provided within the plurality of trenches, respectively; an insulating film covering two or more of the plurality of trench electrodes; A first electrode provided on the insulating film, the insulating film includes an opening provided between the two or more trench electrodes covered with the insulating film; the first electrode is provided on the semiconductor substrate so as to cover the opening; an upper surface of each of the plurality of trench electrodes includes a first recess; an upper surface of the insulating film includes a second recess directly above the first recess; a top surface of the first electrode includes a third recess directly above the opening,

[0179] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the third recess is further provided directly above the second recess on the upper surface of the first electrode.

[0180] (Appendix 3) Further comprising a second electrode provided on the first electrode, 3. The semiconductor device of claim 1, wherein an upper surface of the second electrode includes a fourth recess directly above the third recess.

[0181] (Appendix 4) 4. The semiconductor device according to claim 3, wherein a depth of the fourth recess is shallower than a depth of the third recess.

[0182] (Appendix 5) 5. The semiconductor device according to claim 3, wherein the depth of the fourth recess is shallower than a depth of the second recess and a depth of the opening.

[0183] (Appendix 6) 6. The semiconductor device according to claim 3, wherein the depth of the fourth recess is shallower than the depth of the first recess.

[0184] (Appendix 7) 7. The semiconductor device according to claim 1, wherein a bottom of the first recess is provided at a position lower than the upper surface of the semiconductor substrate.

[0185] (Appendix 8) 8. The semiconductor device according to claim 1, wherein an upper end of each of the plurality of trench electrodes is located lower than the upper surface of the semiconductor substrate.

[0186] (Appendix 9) 9. The semiconductor device according to claim 1, wherein the insulating film has a single-layer structure including an oxide film.

[0187] (Appendix 10) 10. The semiconductor device according to claim 1, wherein the insulating film has a laminated structure including two or more types of oxide films having different dopant concentrations.

[0188] (Appendix 11) 4. The semiconductor device according to claim 3, wherein the first electrode has a thickness greater than a thickness of the second electrode.

[0189] (Appendix 12) 4. The semiconductor device according to claim 3, wherein the second electrode has a thickness greater than a thickness of the first electrode.

[0190] (Appendix 13) 13. The semiconductor device according to claim 1, wherein a width of a bottom of the opening is greater than a height of the insulating film forming a sidewall of the opening.

[0191] (Appendix 14) The semiconductor device according to claim 3, wherein the second electrode has a layered structure including two or more types of metal layers.

[0192] (Appendix 15) 15. The semiconductor device according to claim 1, wherein the first electrode is in contact with the top surface of the semiconductor substrate at a bottom of the opening.

[0193] (Appendix 16) 16. The semiconductor device according to any one of claims 1 to 15, wherein each of the two or more trench electrodes covered with the insulating film is a gate electrode of an IGBT (Insulated Gate Bipolar Transistor) formed on the semiconductor substrate.

[0194] (Appendix 17) The plurality of trench electrodes include The two or more trench electrodes include a plurality of first trench electrodes covered with the insulating film; at least one second trench electrode provided inside the opening of the insulating film; each of the plurality of first trench electrodes is a gate electrode of an IGBT formed on the semiconductor substrate; the at least one second trench electrode is not covered with the insulating film and is electrically connected to the first electrode; 17. The semiconductor device of claim 1, wherein the first recess in the top surface of the at least one second trench electrode forms a part of a bottom of the opening.

[0195] (Appendix 18) the at least one second trench electrode is formed inside each of the plurality of trenches via a trench insulating film provided along an inner wall of each of the plurality of trenches; 18. The semiconductor device of claim 17, wherein an upper surface of the trench insulating film in contact with the at least one second trench electrode includes a fifth recess located below the upper surface of the semiconductor substrate.

[0196] (Appendix 19) A method for manufacturing the semiconductor device according to claim 3, comprising the steps of: forming the first electrode by a sputtering method; and forming the second electrode by plating.

[0197] (Appendix 20) A method for manufacturing a semiconductor device according to claim 17, comprising the steps of: preparing the semiconductor substrate including the plurality of trenches and the plurality of trench electrodes respectively formed within the plurality of trenches; forming the insulating film covering the first trench electrodes among the plurality of trench electrodes; The step of forming the insulating film includes: forming the insulating film on the plurality of trench electrodes; removing the insulating film on the at least one second trench electrode among the plurality of trench electrodes to form the opening in the insulating film between the plurality of first trench electrodes covered with the insulating film; The method for manufacturing a semiconductor device, wherein the first recess in the top surface of the at least one second trench electrode forms a part of a bottom of the opening.

[0198] (Appendix 21) A method for manufacturing a semiconductor device according to claim 18, comprising the steps of: preparing the semiconductor substrate including the plurality of trenches and the plurality of trench electrodes respectively formed within the plurality of trenches; forming the insulating film covering the first trench electrodes among the plurality of trench electrodes; forming the insulating film on the plurality of trench electrodes; removing the insulating film on the at least one second trench electrode among the plurality of trench electrodes to form the opening in the insulating film between the plurality of first trench electrodes covered with the insulating film; 2. A method for manufacturing a semiconductor device, wherein the step of forming the opening includes removing an upper portion of the trench insulating film in contact with the at least one second trench electrode to form the fifth recess. [Explanation of symbols]

[0199] 1n - 1 n-type drift layer, 2 n-type carrier accumulation layer, 3 n-type buffer layer, 4 interlayer insulating film, 4a opening, 5 barrier metal, 6 emitter electrode, 6a termination electrode, 6b first emitter electrode, 6c second emitter electrode, 7 collector electrode, 8 trench structure, 9 oxide film, 10 IGBT region, 11 active trench, 11a gate trench electrode, 11b gate trench insulating film, 12 dummy trench, 12a dummy trench electrode, 12b dummy trench insulating film, 13 n + Mold source layer, 14 p + 15 p-type base layer, 16 p-type collector layer, 16a p-type termination collector layer, 20 diode region, 21 diode trench, 21a diode trench electrode, 21b diode trench insulating film, 24 p +p-type contact layer, 25 p-type anode layer, 26 n + a p-type cathode layer, 30 a termination region, 31 a p-type termination well layer, 32 a n + type channel stopper layer, 33 semi-insulating film, 34 termination protection film, 40 pad region, 41 control pad, 41a current sense pad, 41b Kelvin emitter pad, 41c gate pad, 41d temperature sense diode pad, 41e temperature sense diode pad, 51 first recess, 52 second recess, 53 third recess, 54 fourth recess, 55 fifth recess, 82 region, 83 region, 100 semiconductor device, 101 semiconductor device, P region, Q region, R region.

Claims

1. A plurality of trenches provided on the upper surface of a semiconductor substrate, a plurality of trench electrodes respectively provided inside the plurality of trenches, an insulating film covering two or more of the plurality of trench electrodes, a first electrode provided on the insulating film, and comprising: the insulating film includes an opening provided between the two or more trench electrodes covered by the insulating film, the first electrode is provided on the semiconductor substrate so as to close the opening, the upper surface of each of the plurality of trench electrodes includes a first recess, the upper surface of the insulating film includes a second recess directly above the first recess, the upper surface of the first electrode includes a third recess directly above the opening, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the third recess is further provided directly above the second recess on the upper surface of the first electrode.

3. Further comprising a second electrode provided on the first electrode, the upper surface of the second electrode includes a fourth recess directly above the third recess, the semiconductor device according to claim 1.

4. The semiconductor device according to claim 3, wherein the depth of the fourth recess is shallower than the depth of the third recess.

5. The semiconductor device according to claim 4, wherein the depth of the fourth recess is shallower than the depth of the second recess and the depth of the opening.

6. The semiconductor device according to claim 5, wherein the depth of the fourth recess is shallower than the depth of the first recess.

7. The semiconductor device according to claim 1, wherein the bottom of the first recess is provided at a position lower than the upper surface of the semiconductor substrate.

8. The semiconductor device according to claim 1, wherein the upper end of each of the plurality of trench electrodes is provided at a position lower than the upper surface of the semiconductor substrate.

9. The semiconductor device according to claim 1, wherein the insulating film has a single-layer structure including an oxide film.

10. The semiconductor device according to claim 1, wherein the insulating film has a laminated structure including two or more oxide films having different dopant concentrations.

11. The semiconductor device according to claim 3, wherein the thickness of the first electrode is thicker than the thickness of the second electrode.

12. The semiconductor device according to claim 3, wherein the thickness of the second electrode is thicker than the thickness of the first electrode.

13. The semiconductor device according to claim 1, wherein the width of the bottom of the opening is larger than the height of the insulating film forming the side wall of the opening.

14. The semiconductor device according to claim 3, wherein the second electrode has a laminated structure including two or more metal layers.

15. The semiconductor device according to claim 1, wherein the first electrode is in contact with the upper surface of the semiconductor substrate at the bottom of the opening.

16. The semiconductor device according to claim 1, wherein each of the two or more trench electrodes covered with the insulating film is a gate electrode of an IGBT (Insulated Gate Bipolar Transistor) formed in the semiconductor substrate.

17. The plurality of trench electrodes are As the two or more trench electrodes, a plurality of first trench electrodes covered with the insulating film, And at least one second trench electrode provided inside the opening of the insulating film, and Each of the plurality of first trench electrodes is a gate electrode of an IGBT formed in the semiconductor substrate, The at least one second trench electrode is not covered with the insulating film and is electrically connected to the first electrode, The first recess on the upper surface of the at least one second trench electrode forms a part of the bottom of the opening. The semiconductor device according to claim 1.

18. The at least one second trench electrode is formed inside each of the plurality of trenches through a trench insulating film provided along the inner wall of each of the plurality of trenches, The upper surface of the trench insulating film in contact with the at least one second trench electrode includes a fifth recess located below the upper surface of the semiconductor substrate. The semiconductor device according to claim 17.

19. A method for manufacturing a semiconductor device according to claim 3, comprising: Forming the first electrode by a sputtering method; and Forming the second electrode by a plating method. A method for manufacturing a semiconductor device.

20. A method for manufacturing a semiconductor device according to claim 17, comprising: Preparing the semiconductor substrate including the plurality of trenches and the plurality of trench electrodes respectively formed inside the plurality of trenches; and Forming an insulating film covering the plurality of first trench electrodes among the plurality of trench electrodes. The step of forming the insulating film Forming the insulating film on the plurality of trench electrodes. removing the insulating film on the at least one second trench electrode among the plurality of trench electrodes to form the opening of the insulating film between the plurality of first trench electrodes covered by the insulating film; A method of manufacturing a semiconductor device, wherein the first recess on the upper surface of the at least one second trench electrode forms a part of the bottom of the opening.

21. A method of manufacturing a semiconductor device according to claim 18, preparing the semiconductor substrate including the plurality of trenches and the plurality of trench electrodes respectively formed inside the plurality of trenches; forming an insulating film covering the plurality of first trench electrodes among the plurality of trench electrodes; The step of forming the insulating film includes forming the insulating film on the plurality of trench electrodes; removing the insulating film on the at least one second trench electrode among the plurality of trench electrodes to form the opening of the insulating film between the plurality of first trench electrodes covered by the insulating film; The step of forming the opening includes removing an upper portion of the trench insulating film in contact with the at least one second trench electrode to form the fifth recess. A method of manufacturing a semiconductor device.

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