Semiconductor device
The semiconductor device improves saturation current and reduces latch-up and power loss by employing a structured drift region with trench and mesa portions, optimized doping, and specific electrode configurations, addressing the limitations of existing IGBTs.
Patent Information
- Application Number
- JP2024172716
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2017-05-16
- Filing Date
- 2024-10-01
- Publication Date
- 2024-12-13
Smart Images
Figure 2024174159000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to a semiconductor device. [Background technology]
[0002] 2. Description of the Related Art Conventionally, semiconductor devices such as insulated gate bipolar transistors (IGBTs) are known (see, for example, Patent Document 1). Patent Document 1: JP 2007-311627 A Summary of the Invention [Problem to be solved by the invention]
[0003] In semiconductor devices, it is preferable to improve characteristics such as saturation current. [Means for solving the problem]
[0004] In a first aspect of the present invention, there is provided a semiconductor device including a drift region of a first conductivity type provided in a semiconductor substrate. The semiconductor device may include a base region of a second conductivity type provided between an upper surface of the semiconductor substrate and the drift region. Any of the semiconductor devices may include a plurality of trench portions extending in a predetermined first direction on the upper surface of the semiconductor substrate, the trench portions including adjacent first and second trench portions. Any of the semiconductor devices may include an N+ type region of a first conductivity type provided adjacent to the first trench portion in a mesa portion, which is a portion of the semiconductor substrate sandwiched between the first and second trench portions. Any of the semiconductor devices may include a contact region of a second conductivity type provided adjacent to the second trench portion in the mesa portion. In any of the semiconductor devices, at least one of the N+ type region and the contact region may be provided in a stripe shape extending in the first direction in a top view of the semiconductor substrate. In any of the above semiconductor devices, the contact region may have a plurality of peaks in a doping concentration distribution in a depth direction.
[0005] In the doping concentration distribution of any of the above semiconductor devices, the multiple peaks may include a first peak and a second peak that is located closer to the bottom surface of the semiconductor substrate than the first peak and is lower than the first peak. In the doping concentration distribution of any of the above semiconductor devices, the first peak and the second peak may be higher than the doping concentration of the base region. In any of the above semiconductor devices, the N+ type region may have at least one peak in the doping concentration distribution at a position different from the first peak and the second peak.
[0006] Any of the above semiconductor devices may include a trench contact portion provided from an upper surface of the semiconductor substrate to an interior of the semiconductor substrate. Any of the above semiconductor devices may include a high concentration region of a second conductivity type that is in contact with the trench contact portion and has a doping concentration higher than that of the contact region.
[0007] In a second aspect of the present invention, there is provided a semiconductor device including a drift region of a first conductivity type provided in a semiconductor substrate. The semiconductor device may include a base region of a second conductivity type provided between an upper surface of the semiconductor substrate and the drift region. Any of the semiconductor devices may include a plurality of trench portions extending in a predetermined first direction on the upper surface of the semiconductor substrate, the trench portions including adjacent first and second trench portions. Any of the semiconductor devices may include an N+ type region of a first conductivity type provided adjacent to the first trench portion between the upper surface of the semiconductor substrate and the base region in a mesa portion that is a portion of the semiconductor substrate sandwiched between the first and second trench portions. Any of the semiconductor devices may include a contact region of a second conductivity type provided adjacent to the second trench portion in the mesa portion. Any of the semiconductor devices may include a trench contact portion provided from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate. Any of the above semiconductor devices may include a high concentration region of a second conductivity type, the high concentration region having a doping concentration higher than that of the contact region, provided between the trench contact portion and the contact region. In any of the above semiconductor devices, at least one of the N+ type region and the contact region may be provided in a stripe shape extending in the first direction in a top view of the semiconductor substrate.
[0008] Any of the above semiconductor devices may include an interlayer insulating film provided above an upper surface of the semiconductor substrate, a contact hole penetrating the interlayer insulating film and connected to the trench contact portion, and an electrode filled in the trench contact portion and the contact hole. In any of the above semiconductor devices, the electrode may have a barrier metal containing titanium and a plug containing tungsten. In any of the above semiconductor devices, the N+ type region, the contact region, and the contact hole may be provided in a stripe shape extending in the first direction.
[0009] Any of the above semiconductor devices may include a conductive material containing tungsten that is filled in the trench contact portion. In any of the above semiconductor devices, the first trench portion may be a gate trench portion. In any of the above semiconductor devices, the second trench portion may be a dummy trench portion.
[0010] In any of the above semiconductor devices, the contact region may have a doping concentration higher than that of the base region. In any of the above semiconductor devices, the depth of the contact region from the top surface of the semiconductor substrate may be 1.5 times or more the depth of the N+ type region from the top surface of the semiconductor substrate.
[0011] In any of the above semiconductor devices, the length of the stripe shape in the first direction may be ten times or more as large as the width in a second direction perpendicular to the first direction in a top view of the semiconductor device. In the second direction perpendicular to the first direction in a top view of the semiconductor device, the width of a lower surface of the N+ type region may be smaller than the width of a lower surface of the contact region.
[0012] In any of the above semiconductor devices, the mesa portion may be provided in a transistor portion including a transistor. In any of the above semiconductor devices, the transistor portion may include a second mesa portion in which the N+ type region is not provided. In any of the above semiconductor devices, the semiconductor substrate may be any of a silicon substrate, a silicon carbide substrate, and a nitride semiconductor substrate.
[0013] The above summary of the invention does not list all the features of the present invention. Subcombinations of these features may also be inventions. [Brief description of the drawings]
[0014] [Figure 1] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2]1 is a top view showing an example of an emitter region 12 and a contact region 15 in two mesa portions 60 in a transistor portion 70. FIG. [Diagram 3] FIG. 2 is a diagram showing an example of a-a cross section in FIG. [Figure 4] 2 is a cross-sectional view showing an example of a mesa portion 60 sandwiched between a gate trench portion 40 and a dummy trench portion 30. FIG. [Diagram 5] 2 is a cross-sectional view showing an example of a mesa portion 60 sandwiched between a gate trench portion 40 and a dummy trench portion 30. FIG. [Figure 6] 6 is a diagram showing an example of a doping concentration distribution of the emitter region 12 in the bb cross section shown in FIG. 5 and a doping concentration distribution of the contact region 15 in the cc cross section. [Figure 7] 2 is a cross-sectional view showing an example of a mesa portion 60 sandwiched between a gate trench portion 40 and a dummy trench portion 30. FIG. [Figure 8] 13 is a top view showing another example of the emitter region 12 and the contact region 15 in the two mesa portions 60 in the transistor portion 70. FIG. [Figure 9] 13 is a top view showing another example of the emitter region 12 and the contact region 15 in the two mesa portions 60 in the transistor portion 70. FIG. [Figure 10] 1 is a diagram showing an example of paths through which electron current and displacement current flow in the vicinity of a mesa portion 60 in an example having only one accumulation region 16. FIG. [Figure 11] 1 is a diagram showing an electron current and a displacement current at the time of turn-on in a semiconductor device 100 having a first accumulation region 16-1 and a second accumulation region 16-2. FIG. [Figure 12] 2 is a diagram showing another example of the aa cross section of the semiconductor device 100. FIG. [Figure 13] 13 is a diagram showing another example of the top surface of the semiconductor device 100. FIG. [Figure 14] FIG. 14 is a diagram showing an example of a-a cross section in FIG. [Figure 15] FIG. 1 is a top view illustrating an example of a semiconductor device 200 according to an embodiment of the present invention. [Figure 16] FIG. 16 is a diagram showing an example of a cross section dd in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0015] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.
[0016] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.
[0017] In this specification, technical matters may be described using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and a depth direction perpendicular to the top surface of the semiconductor substrate is defined as the Z axis.
[0018] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities.
[0019] 1 is a diagram partially illustrating the top surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80. The transistor section 70 includes a transistor such as an IGBT. The diode section 80 is provided adjacent to the transistor section 70 on the top surface of a semiconductor substrate, and includes a diode such as an FWD (Free Wheel Diode). FIG. 1 shows the chip top surface around the chip end, and omits other regions.
[0020] 1 shows an active region of the semiconductor substrate in semiconductor device 100, but semiconductor device 100 may have an edge termination structure surrounding the active region. The active region refers to a region through which current flows when semiconductor device 100 is controlled to be in an on-state. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure that combines these.
[0021] The semiconductor device 100 of this example is provided inside a semiconductor substrate and includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 that are exposed on the upper surface of the semiconductor substrate. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate electrode 50 that are provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate electrode 50 are provided separately from each other.
[0022] An interlayer insulating film is provided between the emitter electrode 52 and the gate electrode 50 and the upper surface of the semiconductor substrate, but is omitted in Fig. 1. In the interlayer insulating film of this example, a contact hole 56, a contact hole 49, and a contact hole 54 are provided so as to penetrate the interlayer insulating film.
[0023] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. An insulating film such as an oxide film is provided between the connection portion 25 and the upper surface of the semiconductor substrate.
[0024] The gate electrode 50 contacts the gate wiring 48 through the contact hole 49. The gate wiring 48 is formed of polysilicon doped with impurities or the like. The gate wiring 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate. The gate wiring 48 is not connected to the dummy conductive portion in the dummy trench portion 30. The gate wiring 48 in this example is provided from below the contact hole 49 to the tip of the gate trench portion 40. An insulating film such as an oxide film is provided between the gate wiring 48 and the upper surface of the semiconductor substrate. At the tip of the gate trench portion 40, the gate conductive portion is exposed to the upper surface of the semiconductor substrate and contacts the gate wiring 48.
[0025] The emitter electrode 52 and the gate electrode 50 are made of a material containing a metal. For example, at least a portion of each electrode is made of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal made of titanium or a titanium compound under the region made of aluminum or the like, and may have a plug made of tungsten or the like in the contact hole.
[0026] The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the Y-axis direction in this example) in the region of the transistor portion 70. In the transistor portion 70, the one or more gate trench portions 40 and the one or more dummy trench portions 30 may be provided alternately along the arrangement direction.
[0027] The gate trench portion 40 in this example may have two extension portions 39 extending along an extension direction (the X-axis direction in this example) parallel to the upper surface of the semiconductor substrate and perpendicular to the arrangement direction, and a connection portion 41 connecting the two extension portions 39. It is preferable that at least a part of the connection portion 41 is formed in a curved shape. By connecting the ends of the two extension portions 39 of the gate trench portion 40, electric field concentration at the ends of the extension portions 39 can be alleviated. The gate wiring 48 may be connected to the gate conductive portion at the connection portion 41 of the gate trench portion 40.
[0028] The dummy trench portion 30 of this example is provided between the extension portions 39 of the gate trench portion 40. The dummy trench portion 30 may have a U-shape on the upper surface of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 of this example has two extension portions 29 extending along the extension direction and a connection portion 31 connecting the two extension portions 29. In another example, the dummy trench portion 30 may have a linear shape extending in the extension direction without having the connection portion 31.
[0029] In the diode section 80, a plurality of dummy trench sections 30 are continuously arranged. Also, in the region of the transistor section 70 adjacent to the diode section 80, a plurality of dummy trench sections 30 may be continuously arranged. In this example, the linear extensions (31, 29) of each trench section are regarded as one trench section.
[0030] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is of the second conductivity type, and is provided within a predetermined range from the end of the active region on the side where the gate electrode 50 is provided. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate electrode 50 side are provided in the well region 11. The bottom of the end of the dummy trench portion 30 in the extension direction may be covered by the well region 11.
[0031] A base region 14 is provided in the mesa portion 60 sandwiched between each trench portion. The base region 14 is of a second conductivity type having a lower doping concentration than the well region 11. In this example, the base region 14 is of P-type. The mesa portion 60 is a portion of the semiconductor substrate sandwiched between two adjacent trench portions, and may be a portion from the top surface of the semiconductor substrate to the depth of the deepest bottom of each trench portion. In this example, a base region 14-e is disposed at both ends in the X-axis direction of each mesa portion 60 (only one end in the X-axis direction is shown in FIG. 1).
[0032] A contact region 15 of a second conductivity type having a doping concentration higher than that of the base region 14 is selectively provided on the upper surface of the mesa portion 60. In this example, the contact region 15 is of P+ type. Also, an emitter region 12 of a first conductivity type having a doping concentration higher than that of the semiconductor substrate is selectively provided on the upper surface of the mesa portion 60 of the transistor portion 70. In this example, the emitter region 12 is of N+ type.
[0033] The emitter region 12 is provided adjacent to the gate trench portion 40 on the upper surface of the mesa portion 60. The emitter region 12 may be provided adjacent to the dummy trench portion 30 on the upper surface of the mesa portion 60, or may be provided separately from the dummy trench portion 30. The emitter region 12 in the example of FIG.
[0034] The contact region 15 of the transistor portion 70 is provided adjacent to the dummy trench portion 30 on the upper surface of the mesa portion 60. The contact region 15 may be provided adjacent to the gate trench portion 40 on the upper surface of the mesa portion 60, or may be provided separately. The contact region 15 in the example of FIG. 1 is adjacent to the gate trench portion 40 at an end of the contact region 15 in the X-axis direction. Each of the emitter region 12 and the contact region 15 has a portion exposed by the contact hole 54.
[0035] At least one of the emitter region 12 and the contact region 15 in the transistor section 70 is provided in a stripe shape extending in the extension direction (X-axis direction) of the trench section on the upper surface of the semiconductor substrate. The stripe shape means that the length in the extension direction (X-axis direction) of the trench section is longer than the width in the arrangement direction (Y-axis direction) of the trench sections. The length and width may refer to the maximum length and maximum width in the X-axis direction and Y-axis direction. The stripe shape may refer to a shape in which the length is twice or more than the width, four times or more than the width, or ten times or more than the width.
[0036] 1, one stripe-shaped emitter region 12 and one stripe-shaped contact region 15 are provided in each mesa portion 60 of the transistor portion 70. In another example, at least one of the emitter region 12 and the contact region 15 may be provided discretely in the X-axis direction. In other words, at least one of the emitter region 12 and the contact region 15 may be provided in a plurality of regions spaced apart from each other in the X-axis direction.
[0037] In this example, the mesa portion 60 of the diode portion 80 is not provided with an emitter region 12. In the mesa portion 60 of the diode portion 80, the contact region 15 or the base region 14 is provided across the mesa portion 60 from one dummy trench portion 30 to the other dummy trench portion 30. In other words, on the upper surface of the semiconductor substrate, the width in the Y-axis direction of the mesa portion 60 of the diode portion 80 is equal to the width in the Y-axis direction of the contact region 15 or the base region 14 provided in the mesa portion 60 of the diode portion 80.
[0038] As an example, the mesa portion 60 of the diode portion 80 adjacent to the transistor portion 70 is provided with the contact region 15 in the entire region sandwiched between the base regions 14-e. Similarly, the mesa portion 60 of the transistor portion 70 adjacent to the diode portion 80 may be provided with the contact region 15 in the entire region sandwiched between the base regions 14-e. The mesa portion 60 of the diode portion 80 not adjacent to the transistor portion 70 may be provided with a contact region 15 having a smaller area exposed on the upper surface of the semiconductor substrate than the contact region 15 of the mesa portion 60 adjacent to the transistor portion 70. As an example, the mesa portion 60 of the diode portion 80 not adjacent to the transistor portion 70 is provided with the contact regions 15-e at both ends in the X-axis direction of the region sandwiched between the base regions 14-e, and the base region 14 is provided in the entire region sandwiched between the contact regions 15-e.
[0039] In the transistor section 70, the contact holes 54 are provided above the contact region 15 and the emitter region 12. In the diode section 80, the contact holes 54 are provided above the contact region 15 and the base region 14. None of the contact holes 54 are provided above the base region 14-e and the well region 11 that are arranged at both ends of the mesa section 60 in the X-axis direction.
[0040] The semiconductor device 100 has a first conductivity type accumulation region 16 selectively provided below the base region 14 inside the semiconductor substrate. In Fig. 1, the range in which the accumulation region 16 is provided is indicated by a dashed line. The diode section 80 has a first conductivity type cathode region 82 in a region on the lower surface side of the semiconductor substrate. In Fig. 1, the range in which the cathode region 82 is provided is indicated by a dashed line. A second conductivity type collector region may be provided in a region on the lower surface side of the semiconductor substrate where the cathode region 82 is not provided.
[0041] 2 is a top view showing an example of the emitter region 12 and the contact region 15 in two mesa portions 60 in the transistor portion 70. The two mesa portions 60 in this example are sandwiched between the gate trench portion 40 and the dummy trench portion 30.
[0042] In the example of FIG. 2, both the emitter region 12 and the contact region 15 have a stripe shape. The emitter region 12 is disposed along the gate trench portion 40. The length L1 of the emitter region 12 in the X-axis direction in this example is shorter than the length L2 of the region in which the emitter region 12 and the contact region 15 are provided (in this example, the region sandwiched between two base regions 14-e). In the emitter region 12 in this example, both ends in the X-axis direction are disposed away from the base region 14-e. In other examples, both ends in the X-axis direction of the emitter region 12 may be in contact with the base region 14-e. The length L1 of the emitter region 12 may be greater than 50% of the length L2, may be 80% or more, or may be 100%.
[0043] The contact region 15 of this example is disposed along the dummy trench portion 30. The length of the contact region 15 in the X-axis direction is L2. Both ends of the contact region 15 in the X-axis direction are in contact with the base region 14-e. The contact region 15 is also provided in a region between the emitter region 12 and the base region 14-e. Both ends of the contact region 15 in the X-axis direction of another example may be separated from the base region 14-e. In this case, the emitter region 12 may be provided between the contact region 15 and the base region 14-e. The length of the contact region 15 in the X-axis direction may be greater than 50% of the length L2, may be 80% or more, or may be 100%.
[0044] 2, the position where the contact hole 54 is disposed is indicated by a dashed line. The length L3 of the contact hole 54 in the X-axis direction may be longer than the length L1. The length L3 may be shorter than the length L2. Both ends of the contact hole 54 in the X-axis direction may be in the contact region 15.
[0045] 2, the width W1 of the emitter region 12 in the Y-axis direction is half the width W1+W2 of the mesa portion 60. The width W2 of the contact region 15 in the portion sandwiched between the emitter region 12 and the mesa portion 60 may be equal to the width W1 of the emitter region 12. The width W1 being equal to the width W2 may be in the range of 40% or more and 60% or less of the width W2. In another example, the width W1 of the emitter region 12 in the Y-axis direction may be smaller than the width W1+W2 of the mesa portion 60. The width W1 of the emitter region 12 in the Y-axis direction may be smaller than the width W2 of the contact region 15 in the Y-axis direction. The width W3 of the contact hole 54 in the Y-axis direction may be larger than the width W1.
[0046] The structure shown in FIG. 1 and FIG. 2 allows the length of the emitter region 12 adjacent to the gate trench portion 40 to be increased. This increases the channel area, thereby increasing the saturation current of the semiconductor device 100. When the semiconductor device 100 is turned off, etc., and carriers such as holes stored inside the semiconductor substrate are extracted to the emitter electrode 52, the carriers present below the emitter region 12 move along the lower surface of the emitter region 12 through the base region 14 toward the contact region 15. If the distance traveled along the lower surface of the emitter region 12 becomes large, the distance traveled through the base region 14, which has a relatively high resistance, becomes large, and latch-up may occur. In this example, the maximum distance traveled by the carriers is approximately the width W1 of the emitter region 12, so that the carriers can be extracted efficiently. This makes it possible to suppress latch-up.
[0047] Fig. 3 is a diagram showing an example of the aa cross section in Fig. 1. The aa cross section is a YZ plane passing through the emitter region 12. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is provided on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 38.
[0048] Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are formed of a conductive material such as metal. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 is referred to as the depth direction (Z-axis direction).
[0049] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. The semiconductor substrate 10 includes a drift region 18 of a first conductivity type. The drift region 18 in this example is an N-type. The drift region 18 may be a remaining region without other doping regions being formed.
[0050] The semiconductor substrate 10 is provided with a P-type base region 14 between an upper surface 21 of the semiconductor substrate 10 and the drift region 18, the base region 14 having a lower doping concentration than the contact region 15. The gate trench portion 40 and the dummy trench portion 30 are provided from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to the inside of the semiconductor substrate 10 (the drift region 18 in this example). As described above, the mesa portion 60 is a region sandwiched between the gate trench portion 40 and the dummy trench portion 30 inside the semiconductor substrate 10. Each mesa portion 60 may be provided with a base region 14.
[0051] In this cross section, an emitter region 12 and a contact region 15 are provided in a mesa portion 60 of a transistor portion 70. The emitter region 12 is provided inside the mesa portion 60, between an upper surface 21 of the semiconductor substrate 10 and the drift region 18. The emitter region 12 in this example is provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10, in a region adjacent to the gate trench portion 40.
[0052] The contact region 15 is provided between the upper surface 21 of the semiconductor substrate 10 and the drift region 18 inside the mesa portion 60. The contact region 15 of this example is provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10 in a region adjacent to the dummy trench portion 30.
[0053] Among the mesa portions 60 of the transistor portion 70, the mesa portion 60 adjacent to the diode portion 80 may not be provided with the emitter region 12, and the contact region 15 may be provided adjacent to both of the two dummy trench portions 30. The other structures of the mesa portion 60 are the same as those of the other mesa portions 60.
[0054] In this cross section, the mesa portion 60 of the diode portion 80 is provided with a base region 14. In this example, neither the contact region 15 nor the emitter region 12 is provided in this cross section of the mesa portion 60 of the diode portion 80. Note that, in the mesa portion 60 of the diode portion 80 adjacent to the transistor portion 70, a contact region 15 may be provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10.
[0055] In this example, in each mesa portion 60, an N+ type accumulation region 16 having a doping concentration higher than that of the drift region 18 is provided between the base region 14 and the drift region 18. The accumulation region 16 may be disposed above the lower end of each trench portion.
[0056] Also, each mesa portion 60 may be provided with a first accumulation region 16-1 and a second accumulation region 16-2. The first accumulation region 16-1 and the second accumulation region 16-2 are provided at different positions in the depth direction perpendicular to the upper surface of the semiconductor substrate 10. Each accumulation region 16 has a peak at a different position in the doping concentration distribution in the depth direction. In this specification, the first accumulation region 16-1 and the second accumulation region 16-2 may be simply referred to as accumulation region 16. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in the mesa portion 60.
[0057] By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. In addition, by providing the two accumulation regions 16 at different depth positions, the electron current that has passed through the channel region adjacent to the gate trench portion 40 in each base region 14 can be caused to flow near the center in the Y-axis direction of the mesa portion 60. Therefore, the displacement current that flows from the vicinity of the lower end of the dummy trench portion 30 to the gate trench portion 40 side at the time of turn-on can be suppressed, and the power loss at the time of turn-on can be reduced. The suppression of the displacement current will be described later.
[0058] In both the transistor section 70 and the diode section 80, an N+ type buffer region 20 is provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.
[0059] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. As an example, the diode section 80 is a region overlapping with the cathode region 82 in a direction perpendicular to the lower surface 23 of the semiconductor substrate 10. In addition, the transistor section 70 is a region in which predetermined unit configurations including emitter regions 12 and contact regions 15 are regularly arranged, among the region overlapping with the collector region 22 in a direction perpendicular to the lower surface 23 of the semiconductor substrate 10.
[0060] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also extends through these regions to reach the drift region 18. The trenches extending through the doped region are not limited to those manufactured in the order of forming the doped region and then the trenches. The trenches extending through the doped region also include those formed between the trenches after the trenches are formed.
[0061] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.
[0062] The gate conductive portion 44 includes at least a region facing the adjacent base region 14 in the depth direction, with the gate insulating film 42 sandwiched therebetween. The gate trench portion 40 in this cross section is covered with the interlayer insulating film 38 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.
[0063] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy trench portion 30 in the cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).
[0064] 4 is a cross-sectional view showing an example of a mesa portion 60 sandwiched between a gate trench portion 40 and a dummy trench portion 30. The cross section is a YZ plane perpendicular to the extension direction of each trench portion, emitter region 12, and contact region 15 on the upper surface 21 of the semiconductor substrate 10. The mesa portion 60 is provided with the emitter region 12 adjacent to the gate trench portion 40 and the contact region 15 adjacent to the dummy trench portion 30.
[0065] The contact region 15 may be provided to a position deeper than the emitter region 12 as viewed from the upper surface 21 of the semiconductor substrate 10. In other words, the depth D2 from the upper surface 21 to the lower end of the contact region 15 may be greater than the depth D1 from the upper surface 21 to the lower end of the emitter region 12. With this configuration, the area of the lower surface of the emitter region 12 as viewed from the lower surface 23 of the semiconductor substrate 10 can be reduced. Therefore, the distance that carriers such as holes move along the lower surface of the emitter region 12 during turn-off or the like can be reduced. D2 may be 1.2 times or more, or may be 1.5 times or more, of D1. In addition, the width W3 in the Y-axis direction of the lower surface of the emitter region 12 as viewed from the lower surface 23 of the semiconductor substrate 10 may be smaller than the width W4 of the lower surface of the contact region 15, and may be 75% or less, or may be 50% or less.
[0066] The contact region 15 and the emitter region 12 have a cross-sectional boundary line 93 in the cross section. The inclination θ between the cross-sectional boundary line 93 and the upper surface 21 of the semiconductor substrate 10 may be 70 degrees or more and 110 degrees or less. In other words, the cross-sectional boundary line 93 may be substantially perpendicular to the upper surface 21. The inclination θ may be 80 degrees or more and 100 degrees or less. The inclination θ may be 90 degrees or less. This allows the area of the lower surface of the emitter region 12 and the area of the lower surface of the contact region 15, as viewed from the lower surface 23 side of the semiconductor substrate 10, to be accurately adjusted. Therefore, it is possible to prevent the contact region 15 from covering the entire lower surface of the emitter region 12 while increasing the area of the lower surface of the contact region 15.
[0067] The inclination of the cross-sectional boundary line 93 may be the inclination of a straight line connecting an end 91 of the emitter region 12 on the upper surface 21 of the semiconductor substrate 10 and a point 92 on the cross-sectional boundary line 93 at a predetermined depth position D3 in the YZ plane. The depth position D3 may be, for example, a point that is 60% or more and 90% or less of the depth D1 of the emitter region 12. More specifically, the depth position D3 may be 60%, 70%, 80%, or 90% of the depth D1.
[0068] If the contact region 15 is provided deep in the Z-axis direction along the dummy trench portion 30, the collector-emitter capacitance increases. If the emitter region 12 is provided long in the X-axis direction along the gate trench portion 40, the gate-emitter capacitance increases. By increasing the gate-emitter capacitance, the transconductance (Gm) can be increased, and the saturation current density can be increased when the semiconductor device is short-circuited. By adjusting the depth D2 of the contact region 15 and the length L1 of the emitter region 12, these capacitances can be adjusted to provide a semiconductor device 100 with predetermined performance.
[0069] FIG. 5 is a cross-sectional view showing an example of a mesa portion 60 sandwiched between the gate trench portion 40 and the dummy trench portion 30. As shown in FIG.
[0070] 6 is a diagram showing an example of the doping concentration distribution of the emitter region 12 in the bb cross section shown in FIG. 5 and the doping concentration distribution of the contact region 15 in the cc cross section. In this example, the doping concentration distribution of the contact region 15 has multiple peaks (C1, C2) in the depth direction (Z-axis direction) perpendicular to the upper surface 21 of the semiconductor substrate 10. Also, the doping concentration distribution of the emitter region 12 has multiple peaks (B1, B2) in the depth direction (Z-axis direction) perpendicular to the upper surface 21 of the semiconductor substrate 10. The doping concentrations shown in FIG. 6 correspond to the concentration difference between the donor and the acceptor (net doping concentration).
[0071] By having multiple peaks in the doping concentration distribution, each doped region can be formed to a deeper position. In other words, by changing the range of the impurity ions when ion-implanting the impurity and injecting the impurity into the semiconductor substrate 10 multiple times, deep doped regions can be easily formed. For example, the acceleration energy can be controlled by changing the type of impurity to be implanted, the ion valence of the impurity, the acceleration voltage, etc., to adjust the range of the impurity.
[0072] The dopant having the highest concentration may be the same type at each peak position (C1, C2) of the doping concentration distribution in the contact region 15. As an example, the dopant is boron (B).
[0073] The dopants having the highest concentration may be different types at any two peak positions of the doping concentration distribution of the emitter region 12. For example, the dopant at the shallowest peak B1 of the doping concentration distribution of the emitter region 12 is arsenic (As), and the dopant at the other peak B2 is phosphorus (P). Phosphorus may be implanted using the mask used when implanting arsenic.
[0074] When forming an N-type region at a shallow position, the N-type region can be easily formed by using arsenic as a dopant. However, when arsenic is implanted deep into the semiconductor substrate 10, the acceleration voltage becomes too large. In contrast, by using phosphorus or the like as a dopant, the deep emitter region 12 can be easily formed.
[0075] Moreover, the peak positions (C1, C2) in the doping concentration distribution of the contact region 15 and the peak positions (B1, B2) in the doping concentration distribution of the emitter region 12 may be different. More specifically, the peak positions in the doping concentration distribution of the contact region 15 and the peak positions in the doping concentration distribution of the emitter region 12 may be alternately arranged in the depth direction. In this example, the peak positions B1, C1, B2, and C2 are arranged in this order from the upper surface 21 side of the semiconductor substrate 10. With this structure, it is possible to suppress the diffusion of N-type and P-type dopants in the Y-axis direction over a long range in the depth direction. Therefore, the inclination of the cross-sectional boundary line 93 can be easily controlled.
[0076] FIG. 7 is a cross-sectional view showing an example of a mesa portion 60 sandwiched between a gate trench portion 40 and a dummy trench portion 30. The cross section is a YZ plane. The widths of the emitter region 12 in the Y-axis direction at the peak positions B1 and B2 shown in FIG. 6 are W5 and W6. The width W6 may be 80% or more and 120% or less, or 90% or more and 110% or less, of the width W5. Alternatively, the width W6 may be 80% or more and 90% or less of the width W5. By having a doping concentration distribution as shown in FIG. 6, it is possible to easily form an emitter region 12 having a uniform width in the Y-axis direction over a long range in the depth direction.
[0077] 8 is a top view showing another example of the emitter regions 12 and the contact regions 15 in the two mesa portions 60 in the transistor portion 70. In this example, a plurality of emitter regions 12 are arranged discretely in the X-axis direction. Each emitter region 12 has a stripe shape. A contact region 15 may be arranged between each of the emitter regions 12. The other structures are similar to the example shown in FIG. 2.
[0078] This structure also makes it possible to increase the saturation current of the semiconductor device 100. Furthermore, latch-up of the semiconductor device 100 can be suppressed.
[0079] FIG. 9 is a top view showing another example of the emitter regions 12 and the contact regions 15 in the two mesa portions 60 in the transistor portion 70. In this example, a plurality of contact regions 15 are arranged discretely in the X-axis direction. Each contact region 15 has a stripe shape. An emitter region 12 may be arranged between each contact region 15. The other structures are similar to the example shown in FIG. 2. In addition, an emitter region 12 may be arranged between the contact region 15 and the base region 14-e.
[0080] This structure also makes it possible to increase the saturation current of the semiconductor device 100. Furthermore, latch-up of the semiconductor device 100 can be suppressed.
[0081] Fig. 10 is a diagram showing an example of paths through which electron current and displacement current flow near the mesa portion 60 in an example having only one accumulation region 16. Fig. 10 shows the current paths at the time of turn-on. At the time of turn-on, the voltage of the gate conductive portion 44 gradually rises from 0 [V]. As a result, negative charges are induced near the gate trench portion 40 of the base region 14, forming a channel.
[0082] The main current in the initial stage of turn-on is electron current, not hole current. The initial stage is the period from just before the gate voltage Vge reaches the threshold voltage to just before the Miller period, during which Vge becomes constant at approximately the threshold voltage. When Vge approaches the threshold voltage, the channel begins to open and electrons begin to be injected into the drift region.
[0083] 10, electrons flowing downward from the channel may flow once in the arrangement direction (the Y-axis direction, or the direction from the vicinity of the gate trench portion 40 toward the center of the mesa portion 60) in the accumulation region 16. However, in the drift region 18 below the accumulation region 16, the vicinity of the gate trench portion 40 has a lower impedance than the drift region 18 because an electron accumulation layer has already been formed (the threshold voltage at which the electron accumulation layer is formed in the N-type region is much lower than the threshold voltage of the inversion layer in the P-type region). Therefore, the electron current mainly flows near the gate trench portion 40.
[0084] When the electrons reach the collector region 22 on the back surface, holes start to be injected from the collector region 22 to the buffer region 20 and the drift region 18. As a result, holes are accumulated near the bottom end of the trench portion. As an example, holes are accumulated at a rate of 1E+16 [cm -3 ] order.
[0085] The holes gather at the lower end of the gate trench portion 40 and the lower end of the dummy trench portion 30. In particular, since the dummy conductive portion 34 has the same potential as the emitter electrode 52, a hole inversion layer is likely to form on the side wall of the dummy trench portion 30. The holes injected from the collector region 22 gather near this hole inversion layer. The holes are continuously distributed from the dummy trench portion 30 to the lower end of the gate trench portion 40. Due to this hole distribution, a large displacement current flows near the lower end of the gate trench portion 40 when turned on.
[0086] The displacement current caused by the accumulation of holes causes charging of the gate conductive portion 44 that faces the gate insulating film 42. This charging of the gate conductive portion 44 causes an instantaneous increase in the gate electrode Vge. The larger the displacement current, the more the gate conductive portion 44 is charged, and therefore the more quickly the potential of the gate conductive portion 44 rises. As a result, the potential of the gate conductive portion 44 instantaneously exceeds the gate threshold value.
[0087] This initiates a large injection of electrons and holes, increasing the collector-emitter current. The rate of voltage decrease (dV / dt) of the collector-emitter voltage increases according to the rate of change of the current caused by the increase in the collector-emitter current. The larger the displacement current, the larger the dV / dt. In particular, the less the accumulated holes can flow to the emitter electrode 52, the larger the displacement current and the larger the instantaneous increase in the potential of the gate conductive portion 44. Therefore, in the example of FIG. 10, dV / dt becomes relatively large, and the electromagnetic noise also becomes relatively large.
[0088] 11 is a diagram showing the electron current and the displacement current at the time of turn-on in the semiconductor device 100 having the first accumulation region 16-1 and the second accumulation region 16-2. In this example, too, the electrons that have passed through the channel go in the arrangement direction (Y-axis direction) in the first accumulation region 16-1. However, in this example, the second accumulation region 16-2 is provided below the first accumulation region 16-1.
[0089] In this example, the impedance for the electron current is lower in the path that flows directly from the first accumulation region 16-1 to the second accumulation region 16-2 than in the path that flows from the vicinity of the center of the first accumulation region 16-1 back to the vicinity of the gate trench portion 40 to the second accumulation region 16-2. Holes are likely to accumulate in the high-concentration hole region adjacent to the gate trench portion 40 below each accumulation region 16. In addition, the electron current flows not in the vicinity of the gate trench portion 40 but in the vicinity of the center of the mesa portion 60, which promotes the accumulation of holes in the high-concentration hole region. Therefore, the flow of the electron current to the vicinity of the center of the mesa portion 60 is promoted. In FIG. 11, the high-concentration hole region in which holes are accumulated is shown typically, but the high-concentration hole region may exist only in the vicinity of the boundary between the gate trench portion 40 and the semiconductor substrate 10.
[0090] As described above, the electron current in this example does not return to the vicinity of the gate trench portion 40, but travels downward near the center of the mesa portion 60 sandwiched between the gate trench portion 40 and the dummy trench portion 30. In other words, the electron current in this example flows near the center of the mesa portion 60, not near the gate trench portion 40. The effect of the electron current flowing near the center of the mesa portion 60 is produced by arranging a plurality of accumulation regions in the depth direction.
[0091] When the electron current flows near the center of the mesa portion 60, the hole distribution near the bottom of the mesa portion 60 is divided near the center of the mesa portion 60. Therefore, the holes on the dummy trench portion 30 side of the electron current path do not flow to the gate trench portion 40 side. This division of the hole distribution at the center of the mesa portion 60 suppresses the accumulation of holes at the bottom end of the gate trench portion 40. As a result, the displacement current can be reduced in the example of FIG. 11 compared to the example of FIG. 10. Since the displacement current can be reduced, the charging of the gate conductive portion 44 is also reduced, and the instantaneous increase of the gate electrode Vge is also suppressed. This also suppresses the voltage reduction rate (dV / dt) of the collector-emitter voltage.
[0092] The inventors of the present invention have confirmed through simulations that holes are distributed mainly in the lower end of the gate trench portion 40 and the lower end and side portions of the dummy trench portion 30, and are hardly distributed in the center portion of the mesa portion 60. As an example, the density of holes near the lower end of the gate trench portion 40 and the lower end of the dummy trench portion 30 is 1E+13 [cm -3 ], and in the example of Figure 10, -3 ] is much lower than 1E+13. 13 This is what I mean.
[0093] Although not limited to the above reasons, it is considered that the hole distribution in the example of Fig. 11 is caused by the hole distribution being divided by the electron current between the gate trench portion 40 and the dummy trench portion 30. Also, due to the hole distribution, a smaller displacement current than that in the example of Fig. 10 flows from the vicinity of the bottom end of the dummy trench portion 30 to the vicinity of the bottom end of the gate trench portion 40 at the time of turn-on.
[0094] Therefore, in this example, the displacement current is smaller than in the example of Fig. 10, so that dV / dt is smaller than in the example of Fig. 11, and electromagnetic noise can also be reduced. Also, in this example, it is not necessary to connect an additional gate resistor Rg to the gate conductive portion 44 for the purpose of suppressing a rapid rise in the potential of the gate conductive portion 44. Alternatively, if a small gate resistor Rg is connected to the gate conductive portion 44, a rapid rise in the potential of the gate conductive portion 44 can be suppressed. Therefore, the power loss at the time of turn-on can be reduced compared to the example of Fig. 10.
[0095] The number of accumulation regions 16 provided in the mesa portion 60 may be two. The number of accumulation regions 16 may be three or more, but there is a possibility that the accumulation of carriers will be too large. This may result in degradation of characteristics, for example, at turn-off. However, the number of accumulation regions 16 provided in the mesa portion 60 is not limited to two. Also, the number of accumulation regions 16 provided in the mesa portion 60 may be one.
[0096] 12 is a diagram showing another example of the aa cross section of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 described in FIGS. 1 to 11 in that a trench contact portion 55 is provided in the mesa portion 60 adjacent to the gate trench portion 40. The structure other than the trench contact portion 55 may be the same as the semiconductor device 100 of any of the aspects described in FIGS. 1 to 11. The trench contact portion 55 may also be provided in the mesa portion 60 not adjacent to the gate trench portion 40. Each trench contact portion 55 is a space provided in a region of the upper surface 21 of the semiconductor substrate 10 exposed by the contact hole 54.
[0097] The trench contact portion 55 provided in the mesa portion 60 adjacent to the gate trench portion 40 contacts each of the emitter region 12 and the contact region 15, and is provided from the upper surface 21 of the semiconductor substrate 10 to a position shallower than the bottom of the emitter region 12. The bottom of the emitter region 12 is the portion that is farthest from the upper surface 21 of the semiconductor substrate 10 in the Z-axis direction.
[0098] The trench contact portion 55 may be provided with an emitter electrode 52, or may be filled with a conductive material connected to the emitter electrode 52. The conductive material filled in the trench contact portion 55 may include tungsten. By providing the trench contact portion 55, the contact resistance between the emitter region 12 and the contact region 15 and the emitter electrode 52 can be reduced. By reducing the contact resistance between the contact region 15 and the emitter electrode 52, the latch-up resistance of the semiconductor device 100 can be improved. By providing the emitter region 12 in a stripe shape and providing the trench contact portion 55, it is possible to achieve a large current and high speed while maintaining the latch-up resistance.
[0099] A high-concentration region 26 of the second conductivity type having a higher doping concentration than the contact region 15 may be provided in a region of the contact region 15 that contacts the trench contact portion 55. The doping concentration of the high-concentration region 26 may be two or more times, five or more times, or ten or more times the doping concentration of the contact region 15. By providing the high-concentration region 26, the contact resistance between the contact region 15 and the emitter electrode 52 can be further reduced.
[0100] The trench contact portion 55 provided in the mesa portion 60 not adjacent to the gate trench portion 40 contacts the base region 14 or the contact region 15. The trench contact portion 55 provided in the mesa portion 60 not adjacent to the gate trench portion 40 and the trench contact portion 55 provided in the mesa portion 60 adjacent to the gate trench portion 40 may be formed to the same depth or to different depths. As an example, the trench contact portion 55 provided in the mesa portion 60 not adjacent to the gate trench portion 40 may be formed to a depth deeper than the trench contact portion 55 provided in the mesa portion 60 adjacent to the gate trench portion 40.
[0101] Fig. 13 is a diagram showing another example of the top surface of the semiconductor device 100. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Figs. 1 to 11 in that the width of the contact hole 54 in the Y-axis direction is larger than the width of any of the mesa portions 60 in the Y-axis direction. The structure other than the contact hole 54 may be the same as that of the semiconductor device 100 of any of the aspects shown in Figs. 1 to 11.
[0102] In this example, the contact hole 54 is provided continuously over the entire Y-axis direction in the diode section 80. That is, the width of the contact hole 54 provided above the diode section 80 in the Y-axis direction is larger than the width of the diode section 80 in the Y-axis direction.
[0103] The transistor section 70 has a contact hole 54 provided in a region other than the gate trench section 40 and a region adjacent to the gate trench section 40. In other words, the gate trench section 40 and a region adjacent to the gate trench section 40 are covered with the interlayer insulating film 38, and the other regions are not covered with the interlayer insulating film 38. The contact hole 54 may be provided continuously above the mesa section 60 sandwiched between the dummy trench sections 30, above the dummy trench section 30, and above a part of the mesa section 60 sandwiched between the gate trench section 40 and the dummy trench section 30. The contact hole 54 may cover a part of the emitter region 12 adjacent to the gate trench section 40 in the Y-axis direction and expose a part of it.
[0104] By providing the contact hole 54 continuously above the dummy trench portion 30, it becomes easier to ensure the distance between the gate trench portion 40 and the contact hole 54. This makes it easier to make the mesa portion 60 fine.
[0105] Fig. 14 is a diagram showing an example of the aa cross section in Fig. 13. As described above, the interlayer insulating film 38 is provided above the gate trench portion 40 in the Y-axis direction and above a part of the mesa portion 60 adjacent to the gate trench portion 40, and the contact hole 54 is provided in the remaining region in the Y-axis direction.
[0106] In the mesa portion 60 adjacent to the gate trench portion 40, the interlayer insulating film 38 covers a portion of the emitter region 12 adjacent to the gate trench portion 40, but does not cover a portion of the emitter region 12 adjacent to the contact region 15. In addition, the interlayer insulating film 38 does not cover the contact region 15 even partially. In addition, the upper portions of the mesa portion 60 and the dummy trench portion 30 that are not adjacent to the gate trench portion 40 in the cross section are not covered by the interlayer insulating film 38.
[0107] 15 is a top view showing an example of a semiconductor device 200 according to an embodiment of the present invention. The semiconductor device 200 is different from the semiconductor device 100 in the arrangement of the emitter region 12 and the contact region 15 in the transistor section 70. The other structures are similar to those of the semiconductor device 100.
[0108] In each mesa portion 60 of the transistor portion 70, the emitter regions 12 and the contact regions 15 are alternately arranged in the X-axis direction. On the upper surface of the semiconductor substrate, each of the emitter regions 12 and the contact regions 15 is provided from one trench portion arranged on both sides of the mesa portion 60 to the other trench portion. In other words, the width of the emitter regions 12 and the contact regions 15 in the Y-axis direction is equal to the width of the mesa portion 60 in the Y-axis direction. The length of the emitter regions 12 and the contact regions 15 in the X-axis direction may be smaller than, the same as, or larger than the width in the Y-axis direction.
[0109] Fig. 16 is a diagram showing an example of the dd cross section in Fig. 15. The dd cross section is an XZ plane that passes through the mesa portion 60 of the transistor portion 70, is parallel to the X-axis direction, and is perpendicular to the upper surface 21 of the semiconductor substrate 10. As described above, in the mesa portion 60, the emitter regions 12 and the contact regions 15 are alternately arranged in the X-axis direction.
[0110] In this example, in the cross section, the inclination θ of the cross-sectional boundary line 93 of the contact region 15 and the emitter region 12 with respect to the upper surface 21 of the semiconductor substrate 10 is not less than 70 degrees and not more than 110 degrees. The inclination θ of the cross-sectional boundary line 93 may be the inclination of a straight line connecting the end portion 91 and the point 92, similar to the cross-sectional boundary line 93 described in Fig. 4. Note that, in all boundaries of the contact region 15 and the emitter region 12, the cross-sectional boundary line 93 is preferably not less than 70 degrees and not more than 110 degrees.
[0111] As a result, since the cross-sectional boundary line 93 is approximately vertical, the length in the X-axis direction of the emitter region 12 can be adjusted with precision. As a result, the length in the X-axis direction of the region where the emitter region 12 and the gate trench portion 40 are adjacent to each other (i.e., the channel width) can be adjusted with precision.
[0112] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]
[0113] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 25 connection portion, 26 high concentration region, 29 extension portion, 30 dummy trench portion, 31 connection portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 extension portion, 40 5. Gate trench portion, 41. Connection portion, 42. Gate insulating film, 44. Gate conductive portion, 48. Gate wiring, 49. Contact hole, 50. Gate electrode, 52. Emitter electrode, 54. Contact hole, 55. Trench contact portion, 56. Contact hole, 60. Mesa portion, 70. Transistor portion, 80. Diode portion, 82. Cathode region, 91. End portion, 92. Point, 93. Cross-section boundary line, 100. Semiconductor device, 200. Semiconductor device
Claims
1. a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided between an upper surface of the semiconductor substrate and the drift region; A plurality of trench portions extending in a predetermined first direction on an upper surface of the semiconductor substrate, the trench portions including adjacent first and second trench portions; a mesa portion that is a portion of the semiconductor substrate sandwiched between the first trench portion and the second trench portion, an N+ type region of a first conductivity type provided adjacent to the first trench portion between an upper surface of the semiconductor substrate and the base region; a contact region of a second conductivity type provided adjacent to the second trench portion in the mesa portion; Equipped with When viewed from above on the semiconductor substrate, at least one of the N+ type region and the contact region is provided in a stripe shape extending in the first direction, The contact region has a plurality of peaks in a doping concentration distribution in a depth direction. Semiconductor device.
2. In the doping concentration distribution, the plurality of peaks include a first peak and a second peak that is located closer to the bottom surface of the semiconductor substrate than the first peak and is lower than the first peak, and the first peak and the second peak are higher than the doping concentration of the base region. The semiconductor device according to claim 1 .
3. The N+ type region has at least one peak in the doping concentration distribution at a position different from the first peak and the second peak. The semiconductor device according to claim 2 .
4. a trench contact portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate; a high concentration region of a second conductivity type that is in contact with the trench contact portion and has a doping concentration higher than that of the contact region; The semiconductor device according to claim 1 , further comprising:
5. a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided between an upper surface of the semiconductor substrate and the drift region; A plurality of trench portions extending in a predetermined first direction on an upper surface of the semiconductor substrate, the trench portions including adjacent first and second trench portions; a mesa portion that is a portion of the semiconductor substrate sandwiched between the first trench portion and the second trench portion, an N+ type region of a first conductivity type provided adjacent to the first trench portion between an upper surface of the semiconductor substrate and the base region; a contact region of a second conductivity type provided adjacent to the second trench portion in the mesa portion; a trench contact portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate; a high concentration region of a second conductivity type provided between the trench contact portion and the contact region and having a doping concentration higher than that of the contact region; Equipped with When viewed from above on the semiconductor substrate, at least one of the N+ type region and the contact region is provided in a stripe shape extending in the first direction. Semiconductor device.
6. an interlayer insulating film provided above an upper surface of the semiconductor substrate; a contact hole penetrating the interlayer insulating film and connected to the trench contact portion; an electrode filled in the trench contact portion and the contact hole; Equipped with The electrode includes a barrier metal including titanium and a plug including tungsten.
6. The semiconductor device according to claim 4.
7. The N+ type region, the contact region, and the contact hole are provided in a stripe shape extending in the first direction. The semiconductor device according to claim 6.
8. A conductive material including tungsten is provided to fill the trench contact portion.
6. The semiconductor device according to claim 4.
9. the first trench portion is a gate trench portion, The second trench portion is a dummy trench portion. The semiconductor device according to claim 1 .
10. the contact region is more highly doped than the base region; The depth of the contact region from the upper surface of the semiconductor substrate is 1.5 times or more the depth of the N+ type region from the upper surface of the semiconductor substrate. The semiconductor device according to claim 1 .
11. The length of the stripe shape in the first direction is 10 times or more as large as the width in a second direction perpendicular to the first direction in a top view. The semiconductor device according to claim 1 .
12. In a second direction perpendicular to the first direction in a top view, a width of a lower surface of the N+ type region is smaller than a width of a lower surface of the contact region. The semiconductor device according to claim 1 .
13. the mesa portion is provided in a transistor portion including a transistor, The transistor portion includes a second mesa portion in which the N+ type region is not provided. The semiconductor device according to claim 1 .
14. The semiconductor substrate is any one of a silicon substrate, a silicon carbide substrate, and a nitride semiconductor substrate. The semiconductor device according to claim 1 .