Frequency synthesizer and wireless communication device

Abstract

To provide a frequency synthesizer having a smaller circuit scale and power consumption than before while being able to switch phases at a high speed.SOLUTION: An accumulator 12 generates a count value that increases or decreases with a predetermined step width within a predetermined range according to a clock signal. Digital / analog converters 13-1, 13-2 generate a ramp voltage that increases or decreases according to the count value. Reference voltage circuits 15-1, 15-2 generate multiple reference voltages. Signal generating circuits 14-1, 14-2 generate output frequency signals having phases different from each other, respectively, based on the ramp voltage and the multiple reference voltages. Each of the multiple signal generating circuits 14-1, 14-2 performs analog signal processing to generate an output frequency signal having a signal level that changes with a waveform similar to a sine wave or a cosine wave according to the ramp voltage.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a frequency synthesizer and a wireless communication device including the same. [Background technology]

[0002] The fifth generation mobile communication system (5G) has been put into practical use, and the sixth generation mobile communication system (6G) is currently under development. In order to further increase capacity for 6G, the use of millimeter waves and terahertz waves is being considered. As the frequency increases, it becomes more difficult for radio waves to propagate, so the use of phased array antennas is being widely considered in order to extend communication distances by concentrating the beam. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] "A Technical Tutorial on Digital Signal Synthesis", Analog Devices, Inc., 1999 [Retrieved November 30, 2021], Internet <URL:https: / / www.analog.com / media / en / training-seminars / design-handbooks / Technical-Tutorial-DDS / technical-tutorial-DDS.pdf> Summary of the Invention [Problem to be solved by the invention]

[0004] In order to quickly search for a moving object or track a fast moving object using a phased array antenna, multiple phase shifters that operate at high speed are required. As a frequency synthesizer capable of switching the phase at high speed, for example, a direct digital synthesizer is known. The direct digital synthesizer is disclosed in, for example, Non-Patent Document 1. A conventional direct digital synthesizer includes, for example, an accumulator, a lookup table, and a digital-to-analog converter (DAC). The accumulator is a digital circuit that generates a phase value of an output signal. The lookup table is a ROM that stores a correspondence table of the phase and amplitude of a sine wave, and converts the phase value generated by the accumulator into an amplitude value. The digital-to-analog converter converts the amplitude value generated by the lookup table into a voltage, and generates a voltage signal having a sine wave waveform.

[0005] Since a direct digital synthesizer is composed of a large-scale digital circuit including a ROM, the circuit scale is large and consumes a lot of power when operated at high speed. In addition, if a phased array antenna is realized using a conventional frequency synthesizer, a frequency synthesizer must be provided for each antenna element, which increases the circuit scale and power consumption, making it difficult to install in a mobile terminal device. Therefore, a frequency synthesizer that can switch phases at high speed while having a smaller circuit scale and power consumption than conventional ones is required.

[0006] An object of the present disclosure is to provide a frequency synthesizer that is capable of switching phases at high speed while having a smaller circuit scale and power consumption than conventional ones, and to provide a wireless communication device including such a frequency synthesizer. [Means for solving the problem]

[0007] A frequency synthesizer according to a first aspect of the present disclosure includes: an accumulator that generates a count value that increases or decreases in a predetermined step size within a predetermined range in response to a clock signal; at least one first digital-to-analog converter that generates a ramp voltage that increases or decreases in response to the count value; at least one reference voltage circuit for generating a plurality of reference voltages; a plurality of signal generating circuits each generating an output frequency signal having a different phase from each other based on the ramp voltage and the plurality of reference voltages; each of the plurality of signal generating circuits generates an output frequency signal having a signal level that changes in a waveform similar to a sine wave or a cosine wave in response to the lamp voltage by analog signal processing; The first digital-to-analog converter and the reference voltage circuit supply to the multiple signal generation circuits a ramp voltage that differs for each of the signal generation circuits and the multiple reference voltages that are common among the multiple signal generation circuits, or supply to the multiple signal generation circuits a ramp voltage that is common among the multiple signal generation circuits and the multiple reference voltages including a different combination of voltages for each of the signal generation circuits.

[0008] According to a second aspect of the present disclosure, there is provided a frequency synthesizer comprising: Each of the at least one reference voltage circuit includes a voltage divider resistor that generates the multiple reference voltages.

[0009] According to a third aspect of the present disclosure, there is provided a frequency synthesizer comprising: each of the at least one reference voltage circuit includes a plurality of second digital-to-analog converters that generate the plurality of reference voltages having magnitudes according to a plurality of voltage setting values; The second digital-to-analog converter has at least partially the same components and layout as the first digital-to-analog converter.

[0010] According to a fourth aspect of the present disclosure, the frequency synthesizer according to any one of the first to third aspects includes: a plurality of first digital-to-analog converters; and at least one first adder that adds a phase setting value to the count value to provide a different count value for each of the first digital-to-analog converters.

[0011] According to a fifth aspect of the present disclosure, the frequency synthesizer according to any one of the first to third aspects includes: a plurality of first digital-to-analog converters; at least one third digital-to-analog converter that generates a first bias voltage having a magnitude corresponding to a phase setting value so as to supply a different ramp voltage to each of the signal generating circuits, and adds the first bias voltage to the ramp voltage generated by at least one of the plurality of first digital-to-analog converters; the third digital-to-analog converter having components and a layout at least partially identical to the components and a layout of the first digital-to-analog converter;

[0012] According to a frequency synthesizer according to a sixth aspect of the present disclosure, the frequency synthesizer according to the first aspect includes: a first digital-to-analog converter; a plurality of reference voltage circuits; each of the plurality of reference voltage circuits includes a plurality of second digital / analog converters that generate the plurality of reference voltages having magnitudes according to a plurality of voltage setting values; at least one of the plurality of reference voltage circuits includes a plurality of second adders that add a phase set value to the plurality of voltage set values ​​so as to provide a different voltage set value for each of the reference voltage circuits; The second digital-to-analog converter has at least partially the same components and layout as the first digital-to-analog converter.

[0013] According to a seventh aspect of the present disclosure, the frequency synthesizer according to the first aspect includes: a first digital-to-analog converter; a plurality of reference voltage circuits; each of the plurality of reference voltage circuits includes a plurality of second digital / analog converters that generate the plurality of reference voltages having magnitudes according to a plurality of voltage setting values; at least one of the plurality of reference voltage circuits generates a second bias voltage having a magnitude corresponding to a phase setting value so as to supply a different reference voltage to each of the signal generating circuits; and a plurality of fourth digital-to-analog converters add the second bias voltage to the reference voltage generated by the plurality of second digital-to-analog converters; The second and fourth digital-to-analog converters have at least partially the same components and layout as the first digital-to-analog converter.

[0014] According to an eighth aspect of the present disclosure, in the frequency synthesizer according to any one of the first to seventh aspects, Each of the plurality of signal generating circuits a first differential amplifier for comparing the ramp voltage against a first reference voltage to generate a first differential output signal; a second differential amplifier that compares the ramp voltage against a second reference voltage, the second reference voltage being higher than the first reference voltage, to generate a second differential output signal; a third differential amplifier that compares the ramp voltage to a third reference voltage higher than the second reference voltage to generate a third differential output signal; The output frequency signal is the sum of the first and third differential output signals and an inverse of the second differential output signal.

[0015] According to a ninth aspect of the present disclosure, in the frequency synthesizer according to the eighth aspect, Each of the first to third differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors.

[0016] A wireless communication device according to a tenth aspect of the present disclosure includes a frequency synthesizer according to one of the first to ninth aspects. Effect of the Invention

[0017] According to one aspect of the present disclosure, it is possible to provide a frequency synthesizer that is capable of switching phases at high speed while having a smaller circuit scale and power consumption than conventional ones. [Brief description of the drawings]

[0018] [Figure 1] 1 is a block diagram showing a configuration of a frequency synthesizer 101 according to a first embodiment. [Diagram 2] 2 is a graph showing roughly waveforms of signals generated in frequency synthesizer 101 of FIG. 1. [Diagram 3] 2 is a block diagram showing a configuration of an accumulator 12 in FIG. 1. [Figure 4] 2 is a diagram showing an example of a count value cnt1 generated by the accumulator 12 of FIG. 1. [Diagram 5] 2 is a circuit diagram showing a configuration of digital / analog converters 13-1 and 13-2 in FIG. [Figure 6] 6 is a diagram for explaining the operation of the digital / analog converters 13-1 and 13-2 in FIG. 5. [Figure 7] 2 is a circuit diagram showing configurations of signal generating circuits 14-1 and 14-2 and reference voltage circuits 15-1 and 15-2 in FIG. [Figure 8] 8 is a circuit diagram showing an example of the configuration of differential amplifiers 41 to 43 in FIG. 7. [Figure 9] 8 is a circuit diagram showing another example of the configuration of the differential amplifiers 41 to 43 of FIG. 7. [Figure 10] 8 is a graph roughly illustrating the operating characteristics of each of the differential amplifiers 41 to 43 in FIG. [Figure 11] 8 is a graph showing a schematic change in the operating characteristics when different reference voltages Vmid and Vtop are set for the pair of differential amplifiers 42 and 43 in FIG. 7. [Figure 12] 8 is a graph showing roughly the characteristics of a current Isum generated by the signal generating circuits 14-1 and 14-2 of FIG. 7. [Figure 13] 8 is a diagram for explaining the operation of the signal generating circuits 14-1 and 14-2 in FIG. 7. [Figure 14] FIG. 11 is a block diagram showing a configuration of a frequency synthesizer 101A according to a second embodiment. [Figure 15] FIG. 11 is a block diagram showing a configuration of a frequency synthesizer 101B according to a third embodiment. [Figure 16] 16 is a circuit diagram showing a configuration of a reference voltage circuit 16 of FIG. 15. [Figure 17] FIG. 13 is a block diagram showing a partial configuration of a frequency synthesizer according to a modified example of the third embodiment. [Figure 18] FIG. 13 is a block diagram showing a configuration of a frequency synthesizer 101C according to a fourth embodiment. [Figure 19] 19 is a circuit diagram showing a configuration of a digital / analog converter 17 in FIG. 18. [Figure 20] FIG. 13 is a block diagram showing a configuration of a frequency synthesizer 101D according to a fifth embodiment. [Figure 21] 21 is a circuit diagram showing a configuration of a reference voltage circuit 18 of FIG. 20. [Figure 22] 21 is a diagram for explaining the operation of the signal generating circuits 14-1 and 14-2 in FIG. 20. [Figure 23] FIG. 13 is a block diagram showing the configuration of a frequency synthesizer 101E according to a sixth embodiment. [Figure 24] 24 is a circuit diagram showing a configuration of a reference voltage circuit 19 of FIG. 23. [Diagram 25] FIG. 13 is a block diagram showing a configuration of a wireless communication device 200 according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, a frequency synthesizer and a wireless communication device according to embodiments of the present disclosure will be described with reference to the drawings. In each drawing, the same reference numerals denote similar components.

[0020] [First embodiment] Fig. 1 is a block diagram showing the configuration of a frequency synthesizer 101 according to the first embodiment. Fig. 2 is a graph showing schematic waveforms of signals generated in frequency synthesizer 101 of Fig. 1.

[0021] 1 includes a clock signal source 11, an accumulator 12, digital-to-analog converters (DACs) 13-1 and 13-2, signal generating circuits 14-1 and 14-2, reference voltage circuits 15-1 and 15-2, and an adder 20.

[0022] A clock signal source 11 generates a clock signal clk having a predetermined clock frequency fclk. In general, the clock signal clk has a clock frequency fclk of a fixed value.

[0023] The accumulator 12 generates a count value cnt1 that increases or decreases in a predetermined range by a predetermined step size in response to the clock signal clk. In the example of FIG. 1, the accumulator 12 has a size of n bits, i.e., 0 to 2 n It is possible to generate an n-bit digital count value cnt1 that varies from -1 to 1. The count value cnt1 varies within a predetermined range (i.e., 0 to 2) in response to the clock signal clk, as shown in FIG. n The count value cnt1 increases in a predetermined step size within the range of 2 -1. n When it exceeds -1, it overflows and goes to 2. n The accumulator 12 also receives an n-bit frequency setting value K from an external control circuit (not shown). The frequency setting value K is determined by the number of bits n of the accumulator 12 and has a time period T0=2 nThis indicates the number of times that the count value cnt1 overflows in / fclk (in the example of FIG. 2, K=2).

[0024] The count value cnt1 is supplied as is to the digital-to-analog converter 13-1. In addition, the adder 20 adds a phase set value P to the count value cnt1 to generate a count value cnt2. The count value cnt2 is supplied to the digital-to-analog converter 13-1. The phase set value P is an n-bit digital value indicating a desired phase difference that the output frequency signals Vout1, Vout2 output from the signal generating circuits 14-1, 14-2 should have. By adding the phase set value P to the count value cnt1 using the adder 20, a different count value is supplied to each of the digital-to-analog converters 13-1, 13-2.

[0025] The digital / analog converter 13-1 generates a ramp voltage Vrmp1 that increases or decreases according to the count value cnt1, and the digital / analog converter 13-2 generates a ramp voltage Vrmp2 that increases or decreases according to the count value cnt2. In other words, the digital / analog converters 13-1 and 13-2 convert the digital count values ​​cnt1 and cnt2 into analog ramp voltages Vrmp1 and Vrmp2, respectively. In the example of Fig. 2, the ramp voltage Vrmp1 increases from a minimum value (or a minimum value) to a maximum value (or a maximum value) twice in the time period T0.

[0026] The reference voltage circuits 15-1 and 15-2 generate the same multiple reference voltages Vtop, Vmid, and Vbot. The voltage Vmid is higher than the voltage Vbot, and the voltage Vtop is higher than the voltage Vmid. The reference voltages Vtop, Vmid, and Vbot are equally spaced.

[0027] The digital / analog converters 13-1 and 13-2 supply different ramp voltages Vrmp1 and Vrmp2 to the signal generating circuits 14-1 and 14-2 for each of the signal generating circuits 14-1 and 14-2. The reference voltage circuits 15-1 and 15-2 supply a plurality of reference voltages Vtop, Vmid, and Vbot common to the signal generating circuits 14-1 and 14-2 to the signal generating circuits 14-1 and 14-2.

[0028] The signal generating circuit 14-1 generates an output frequency signal Vout1 based on the ramp voltage Vrmp1 and the reference voltages Vtop, Vmid, and Vbot. The signal generating circuit 14-2 generates an output frequency signal Vout2 based on the ramp voltage Vrmp2 and the reference voltages Vtop, Vmid, and Vbot. Each of the signal generating circuits 14-1 and 14-2 generates the output frequency signals Vout1 and Vout2 by analog signal processing, the output frequency signals Vout1 and Vout2 having signal levels that change in a waveform similar to a sine wave or a cosine wave according to the ramp voltages Vrmp1 and Vrmp2. The output frequency signals Vout1 and Vout2 have different phases from each other. In the example of FIG. 2, the output frequency signals Vout1 and Vout2 have signal levels that change in response to the phase values ​​of the sine wave from 0 to 4π in a time period T0.

[0029] Here, "a waveform similar to a sine wave (or a cosine wave)" means a waveform of a periodic signal consisting of a combination of hyperbolic sine functions that can sufficiently approximate a sine wave (or a cosine wave), as will be described later with reference to Figures 10 to 12. In addition, the output frequency signals Vout1 and Vout2 may include a small error from a sine wave (or a cosine wave) due to manufacturing variations in the components of the frequency synthesizer 101, overflow of the accumulator 12, and the like.

[0030] The count values ​​cnt1, cnt2, the lamp voltages Vrmp1, Vrmp2, and the output frequency signals Vout1, Vout2 each change periodically with a time period T0.

[0031] 1 is a direct digital synthesizer that can generate sine or cosine wave signals of any frequency without using a lookup table. The frequency synthesizer 101 can switch the phase at high speed, while reducing the circuit size and power consumption compared to conventional direct digital synthesizers. The frequency synthesizer 101 can also generate output frequency signals Vout1 and Vout2 having any phase difference that changes according to the phase setting value P.

[0032] Fig. 3 is a block diagram showing the configuration of the accumulator 12 in Fig. 1. The accumulator 12 is a digital circuit including an n-bit adder 21 and an n-bit latch 22. The adder 21 adds a frequency setting value K to a count value cnt1 output from the latch 22 and outputs the result. The latch 22 stores the output value of the adder 21. At each rising edge of the clock signal clk, the latch 22 outputs the currently stored value as the count value cnt1 and stores the output value of the adder 21.

[0033] Fig. 4 is a diagram showing an example of the count value cnt1 generated by the accumulator 12 of Fig. 1. Fig. 5 shows the case where n=4 and K=3. When n=4, the accumulator 12 stores a count value from 0 to 2. nThe adder 21 generates a count value that is cumulatively added within the range of -1, i.e., 0 to 15. When the result of the addition is 16 or more, the adder 21 overflows, and as a result, outputs a value obtained by subtracting 16 from the original result of the addition. When the frequency setting value K=3, the count value cnt1 increases by 3 at each rising edge of the clock signal clk, and after 15, it should be 18, but overflows and becomes 2, and then the count value cnt1 increases by 3 again. When the frequency setting value K=1, the count value cnt1 increases by 1 at each rising edge of the clock signal clk, and after 15, it should be 16, but overflows and becomes 0, and then the count value cnt1 increases by 1 again. When the frequency setting value K=5, the count value cnt1 increases by 5 at each rising edge of the clock signal clk, and after 15, it should be 20, but overflows and becomes 4, and then the count value cnt1 increases by 5 again. The overflow of the count value cnt1 occurs, on average, at f=K×fclk / 2 n It is generated at a period of

[0034] The frequency of the output frequency signals Vout1 and Vout2 is equal to the frequency of the count value cnt1, and is K×fclk / 2. n The number of bits n of accumulator 12 is determined according to the number of channels used by the wireless communication device incorporating frequency synthesizer 101, and generally, n=8 to 12 is sufficient.

[0035] 5 is a circuit diagram showing the configuration of the digital / analog converters 13-1 and 13-2 in FIG. 1. The digital / analog converters 13-1 and 13-2 have the same configuration. Each of the digital / analog converters 13-1 and 13-2 includes a resistor R0, switches 31-1 to 31-(2 n -1), and constant current sources 32-1 to 32-(2 n -1). Switches 31-1 to 31-(2 n The constant current sources 32-1 to 32-(2 n -1) also have the same characteristics as each other and generate a predetermined current I.

[0036] In this specification, the switches 31-1 to 31-(2 n -1) are collectively referred to as "switches 31", and constant current sources 32-1 to 32-(2 n -1) are collectively referred to as "constant current source 32."

[0037] The example of FIG. 5 shows a case where n=3 bits. The digital / analog converters 13-1 and 13-2 are 3 It is provided with -1=7 switches 31 and 7 constant current sources 32. The count values ​​cnt1 and cnt2 are composed of three bits b1 to b3, with b1 being the least significant bit and b3 being the most significant bit. One switch 31 is turned on / off in response to bit b1, two switches 31 are turned on / off in conjunction with each other in response to bit b2, and four switches 31 are turned on / off in conjunction with each other in response to bit b3.

[0038] FIG. 6 is a diagram for explaining the operation of the digital / analog converters 13-1 and 13-2 in FIG. 5. The horizontal axis of FIG. 6 indicates a code consisting of bits b3, b2, and b1 of the count value, and the vertical axis indicates the lamp voltages Vrmp1 and Vrmp2 corresponding to each code. When all the switches 31 are turned off (i.e., when the count value cnt1 is "000"), the lamp voltage Vrmp1 is equal to the power supply voltage Vcc. Each time one switch 31 is turned on, the lamp voltage Vrmp1 drops from the power supply voltage Vcc by I×R0. When all the switches 31 are turned on (i.e., when the count value cnt1 is "111"), the lamp voltage Vrmp1 becomes Vcc-7×I×R0. Also, the lamp voltage Vrmp2 changes with a difference of P·I·R0 with respect to the lamp voltage Vrmp1.

[0039] Although FIG. 4 illustrates an accumulator 12 with n=4, and FIG. 5 and FIG. 6 illustrate digital-to-analog converters 13-1, 13-2 with n=3, it should be noted that the number of bits n of digital-to-analog converters 13-1, 13-2 is set equal to the number of bits n of accumulator 12.

[0040] The digital / analog converters 13-1 and 13-2 in FIG. 5 are current-adding converters that excel in high-speed operation, but any other type of converter may be used.

[0041] Fig. 7 is a circuit diagram showing the configurations of the signal generating circuits 14-1, 14-2 and the reference voltage circuits 15-1, 15-2 of Fig. 1. The signal generating circuits 14-1, 14-2 have the same configuration, and the reference voltage circuits 15-1, 15-2 have the same configuration.

[0042] Each of the signal generating circuits 14-1 and 14-2 includes differential amplifiers 41 to 43 and resistors R11 and R12. The signal generating circuit 14-1 operates as follows. The differential amplifier 41 compares the ramp voltage Vrmp1 with a reference voltage Vbot to generate a first differential output signal. The differential amplifier 42 compares the ramp voltage Vrmp1 with a reference voltage Vmid higher than the reference voltage Vbot to generate a second differential output signal. The differential amplifier 43 compares the ramp voltage Vrmp1 with a reference voltage Vtop higher than the reference voltage Vmid to generate a third differential output signal. The output terminals of the differential amplifiers 41 to 43 are connected to the terminals of the power supply voltage Vcc via the resistors R11 and R12. The output frequency signal Vout1 is the sum of the differential output signals of the differential amplifiers 41 and 43 and an inverted signal of the differential output signal of the differential amplifier 42. Similarly to the signal generating circuit 14-1, the signal generating circuit 14-2 also generates an output frequency signal Vout2 based on the ramp voltage Vrmp2 and the reference voltages Vtop, Vmid, and Vbot.

[0043] Each of the reference voltage circuits 15-1 and 15-2 includes resistors R21 to R24. The resistors R21 to R24 are connected in series between a terminal of a positive power supply voltage Vcc and a terminal of a negative power supply voltage Vee, and are voltage dividing resistors (or resistor ladders) that generate the reference voltages Vtop, Vmid, and Vbot from the power supply voltages Vcc and Vee. The resistance values ​​of the resistors R22 and R23 are set to be equal to each other.

[0044] Fig. 8 is a circuit diagram showing an example of the configuration of the differential amplifiers 41 to 43 of Fig. 7. Each of the differential amplifiers 41 to 43 includes a pair of bipolar transistors Q1, Q2, a constant current source 51, and resistors Ra to Rd. A ramp voltage Vrmp (i.e., ramp voltage Vrmp1 or Vrmp2) is applied to the base of the bipolar transistor Q1, and a reference voltage Vx (x=top, mid, bot) is applied to the base of the bipolar transistor Q2. An output current Ix flows through output terminals dout1 and dout2 according to the potential difference between the ramp voltage Vrmp and the reference voltage Vx.

[0045] Fig. 9 is a circuit diagram showing another example of the configuration of the differential amplifiers 41 to 43 of Fig. 7. The signal generating circuit 14 may include differential amplifiers 41A to 43A of Fig. 9 instead of the differential amplifiers 41 to 43 of Fig. 8. Each of the differential amplifiers 41A to 43A includes a pair of field effect transistors Q1A and Q2A instead of the bipolar transistors Q1 and Q2 of Fig. 8.

[0046] Fig. 10 is a graph that shows the schematic operation characteristics of each of the differential amplifiers 41-43 in Fig. 7. The output current Ix of each of the differential amplifiers 41-43 varies approximately with the characteristics of a hyperbolic sine function tanh(Vrmp) with respect to the ramp voltage Vrmp (solid line) or the characteristics of its inverted signal (dashed line). When the ramp voltage Vrmp is in a predetermined voltage range Vtran centered on the reference voltage Vx, the output current Ix varies according to the ramp voltage Vrmp, but when the ramp voltage Vrmp is outside the voltage range Vtran, the output current Ix does not substantially vary even if the ramp voltage Vrmp changes.

[0047] FIG. 11 is a graph showing a change in the operating characteristics when different reference voltages Vmid and Vtop are set for the pair of differential amplifiers 42 and 43 in FIG. 7. The upper, middle, and lower parts of FIG. 11 show the current Isum', which is the sum of the output currents of the differential amplifiers 42 and 43, with respect to the change in the ramp voltage Vrmp. The upper part of FIG. 11 shows the case where reference voltages Vmid and Vtop (shown as reference voltages V2a and V3a) having a large difference are set, the lower part of FIG. 11 shows the case where reference voltages Vmid and Vtop (shown as reference voltages V2c and V3c) having a small difference are set, and the middle part of FIG. 11 shows the case where reference voltages Vmid and Vtop (shown as reference voltages V2b and V3b) having an intermediate difference between them are set. By combining the differential amplifiers 42 and 43 each having a hyperbolic sine function characteristic, the current Isum' fluctuates with the characteristic of two hyperbolic sine functions connected with respect to the ramp voltage Vrmp. In the upper and lower parts of Fig. 11, the current Isum' deviates significantly from the waveform of a half cycle of a sine wave. On the other hand, in the middle part of Fig. 11, it can be seen that the current Isum' can be well approximated to the waveform of a half cycle of a sine wave by appropriately setting the difference between the reference voltages Vmid and Vtop.

[0048] Similarly, by appropriately setting the difference between the reference voltages Vbot and Vmid, the sum of the output currents of the differential amplifiers 41 and 42 can also be made to closely approximate the waveform of the remaining half cycle of the sine wave.

[0049] FIG. 12 is a graph that shows the characteristics of the current Isum generated by the signal generating circuits 14-1 and 14-2 in FIG. 7. FIG. 12 shows the current Isum, which is the sum of the output currents of the differential amplifiers 41 to 43, with respect to the change in the ramp voltage Vrmp. When the digital / analog converters 13-1 and 13-2 have the configuration shown in FIG. 5, the voltage range Vbot to Vtop is divided into eight parts, and eight ramp voltages Vrmp shown by the arrows in FIG. 12 are generated. The current Isum when the ramp voltage Vrmp=Vbot is equal to the current Isum when the ramp voltage Vrmp=Vtop is generated. Therefore, as shown in FIG. 12, the digital / analog converters 13-1 and 13-2 do not need to be able to generate the ramp voltage Vrmp=Vbot as long as they can generate the ramp voltage Vrmp=Vtop. By appropriately setting the difference between the reference voltages Vtop, Vmid, and Vbot, the current Isum output from the differential amplifiers 41 to 43 can be well approximated to the waveform of the entire cycle of a sine wave.

[0050] When the count value cnt1 is generated in the order of 000, 001, 010, ..., 111 and the ramp voltage Vrmp of Fig. 6 is generated according to these codes, a current Isum that changes with a waveform similar to a sine wave is generated according to the characteristics of Fig. 12. When the current Isum flows through a load resistor (not shown), an output frequency signal Vout is generated having a voltage that changes with a waveform similar to a sine wave.

[0051] FIG. 13 is a diagram for explaining the operation of the signal generating circuits 14-1 and 14-2 in FIG. 7. As described above, a different count value is provided for each of the digital / analog converters 13-1 and 13-2 by adding the phase setting value P to the count value cnt1 using the adder 20. As a result, at the moment when a certain count value cnt1 is generated, the ramp voltage Vrmp2 has a value different from the ramp voltage Vrmp1. The differential amplifiers 41 to 43 of the signal generating circuit 14-1 generate output currents based on the ramp voltage Vrmp1 and the reference voltages Vtop, Vmid, and Vbot, respectively, and the sum of these currents becomes the current Isum1. Also, the differential amplifiers 41 to 43 of the signal generating circuit 14-2 generate output currents based on the ramp voltage Vrmp2 and the reference voltages Vtop, Vmid, and Vbot, respectively, and the sum of these currents becomes the current Isum2. 13, I1 indicates the value of current Isum1 generated when count value cnt1=0, and I2 indicates the value of current Isum2 generated when count value cnt2=cnt1+P=P. According to Fig. 13, it can be seen that current Isum2 has a phase that leads current isum1 by the phase setting value P. Therefore, signal generating circuits 14-1 and 14-2 generate output frequency signals Vout1 and Vout2 having a phase difference that changes according to phase setting value P.

[0052] Frequency synthesizer 101 according to the first embodiment can generate a sine wave or cosine wave signal of any frequency without using a look-up table by generating a sine wave through analog signal processing by signal generating circuits 14-1 and 14-2. Frequency synthesizer 101 can switch phases at high speed, while reducing the circuit size and power consumption compared to conventional direct digital synthesizers.

[0053] Conventional frequency synthesizers are provided with a ROM containing several thousand to several tens of thousands of transistors to store a lookup table, and the ROM consumes approximately 30 to 40% of the total power consumption of the frequency synthesizer. According to frequency synthesizer 101 of the first embodiment, the lookup table is no longer necessary, and therefore the circuit scale and power consumption can be significantly reduced compared to conventional ones.

[0054] According to the frequency synthesizer 101 of the first embodiment, by using the accumulator 12, it is possible to set the frequencies of the output frequency signals Vout1 and Vout2 precisely without using a look-up table.

[0055] In addition, the count value cnt1 may contain unwanted waves in addition to the desired frequency and its harmonics. As described above, the overflow of the count value cnt1 occurs on average at a frequency of f=K×fclk / 2. n If the frequency synthesizer 101 according to the first embodiment generates a sine wave by analog signal processing in the signal generating circuit 14, it is possible to suppress unnecessary waves and obtain output frequency signals Vout1, Vout2 with little jitter and high frequency purity.

[0056] According to the frequency synthesizer 101 according to the first embodiment, the output frequency signals Vout1, Vout2 having an arbitrary phase difference that changes according to the phase setting value P can be generated.

[0057] According to the frequency synthesizer 101 of the first embodiment, the count value cnt1 output from the accumulator 12 is shared by a circuit portion including the digital / analog converter 13-1 and the signal generating circuit 14-1 and a circuit portion including the digital / analog converter 13-2 and the signal generating circuit 14-2. The frequency synthesizer 101 includes only one accumulator 12. Therefore, it is possible to reduce the circuit size and power consumption compared to the case where an accumulator is provided for each signal generating circuit.

[0058] [Second embodiment] FIG. 14 is a block diagram showing a configuration of a frequency synthesizer 101A according to a second embodiment. The frequency synthesizer 101A has a configuration in which the reference voltage circuit 15-2 of FIG. 1 is removed. In the example of FIG. 1, the reference voltage circuits 15-1 and 15-2 generate the same reference voltages Vtop, Vmid, and Vbot. Therefore, the reference voltage generated by one reference voltage circuit 15-1 may be shared by the signal generating circuits 14-1 and 14-2. By providing only one reference voltage circuit 15-1, the circuit scale can be reduced. In addition, since the same reference voltages Vtop, Vmid, and Vbot can be reliably supplied to the signal generating circuits 14-1 and 14-2, a frequency synthesizer 101A with higher accuracy than a case in which separate signal generating circuits 14-1 and 14-2 are used can be provided.

[0059] [Third embodiment] 15 is a block diagram showing the configuration of a frequency synthesizer 101B according to the third embodiment. Frequency synthesizer 101B includes a reference voltage circuit 16 instead of reference voltage circuit 15 in FIG.

[0060] Fig. 16 is a circuit diagram showing a configuration of the reference voltage circuit 16 of Fig. 15. The reference voltage circuit 16 includes a plurality of digital / analog converters 61 to 63. The digital / analog converters 61 to 63 convert a plurality of predetermined voltage setting values ​​"0", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", "24", "35", "36", "47", "58", "69", "79", "80", "99", "109", "119", "120", "139", "140", "159", "160", "170", "181", "190", "241", "191", "2 n+1 " and "2 n", and generates a plurality of reference voltages Vtop, Vmid, and Vbot in response to the above. Digital-to-analog converters 61-63 are replica circuits of digital-to-analog converters 13-1 and 13-2, and have at least partially the same components and layout as those of digital-to-analog converters 13-1 and 13-2.

[0061] In the first and second embodiments, the ramp voltages Vrmp1 and Vrmp2 are generated by the digital / analog converters 13-1 and 13-2, and the reference voltages Vtop, Vmid, and Vbot are generated by the voltage dividing resistors R21 to R24. In other words, the ramp voltages Vrmp1 and Vrmp2 and the reference voltages Vtop, Vmid, and Vbot are generated by different mechanisms. As a result, there is a risk that the output frequency signals Vout1 and Vout2 may fluctuate due to manufacturing variations in elements such as transistors and resistors, fluctuations in the power supply voltage, and fluctuations in element characteristics caused by temperature. In the second embodiment, the reference voltages Vtop, Vmid, and Vbot are generated by the digital / analog converters 61 to 63, which are replica circuits of the digital / analog converters 13-1 and 13-2, thereby improving the PVT (process, power supply voltage, and temperature) fluctuation resistance.

[0062] The example of Fig. 16 shows the case where n=3 bits, as in the example of Fig. 5. In this case, as described above, the digital / analog converters 13-1 and 13-2 are 3 Each of the digital-to-analog converters 61 and 62 has the same seven switches 31 and seven constant current sources 32 as those in the digital-to-analog converters 13-1 and 13-2. The digital-to-analog converter 63 has the same seven switches 31 and seven constant current sources 32 as those in the digital-to-analog converters 13-1 and 13-2, and further has an additional switch 33 and constant current source 34 having the same characteristics as those of the switches 31 and the constant current source 32.

[0063] In the digital-to-analog converter 63, all of the switches 31 and 33 are preset to be turned on, thereby generating the reference voltage Vbot. In the digital-to-analog converter 62, four of the switches 31 are preset to be turned on and the remaining three switches 31 are preset to be turned off, thereby generating the reference voltage Vmid. In the digital-to-analog converter 61, all of the switches 31 are preset to be turned off, thereby generating the reference voltage Vtop.

[0064] The digital / analog converters 61 to 63 have at least partly the same components and layout as those of the digital / analog converters 13-1 and 13-2. This makes it possible to reduce the influence of manufacturing variations in elements and fluctuations in power supply voltage. In addition, the digital / analog converters 13 and 61 to 63 may be arranged close to each other to reduce the influence of temperature-related fluctuations in element characteristics.

[0065] To improve the symmetry of the digital-to-analog converters 13 and 61-63, the digital-to-analog converters 13, 61, and 62 may further include a switch 33 and a constant current source 34 similar to those in the digital-to-analog converter 63.

[0066] Since the differential amplifier has a large common-mode rejection ratio (CMRR), even if there is a PVT fluctuation, if the same fluctuation is input to the two input signals of the differential amplifier, the fluctuation is cancelled out. Therefore, according to the frequency synthesizer 101B according to the third embodiment, it is possible to greatly improve the PVT fluctuation resistance.

[0067] When a frequency synthesizer includes multiple reference voltage circuits corresponding to multiple signal generating circuits as in the example of FIG. 1, each reference voltage circuit may include multiple digital-to-analog converters instead of voltage dividing resistors R21-R24 as in the example of FIG. 16.

[0068] Fig. 17 is a block diagram showing a configuration of a part of a frequency synthesizer according to a modification of the third embodiment. Frequency synthesizer 101B in Fig. 15 may include digital / analog converters 61A and 62A in Fig. 17 instead of digital / analog converters 61 and 62 in Fig. 16. Digital / analog converters 61A and 62A have a configuration in which switch 31 that is turned off and constant current source 32 connected thereto are removed from digital / analog converters 61 and 62 in Fig. 16. Digital / analog converters 61A, 62A, and 63 have the same components and layout as digital / analog converters 13-1 and 13-2 with respect to elements through which current flows. Furthermore, by removing elements through which no current flows from the digital / analog converter, it is possible to reduce the circuit size while improving the PVT variation resistance.

[0069] [Fourth embodiment] 18 is a block diagram showing the configuration of a frequency synthesizer 101C according to the fourth embodiment. Frequency synthesizer 101C includes a digital / analog converter 17 instead of adder 20 in FIG.

[0070] By removing adder 20, digital-to-analog converter 13-2 generates a ramp voltage that is the same as ramp voltage Vrmp1 generated by digital-to-analog converter 13-1.

[0071] Digital-to-analog converter 17 generates a bias voltage having a magnitude according to phase setting value P. Next, digital-to-analog converter 17 adds the bias voltage to the ramp voltage generated by digital-to-analog converter 13-2 to generate ramp voltage Vrmp2. Different ramp voltages Vrmp1 and Vrmp2 are supplied to signal generating circuits 14-1 and 14-2.

[0072] Figure 19 is a circuit diagram showing the configuration of digital / analog converter 17 of Figure 18. Digital / analog converter 17 has a configuration in which resistor R0, i.e., the load, is removed from digital / analog converters 13-1 and 13-2 of Figure 5. Therefore, digital / analog converter 17 has at least part of the same components and layout as those of digital / analog converters 13-1 and 13-2.

[0073] In the first to third embodiments, the phase setting value P is digitally added to the count value cnt1 to realize output frequency signals Vout1, Vout2 having an arbitrary phase difference that changes according to the phase setting value P. However, the digital adder increases the circuit scale. In the fourth embodiment, a bias voltage generated by a digital / analog converter 17 is analogically added to the lamp voltage to realize a function equivalent to that of the adder 20. This makes the digital adder unnecessary, and the circuit scale can be reduced.

[0074] [Fifth embodiment] 20 is a block diagram showing the configuration of a frequency synthesizer 101D according to the fifth embodiment. The frequency synthesizer 101D includes a reference voltage circuit 18 instead of the digital / analog converters 13-2 and 17 in FIG.

[0075] The ramp voltage Vrmp1 generated by the digital / analog converter 13-1 is supplied to both of the signal generating circuits 14-1 and 14-2.

[0076] The reference voltage circuit 16 in FIG. 20 includes three digital / analog converters 61 to 63, as described with reference to FIG.

[0077] Fig. 21 is a circuit diagram showing the configuration of the reference voltage circuit 18 of Fig. 20. The reference voltage circuit 18 includes digital / analog converters 61-63 and adders 71-73. The digital / analog converters 61-63 of the reference voltage circuit 18 are configured similarly to the digital / analog converters 61-63 of the reference voltage circuit 16. The adders 71-73 add voltage setting values ​​"0", "2", and "3" for the digital / analog converters 61-63. n+1 " and "2 n " and a phase set value P is added to it. As a result, the voltage set values ​​supplied to the digital / analog converters 61-63 of reference voltage circuit 18 differ from the voltage set values ​​supplied to the digital / analog converters 61-63 of reference voltage circuit 16. As a result, reference voltage circuit 16 generates reference voltages Vtop1, Vmid1, and Vbot1, and reference voltage circuit 18 generates different reference voltages Vtop2, Vmid2, and Vbot2. Digital / analog converters 61-63 of reference voltage circuits 16 and 18 have at least partially the same components and layout as the components and layout of digital / analog converter 13-1.

[0078] The digital / analog converter 13-1 supplies a common ramp voltage Vrmp1 between the signal generating circuits 14-1 and 14-2 to the signal generating circuits 14-1 and 14-2. The reference voltage circuits 16 and 18 supply a plurality of reference voltages Vtop1, Vmid1, Vbot1 or Vtop2, Vmid2, Vbot2 including different combinations of voltages for each of the signal generating circuits 14-1 and 14-2 to the signal generating circuits 14-1 and 14-2.

[0079] 22 is a diagram for explaining the operation of the signal generating circuits 14-1 and 14-2 in FIG. 20. As described above, the voltage setting values ​​"0", "2 n+1 " and "2 nBy adding the phase setting value P to ", a different voltage setting value is supplied to the digital / analog converters 61 to 63 for each of the signal generating circuits 14-1 and 14-2. As a result, the reference voltages Vtop2, Vmid2, and Vbot2 have values ​​different from the reference voltages Vtop1, Vmid1, and Vbot1. The differential amplifiers 41 to 43 of the signal generating circuit 14-1 generate output currents based on the ramp voltage Vrmp1 and the reference voltages Vtop1, Vmid1, and Vbot1, respectively, and the sum of these currents becomes the current Isum1. The differential amplifiers 41 to 43 of the signal generating circuit 14-2 generate output currents based on the ramp voltage Vrmp1 and the reference voltages Vtop2, Vmid2, and Vbot2, respectively, and the sum of these currents becomes the current Isum2. According to FIG. 22, it can be seen that the current Isum2 has a phase leading the current isum1 by the phase setting value P. Therefore, the signal generating circuits 14-1 and 14-2 generate the output frequency signals Vout1 and Vout2 having a phase difference that changes according to the phase setting value P.

[0080] In the first to fourth embodiments, the signal generating circuits 14-1 and 14-2 operate based on the ramp voltages Vrmp1 and Vrmp2 that are different for each of the signal generating circuits 14-1 and 14-2, and on a plurality of reference voltages Vtop, Vmid, and Vbot that are common to the plurality of signal generating circuits 14-1 and 14-2. In the fifth embodiment, the signal generating circuits 14-1 and 14-2 operate based on the ramp voltage Vrmp1 that is common to the plurality of signal generating circuits 14-1 and 14-2, and on a plurality of reference voltages Vtop1, Vmid1, and Vbot1 or Vtop2, Vmid2, and Vbot2 that include a different combination of voltages for each of the signal generating circuits 14-1 and 14-2. As a result, according to the frequency synthesizer 101D according to the fifth embodiment, the signal generating circuits 14-1 and 14-2 can generate output frequency signals Vout1 and Vout2 having an arbitrary phase difference that changes according to the phase setting value P, as in the first to fourth embodiments. Since the accumulator 12 and the digital / analog converter 13-1, which operate at high speed, can be shared by a plurality of signal generating circuits 14-1 and 14-2, power consumption can be reduced more than in the first to fourth embodiments.

[0081] [Sixth embodiment] 23 is a block diagram showing the configuration of a frequency synthesizer 101E according to the sixth embodiment. The frequency synthesizer 101E includes a reference voltage circuit 19 instead of the reference voltage circuit 18 in FIG.

[0082] Fig. 24 is a circuit diagram showing a configuration of reference voltage circuit 19 of Fig. 23. Reference voltage circuit 19 includes digital / analog converters 81-83 instead of adders 71-73 of Fig. 21. Digital / analog converters 81-83 generate bias voltages having magnitudes according to phase setting value P. Digital / analog converters 81-83 then add the bias voltages to the reference voltages generated by digital / analog converters 61-63. As a result, reference voltage circuits 16, 19 supply different reference voltages to signal generating circuits 14-1, 14-2. Digital / analog converters 61-63, 81-83 have components and layouts that are at least partially the same as those of digital / analog converter 13-1.

[0083] In the fifth embodiment, the phase set value P is digitally added to the voltage set value to realize output frequency signals Vout1, Vout2 having an arbitrary phase difference that changes according to the phase set value P. On the other hand, in the sixth embodiment, a function equivalent to that of the adders 71-73 is realized by analogically adding the bias voltage to the reference voltage using digital / analog converters 81-83. This makes digital adders unnecessary, and allows the circuit scale to be reduced.

[0084] [Seventh embodiment] 25 is a block diagram showing the configuration of a wireless communication device 200 according to the seventh embodiment. The wireless communication device 200 includes a transmission circuit 201, mixers 202-1 to 202-4, amplifiers 203-1 to 203-4, antenna elements 204-1 to 204-4, a control circuit 205, a frequency synthesizer 206, and frequency multipliers 207-1 to 207-4.

[0085] Transmission circuit 201 sends a baseband signal including data to be transmitted to mixers 202-1 to 202-4.

[0086] Frequency synthesizer 206 is configured in the same manner as any of the frequency synthesizers according to the first to sixth embodiments. However, frequency synthesizer 206 includes four signal generating circuits and the like according to the number of antenna elements 204-1 to 204-4. Frequency synthesizer 206 has equivalent functions of signal source 211 and phase shifters 212-1 to 212-4 of the prior art, and generates a plurality of high-frequency signals having a predetermined frequency with a predetermined phase difference between them. Digital control signals k1 to k4 are input to frequency synthesizer 206 from control circuit 205. Frequency synthesizer 206 changes the phases of the high-frequency signals according to the digital control signals k1 to k4. Control circuit 205 changes the phases of the high-frequency signals independently and arbitrarily using digital control signals k1 to k4.

[0087] Frequency multipliers 207-1 to 207-4 multiply the frequencies of the high frequency signals output from phase shifters 212-1 to 212-4 and send the multiplied signals to mixers 202-1 to 202-4.

[0088] Mixers 202-1 to 202-4 modulate the high-frequency signals (radio frequency signals) input from frequency multipliers 207-1 to 207-4 with the baseband signal input from transmission circuit 201. Output signals from mixers 202-1 to 202-4 are amplified by amplifiers 203-1 to 203-4, respectively, and then radiated from antenna elements 204-1 to 204-4, respectively.

[0089] The antenna elements 204-1 to 204-4 operate as a phased array antenna device by changing the phase of the radio frequency signal to be transmitted by the phase shifters 212-1 to 212-4. By changing the phase of the radio frequency signal with high precision using the phase shifters 212-1 to 212-4, the directivity of the antenna device can be further increased.

[0090] 25 shows a wireless communication device 200 including a transmission circuit 201, but the frequency synthesizers according to the first to sixth embodiments are similarly applicable to wireless communication devices including a reception circuit. When the wireless communication device includes a reception circuit, the arrival direction may be estimated based on the received signal, or a beam may be directed to the arrival direction using a phase shifter.

[0091] According to the seventh embodiment, for example, a wireless communication device utilizing high frequency bands such as millimeter waves and terahertz waves can be provided.

[0092] According to the seventh embodiment, the phase between array antennas can be switched quickly with low power consumption, making it possible to quickly search for a moving object and track a fast moving object.

[0093] According to the seventh embodiment, a phased array antenna can be realized without a phase shifter.

[0094] [Other embodiments] The embodiments and modified examples described above may be combined in any manner.

[0095] 2 and 23, the count value cnt1 increases with time, but the accumulator of the frequency synthesizer according to the embodiment may be configured so that the count value cnt1 decreases with time. Also, in the example of Fig. 2, the ramp voltages Vrmp1, Vrmp2 increase with time, but the digital-to-analog converter of the frequency synthesizer according to the embodiment may be configured so that the ramp voltages Vrmp1, Vrmp2 decrease with time. [Industrial Applicability]

[0096] A frequency synthesizer and a wireless communication device according to an aspect of the present disclosure are applicable to a mobile station or a portable terminal device of a wireless communication system. [Explanation of symbols]

[0097] 11 Clock Signal Source 12 Accumulator 13-1, 13-2 Digital-to-Analog Converter (DAC) 14-1,14-2 Signal generation circuit 15-1, 15-2, 16, 16A Reference voltage circuit 17 Digital to Analog Converter (DAC) 18,19 Reference voltage circuit 20 Adder 21 Adder 22 Latch 31-1~31-(2 n -1) Switch 32-1~32-(2 n -1) Constant current source 33 Switch 34 Constant current source 41~46 Differential amplifier 51 Constant current source 61, 61A, 62, 62A, 63 Digital-to-Analog Converter (DAC) 71~73 Adder 81~83 Digital / Analog Converter (DAC) 101, 101A~101E Frequency Synthesizers 200 Wireless communication device 201 Transmitting circuit 202-1~202-4 Mixer 203-1~203-4 Amplifier 204-1~204-4 Antenna elements 205 Control circuit 206 Frequency Synthesizer 207-1~207-4 Frequency multiplier 211 Signal source 212-1~212-4 Phase shifter R0,R11,R12,R21~R24,Ra~Rd Resistance Q1, Q2 Bipolar transistor Q1A, Q2A Field effect transistor

Claims

1. an accumulator that generates a count value that increases or decreases in a predetermined step size within a predetermined range in response to a clock signal; at least one first digital-to-analog converter that generates a ramp voltage that increases or decreases in response to the count value; at least one reference voltage circuit for generating a plurality of reference voltages; a plurality of signal generating circuits each generating an output frequency signal having a different phase from each other based on the ramp voltage and the plurality of reference voltages; each of the plurality of signal generating circuits generates an output frequency signal having a signal level that changes in a waveform similar to a sine wave or a cosine wave in response to the lamp voltage by analog signal processing; the first digital / analog converter and the reference voltage circuit supply to the signal generating circuits a ramp voltage different for each of the signal generating circuits and the reference voltages common to the signal generating circuits, or supply to the signal generating circuits a ramp voltage common to the signal generating circuits and the reference voltages including a combination of voltages different for each of the signal generating circuits. Frequency synthesizer.

2. Each of the at least one reference voltage circuit includes a voltage divider resistor that generates the plurality of reference voltages.

2. The frequency synthesizer of claim 1.

3. each of the at least one reference voltage circuit includes a plurality of second digital-to-analog converters that generate the plurality of reference voltages having magnitudes according to a plurality of voltage setting values; the second digital-to-analog converter having components and a layout at least partially identical to the components and a layout of the first digital-to-analog converter; 2. The frequency synthesizer of claim 1.

4. The frequency synthesizer includes: a plurality of first digital-to-analog converters; at least one first adder that adds a phase setting value to the count value to provide a different count value for each of the first digital-to-analog converters; A frequency synthesizer according to any one of claims 1 to 3.

5. The frequency synthesizer includes: a plurality of first digital-to-analog converters; at least one third digital-to-analog converter that generates a first bias voltage having a magnitude according to a phase setting value so as to supply a different ramp voltage to each of the signal generating circuits, and adds the first bias voltage to the ramp voltage generated by at least one of the plurality of first digital-to-analog converters; the third digital-to-analog converter having components and a layout at least partially the same as the components and a layout of the first digital-to-analog converter; A frequency synthesizer according to any one of claims 1 to 3.

6. The frequency synthesizer includes: a first digital-to-analog converter; a plurality of reference voltage circuits; each of the plurality of reference voltage circuits includes a plurality of second digital / analog converters that generate the plurality of reference voltages having magnitudes according to a plurality of voltage setting values; at least one of the plurality of reference voltage circuits includes a plurality of second adders that add a phase set value to the plurality of voltage set values ​​so as to provide a different voltage set value for each of the reference voltage circuits; the second digital-to-analog converter having components and a layout at least partially identical to the components and a layout of the first digital-to-analog converter; 2. The frequency synthesizer of claim 1.

7. The frequency synthesizer includes: a first digital-to-analog converter; a plurality of reference voltage circuits; each of the plurality of reference voltage circuits includes a plurality of second digital / analog converters that generate the plurality of reference voltages having magnitudes according to a plurality of voltage setting values; at least one of the plurality of reference voltage circuits generates a second bias voltage having a magnitude corresponding to a phase setting value so as to supply a different reference voltage to each of the signal generating circuits; and a plurality of fourth digital-to-analog converters add the second bias voltage to the reference voltage generated by the plurality of second digital-to-analog converters; the second and fourth digital-to-analog converters have components and layouts at least partially similar to the components and layout of the first digital-to-analog converter; 2. The frequency synthesizer of claim 1.

8. Each of the plurality of signal generating circuits a first differential amplifier for comparing the ramp voltage against a first reference voltage to generate a first differential output signal; a second differential amplifier for comparing the ramp voltage against a second reference voltage, the second reference voltage being higher than the first reference voltage, to generate a second differential output signal; a third differential amplifier for comparing the ramp voltage to a third reference voltage higher than the second reference voltage to generate a third differential output signal; the output frequency signal is a sum of the first and third differential output signals and an inverted signal of the second differential output signal.

2. The frequency synthesizer of claim 1.

9. Each of the first to third differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors.

9. The frequency synthesizer of claim 8.

10. A frequency synthesizer comprising: Wireless communication device.

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