Integrator and delta-sigma modulator

Abstract

To provide an integrator and a delta-sigma modulator capable of reducing a circuit scale.SOLUTION: A delta-sigma modulator includes: an integrator 100 having a first-order delay part 82 for outputting an output signal AOUT obtained by delaying a signal according to an input signal AIN, a first feedback part 10 for generating a first feedback signal according to the output signal, a second feedback part 20 for generating a second feedback signal according to the output signal, and an adding / subtracting part 80 for adding / subtracting the first feedback signal and the second feedback signal and / from the input signal and inputting it to the delay part; and a control part 114 for causing the second feedback part to operate as a delay circuit during a first period and to operate as a gain circuit having a gain smaller than 0 during a second period.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an integrator and a delta-sigma modulator. [Background technology]

[0002] Conventionally, as a method for achieving high resolution with low power consumption, there has been known an incremental delta-sigma modulator that operates as an integrator with a first-order feedback coefficient of 1 until a predetermined period has elapsed, and then operates as an amplifier with a first-order feedback coefficient greater than 1 after the predetermined period has elapsed (see, for example, Patent Document 1). [Prior art document] [Patent documents] Patent Document 1: JP 2019-118100 A Summary of the Invention

[0003] In a first aspect of the present invention, there is provided an integrator. The integrator may include a first-order delay section that outputs an output signal obtained by delaying a signal corresponding to an input signal. Any of the integrators may include a first feedback section that generates a first feedback signal corresponding to the output signal. Any of the integrators may include a second feedback section that generates a second feedback signal corresponding to the output signal. Any of the integrators may include an adder / subtracter section that adds / subtracts the first feedback signal and the second feedback signal to / from the input signal and inputs the result to the delay section. Any of the integrators may include a control section that operates the second feedback section as a delay circuit in a first period and operates the second feedback section as a gain circuit having a gain smaller than 0 in a second period.

[0004] In any of the integrators described above, the second feedback section may generate the second feedback signal using a common capacitor both when functioning as the delay circuit and when functioning as the gain circuit.

[0005] In any of the above integrators, the second feedback section may have a first capacitor that accumulates a charge according to the output signal. In any of the above integrators, the second feedback section may have a first polarity switching section that changes the polarity of the first capacitor between the first period and the second period. In the second feedback section, the second feedback section may have a first charge / discharge switching section that switches between charging the first capacitor and connecting the first capacitor to the addition / subtraction section according to the output signal during each of the first period and the second period.

[0006] In any of the integrators described above, the first polarity switching unit may switch the polarity of the first capacitor so as to subtract the second feedback signal corresponding to the charge stored in the first capacitor from the input signal during the first period, and to add the second feedback signal corresponding to the charge stored in the first capacitor to the input signal during the second period.

[0007] In any of the above integrators, the first charge / discharge switching unit may change a switching period for switching between charging the first capacitor and connecting the first capacitor to the addition / subtraction unit in accordance with the output signal during the first period and the second period.

[0008] In any of the integrators described above, the first charge / discharge switching unit may set the switching cycle in the second period to be shorter than the switching cycle in the first period.

[0009] In any of the integrators described above, the first charge / discharge switch unit may stop charging / discharging the first capacitor during the second period.

[0010] In any of the above integrators, the second feedback section may include a second capacitor provided in parallel with the first capacitor and accumulating a charge according to the output signal. In any of the above integrators, the second feedback section may include a second polarity switching section that changes the polarity of the second capacitor between the first period and the second period. In any of the above integrators, the second feedback section may include a second charge / discharge switching section that switches between charging the second capacitor and connecting the second capacitor to the addition / subtraction section according to the output signal during each of the first period and the second period.

[0011] In any of the integrators described above, the second polarity switching section may set the polarity of the second capacitor to be the same as the polarity of the first capacitor.

[0012] In any of the integrators described above, the second charge / discharge switching unit may charge the second capacitor at a different timing from the first capacitor during the first period, and connect the second capacitor to the addition / subtraction unit at a different timing from the first capacitor.

[0013] In any of the integrators described above, the second charge / discharge switch unit may stop charging / discharging the second capacitor during the second period.

[0014] In any of the integrators described above, the second charge / discharge switching unit may connect the second capacitor to the addition / subtraction unit at the same timing as the first capacitor during the second period.

[0015] In any of the above integrators, the first feedback section may have a third capacitor that accumulates a charge according to the output signal.In any of the above integrators, the first feedback section may include a capacitance switching section that switches whether the first capacitor, the second capacitor, or the third capacitor functions as one of the capacitors of the first feedback section and the second feedback section.

[0016] In a second aspect of the present invention, there is provided a delta-sigma modulator comprising the integrator according to the first aspect. The delta-sigma modulator may comprise an analog-to-digital converter for converting the output signal into a digital signal. The delta-sigma modulator may comprise a digital-to-analog converter for generating a feedback signal according to an output of the analog-to-digital converter and subtracting the feedback signal from the input signal.

[0017] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0018] [Figure 1] 1 shows an example of the configuration of a delta-sigma modulator 200 using an integrator 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram illustrating an example of the configuration of an integrator 100. [Diagram 3] FIG. 2 is a diagram illustrating a specific example of the configuration of an integrator 100. [Figure 4] 11 is a timing chart showing an example of each signal φk in a first period. [Diagram 5] 10 is a timing chart showing an example of each signal φk in a second period. [Figure 6] 13 is a timing chart showing another example of each signal φk in the second period. [Figure 7] 13 is a timing chart showing another example of each signal φk in the second period. [Figure 8] 13 is a timing chart showing another example of each signal φk in the second period. [Figure 9] FIG. 4 is a diagram illustrating another exemplary configuration of the integrator 100. [Figure 10] FIG. 4 is a diagram illustrating another exemplary configuration of the integrator 100. [Figure 11] FIG. 11 is a diagram illustrating an example of switching the roles of capacitors in a first period. [Figure 12]11 is a diagram showing an example of switching the role of each capacitor in a plurality of first periods. FIG. [Figure 13] 1 is a diagram showing an example of a signal-to-noise ratio SNR of an output signal AOUT of an integrator 100. FIG. [Figure 14] 1 is a diagram showing an example of a signal-to-noise ratio SNR of an output signal AOUT of an integrator 100. FIG. [Figure 15] FIG. 13 is a diagram illustrating another exemplary configuration of the delta-sigma modulator 200. [Figure 16] 16 is a diagram illustrating a specific example of the configuration of the delta-sigma modulator 200 illustrated in FIG. 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0020] 1 shows an example of the configuration of a delta-sigma modulator 200 using an integrator 100 according to an embodiment of the present invention. The delta-sigma modulator 200 is an example of a circuit using the integrator 100, and the circuit in which the integrator 100 is provided is not limited to the delta-sigma modulator 200.

[0021] The delta-sigma modulator 200 receives an analog signal A SIG to the digital signal D OUT As an example, the delta-sigma modulator 200 is an incremental AD converter that resets the integrated value of the integrator 100 to an initial value for each AD conversion cycle. The delta-sigma modulator 200 alternates between an AD conversion period and a reset period.

[0022] The AD conversion period in the delta-sigma modulator 200 of this example has a first period and a second period. The second period is a period following the first period. That is, the operation in the delta-sigma modulator 200 repeats the first period, the second period, and the reset period in order. The integrator 100 of this example operates as an integrator with a first-order feedback coefficient of 1 in the first period, and operates as an integrator with a first-order feedback coefficient greater than 1 in the second period. This allows the integrator 100 to have a high resolution.

[0023] 1 includes an adder-subtractor unit 110, an integrator 100, an analog-to-digital converter (referred to as an AD conversion unit 120), and a digital-to-analog converter (referred to as a DA conversion unit 130). The delta-sigma modulator 200 may further include a control unit 114 and a reset circuit 116. The adder-subtractor unit 110 receives an analog signal A SIG From feedback signal A FB Input signal A is subtracted IN In this example, the feedback signal A FB and input signal A IN is an analog signal.

[0024] The integrator 100 receives an input signal A SIG The output signal A is the integrated OUT The integrator 100 may be an analog integrator. The control unit 114 controls the integrator 100. In this example, the control unit 114 causes the integrator 100 to perform different integral operations in the first period and the second period described above. A reset circuit 116 resets the output signal A output by the integrator 100 every time an AD conversion period ends. OUT Resets the value of to its initial value.

[0025] The AD conversion unit 120 outputs the output signal A OUT to the digital signal D OUT The AD conversion unit 120 converts the output signal A OUT The AD conversion section 120 may quantize the binary digital signal D OUTFor example, the AD conversion section 120 may output an output signal A OUT A 1-bit quantizer outputs one pulse when the value of analog signal A is equal to or greater than a preset value, and does not output a pulse when the value is less than the preset value. SIG The magnitude of the digital signal D is converted into the density of the pulses during the AD conversion. OUT may be output.

[0026] The DA conversion unit 130 converts the digital signal D output by the AD conversion unit 120 into OUT Feedback signal A according to FB Generates feedback signal A FB For example, a digital signal D OUT When the AD conversion unit 120 is a 1-bit quantizer, the DA conversion unit 130 generates a feedback signal A of a preset magnitude every time the AD conversion unit 120 outputs a pulse. FB may be generated.

[0027] 2 is a diagram showing an example of the configuration of the integrator 100. The integrator 100 includes a delay section 82, a first feedback section 10, a second feedback section 20, and an adder-subtractor section 80. The delay section 82 receives an input signal A IN Signal A according to PRE Output signal A is a delayed version of OUT The delay unit 82 is a first-order delay circuit having a transfer coefficient with a maximum order of 1.

[0028] The delay unit 82 in this example generates a delay of one period of the supplied clock signal. Each clock signal described in this specification has a common period unless otherwise specified. The adder / subtracter unit 80 adds an input signal A IN A signal A is obtained by adding the first feedback signal FB1 to A and subtracting the second feedback signal FB2 from A. PRE Generate.

[0029] The first feedback section 10 outputs an output signal A OUTThe first feedback section 10 generates a first feedback signal FB1 according to the output signal A OUT The gain circuit 17 in this example has a gain of 2.

[0030] The second feedback section 20 outputs the output signal A OUT 1 operates the second feedback section 20 as a delay circuit in the first period, and operates the second feedback section 20 as a gain circuit having a gain smaller than 0 in the second period. That is, in the second period, the second feedback section 20 operates as a gain circuit having a gain of a negative value.

[0031] The second feedback section 20 of this example includes a delay circuit 22, a gain circuit 24, and a selection section 50. The delay circuit 22 outputs an output signal A OUT The delay time of the delay circuit 22 may be the same as the delay time of the delay unit 82. The delay circuit 22 in this example delays the output signal A by one cycle of the clock signal. OUT The gain circuit 24 delays and outputs the output signal A OUT is amplified by a predetermined gain -x and output, where x is a value greater than 0, and may be a value of 1 or greater, or may be a value of 2 or greater.

[0032] The selection section 50 selects whether the second feedback section 20 operates as the delay circuit 22 or as the gain circuit 24. The selection section 50 may be a circuit that selects and outputs either the output of the delay circuit 22 or the output of the gain circuit 24.

[0033] 2, the delay circuit 22 and the gain circuit 24 are shown as separate circuits, but some or all of the elements of the delay circuit 22 and the gain circuit 24 may be common. The selection section 50 may select whether the second feedback section 20 operates as the delay circuit 22 or as the gain circuit 24 by controlling these elements. By commonizing at least some of the delay circuit 22 and the gain circuit 24, the circuit scale of the second feedback section 20 can be reduced.

[0034] The adder / subtractor unit 80 receives the input signal A IN The adder / subtracter 80 adds / subtracts the first feedback signal FB1 and the second feedback signal FB2 to / from the input signal A and inputs the result to the delay unit 82. The adder / subtracter 80 adds / subtracts the first feedback signal FB1 to / from the input signal A IN In this example, the adder / subtractor unit 80 adds the second feedback signal FB2 to the input signal A IN Subtract from .

[0035] In a first period in which the second feedback section 20 functions as the delay circuit 22, the integrator 100 operates as an integrator with a first-order feedback coefficient of 1. In a second period in which the second feedback section 20 functions as the gain circuit 24, the integrator 100 operates as an integrator with a first-order feedback coefficient greater than 1. In the example of Fig. 2, the feedback coefficient in the second period is 1+x. This allows the integrator 100 to have a high resolution.

[0036] Output signal A in the first period OUT is the number 1.

number

number

[0037] Each component of the integrator 100 operates every time a pulse of the clock signal is input. If the number of pulses of the clock signal input during the first period is m, the transfer function of the integrator 100 during the first period can be transformed into the following equation 3.

number

[0038] An error may occur in the integrator 100. The error in the integrator 100 occurs in the output of the gain circuit 24 or the input of the delay circuit 22, etc. The error is caused by a charge transfer error when the integrator 100 is operating. If an error occurs in the integrator 100, the error increases every time the integrator 100 operates in response to a clock signal. In the integrator 100 of this example, during the first period, the output of the delay circuit 22 is input to the input signal A. IN Therefore, even if an error occurs in the integrator 100, the component of the error is subtracted by the second feedback signal FB2, and the error can be prevented from being amplified.

[0039] If the number of pulses of the clock signal input during the second period is n, the transfer function of the integrator 100 during the second period can be transformed into the following equation 4.

number

[0040] In the integrator 100 of this embodiment, the first period is provided in addition to the second period. This limits the number of pulses n in the second period, and even if the second period can only be provided in a part of the AD conversion period, the input signal A IN In addition, since the first period has elapsed, the operation of the integrator 100 becomes relatively stable in the second period, and the occurrence of an error is suppressed. According to the integrator 100, the input signal A can be amplified while suppressing the amplification of the error in the first period. IN In the second period, the input signal A is amplified with a high amplification factor. IN can be amplified.

[0041] Using the multiplication of the transfer functions shown in Equation 3 and Equation 4, the output signal A of the integrator 100 is expressed as Equation 5. OUT is shown.

number

[0042] Fig. 3 is a diagram showing a specific example of the configuration of the integrator 100. The integrator 100 has an amplifier 62. The amplifier 62 shown in Fig. 3 is a differential input amplifier. The positive input of the amplifier 62 may be connected to a reference potential. When both the input and output of the amplifier 62 are differential, a configuration other than the amplifier 62 shown in Fig. 3 may be provided for the positive side of the amplifier 62.

[0043] The integrator 100 of this example has a switched capacitor 70, an amplifier circuit 60, a first feedback section 10, and a second feedback section 20. The switched capacitor 70 and the amplifier circuit 60 function as the addition / subtraction section 80 and the delay section 82 shown in FIG.

[0044] The switched capacitor 70 includes a capacitor 75, a switch 71, a switch 72, a switch 73, and a switch 74. The on and off states of each switch are controlled by a signal φk (k is an integer or two integers connected by an underscore). In the drawings attached to this specification, a plurality of switches having the same signal φk in parentheses following the reference numerals have the same on and off states. In this example, when the signal φk indicates an H level, the corresponding switch is in an on state, and when the signal φk indicates an L level, the corresponding switch is in an off state.

[0045] A switch 71 and a switch 72 are connected to one electrode of the capacitor 75. The switch 71 applies an input signal A IN The switch 72 switches whether or not the corresponding electrode of the capacitor 75 is connected to a reference potential. The other electrode of the capacitor 75 is connected to switches 73 and 74. The switch 73 switches whether or not the corresponding electrode of the capacitor 75 is connected to the amplifier circuit 60. The switch 74 switches whether or not the corresponding electrode of the capacitor 75 is connected to a reference potential. The reference potential is, for example, 0V.

[0046] The switches 71 and 74 are controlled by a signal φ1. The switches 72 and 73 are controlled by a signal φ2. When the signal φ1 indicates an on state and the signal φ2 indicates an off state, the capacitor 75 is connected to the input signal A. IN When the signal φ1 indicates an off state and the signal φ2 indicates an on state, the voltage of the capacitor 75 is applied to the amplifier circuit 60. For example, the signal φ1 is a clock signal and the signal φ2 is an inverted clock signal.

[0047] The amplifier circuit 60 has an amplifier 62, a feedback capacitor 64, and a switch 66. A capacitor 75 and a switch 74 are connected to the negative input terminal of the amplifier 62 via a switch 73. In addition, the first feedback section 10 and the second feedback section 20 are each connected to the negative input terminal of the amplifier 62 in parallel with the switch 73.

[0048] A feedback capacitor 64 and a switch 66 are connected in parallel between the output terminal and the negative input terminal of the amplifier 62. The feedback capacitor 64 stores the signal input to the negative input terminal of the amplifier 62. The feedback capacitor 64 is connected in parallel to the input signal A. IN , a first feedback signal FB1 and a second feedback signal FB2 are input to the feedback capacitor 64. IN The feedback signal FB1 and the feedback signal FB2 are added to each other and subtracted from each other.

[0049] The voltage across the feedback capacitor 64 is OUT The switch 66 switches between connecting and not connecting the two electrodes of the feedback capacitor 64. By connecting the two electrodes of the feedback capacitor 64, the charge stored in the feedback capacitor 64 is discharged, and the output signal A OUT The voltage of the output signal A is reset to a reference potential (for example, 0 V). The switch 66 may be controlled by the reset circuit 116 shown in FIG. 1. The reset circuit 116 turns on the switch 66 to reset the output signal A every time one AD conversion is completed (i.e., every time one first period and one second period have elapsed). OUT The voltage may be reset.

[0050] The first feedback section 10 of this example includes a third capacitor 15, a switch 11, a switch 12, a switch 13, and a switch 14. The third capacitor 15 is connected to the output signal A OUT The charge stored corresponds to the

[0051] A switch 11 and a switch 12 are connected to one electrode of the third capacitor 15. The switch 11 switches whether or not the electrode of the third capacitor 15 is connected to the feedback capacitor 64. The switch 12 switches whether or not the electrode of the third capacitor 15 is connected to a reference potential. A switch 13 and a switch 14 are connected to the other electrode of the third capacitor 15. The switch 13 switches whether or not the electrode of the third capacitor 15 is connected to an output terminal of the amplifier 62. The switch 14 switches whether or not the electrode of the third capacitor 15 is connected to a reference potential.

[0052] The switches 11 and 14 are controlled by a signal φ2. The switches 12 and 13 are controlled by a signal φ1. When the signal φ1 indicates an on state and the signal φ2 indicates an off state, the third capacitor 15 supplies the output signal A OUT When the signal φ1 indicates an OFF state and the signal φ2 indicates an ON state, the charge of the third capacitor 15 is transferred to the feedback capacitor 64. As a result, the first feedback signal FB1 is IN is added to.

[0053] The second feedback section 20 has a switched capacitor 30, a switched capacitor 40, and a selection section 50. The switched capacitor 30 and the switched capacitor 40 cooperate to function as a delay circuit 22 and also function as a gain circuit 24. That is, the second feedback section 20 of this example has a common circuit that functions as the delay circuit 22 and the gain circuit 24.

[0054] For example, the second feedback section 20 generates the second feedback signal FB2 using a common capacitor (for example, the first capacitor 35) both when functioning as the delay circuit 22 and when functioning as the gain circuit 24. By sharing the circuitry of the delay circuit 22 and the gain circuit 24 in this way, the overall circuit size can be reduced. The selection section 50 switches between causing the switched capacitor 30 and the switched capacitor 40 to function as the delay circuit 22 or as the gain circuit 24.

[0055] The switched capacitor 30 includes a first capacitor 35, a switch 31, a switch 32, a switch 33, and a switch 34. The first capacitor 35 is connected to an output signal A OUT The switches 31, 32, 33, and 34 store electric charges according to the output signal A during each of the first and second periods. OUT The first charge / discharge switching unit 64 functions as a first charge / discharge switching unit that switches between charging the first capacitor 35 and connecting the first capacitor to the feedback capacitor 64 in response to the input of the first charge / discharge switch 64.

[0056] A switch 31 and a switch 32 are connected to one electrode of the first capacitor 35. The switch 31 switches whether or not the electrode of the first capacitor 35 is connected to the feedback capacitor 64. The switch 32 switches whether or not the electrode of the first capacitor 35 is connected to the selection unit 50. A switch 33 and a switch 34 are connected to the other electrode of the first capacitor 35. The switch 33 switches whether or not the electrode of the first capacitor 35 is connected to the selection unit 50. The switch 34 switches whether or not the electrode of the first capacitor 35 is connected to the reference potential.

[0057] The switches 31 and 34 are controlled by a signal φ2_1. The switches 32 and 33 are controlled by a signal φ1_1. When the signal φ1_1 indicates an ON state and the signal φ2_1 indicates an OFF state, the first capacitor 35 selects the output signal A OUTThe selection section 50 switches which of the two electrodes of the first capacitor 35 is connected to the reference potential and which is connected to the output terminal of the amplifier 62. As a result, the reference potential is applied to which electrode of the first capacitor 35, and the output signal A is applied to which electrode. OUT is applied.

[0058] In this specification, which electrode of a capacitor is connected to the reference potential may be referred to as the polarity of the capacitor. In other words, the polarity of a capacitor is different when the reference potential is applied to one electrode of the capacitor and when the reference potential is applied to the other electrode of the capacitor.

[0059] When the signal φ1_1 indicates an OFF state and the signal φ2_1 indicates an ON state, the charge of the first capacitor 35 is transferred to the feedback capacitor 64. Depending on the polarity of the first capacitor 35, the voltage of the first capacitor 35 is IN is added to or subtracted from.

[0060] The switched capacitor 40 includes a second capacitor 45, a switch 41, a switch 42, a switch 43, and a switch 44. The second capacitor 45 is provided in parallel with the first capacitor 35, and OUT The switches 41, 42, 43, and 44 store electric charges according to the output signal A during each of the first and second periods. OUT The second capacitor 45 is charged or connected to the feedback capacitor 64 in response to the second charge / discharge switching unit 66.

[0061] A switch 41 and a switch 42 are connected to one electrode of the second capacitor 45. The switch 41 switches whether or not the electrode of the second capacitor 45 is connected to the feedback capacitor 64. The switch 42 switches whether or not the electrode of the second capacitor 45 is connected to the selection unit 50. A switch 43 and a switch 44 are connected to the other electrode of the second capacitor 45. The switch 43 switches whether or not the electrode of the second capacitor 45 is connected to the selection unit 50. The switch 44 switches whether or not the electrode of the second capacitor 45 is connected to the reference potential.

[0062] The switches 41 and 44 are controlled by a signal φ2_2. The switches 42 and 43 are controlled by a signal φ1_2. When the signal φ1_2 indicates an ON state and the signal φ2_2 indicates an OFF state, the second capacitor 45 selects the output signal A OUT The battery is charged according to the

[0063] The selection section 50 switches which of the two electrodes of the second capacitor 45 is connected to the reference potential and which is connected to the output terminal of the amplifier 62. This switches the polarity of the second capacitor 45.

[0064] When the signal φ1_2 indicates an OFF state and the signal φ2_2 indicates an ON state, the charge of the second capacitor 45 is transferred to the feedback capacitor 64. Depending on the polarity of the second capacitor 45, the voltage of the second capacitor 45 is IN is added to or subtracted from.

[0065] The selection unit 50 has a first polarity switching unit 51 and a second polarity switching unit 52. The first polarity switching unit 51 makes the polarity of the first capacitor 35 different between the first period and the second period. The second polarity switching unit 52 makes the polarity of the second capacitor 45 different between the first period and the second period.

[0066] The first polarity switching unit 51 of this example has a switch 53, a switch 54, a switch 55, and a switch 56. The switch 53 switches whether or not the other electrode of the first capacitor 35 is connected to the ground potential via the switch 33. The switch 54 switches whether or not the other electrode of the first capacitor 35 is connected to the output terminal of the amplifier 62 via the switch 33. The switch 55 switches whether or not one electrode of the first capacitor 35 is connected to the ground potential via the switch 32. The switch 56 switches whether or not one electrode of the first capacitor 35 is connected to the output terminal of the amplifier 62 via the switch 32.

[0067] The on / off states of the switches 53 and 56 are the same, and the on / off states of the switches 54 and 55 are the same. As a result, the first polarity switching unit 51 switches which electrode of the first capacitor 35 the ground potential is applied to and which electrode is connected to the output terminal of the amplifier 62.

[0068] The second polarity switching unit 52 of this example has the same configuration as the first polarity switching unit 51. The second polarity switching unit 52 may set the polarity of the second capacitor 45 to the same polarity as the polarity of the first capacitor 35. The first capacitor 35 and the second capacitor 45 each have a first electrode connected to the input terminal of the amplifier 62 and a second electrode on the opposite side to the first electrode.

[0069] Making the polarity of capacitors the same means applying a reference potential to the same electrode of each capacitor. For example, when a reference potential is applied to the first electrode of each of two capacitors, or when a reference potential is applied to the second electrode of each of two capacitors, the polarity of the two capacitors is the same.

[0070] In the second polarity switching unit 52, the switch 53 switches, via the switch 43, whether or not the second electrode of the second capacitor 45 is connected to the ground potential. The switch 54 switches, via the switch 43, whether or not the second electrode of the second capacitor 45 is connected to the output terminal of the amplifier 62. The switch 55 switches, via the switch 42, whether or not the first electrode of the second capacitor 45 is connected to the ground potential. The switch 56 switches, via the switch 42, whether or not the first electrode of the second capacitor 45 is connected to the output terminal of the amplifier 62. The switches of the first polarity switching unit 51 and the second polarity switching unit 52 may be controlled by the control unit 114.

[0071] 4 is a timing chart showing an example of each signal φk in the first period. As described above, in the first period, the second feedback section 20 functions as the delay circuit 22. In the first period, the first polarity switching section 51 and the second polarity switching section 52 switch the second feedback signal FB2 according to the charges stored in the first capacitor 35 and the second capacitor 45 to the input signal A. IN The polarity of each capacitor is controlled so that it is subtracted from

[0072] In the first period, the switches 53 and 56 of the first polarity switching unit 51 and the second polarity switching unit 52 are turned on, and the switches 54 and 55 are turned off. As a result, the voltages of the first capacitor 35 and the second capacitor 45 are subtracted from the feedback capacitor 64.

[0073] Each switch of the switched capacitor 30 charges the first capacitor 35 in response to the signal φ1_1. Each switch of the switched capacitor 30 connects the first capacitor 35 to the feedback capacitor 64 in response to the signal φ2_1. This causes the feedback capacitor 64 to discharge in response to the charge of the first capacitor 35. Whether the feedback capacitor 64 is charged or discharged in response to the electric field of the first capacitor 35 depends on the polarity of the first capacitor 35.

[0074] Each switch of the switched capacitor 40 charges the second capacitor 45 in response to the signal φ1_2. Each switch of the switched capacitor 40 connects the second capacitor 45 to the feedback capacitor 64 in response to the signal φ2_2. This causes the feedback capacitor 64 to be discharged in response to the charge of the second capacitor 45. Whether the feedback capacitor 64 is charged or discharged in response to the electric field of the second capacitor 45 depends on the polarity of the second capacitor 45. As shown in FIG. 4, in the first period, the second capacitor 45 is charged at a different timing from the first capacitor 35, and the second capacitor 45 is connected to the feedback capacitor 64 at a different timing from the first capacitor 35.

[0075] In the example of FIG. 4, at time t1, the signals φ1 and φ1_1 are in the ON state, and the other signals are in the OFF state. As a result, the capacitor 75 is IN and the first capacitor 35 and the third capacitor 15 are charged in response to the output signal A OUT The battery is charged according to the

[0076] At time t2, the signals φ2 and φ2_2 are in the ON state, and the other signals are in the OFF state, so that the charge of the capacitor 75 is transferred to the feedback capacitor 64, and the feedback capacitor 64 is discharged according to the charge of the second capacitor 45, and is charged according to the charge of the third capacitor 15.

[0077] At time t3, the signals φ1 and φ1_2 are in the ON state, and the other signals are in the OFF state. As a result, the capacitor 75 is IN and the second capacitor 45 and the third capacitor 15 are charged in response to the output signal A OUT The battery is charged according to the

[0078] At time t4, the signals φ2 and φ2_1 are in the ON state, and the other signals are in the OFF state. As a result, the capacitor 75 is INThe feedback capacitor 64 is discharged according to the charge on the first capacitor 35, and the feedback capacitor 64 is charged according to the charge on the third capacitor 15. After time t5, the operations from time t1 to time t4 are repeated.

[0079] In this example, the periods of the signals φ1_1, φ1_2, φ2_1, and φ2_2 are twice as long as the periods of the signals φ1 and φ2. That is, the operation period of the switched capacitor 30 and the switched capacitor 40 is twice as long as the operation period of the switched capacitor 70 and the first feedback section 10. For this reason, the second feedback section 20 can function as a delay circuit 22.

[0080] 5 is a timing chart showing an example of each signal φk in the second period. As described above, in the second period, the second feedback section 20 functions as the gain circuit 24. In the second period, the first polarity switching section 51 and the second polarity switching section 52 output the second feedback signal FB2 corresponding to the charge stored in the first capacitor 35 and the charge stored in the second capacitor 45 to the input signal A. IN The polarities of the first capacitor 35 and the second capacitor 45 are switched so as to be added to each other.

[0081] In the second period, the switches 53 and 56 of the selection unit 50 are turned off, and the switches 54 and 55 are turned on. This causes the voltages of the first capacitor 35 and the second capacitor 45 to be added to the feedback capacitor 64.

[0082] In the present embodiment, each switch of the switched capacitor 30 has a different switching period in the first period and the second period. OUTThis is a period in which whether to charge the first capacitor 35 or connect the first capacitor 35 to the feedback capacitor 64 (functioning as an adding / subtracting unit) is switched depending on the input of the switched capacitor 40. In the second period, each switch of the switched capacitor 40 in this example stops charging / discharging the second capacitor 45. In this way, by switching the polarity of each capacitor and switching the operation period of each switched capacitor, it is possible to switch whether the second feedback unit 20 functions as the delay circuit 22 or the gain circuit 24.

[0083] In the examples of Figures 4 and 5, the period in which pulses are generated in the signals φ1_1 and φ2_1 corresponds to the switching period. Each switch of the switched capacitor 30 may operate so that the switching period in the second period is shorter than the switching period in the first period. In the example of Figure 4, the pulse period of the signals φ1_1 and φ2_1 in the first period is twice the period of the signals φ1 and φ2. In the example of Figure 5, the pulse period of the signals φ1_1 and φ2_1 in the first period is the same as the period of the signals φ1 and φ2.

[0084] 5, at time t6, the signals φ1 and φ1_1 are in the ON state, and the other signals are in the OFF state. IN and the first capacitor 35 and the third capacitor 15 are charged in response to the output signal A OUT The battery is charged according to the

[0085] At time t7, the signals φ2 and φ2_1 are in the ON state, and the other signals are in the OFF state, so that the charge of the capacitor 75 is transferred to the feedback capacitor 64, and the feedback capacitor 64 is charged according to the charges of the first capacitor 35 and the third capacitor 15.

[0086] After time t8, the operations at time t6 and time t7 are repeated. As a result, the switched capacitor 30 operates as the gain circuit 24. The switched capacitor 40 is not charged or discharged during the second period. The capacitances of the capacitor 75, the feedback capacitor 64, the first capacitor 35, and the second capacitor 45 may be the same. In this case, the gain -x of the gain circuit 24 becomes -1, and the integrator 100 exponentially amplifies the input signal A with a gain of three times (2+x=2+1=3) as shown in Equation 4. IN Amplify.

[0087] 6 is a timing chart showing another example of each signal φk in the second period. In this example, the waveforms of the signals φ1_2 and φ2_2 are different from the example shown in FIG 5. The waveforms of the other signals are the same as the example shown in FIG 5.

[0088] In the second period, each switch of the switched capacitor 40 in this example charges and discharges the second capacitor 45 at the same timing as the first capacitor 35. As shown in FIG. 6, the waveforms of the signals φ1_2 and φ2_2 may be the same as the waveforms of the signals φ1_1 and φ2_1. In this example, since the switched capacitor 40 operates as a circuit with a gain of 1, the gain -x of the second feedback section 20 is -2, and the integrator 100 exponentially increases the input signal A with a gain of 4 times. IN Amplify.

[0089] 6, the waveforms of the signals φ1_2 and φ2_2 are the same as the waveforms of the signals φ1_1 and φ2_1. In another example, the waveform of the signal φ1_2 may be obtained by inverting the waveform of the signal φ1_1, and the waveform of the signal φ2_2 may be obtained by inverting the waveform of the signal φ2_1.

[0090] 7 is a timing chart showing another example of each signal φk in the second period. In this example, the waveforms of the signals φ1_1, φ1_2, φ2_1, and φ2_2 are different from those in the example shown in FIG. 5. The waveforms of the other signals are the same as those in the example shown in FIG.

[0091] In this example, each switch of the switched capacitor 30 stops charging / discharging the first capacitor 35 during the second period. Also, each switch of the switched capacitor 40 stops charging / discharging the second capacitor 45 during the second period. In this example, the gain -x of the second feedback section 20 becomes 0, and the integrator 100 operates as an amplifier with a gain of 2x.

[0092] 8 is a timing chart showing another example of each signal φk in the second period. In this example, the waveforms of the signals φ1_1 and φ2_1 are interchanged with the waveforms of the signals φ1_2 and φ2_2. The waveforms of the other signals are the same as those in the example shown in FIG. 5. That is, the switched capacitor 30 in this example operates in the same manner as the switched capacitor 40 in the example of FIG. 5, and the switched capacitor 40 in this example operates in the same manner as the switched capacitor 30 in the example of FIG. 5.

[0093] In the second period, each switch of the switched capacitor 30 in this example stops charging / discharging the first capacitor 35. In the second period, each switch of the switched capacitor 40 charges / discharges the second capacitor 45. The integrator 100 in this example exponentially ampli?es the input signal A at a gain of 3 times as in the example of FIG. IN Amplify.

[0094] The control unit 114 may combine the controls in the second periods shown in Fig. 5, Fig. 6, Fig. 7, and Fig. 8. That is, the control unit 114 may perform any of the controls shown in Fig. 5 to Fig. 8 in the second period of a certain AD conversion period, and perform other controls shown in Fig. 5 to Fig. 8 in the second period of another AD conversion period.

[0095] By such control, the integrator 100 can function with various characteristics in the second period. In addition, the gain of the integrator 100 is the same in the examples of Figures 5 and 8. However, in the examples of Figures 5 and 8, the capacitor (first capacitor 35 or second capacitor 45) that operates in the second period is different. Therefore, by combining the operations shown in Figures 5 and 8, the influence of the variation in the characteristics of the capacitors can be reduced.

[0096] 9 is a diagram showing another example of the configuration of the integrator 100. The integrator 100 in this example is a third-order integrator, but the integrator 100 may be a higher-order integrator. The integrator 100 in this example includes a third feedback section 21 in addition to the configuration shown in FIG. 2. The gain of the gain circuit 17 of the first feedback section 10 in this example is 3.

[0097] 2, the second feedback section 20 of this example has a gain circuit 23. The gain circuit 23 of this example amplifies the output of the delay circuit 22 by a gain of three times and inputs the amplified output to the selection section 50.

[0098] The third feedback section 21 includes a delay circuit 26, a gain circuit 27, and a selection section 28. The delay circuit 26 outputs an output signal A OUT The delay circuit 26 in this example may be a second-order delay circuit that generates a delay twice the period of the clock signal. OUT is amplified by a gain of y and output, where y is a value greater than 0, and may be a value of 1 or greater, or may be a value of 2 or greater.

[0099] The selection unit 28 selects the output of the delay circuit 26 in the first period, and selects the output of the gain circuit 27 in the second period, and outputs the third feedback signal FB3 to the addition / subtraction unit 80. The addition / subtraction unit 80 receives the input signal A IN The first feedback signal FB1 is added to, the second feedback signal FB2 is subtracted from, and the third feedback signal FB3 is added to.

[0100] In this example, the output A of the integrator 100 OUT is shown in Equation 6.

number

[0101] 10 is a diagram showing another example of the configuration of the integrator 100. In FIG. 10, the first feedback section 10 and the second feedback section 20 in the integrator 100 are shown, and other configurations are omitted. The integrator 100 of this example further includes a capacitance switching section 58 in addition to the configuration of the second feedback section 20 shown in FIG. 3. Also, in FIG. 10, the first capacitor 35, the second capacitor 45, and the third capacitor 15 are arranged outside the frame of the switched capacitor 30, the switched capacitor 40, and the first feedback section 10.

[0102] The capacitance switching unit 58 switches whether the first capacitor 35, the second capacitor 45, and the third capacitor 15 function as the first feedback unit 10, the switched capacitor 30, or the switched capacitor 40. The capacitance switching unit 58 assigns one capacitor to each of the first feedback unit 10, the switched capacitor 30, and the switched capacitor 40 at each timing. The capacitance switching unit 58 has a group of switches that can switch whether each capacitor is connected to the first feedback unit 10, the switched capacitor 30, or the switched capacitor 40. Each switch of the capacitance switching unit 58 is controlled by the control unit 114.

[0103] The capacitance switching unit 58 may change which of the first feedback unit 10, the switched capacitor 30, and the switched capacitor 40 each capacitor functions as during at least one of the first period and the second period. The design value of the capacitance of each capacitor in this example is the same. However, the capacitance of each capacitor varies due to manufacturing variations or deterioration over time. When the capacitance of each capacitor varies, if the role of each capacitor is fixed and operated, the influence of the variation may become large. In this example, the role of each capacitor is switched sequentially, thereby suppressing the influence of the variation.

[0104] Fig. 11 is a diagram showing an example of switching the role of each capacitor in the first period. Each signal φk in Fig. 11 is the same as in the example of Fig. 4. In Fig. 11, the role of the capacitor of the first feedback section 10 is SC1, the role of the capacitor of the switched capacitor 30 is SC2, and the role of the capacitor of the switched capacitor 40 is SC3. The first capacitor 35, the second capacitor 45, and the third capacitor 15 each sequentially play the roles of SC1, SC2, and SC3 during the first period.

[0105] The role of each capacitor may transition in a predetermined order. In the example of FIG. 11, the role of each capacitor transitions in the order of SC1, SC3, SC1, SC2, SC1, SC3, .... In another example, the role of each capacitor may transition in a random order. The period during which each capacitor functions as SC1 may be one cycle of the clock signal. The period during which each capacitor functions as SC2 or SC3 may be two cycles of the clock signal. In this way, by sequentially switching the role of each capacitor, the influence of the variation in capacitance of each capacitor can be suppressed.

[0106] 12 is a diagram showing an example of switching the role of each capacitor in a plurality of first periods. The first period A is the first period in a certain AD conversion period, and the first period B is the first period in the next AD conversion period. A second period and a reset period are provided between the first period A and the first period B.

[0107] Each signal φk in the first period is the same as the example in FIG. 4. In FIG. 12, a reset signal RST is shown. In response to the rising edge of the reset signal, the output signal A OUT is reset to an initial value. The reset signal may be generated by the reset circuit 116 at the start of each AD conversion (i.e., at the start of the first period).

[0108] In each first period, the role of each capacitor transitions in a predetermined order, as in the example of FIG. 11. The role of each capacitor at the start of each first period may be the same or different. In the example of FIG. 12, the role of each capacitor at the start of each first period is different. The role of each capacitor at the start of each first period may be set in a predetermined order or may be set randomly. According to this example, the influence of the variation in capacitance of each capacitor can be further suppressed.

[0109] FIG. 13 shows the output signal A of the integrator 100. OUT 13 is a diagram showing an example of a signal-to-noise ratio (SNR) in Example 1. Example 1 is an example in which the role of each capacitor is not changed, and Example 2 is an example in which the role of each capacitor is changed sequentially as shown in FIG. 11. The square plots in FIG. 13 correspond to Example 1, and the black circle plots correspond to Example 2. The dashed line shown in FIG. 13 indicates the position of 4.5σ in the distribution of each plot. In Example 1, the SNR at 4.5σ was 78.9 dB, while in Example 2, the SNR at 4.5σ was 82.1 dB. That is, by performing the control as shown in FIG. 11, the SNR was improved by 3.2 dB.

[0110] FIG. 14 shows the output signal A of the integrator 100. OUT 14 is a diagram showing an example of a signal-to-noise ratio (SNR) in Example 2. Example 2 is similar to FIG. 13. Example 3 is an example in which the role of each capacitor is changed sequentially within the first period while the role of each capacitor is changed at the start of each first period as shown in FIG. 12. The diamond-shaped plots in FIG. 14 correspond to Example 3. In Example 3, the SNR at 4.5σ was 82.9 dB. In Example 3, the SNR was improved by 0.8 dB compared to Example 2.

[0111] 15 is a diagram showing another example of the configuration of the delta-sigma modulator 200. The delta-sigma modulator 200 of this example further includes a feed-forward section 140 in addition to the configuration shown in FIG. OUT and analog signal A SIG Based on the second output signal A SUM and inputs it to the AD conversion unit 120.

[0112] Fig. 16 is a diagram showing a specific example of the configuration of the delta-sigma modulator 200 shown in Fig. 15. The configuration other than the feed-forward section 140 is the same as that of the delta-sigma modulator 200 according to any of the aspects described with reference to Figs. 1 to 15. Fig. 16 shows the configuration of the integrator 100 shown in Fig. 2, but the integrator 100 may be a high-order integrator as shown in Fig. 9. The output signal A in the first period of the integrator 100 in this example is OUT is shown in equation 7.

number

[0113] In the second period, the integrator 100 of this example operates as an integrator having a first order and a feedback coefficient of three. OUT is shown in the following equation 8.

number

[0114] The feedforward section 140 of this example includes a delay circuit 141, a gain circuit 142, a gain circuit 143, a selection section 144, and an adder / subtractor section 145. The delay circuit 141 receives the output signal A of the integrator 100. OUT The gain circuit 142 delays the output signal A by one period of the clock signal. OUT The gain circuit 143 amplifies the output signal A by a gain of -1 and outputs it. OUT is amplified by a gain of 2 and output.

[0115] The selection unit 144 selects and outputs the output of the delay circuit 141 in the first period, and selects and outputs the output of the gain circuit 142 in the second period. SIG The output of the gain circuit 143 is added to the output of the selector 144, and the output of the selector 144 is subtracted from the output signal A SUM Generate.

[0116] Output signal A of the feedforward section 140 in the first period SUM is shown in Equation 9.

number

number

[0117] The control unit 114 and the reset circuit 116 switch the control between the first period and the second period, thereby generating two types of output signals A SUM If the quantization noise generated in the AD conversion unit 120 is E1, the digital signal D output by the delta-sigma modulator 200 in the first period is OUT is shown in Equation 11.

number

[0118] Output signal A of integrator 100 OUT The initial value of analog signal A is 0. SIG is a constant value, the digital signal output by the AD conversion unit 120 in the i-th AD conversion period is D OUT If (i), then analog signal A SIG is shown in equation (12).

number

[0119] From the above equation, the analog signal A input to the delta-sigma modulator 200 is SIG is the digital signal D output by the AD conversion unit 120. OUT and the analog signal A SIG The voltage value is converted to digital value D SIG Furthermore, the quantization noise E1 of the AD conversion unit 120 is expressed by the following equation (13).

number

[0120] Output signal A of the integrator 100 in the second period OUT is shown in Equation 14.

number

number

[0121] At the beginning of the second period, the initial value of the integrator 100 is A OUT (n), so analog signal A SIG is shown in equation (16).

number

[0122] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0123] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0124] 10···first feedback section, 11, 12, 13, 14···switch, 15···third capacitor, 17···gain circuit, 20···second feedback section, 21···third feedback section, 22···delay circuit, 23···gain circuit, 24···gain circuit, 26···delay circuit, 27···gain circuit, 28···selection section, 30···switched capacitor, 31, 32, 33, 34···switch, 35···first capacitor, 40···switched capacitor, 41, 42, 43, 44···switch, 45···second capacitor, 50···selection section, 51···first polarity switching section, 52···second polarity switching section, 53, 5 4, 55, 56···switch, 58···capacitance switching section, 60···amplification circuit, 62···amplifier, 64···feedback capacitor, 66···switch, 70···switched capacitor, 71, 72, 73, 74···switch, 75···capacitor, 80···addition / subtraction section, 82···delay section, 100···integrator, 110···addition / subtraction section, 114···control section, 116···reset circuit, 120···AD conversion section, 130···DA conversion section, 140···feedforward section, 141···delay circuit, 142···gain circuit, 143···gain circuit, 144···selection section, 145···addition / subtraction section, 200···delta-sigma modulator

Claims

1. a first-order delay unit that outputs an output signal obtained by delaying a signal corresponding to an input signal; a first feedback unit that generates a first feedback signal according to the output signal; a second feedback unit that generates a second feedback signal according to the output signal; an adder / subtractor unit that adds / subtracts the first feedback signal and the second feedback signal to / from the input signal and inputs the result to the delay unit; a control unit that operates the second feedback unit as a delay circuit in a first period and operates the second feedback unit as a gain circuit having a gain smaller than 0 in a second period; An integrator comprising:

2. The second feedback section generates the second feedback signal using a common capacitor both when functioning as the delay circuit and when functioning as the gain circuit.

2. The integrator of claim 1.

3. The second feedback unit is a first capacitor for storing a charge corresponding to the output signal; a first polarity switching unit that changes the polarity of the first capacitor between the first period and the second period; a first charge / discharge switching unit that switches between charging the first capacitor and connecting the first capacitor to the addition / subtraction unit in response to the output signal during each of the first period and the second period; 3. The integrator of claim 2, comprising:

4. The first polarity switching unit switches the polarity of the first capacitor so as to subtract the second feedback signal corresponding to the charge stored in the first capacitor from the input signal during the first period and to add the second feedback signal corresponding to the charge stored in the first capacitor to the input signal during the second period.

4. The integrator of claim 3.

5. The first charge / discharge switching unit switches between charging the first capacitor and connecting the first capacitor to the addition / subtraction unit in response to the output signal in a switching cycle different from that in the first period and the second period.

4. The integrator of claim 3.

6. The first charge / discharge switching unit sets the switching cycle in the second period to be shorter than the switching cycle in the first period.

6. The integrator of claim 5.

7. The first charge / discharge switching unit stops charging / discharging the first capacitor during the second period.

4. The integrator of claim 3.

8. The second feedback unit is a second capacitor provided in parallel with the first capacitor and configured to accumulate a charge corresponding to the output signal; a second polarity switching unit that changes the polarity of the second capacitor between the first period and the second period; a second charge / discharge switching unit that switches between charging the second capacitor and connecting the second capacitor to the addition / subtraction unit in response to the output signal during each of the first period and the second period; 8. An integrator according to any one of claims 3 to 7, comprising:

9. The second polarity switching unit sets the polarity of the second capacitor to be the same as the polarity of the first capacitor.

9. The integrator of claim 8.

10. The second charge / discharge switching unit charges the second capacitor at a timing different from that of the first capacitor during the first period, and connects the second capacitor to the addition / subtraction unit at a timing different from that of the first capacitor.

9. The integrator of claim 8.

11. The second charge / discharge switching unit stops charging / discharging the second capacitor during the second period.

11. The integrator of claim 10.

12. The second charge / discharge switching unit charges and discharges the second capacitor at the same timing as the first capacitor during the second period.

11. The integrator of claim 10.

13. the first feedback section has a third capacitor that accumulates a charge according to the output signal; a capacitance switching unit that switches whether the first capacitor, the second capacitor, and the third capacitor function as the capacitors of the first feedback unit or the capacitors of the second feedback unit.

9. The integrator of claim 8.

14. A delta-sigma modulator comprising the integrator of claim 1, an analog-to-digital converter for converting the output signal into a digital signal; a digital-to-analog converter that generates a feedback signal according to an output of the analog-to-digital converter and subtracts the feedback signal from the input signal; A delta-sigma modulator comprising:

Images