Package Including Wire Bonds Bonded to an Integrated Device - Patent application

Abstract

A package comprising: a substrate including a cavity; a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects; a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects; and a plurality of wire bonds coupled to the first integrated device and the second integrated device, the plurality of wire bonds being located over the cavity of the substrate.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 213,875, filed in the United States Patent Office on March 26, 2021, the entire contents of which are incorporated by reference herein for all applicable purposes as if fully set forth below.

[0002] Various features relate to packages that include integrated devices and, more particularly, to packages that include integrated devices and substrates. [Background technology]

[0003] 1 shows a package 100 including a substrate 102, an integrated device 104, and an integrated device 106. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. A plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. There is currently a need to provide a package with better performance. Summary of the Invention [Means for solving the problem]

[0004] Various features relate to packages that include integrated devices and, more particularly, to packages that include integrated devices and substrates.

[0005] One example provides a package including a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, the plurality of wire bonds being located over the cavity of the substrate.

[0006] Another example provides an apparatus including a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a means for wire interconnection coupled to the first integrated device and the second integrated device, the means for wire interconnection being located over the cavity of the substrate.

[0007] In another example, a method for manufacturing a package is provided. The method provides a substrate including a cavity. The method couples a first integrated device to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects. The method couples a second integrated device to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects. The method forms a plurality of wire bonds between the first integrated device and the second integrated device, the plurality of wire bonds overlying the cavity in the substrate.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when read in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a side view of a package including an integrated device and a substrate. [Diagram 2] FIG. 2 is a side view of a package including wire bonds coupled to an integrated device. [Diagram 3] FIG. 2 is a plan view of a package including wire bonds coupled to an integrated device. [Figure 4] FIG. 2 is a plan view of wire bonds coupled to an integrated device. [Diagram 5] FIG. 2 is a close-up plan view of wire bonds attached to an integrated device. [Figure 6] FIG. 2 is a side view of a wire bond coupled to an integrated device. [Figure 7] FIG. 2 is a side view of a package including wire bonds coupled to an integrated device. [Figure 8A] 1A-1C illustrate an exemplary sequence for fabricating an integrated device having pillar interconnects. [Figure 8B] 1A-1C illustrate an exemplary sequence for fabricating an integrated device having pillar interconnects. [Figure 9] 1 illustrates an example flow diagram of a method for fabricating an integrated device having pillar interconnects. [Figure 10A] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 10B] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 10C] FIG. 2 illustrates an exemplary sequence for manufacturing a substrate. [Figure 11] 1 illustrates an example flow diagram of a method for manufacturing a substrate. [Figure 12A] 1A-1C illustrate an exemplary sequence for manufacturing a package including wire bonds coupled to an integrated device. [Figure 12B] 1A-1C illustrate an exemplary sequence for manufacturing a package including wire bonds coupled to an integrated device. [Figure 13] 1 is an example flow diagram of a method for manufacturing a package including wire bonds coupled to an integrated device. [Figure 14] 1A-1C illustrate various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (PIDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description, specific details are given to enable a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring aspects of the present disclosure.

[0011] The present disclosure describes a package including a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, the plurality of wire bonds being located above the cavity of the substrate. The first integrated device includes a first row of a plurality of pads and a second row of a plurality of pads. The second integrated device includes a first row of a plurality of pads and a second row of a plurality of pads. The plurality of wire bonds includes (i) a first plurality of wire bonds coupled to the first row of a plurality of pads of the first integrated device and (ii) a second plurality of wire bonds coupled to the (i) second row of a plurality of pads of the first integrated device and (ii) a second plurality of wire bonds coupled to the second row of a plurality of pads of the second integrated device. The use of multiple wire bonds helps provide a higher density interconnect between integrated devices. Multiple wire bonds can help provide shorter and more direct electrical paths between integrated devices. The package can include an underfill and / or encapsulation layer. The underfill and / or encapsulation layer can help provide strong structural integrity to the integrated devices and substrate, which in turn helps provide a package that includes reliable interconnects between two or more integrated devices.

[0012] Exemplary Package Including Wirebonds Between Integrated Devices 2 shows a side view of a package 200 that includes multiple wire bonds between integrated devices. Package 200 may be coupled to a board (e.g., a printed circuit board (PCB)) through multiple solder interconnects 280. Package 200 provides a package with high density interconnects between integrated devices.

[0013] As shown in FIG. 2, the package 200 includes a substrate 202, a first integrated device 204, a second integrated device 206, a number of wire bonds 210, an underfill 244, an underfill 264, and an encapsulation layer 208.

[0014] As described further below, the multiple wire bonds 210 may be coupled to the integrated devices (e.g., 204, 206) such that when at least one electrical signal (e.g., first electrical signal, second electrical signal) travels between the at least two integrated devices (e.g., 204, 206), the electrical signal bypasses the substrate 202. However, the at least one electrical signal may travel through at least one electrical path defined by the package interconnects, the integrated devices, and / or the substrate.

[0015] The substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder resist layer 224, and a second solder resist layer 226. The substrate 202 also includes a cavity 209 extending through the substrate 202. The cavity 209 may extend through the at least one dielectric layer 220, the first solder resist layer 224, and the second solder resist layer. The cavity 209 may have any shape (e.g., rectangular, square). The substrate 202 may include two or more cavities 209. As described further below, the cavity 209 may be at least partially filled (e.g., completely filled) with an encapsulation layer 208 and / or other materials. In some implementations, the cavity 209 of the substrate 202 may be an area or void that is devoid of the dielectric layer 220 and / or the interconnects 222 of the substrate 202. The substrate 202 may be considered to have a cavity 209 even if the cavity 209 is later filled with one or more materials. As described further below, the cavity 209 in the substrate 202 may allow wire bonds 210 to be formed between the integrated devices (e.g., 204, 206). The wire bonds 210 may be located above the cavity 209 (e.g., above or below the cavity 209, depending on how above or below is arbitrarily defined). In some implementations, the wire bonds 210 may be located at least partially within the cavity 209 of the substrate 202.

[0016] The plurality of interconnects 222 may be configured to provide at least one electrical path to and / or from the board. The plurality of interconnects 222 may be configured to provide at least one electrical path to at least one integrated device (e.g., 204, 206). The plurality of interconnects 222 may be configured to provide at least one electrical path (e.g., electrical connection) between two or more integrated devices (e.g., 204, 206). The plurality of interconnects 222 may have a first minimum pitch and a first minimum line and spacing (L / S). In some implementations, the first minimum line and spacing (L / S) for the plurality of interconnects 222 is in the range of approximately 9 / 9 to 12 / 12 micrometers (μm) (e.g., a minimum line width of approximately 9 to 12 micrometers (μm), a minimum spacing of approximately 9 to 12 micrometers (μm)). Various implementations may use different substrates. The substrate 202 may be a laminate substrate, a coreless substrate, an organic substrate, and / or a core substrate (e.g., including a core layer). In some implementations, the at least one dielectric layer 220 may include a core layer and / or a prepreg layer. The at least one dielectric layer 220 may have a dielectric constant in the range of approximately 3.5 to 3.7. An example of manufacturing the substrate is further described below in FIGS. 10A-10C. As further described below, in some implementations, the substrate 202 may be manufactured using a modified semi-additive process (mSAP) or a semi-additive process (SAP).

[0017] The first integrated device 204 is coupled to a first surface (e.g., a top surface) of the substrate 202. In some implementations, the first integrated device 204 is coupled to the substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. The plurality of pillar interconnects 240 and / or the plurality of solder interconnects 242 may be coupled to a plurality of interconnects 222 of the substrate 202. The plurality of pillar interconnects 240 may help provide a higher density of interconnects between the first integrated device 204 and the substrate 202. The plurality of pillar interconnects 240 may be optional. Thus, the first integrated device 204 may be coupled to the substrate 202 through the plurality of solder interconnects 242. A portion of the first integrated device 204 may be located above the cavity 209. A front surface of the first integrated device 204 may face the substrate 202. The first integrated device 204 includes a plurality of pads 241. As described further below, the plurality of pads 241 may be arranged in rows of pads including a first row of pads and a second row of pads. The first row of pads may be offset relative to the second row of pads, or vice versa. It is noted that the plurality of pads 241 may include three or more rows of pads.

[0018] The second integrated device 206 is coupled to a first surface of the substrate 202. In some implementations, the second integrated device 206 is coupled to the substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. The plurality of pillar interconnects 260 and / or the plurality of solder interconnects 262 may be coupled to the plurality of interconnects 222. The plurality of pillar interconnects 260 may help provide a higher density of interconnects between the second integrated device 206 and the substrate 202. The plurality of pillar interconnects 260 may be optional. Thus, the second integrated device 206 may be coupled to the substrate 202 through a plurality of solder interconnects 262. A portion of the second integrated device 206 may be located above the cavity 209. A front surface of the second integrated device 206 may face the substrate 202. The second integrated device 206 includes a plurality of pads 261. As described further below, the plurality of pads 261 may be arranged in rows of pads including a first row of pads and a second row of pads. The first column of pads may be staggered relative to the second column of pads, or vice versa. It is noted that the plurality of pads 261 may include three or more columns of pads.

[0019] The wire bonds 210 are coupled to the first integrated device 204 and the second integrated device 206. For example, the wire bonds 210 are coupled to (i) the pads 241 of the first integrated device 204 and (ii) the pads 261 of the second integrated device 206. In some implementations, each of the wire bonds 210 may have a diameter of at least 15 micrometers. The wire bonds 210 may have different heights and / or vertical offsets (e.g., different maximum heights and / or maximum vertical offsets) from the surface of the integrated device (e.g., 204, 206), the pads 241, and / or the pads 261. The use of wire bonds 210 with different heights and / or vertical offsets enables high density interconnection between the first integrated device 204 and the second integrated device 206. In some implementations, the plurality of wirebonds 210 may have a density of at least 40 wirebonds per millimeter (e.g., 40 interconnects per millimeter) between the first integrated device 204 and the second integrated device 206. The number of interconnects per millimeter provided by the plurality of wirebonds 210 may be better than the number of interconnects per millimeter provided in the substrate 202. This may occur despite the fact that one or more wirebonds from the plurality of wirebonds 210 may have a minimum diameter of 15 micrometers, while the interconnects in the substrate 202 may have a first minimum linewidth and spacing (L / S) in the range of approximately 9 / 9 to 12 / 12 micrometers (μm) (e.g., minimum linewidth of approximately 9 to 12 micrometers (μm), minimum spacing of approximately 9 to 12 micrometers (μm)). Thus, even though the wire bonds 210 have a thicker dimension, the use of wire bonds having different heights and / or offsets allows more interconnects to be provided per millimeter than the interconnects in the substrate 202. Moreover, the multiple wire bonds 210 provide a shorter and more direct electrical path between the first integrated device 204 and the second integrated device 206.Shorter and more direct electrical paths between integrated devices may result in better integrated device and / or package performance. Example configurations and arrangements of wire bonds 210 are further described below in at least Figures 4-6.

[0020] 2, underfill 244 is disposed between first integrated device 204 and substrate 202. Similarly, underfill 264 is disposed between second integrated device 206 and substrate 202. Underfill 244 may surround multiple pillar interconnects (e.g., 240) and / or multiple solder interconnects (e.g., 242). Underfill 264 may surround multiple pillar interconnects (e.g., 260) and / or multiple solder interconnects (e.g., 262). Underfill 244 and / or 264 may be disposed elsewhere, such as within cavity 209 and / or over first integrated device 204 and second integrated device 206. Underfill 244 and / or 264 may be part of the same underfill or separate underfills.

[0021] The underfill 244 and / or 264 helps provide structural stability to the package 200. In particular, the underfill 244 and / or 264 helps provide a strong and reliable mechanical bond between the first integrated device 204, the second integrated device 206, and the substrate 202. By helping to structurally hold the first integrated device 204 and the second integrated device 206 together with the substrate 202, the underfill 244 and / or 264 helps ensure that a strong and reliable electrical connection (e.g., an electrical path) exists between the first integrated device 204 and the second integrated device 206.

[0022] Various implementations may provide underfill 244 and / or 264 with different materials and / or properties. Underfill 244 and / or 264 may include one or more underfills (e.g., underfill layers). For example, underfill 244 and / or 264 may be formed from a single configuration of underfill. In some implementations, underfill 244 and / or 264 may correspond to several portions and / or layers of underfill that have been separately formed and cured. In some implementations, underfill 244 and / or 264 may include a viscosity of about 10-30 Pascal seconds (Pa·s). These viscosity values ​​may be for a temperature of about 80 degrees Celsius. In some implementations, underfill 244 and / or 264 may include a coefficient of thermal expansion (CTE) of about 10-15 parts per million (ppm). In some implementations, the underfill 244 and / or 264 may include a filler that is approximately 50-90 percent of the weight of the underfill 244 and / or 264. As described further below, the underfill 244 and / or 264 may have capillary properties that allow the underfill 244 and / or 264 to fill small spaces between integrated devices and / or between the integrated devices and the substrate. For example, the viscosity values ​​described above for the underfill 244 and / or 264 allow the underfill 244 and / or 264 to advance and fill small spaces between integrated devices and / or between the integrated devices and the substrate. Underfill 244 and / or underfill 264 and / or other materials that may be placed around pillars and between the integrated devices and the substrate are described further below.

[0023] The encapsulation layer 208 is disposed and formed on the substrate 202. The encapsulation layer 208 may include a mold, a resin, an epoxy, and / or a polymer. The encapsulation layer 208 may be a means for encapsulation. The encapsulation layer 208 may at least partially encapsulate the first integrated device 204 and / or the second integrated device 206. The encapsulation layer 208 may be disposed in a cavity 209 of the substrate 202. The encapsulation layer 208 may at least partially fill the cavity 209 of the substrate 202. It should be noted that even if all of the cavity 209 is filled with the encapsulation layer 208 and / or other materials, the substrate 202 may still be considered to have a cavity 209. The encapsulation layer 208 may help provide structural stability to the package 200.

[0024] The integrated devices (e.g., 204, 206) may include a die (e.g., a semiconductor bare die). The integrated devices may include a logic die, a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor (e.g., a power management integrated circuit (PMIC)), and / or a combination thereof. The integrated devices (e.g., 204, 206) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0025] 3 shows a plan view of a package 200 including multiple wire bonds between integrated devices. The package 200 includes a substrate 202, a cavity 209, a first integrated device 204, a second integrated device 206, and multiple wire bonds 210. The first integrated device 204 and the second integrated device 206 are coupled to the substrate 202. The multiple wire bonds 210 are coupled to the first integrated device 204 and the second integrated device 206. The multiple wire bonds 210 are located above the cavity 209 of the substrate 202. A portion of the first integrated device 204 and / or a portion of the second integrated device 206 may be located above the cavity 209 of the substrate 202. As described above, the cavity 209 may be at least partially filled with an encapsulation layer and / or other material.

[0026] 4 shows an expanded plan view of a plurality of wire bonds coupled to pads of an integrated device. As shown in FIG. 4, a plurality of wire bonds 210 are coupled to a first integrated device 204 and a second integrated device 206. The plurality of wire bonds 210 includes wire bonds 210a, 210b, 210c, 210d, 210e, and 210f. Wire bonds 210a, 210b, and 210c may be part of a first plurality of wire bonds. Wire bonds 210d, 210e, and 210f may be part of a second plurality of wire bonds.

[0027] The first integrated device 204 includes a plurality of pads 241 arranged in a row of pads. The plurality of pads 241 includes pads 241a, 241b, 241c, 241d, 241e, and 241f. Pads 241a, 241b, and 241c may be part of a first row of pads for the first integrated device 204. Pads 241d, 241e, and 241f may be part of a second row of pads for the first integrated device 204. The second row of pads may be offset relative to the first row of pads of the first integrated device 204, or vice versa. The first row of pads may be an inner row of pads. The second row of pads may be an outer row of pads.

[0028] The second integrated device 206 includes a plurality of pads 261 arranged in a row of pads. The plurality of pads 261 includes pads 261a, 261b, 261c, 261d, 261e, and 261f. The pads 261a, 261b, and 261c may be part of a first row of pads for the second integrated device 206. The pads 261d, 261e, and 261f may be part of a second row of pads for the second integrated device 206. The second row of pads may be offset relative to the first row of pads of the second integrated device 206, or vice versa. The first row of pads may be an inner row of pads. The second row of pads may be an outer row of pads. The inner row of pads and the outer row of pads may be defined arbitrarily. For example, an outer row of pads may be a row of pads closer to an edge of the integrated device (e.g., an edge of the integrated device that faces another integrated device) than an inner row of pads. An inner row of pads may be a row of pads closer to a center of the integrated device than an outer row of pads. In some implementations, an integrated device may include several inner rows of pads.

[0029] A first plurality of wire bonds (which include wire bond 210a, wire bond 210b, and wire bond 210c) are coupled to (i) a first row of a plurality of pads (which include pad 241a, pad 241b, and pad 241c) of the first integrated device 204, and (ii) a first row of a plurality of pads (which include pad 261a, pad 261b, and pad 261c) of the second integrated device 206.

[0030] A second plurality of wire bonds (which include wire bond 210d, wire bond 210e, and wire bond 210f) are coupled to (i) a second row of a plurality of pads (which include pad 241d, pad 241e, and pad 241f) of the first integrated device 204 and (ii) a second row of a plurality of pads (which include pad 261d, pad 261e, and pad 261f) of the second integrated device 206.

[0031] 4 shows two rows of pads for each of the integrated devices. However, various implementations may have different numbers of rows of pads each coupled to a plurality of wirebonds. For example, the first integrated device 204 may include a third row of pads offset from the first row of pads, and the second integrated device 206 may include a third row of pads offset from the first row of pads. The third row of pads of the first integrated device 204 and the third row of pads of the second integrated device 206 may be coupled to a third plurality of wirebonds. The third plurality of wirebonds may have a different vertical offset from the first plurality of wirebonds and the second plurality of wirebonds.

[0032] As further shown and described below in at least FIG. 6, the first plurality of wire bonds may be vertically offset from the surface of the integrated device (e.g., may be a maximum vertical offset) different from the vertical offset (e.g., a maximum vertical offset) of the second plurality of wire bonds from the surface of the integrated device.

[0033] The configuration of pads in staggered rows and the use of wirebonds with different vertical offsets aid in providing high density electrical connections between integrated devices. For example, the configuration shown in FIG. 4 illustrates a configuration that can accommodate at least 40 wirebonds per millimeter. The plurality of wirebonds 210 can have wirebonds with a minimum diameter of 15 micrometers. In some implementations, the illustrated configuration can accommodate at least 50 wirebonds per millimeter. In some implementations, the illustrated configuration can accommodate between 40-60 wirebonds per millimeter (e.g., 40, 41, ... 59, 60 wirebonds per millimeter). The high density electrical connections provided by the plurality of wirebonds 210 can aid in providing over 200 channels (e.g., electrical connections) for signals, power, and ground between two integrated devices, each having a minimum length and / or width of about 4 millimeters.

[0034] FIG. 5 shows a plan view of how wire bonds are bonded to pads of an integrated device. FIG. 5 may be a close-up view of the wire bond connections shown in FIG. 4. Wire bond 210a is bonded to pad 241a and pad 261a. Wire bond 210b is bonded to pad 241b and pad 261b. Wire bond 210d is bonded to pad 241d and pad 261d. Wire bond 210a may be partially located on pad 241d and pad 261d. For example, wire bond 210a may at least partially vertically overlap pad 241d and pad 261d. Wire bond 210b may be partially located on pad 241d and pad 261d. For example, wire bond 210b may at least partially vertically overlap pad 241d and pad 261d.

[0035] In some implementations, the first row of pads and the second row of pads may have a center-to-center pitch (e.g., row-to-row pitch (A)) of about 61 micrometers. In some implementations, the first row of pads may have a center-to-center pitch (B) between pads (e.g., between pads 241a and 241b) of about 40.5 micrometers. In some implementations, the second row of pads may have a center-to-center pitch (B) between pads (e.g., between pads 241d and 241f) of about 40.5 micrometers. In some implementations, the staggered pitch (C) (e.g., center-to-center pitch between pads 241a and 241d) is about 20.25 micrometers. However, various implementations may use different dimensions for the various pitches.

[0036] FIG. 6 illustrates a side view of how wire bonds are bonded to pads of an integrated device. FIG. 6 illustrates that different wire bonds may be vertically offset (e.g., maximum vertical offset) from a surface of an integrated device separately. For example, wire bond 210a may be vertically (e.g., vertical distance, maximum vertical distance) offset (E) from a surface of an integrated device (e.g., 204, 206) by about 55 micrometers. Other wire bonds from the plurality of wire bonds 210, such as wire bond 210b and / or wire bond 210c, may be vertically offset by a similar height. In another example, wire bond 210d may be vertically (e.g., vertical distance, maximum vertical distance) offset (D) from a surface of an integrated device (e.g., 204, 206) by about 35 micrometers. Other wire bonds from the plurality of wire bonds 210, such as wire bond 210e and / or wire bond 210f, may be vertically offset by a similar height. Wirebond 210a may be located at least partially over wirebond 210d. The use of different vertical offsets for different sets of wirebonds helps to provide high density interconnects between integrated devices by fitting more interconnects per millimeter between integrated devices.

[0037] FIG. 7 illustrates a package 700 including multiple wire bonds between integrated devices. The package 700 is similar to the package 200 of FIG. 2 and therefore includes the same or similar components as the package 200. As shown in FIG. 7, the package 700 includes a substrate 202, a first integrated device 204, a second integrated device 206, multiple wire bonds 210, and an encapsulation layer 708. The encapsulation layer 708 may be the same as, similar to, or different from the encapsulation layer 208. The encapsulation layer 708 may include a mold underfill (MUF). The encapsulation layer 708 may be disposed over the substrate 202 and within the cavity 209 of the substrate 202. The encapsulation layer 708 may encapsulate the first integrated device 204 and / or the second integrated device 206. The encapsulation layer 708 may encapsulate the pillar interconnects 240 , the solder interconnects 242 , the pillar interconnects 260 , the solder interconnects 262 , and / or the wire bonds 210 .

[0038] It should be noted that the number of wire bonds shown in Figures 2-7 are examples. Different implementations may have different numbers of wire bonds coupled to the integrated device.

[0039] As described above, underfill 244, underfill 264, encapsulation layer 208, and / or encapsulation layer 708 may have certain properties to ensure that the spaces around the pillar interconnects and between the integrated device and the substrate are properly filled to ensure a strong and secure bond between the integrated device and the substrate.

[0040] For example, the underfill (e.g., 244, 264) may include a capillary underfill with good flowability. The capillary underfill (CUF) may include a polymer composite of silica particles and epoxy liquid. One property of the capillary underfill is good flowability when heated, so the capillary underfill can flow into the narrow space between the integrated device and the substrate, which is driven by capillary forces. The capillary underfill may have sufficient silica filler to obtain a final cured material with a low CTE. The capillary underfill is a liquid type that typically freezes at or below -40 degrees Celsius and may be thawed and heated before application.

[0041] The encapsulation layer 208 may include an encapsulant and / or an epoxy molding compound (EMC) that is used to cover the entire package after applying the capillary underfill, and therefore the encapsulation layer can protect the entire package. The encapsulation layer 208 may include a solid pellet that can be stored at room temperature. The encapsulation layer 208 can be heated to become liquid and processed under transfer molding flow to cover the integrated device.

[0042] In some implementations, a molded underfill (MUF) can be used in place of or in conjunction with the underfill (e.g., 244, 264) and / or the encapsulation layer 208. The molded underfill can be a combination of a capillary underfill (e.g., underfill 244) and an EMC (e.g., encapsulation layer 208). The material properties and application format of the molded underfill are the same or similar to those of the regular EMC, but with a very fine filler size, and therefore the molded underfill can be pressed into the gap of the substrate during the transfer molding process into the integrated device. In this way, the molded underfill can replace the capillary underfill and reduce process steps.

[0043] EMC and MUF can have very high filler loadings up to 90 wt%, therefore the cured material properties are better than capillary underfills with lower CTE and high elasticity. In some implementations, MUF can be used to replace CUF when the package requires an encapsulation layer. For packages without an encapsulation layer, only CUF can be used. Table 1 below shows exemplary properties of various materials, underfills, and encapsulation layers. Note that the values ​​for materials are examples. Different materials may have different properties. Moreover, the values ​​shown in Table 1 are not limiting.

[0044] [Table 1]

[0045] It should be noted that the encapsulation layer 708 may be applicable to the package 200 of FIG. 2 or any package described in this disclosure. Similarly, it should be noted that the encapsulation layer 208 may be applicable to the package 700 of FIG. 7 or any package described in this disclosure. It should be noted that the encapsulation layer (e.g., 208, 708) may be formed by one or more encapsulation layers. It should be noted that each of the integrated devices may include additional electrical paths between each other and / or between each and the substrate 202. It should be noted that the paths of the electrical signals that may be shown and / or described in this disclosure are exemplary and / or conceptual. Various implementations may use different paths for the electrical signals. Moreover, the electrical signals and / or electrical paths may travel through various types of interconnects (e.g., vias, traces, pads, pillars), solder interconnects, and / or components (e.g., passive devices). Thus, for example, in some implementations, an electrical signal traveling between an integrated device and another integrated device may travel through at least one intervening component (e.g., a passive device, a capacitor) between the integrated devices. The paths shown and / or described for the electrical signals may also apply to power and / or ground. It should also be noted that two or more multiple wire bonds may be used to facilitate bypassing the substrate. Multiple wire bonds may be used to facilitate electrical coupling between three or more integrated devices. For example, a first integrated device may be configured to be electrically coupled to a second integrated device through a first multiple wire bonds. The first integrated device may be configured to be electrically coupled to a third integrated device through a second multiple wire bonds. The terms "first side" and "second side" of a substrate are arbitrary and may refer to either surface of the substrate. For example, the first side of the substrate may be a bottom side of the substrate and the second side of the substrate may be a top side of the substrate. In another example, the first side of the substrate may be a top side of the substrate and the second side of the substrate may be a bottom side of the substrate.

[0046] Exemplary sequence for fabricating an integrated device having pillar interconnects 8A-8B show an example sequence for providing or fabricating an integrated device having pillar interconnects. In some implementations, the sequence of FIG. 8A-8B can be used to provide or fabricate the integrated device of FIG. 2 (e.g., 204, 206) or any of the integrated devices described in this disclosure.

[0047] It should be noted that the sequences of Figures 8A-8B may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing the integrated device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. Various implementations may manufacture the integrated device differently.

[0048] 8A, stage 1 shows a state after an integrated device 204 is prepared. The integrated device 204 may include a die (e.g., a bare semiconductor die). The integrated device 204 may include a substrate (e.g., a silicon substrate) and a number of transistors (e.g., active devices). The integrated device 204 may include a number of pads 241.

[0049] Stage 2 shows the state after a seed layer 811 is formed on the front side of the integrated device 204. The seed layer 811 may include a metal layer. The seed layer 811 may be deposited on the integrated device 204. A plating process may be used to form the seed layer 811.

[0050] Stage 3 shows the state after a photoresist layer 800 is formed on the seed layer 811. The photoresist layer 800 may be deposited on the seed layer 811.

[0051] Stage 4 shows the state after the photoresist layer 800 has been patterned to create at least one opening 801 in the photoresist layer 800 that exposes a portion of the seed layer 811 .

[0052] 8B, stage 5 depicts the state after a plurality of pillar interconnects 830 and a plurality of solder interconnects 832 have been formed on the seed layer 811 through openings 801 in the photoresist layer 800. The plurality of pillar interconnects 830 may be formed on the seed layer 811 through a plating process. The plurality of solder interconnects 832 may be formed on the plurality of pillar interconnects 830 through a deposition process.

[0053] Stage 6 shows the state after the photoresist layer 800 has been removed and a portion of the seed layer 811 has been removed (e.g., etched). Removing the photoresist layer 800 may include stripping the photoresist layer 800.

[0054] Stage 7 illustrates a state after a reflow solder process that bonds (e.g., joins) the plurality of solder interconnects 832 to the plurality of pillar interconnects 830. Stage 7 may illustrate an integrated device (e.g., 204, 206) having pillar interconnects that may be bonded to a substrate. The plurality of pillar interconnects 830 may represent the plurality of pillar interconnects 240. The plurality of solder interconnects 832 may represent the plurality of solder interconnects 242. The seed layer 811 may be considered part of the pillar interconnects 830.

[0055] Illustrative flow diagram of a method for fabricating an integrated device including pillar interconnects In some implementations, fabricating an integrated device having pillar interconnects includes several processes. Figure 9 shows an example flow diagram of a method 900 for providing or fabricating an integrated device having pillar interconnects. In some implementations, the method 900 of Figure 9 may be used to provide or fabricate the integrated device (e.g., 204, 206) of Figure 2 described in this disclosure. However, the method 900 may be used to provide or fabricate any of the integrated devices and / or one of the integrated devices described in this disclosure.

[0056] 9 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing an integrated device having pillar interconnects. In some implementations, the order of the processes may be changed or modified.

[0057] The method provides (at 905) an integrated device (e.g., 204, 206). Stage 1 of FIG. 8A shows and describes a first integrated device 204 that is provided. The first integrated device 204 may include a die having active devices such as transistors. The integrated device may include a number of pads.

[0058] The method forms (at 910) a seed layer (e.g., 811) on the front side of the integrated device. The seed layer 811 may include a metal layer. The seed layer 811 may be deposited on the integrated device 204. A plating process may be used to form the seed layer 811. Stage 2 of FIG. 8A illustrates and describes an example of forming a seed layer.

[0059] The method includes (at 915) forming a photoresist layer (e.g., 800) over the seed layer (e.g., 811). The photoresist layer 800 may be formed and patterned over the seed layer 811. The photoresist layer 800 may be deposited over the seed layer 811 and patterned to create at least one opening 801 in the photoresist layer 800 that exposes a portion of the seed layer 811. Stages 3-4 of FIG. 8A illustrate an example of forming and patterning a photoresist layer over a seed layer.

[0060] The method forms (at 920) a plurality of pillar interconnects (e.g., 830) and / or a solder interconnect (e.g., 832) on a seed layer (e.g., 811) through openings 801 in a photoresist layer (e.g., 800). The plurality of solder interconnects may be formed on the seed layer through a deposition process. The plurality of pillar interconnects may be formed on the seed layer through a plating process. The plurality of solder interconnects may be formed on the plurality of pillar interconnects through a deposition process. Stage 5 of FIG. 8B illustrates and describes an example of forming a plurality of pillar interconnects and / or a plurality of solder interconnects.

[0061] The method removes (at 925) the photoresist layer (e.g., 800). Removing the photoresist layer may include removing the photoresist layer. Stage 6 of FIG. 8B shows an example of removing the photoresist layer. In some implementations, a portion of the seed layer 811 may also be removed (at 925). An etching process may be used to remove the portion of the seed layer. Stage 6 of FIG. 8B shows and / or describes an example of a portion of the seed layer being removed. It should be noted that forming the photoresist layer, pillar interconnects and / or solder interconnects, and removing the photoresist layer as described at 915, 920, and 925 may be repeated.

[0062] The method performs (at 930) a reflow solder process that couples (e.g., bonds) the plurality of solder interconnects (e.g., 832) to the plurality of pillar interconnects (e.g., 830). Stage 7 of Figure 8B illustrates and describes one example of a reflow solder process.

[0063] In some implementations, the integrated devices are part of a wafer and singulation may be performed to cut the wafer into individual integrated devices. Method 900 may be used to manufacture any of the integrated devices described in this disclosure.

[0064] Exemplary Sequence for Manufacturing a Substrate In some implementations, manufacturing a substrate includes several processes. Figures 10A-10C show an example sequence for providing or manufacturing a substrate. In some implementations, the sequence of Figures 10A-10C may be used to provide or manufacture the substrate 202 of Figure 2. However, the process of Figures 10A-10C may be used to manufacture any of the substrates described in this disclosure.

[0065] 10A-10C may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0066] 10A, stage 1 shows the state after a carrier 1000 is provided and a metal layer is formed on the carrier 1000. The metal layer may be patterned to form interconnects 1002. Plating and etching processes may be used to form the metal layer and the interconnects.

[0067] Stage 2 shows the state after a dielectric layer 1020 is formed over the carrier 1000 and the interconnects 1002. The dielectric layer 1020 may include polyimide, although various implementations may use different materials for the dielectric layer.

[0068] Stage 3 shows the state after a plurality of cavities 1010 have been formed in the dielectric layer 1020. The plurality of cavities 1010 may be formed using an etching process (eg, a photoetching process) or a laser process.

[0069] Stage 4 shows the state after interconnects 1012 have been formed in and on the dielectric layer 1020, including in and on the plurality of cavities 1010. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0070] Stage 5 shows the state after another dielectric layer 1022 is formed over dielectric layer 1020. Dielectric layer 1022 can be the same material as dielectric layer 1020. However, various implementations may use different materials for the dielectric layers.

[0071] Stage 6, as shown in Figure 10B, illustrates the state after a plurality of cavities 1030 have been formed in the dielectric layer 1022. An etching process or a laser process may be used to form the cavities 1030.

[0072] Stage 7 shows the state after interconnects 1014 have been formed in and on the dielectric layer 1022, including in and on the plurality of cavities 1030. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0073] Stage 8 shows the state after another dielectric layer 1024 is formed over dielectric layer 1022. Dielectric layer 1024 can be the same material as dielectric layer 1020. However, various implementations may use different materials for the dielectric layers.

[0074] Stage 9 shows the state after a number of cavities 1040 have been formed in the dielectric layer 1024. An etching process or a laser process may be used to form the cavities 1040.

[0075] 10C, stage 10 shows the state after interconnects 1016 have been formed in and on the dielectric layer 1024, including in and on a plurality of cavities 1040. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0076] Some or all of the interconnects 1002, 1012, 1014 and / or 1016 may define the plurality of interconnects 222 of the substrate 202. The dielectric layers 1020, 1022, 1024 may be represented by at least one dielectric layer 220.

[0077] Stage 11 shows the state after the carrier 1000 has been decoupled (e.g., removed or polished away) from the dielectric layer 220 and separated from the substrate 202 which includes at least one dielectric layer 220 and a plurality of interconnects 222.

[0078] Stage 12 illustrates the state after a first solder resist layer 224 and a second solder resist layer 226 have been formed on the substrate 202. A deposition process may be used to form the first solder resist layer 224 and the second solder resist layer 226.

[0079] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0080] Illustrative Flowchart of a Method for Manufacturing a Substrate In some implementations, manufacturing a substrate includes several processes. Figure 11 shows an example flow diagram of a method 1100 for providing or manufacturing a substrate. In some implementations, the method 1100 of Figure 11 can be used to provide or manufacture the substrate of Figure 2. For example, the method of Figure 11 can be used to manufacture the substrate 202.

[0081] 11 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0082] The method provides (at 1105) a carrier 1000. Various implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or carrier tape. Stage 1 of Figure 10A illustrates an example of a provided carrier.

[0083] The method forms (at 1110) a metal layer on the carrier 1000. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier may include the metal layer. The metal layer on the carrier may be patterned to form the interconnects (e.g., 1002). Stage 1 of FIG. 10A illustrates and describes one example of a metal layer and interconnects formed on the carrier.

[0084] The method forms (at 1115) a dielectric layer 1020 over the carrier 1000 and the interconnects 1002. The dielectric layer 1020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1010) in the dielectric layer 1020. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Stages 2-3 of FIG. 10A illustrate an example of forming the dielectric layer and the cavities in the dielectric layer.

[0085] The method forms (at 1120) interconnects in and on the dielectric layer. For example, interconnects 1012 may be formed in and on the dielectric layer 1020. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Stage 4 of FIG. 10A illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0086] The method forms (at 1125) a dielectric layer 1022 over the dielectric layer 1020 and the interconnects. The dielectric layer 1022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1030) in the dielectric layer 1022. The plurality of cavities may be formed using an etching process or a laser process. Stages 5-6 of Figures 10A-10B show and / or describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0087] The method forms (at 1130) interconnects in and / or on the dielectric layer. For example, interconnects 1014 may be formed. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and in the dielectric layer. Forming the interconnects may also include forming the interconnects within cavities in the dielectric layer. Stage 7 of FIG. 10B illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0088] The method may form additional dielectric layers and additional interconnects as described at 1125 and 1130. Stages 8-10 of Figures 10B-10C show an example of forming interconnects in and on a dielectric layer.

[0089] Once all the dielectric layers and additional interconnects have been formed, the method may decouple (e.g., remove or polish away) the carrier (e.g., 1000) from the dielectric layers 1020, leaving the substrate. In some implementations, the method may form a solder resist layer (e.g., 224, 226) over the substrate.

[0090] Various implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer. For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer.

[0091] Exemplary sequence for manufacturing a package including wire bonds coupled to an integrated device 12A-12B show an example sequence for providing or manufacturing a package including wire bonds coupled to an integrated device. In some implementations, the sequence of FIG. 12A-12B can be used to provide or manufacture a package 200 including a substrate 202 and wire bonds coupled to an integrated device of FIG. 2, or any of the packages described in this disclosure.

[0092] It should be noted that the sequence of Figures 12A-12B may combine one or more stages to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. The sequence of Figures 12A-12B may be used to manufacture one package or several packages simultaneously (as part of a wafer).

[0093] As shown in FIG. 12A, stage 1 shows a state after the substrate 202 is prepared. The substrate 202 may be provided by a supplier or may be manufactured. A process similar to that shown in FIGS. 10A-10C may be used to manufacture the substrate 202. However, various implementations may use different processes to manufacture the substrate 202. Examples of processes that may be used to manufacture the substrate 202 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The substrate 202 may be a laminate substrate, a coreless substrate, an organic substrate, or a substrate including a core layer. In some implementations, the at least one dielectric layer 220 may include a core layer and / or a prepreg layer. The substrate 202 includes a cavity 209. The cavity 209 may be manufactured using a laser process (e.g., laser cutting). The cavity 209 may be formed after the substrate 202 is manufactured and / or provided. In some implementations, the substrate 202 is provided with the cavity 209.

[0094] Stage 2 illustrates a state after integrated device 204 and integrated device 206 are bonded to a first surface (e.g., top surface) of substrate 202. Integrated device 204 is bonded to substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. Integrated device 206 is bonded to substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. Portions of integrated device 204 and portions of integrated device 206 may be located above cavity 209. Integrated device 204 may be bonded to substrate 202 such that a front surface (e.g., active surface) of integrated device 204 faces substrate 202. Similarly, integrated device 206 may be bonded to substrate 202 such that a front surface of integrated device 206 faces substrate 202.

[0095] Stage 3 illustrates the state after underfill 244 has been provided (e.g., formed) between substrate 202 and integrated device 204, and underfill 264 has been provided (e.g., formed) between substrate 202 and integrated device 206. The underfill (e.g., 244, 264) may be provided around the pillar interconnects (e.g., 240, 260) and / or the solder interconnects (e.g., 242, 262) via capillary action and / or capillary forces. The capillary properties of the underfill allow it to fill small spaces and / or small gaps between the integrated device and the substrate.

[0096] As shown in FIG. 12B, stage 4 shows a state after the wire bonds 210 are bonded to the first integrated device 204 and the second integrated device 206. For example, the wire bonds 210 may be formed between the first integrated device 204 and the second integrated device 206. The wire bonds 210 may be bonded to the pads 241 (of the first integrated device 204) and the pads 261 (of the second integrated device 206). The wire bonds 210 may be formed through the cavity 209 of the substrate 202. One advantage of forming the wire bonds 210 after the integrated devices are bonded to the substrate is that the wire bonds 210 are less likely to break and / or fail due to movement between the integrated devices since the integrated devices are fixed relative to each other after bonding to the substrate. Examples of how the wire bonds 210 are bonded to the integrated devices are shown and described at least in FIGS. 4-6.

[0097] Stage 5 illustrates a state after the encapsulation layer 208 is formed on the first side of the substrate 202 such that the encapsulation layer 208 encapsulates the first integrated device 204 and the second integrated device 206. The encapsulation layer 208 may encapsulate the wire bonds 210. The encapsulation layer 208 may at least partially fill the cavity 209 of the substrate 202. The process of forming and / or depositing the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that in some implementations, the encapsulation layer 208 may replace the underfill (e.g., 244, 264), as shown in FIG. 7. Thus, in some implementations, the encapsulation layer 208 may be formed and placed in the area occupied by the underfill 244 and / or 264.

[0098] Stage 6 shows the state after a plurality of solder interconnects 280 have been bonded to the substrate 202. A reflow solder process may be used to bond the plurality of solder interconnects. Stage 8 may show the package 200 including the substrate 202, the first integrated device 204, the second integrated device 206, the underfill 244, the underfill 264, and the encapsulation layer 208, as described at least in FIG.

[0099] The packages described in this disclosure (eg, 200, 700) may be manufactured one at a time, or may be manufactured together as part of one or more wafers and then singulated into individual packages.

[0100] Illustrative flow diagram of a method for manufacturing a package containing wirebonded integrated devices In some implementations, manufacturing a package including wire bonds coupling between integrated devices includes several processes. Figure 13 shows an example flow diagram of a method 1300 for providing or manufacturing a package including wire bonds coupled to integrated devices. In some implementations, the method 1300 of Figure 13 may be used to provide or manufacture the package 200 of Figure 2 described in this disclosure. However, the method 1300 may be used to provide or manufacture any of the packages described in this disclosure.

[0101] It should be noted that the method of Figure 13 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing a package including wire bonds coupled to an integrated device. In some implementations, the order of the processes may be changed or modified.

[0102] The method provides (at 1305) a substrate (e.g., 202). The substrate 202 may be provided by a supplier or may be manufactured. The substrate 202 includes a first side and a second side. The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The substrate 202 may include at least one cavity 209. Various implementations may provide different substrates. A process similar to that shown in FIGS. 10A-10C may be used to manufacture the substrate 202. However, various implementations may use different processes to manufacture the substrate 202. Stage 1 of FIG. 12A is described with an example of providing a substrate.

[0103] The method bonds (at 1310) the integrated device to the substrate. For example, the method may bond the integrated device 204 and the integrated device 206 to a first side (e.g., top side) of the substrate 202. The integrated device 204 is bonded to the substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. The integrated device 206 is bonded to the substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. A portion of the integrated device 204 and a portion of the integrated device 206 may be located above the cavity 209. The integrated device 204 may be bonded to the substrate 202 such that a front side (e.g., active side) of the integrated device 204 faces the substrate 202. Similarly, the integrated device 206 may be bonded to the substrate 202 such that a front side of the integrated device 206 faces the substrate 202. Stage 2 of FIG. 12A illustrates and describes an example of bonding an integrated device to a substrate.

[0104] The method forms (at 1315) at least one underfill between the integrated device and the substrate. For example, the method may provide underfill 244 between the substrate 202 and the integrated device 204, and may provide underfill 264 between the substrate 202 and the integrated device 206. The underfill (e.g., 244, 264) may be provided around the pillar interconnects (e.g., 240, 260) and / or the solder interconnects (e.g., 242, 262) via capillary action and / or capillary forces. The capillary properties of the underfill allow it to fill small spaces and / or small gaps between the integrated device and the substrate. Stage 3 of FIG. 12A illustrates and describes an example of providing an underfill.

[0105] The method includes (at 1320) bonding a plurality of wire bonds 210 to the first integrated device 204 and the second integrated device 206. The plurality of wire bonds 210 may be formed between the first integrated device 204 and the second integrated device 206. The plurality of wire bonds 210 are bonded to a plurality of pads 241 (of the first integrated device 204) and a plurality of pads 261 (of the second integrated device 206). Examples of how the plurality of wire bonds 210 may be bonded to the integrated devices are shown and described in at least Figures 4-6. Stage 4 of Figure 12B shows and describes an example of bonding wire bonds to an integrated device.

[0106] The method may form (at 1325) an encapsulation layer over the substrate. For example, the method may form the encapsulation layer 208 over the first side of the substrate 202 such that the encapsulation layer 208 encapsulates the first integrated device 204 and the second integrated device 206. The encapsulation layer 208 may encapsulate the wire bonds 210. The encapsulation layer 208 may at least partially fill the cavity 209 of the substrate 202. The process of forming and / or depositing the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that in some implementations, the encapsulation layer 208 may replace the underfill (e.g., 244, 264) as shown in FIG. 2. Thus, in some implementations, the encapsulation layer 208 may be formed and placed in the area occupied by the underfill. Stage 5 of FIG. 12B illustrates and describes an example of forming an encapsulation layer.

[0107] The method further comprises (at 1330) bonding a plurality of solder interconnects (e.g., 280) to a second side of the substrate (e.g., 202). A reflow solder process may be used to bond the plurality of solder interconnects. Stage 6 of FIG. 12B illustrates and describes an example of bonding the solder interconnects to a substrate.

[0108] Exemplary Electronic Devices FIG. 14 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1402, a laptop computer device 1404, a fixed location terminal device 1406, a wearable device 1408, or an automobile 1410 may include a device 1400 as described herein. The device 1400 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1402, 1404, 1406, and 1408 and the vehicle 1410 illustrated in FIG. 14 are merely examples. Other electronic devices may also feature device 1400, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0109] One or more of the components, processes, features, and / or functions shown in Figures 2-7, 8A-8B, 9, 10A-10C, 11, 12A-12B, and / or 13-14 may be rearranged and / or combined into a single component, process, feature, or function, or may be combined into several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from the present disclosure. It is also noted that Figures 2-7, 8A-8B, 9, 10A-10C, 11, 12A-12B, and / or 13-14 and corresponding descriptions thereof in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 2-7, 8A-8B, 9, 10A-10C, 11, 12A-12B, and / or 13-14 and corresponding descriptions thereof may be used to manufacture, fabricate, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0110] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some examples, the figures may not be to scale. In some examples, for clarity, not all components and / or parts are shown. In some examples, the positions, locations, sizes and / or shapes of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0111] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, object A and object C may still be considered to be coupled to each other even if they do not physically contact each other directly. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not have an electric current traveling between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulate" means that an object may partially encapsulate or fully encapsulate another object. The terms "top" and "bottom" are arbitrary. A component placed on top may be placed on top of a component placed on the bottom. A top component may be considered a bottom component and vice versa. As described in this disclosure, a first component placed "on" a second component may mean that the first component is placed above or below the second component, depending on how bottom or top is arbitrarily defined.In another example, a first component may be disposed over (e.g., above) a first surface of a second component, and a third component may be disposed over (e.g., below) a second surface of the second component, the second surface facing the first surface. It is further noted that the term "over" as used herein in the context of one component being disposed over another component may be used to mean a component that is disposed on and / or within (e.g., disposed on a surface of or embedded in) the other component. Thus, for example, a first component disposed over a second component may mean (1) that the first component is disposed over, but not in direct contact with, the second component, (2) that the first component is disposed on (e.g., on a surface of) the second component, and / or (3) that the first component is disposed within (e.g., embedded in) the second component. A first component that is located "in" a second component may be located partially within the second component or may be located completely within the second component. As used in this disclosure, the term "about "the value of X"" or "approximately the value of X" means within 10 percent of the "value of X". For example, a value of about 1 or approximately 1 means a value in the range of 0.9 to 1.1.

[0112] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Various implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0113] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process is terminated when its operations are completed.

[0114] The following provides a summary of aspects of the disclosure.

[0115] Aspect 1: A package including a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, the plurality of wire bonds being located above (e.g., above, below) the cavity in the substrate.

[0116] Aspect 2: The package of aspect 1, wherein the plurality of wirebonds includes a first plurality of wirebonds coupled to the first integrated device and the second integrated device, and a second plurality of wirebonds coupled to the first integrated device and the second integrated device. A second vertical distance between the second plurality of wirebonds and the first integrated device is different from a first vertical distance between the first plurality of wirebonds and the first integrated device. The second plurality of wirebonds may be located partially above the first plurality of wirebonds. A vertical distance between the wirebonds and a surface of the integrated device and / or a pad of the integrated device may be a vertical perpendicular distance to the surface of the integrated device and / or a pad of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0117] Aspect 3: The package of aspects 1-2, wherein the first integrated device includes a first row of pads and a second row of pads, and the second integrated device includes a first row of pads and a second row of pads, and the plurality of wire bonds includes: (i) a first plurality of wire bonds coupled to the first row of pads of the first integrated device and (ii) the first row of pads of the second integrated device, and a second plurality of wire bonds coupled to (i) the second row of pads of the first integrated device and (ii) the second row of pads of the second integrated device.

[0118] Aspect 4: The package of aspect 3, wherein a first row of the plurality of pads from the first integrated device is staggered relative to a second row of the plurality of pads from the first integrated device.

[0119] Example 5: The package of Examples 1-4, wherein the plurality of wire bonds between the first integrated device and the second integrated device has a density of at least 40 wire bonds per millimeter.

[0120] Example 6: The package of Examples 1 to 5, wherein each wire bond from the plurality of wire bonds has a minimum diameter of 15 micrometers.

[0121] Example 7: The package of Examples 1-6, further comprising an underfill disposed between (i) the first integrated device and the substrate, and (ii) the second integrated device and the substrate. In some implementations, the underfill comprises an encapsulation layer.

[0122] Aspect 8: The package of aspect 7, wherein the underfill comprises a viscosity of about 10 to 30 Pascal seconds (Pa·s).

[0123] Embodiment 9: The package of embodiments 7 to 8, wherein the underfill comprises a capillary underfill and / or a molded underfill.

[0124] Example 10: The package of Examples 1-9, further comprising an encapsulation layer disposed over the substrate, the first integrated device, and the second integrated device.

[0125] Example 11: The package of Example 10, wherein the cavity of the substrate is at least partially filled with the encapsulation layer. In some implementations, the cavity of the substrate is completely filled with the encapsulation layer.

[0126] In some implementations, aspect 1 may be a package including a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of interconnects, a second integrated device coupled to the substrate through a second plurality of interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, the plurality of wire bonds being located above (e.g., above, below) the substrate cavity. The first plurality of interconnects may include a first plurality of solder interconnects. The second plurality of interconnects may include a second plurality of solder interconnects.

[0127] In some implementations, embodiment 1 may be a package including a substrate, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device.

[0128] Embodiment 12: An apparatus comprising: a substrate including a cavity; a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects; a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects; and means for wire interconnection coupled to the first integrated device and the second integrated device, wherein the means for wire interconnection is located above (e.g., above, below) the cavity of the substrate.

[0129] Aspect 13: The apparatus of aspect 12, wherein the means for wire interconnection includes a first plurality of wire bonds coupled to the first integrated device and the second integrated device, and a second plurality of wire bonds coupled to the first integrated device and the second integrated device, and a second vertical distance between the second plurality of wire bonds and the first integrated device is different from the first vertical distance between the first plurality of wire bonds and the first integrated device. The second plurality of wire bonds may be located partially above the first plurality of wire bonds. The vertical distance between the wire bonds and the surface of the integrated device and / or the pad of the integrated device may be a vertical distance relative to the surface of the integrated device and / or the pad of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0130] Example 14: The apparatus of examples 12-13, wherein the first integrated device includes a first row of pads and a second row of pads, and the second integrated device includes a first row of pads and a second row of pads, and the means for wire interconnection includes (i) a first plurality of wire bonds coupled to the first row of pads of the first integrated device and (ii) the first row of pads of the second integrated device, and a second plurality of wire bonds coupled to (i) the second row of pads of the first integrated device and (ii) the second row of pads of the second integrated device.

[0131] Example 15: The apparatus of example 14, wherein a first row of the plurality of pads from the first integrated device is staggered relative to a second row of the plurality of pads from the first integrated device.

[0132] Example 16: The apparatus of Examples 12-15, wherein the means for wire interconnection between the first integrated device and the second integrated device has a density of at least 40 wire bonds per millimeter.

[0133] Example 17: The apparatus of Examples 12 to 16, wherein each wire bond from the means for wire interconnection has a minimum diameter of 15 micrometers.

[0134] Example 18: The apparatus of Examples 12-17, further comprising an underfill disposed between (i) the first integrated device and the substrate, and (ii) the second integrated device and the substrate. In some implementations, the underfill comprises an encapsulation layer.

[0135] Example 19: The apparatus of Examples 12-18, further comprising a means for encapsulation disposed over the substrate, the first integrated device, and the second integrated device.

[0136]

[0023] Embodiment 20: The apparatus of embodiment 19, wherein the means for encapsulation is further disposed within the cavity of the substrate. The cavity of the substrate can be at least partially filled with the means for encapsulation. The cavity of the substrate can be completely filled with the means for encapsulation.

[0137] Aspect 21: The apparatus of aspects 12 to 20, wherein the apparatus comprises a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0138] In some implementations, aspect 12 may be an apparatus including a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of interconnects, a second integrated device coupled to the substrate through a second plurality of interconnects, and a means for wire interconnection coupled to the first integrated device and the second integrated device, the means for wire interconnection being located above (e.g., above, below) the substrate cavity. The first plurality of interconnects may include a first plurality of solder interconnects. The second plurality of interconnects may include a second plurality of solder interconnects.

[0139] In some implementations, embodiment 12 may be an apparatus that includes a substrate, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a means for wire interconnection coupled to the first integrated device and the second integrated device.

[0140] Aspect 22: A method for manufacturing a package, comprising: providing a substrate including a cavity; coupling a first integrated device to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects; coupling a second integrated device to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects; and forming a plurality of wire bonds between the first integrated device and the second integrated device, the plurality of wire bonds being located above (e.g., above, below) the cavity in the substrate.

[0141] Aspect 23: The method of aspect 22, wherein forming the plurality of wire bonds includes bonding a first plurality of wire bonds to the first integrated device and the second integrated device, and bonding a second plurality of wire bonds to the first integrated device and the second integrated device, and a second vertical distance between the second plurality of wire bonds and the first integrated device is different from the first vertical distance between the first plurality of wire bonds and the first integrated device. The second plurality of wire bonds may be located partially above the first plurality of wire bonds. The vertical distance between the wire bonds and a surface of the integrated device and / or a pad of the integrated device may be a vertical distance to a surface of the integrated device and / or a pad of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0142] Aspect 24: The method of aspects 22-23, wherein the first integrated device includes a first row of pads and a second row of pads, and the second integrated device includes a first row of pads and a second row of pads, and forming the plurality of wire bonds includes: bonding a first plurality of wire bonds to (i) the first row of pads of the first integrated device and (ii) the first row of pads of the second integrated device; and bonding a second plurality of wire bonds to (i) the second row of pads of the first integrated device and (ii) the second row of pads of the second integrated device.

[0143] Example 25: The method of example 24, wherein a first row of the plurality of pads from the first integrated device is staggered relative to a second row of the plurality of pads from the first integrated device.

[0144] Example 26: The method of Examples 22-25, wherein the plurality of wire bonds between the first integrated device and the second integrated device are formed having a density of at least 40 wire bonds per millimeter.

[0145] Example 27: The method of Examples 22-26, further comprising forming an underfill disposed between (i) the first integrated device and the substrate, and (ii) the second integrated device and the substrate.

[0146] Example 28: The method of Examples 22-27, further comprising forming an encapsulation layer disposed over the substrate, the first integrated device, and the second integrated device.

[0147] Example 29: The method of Example 28, further comprising forming an encapsulation layer at least partially within the cavity of the substrate.

[0148] In some implementations, aspect 22 may be a method for manufacturing a package that includes providing a substrate including a cavity, coupling a first integrated device to the substrate through a first plurality of interconnects, coupling a second integrated device to the substrate through a second plurality of interconnects, and forming a plurality of wire bonds between the first integrated device and the second integrated device, the plurality of wire bonds being located above (e.g., above, below) the cavity of the substrate. The first plurality of interconnects may include a first plurality of solder interconnects. The second plurality of interconnects may include a second plurality of solder interconnects.

[0149] Various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and is not intended to limit the scope of the claims. Thus, the present teachings can be easily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. [Explanation of symbols]

[0150] 100 packages 102 Substrate 104 Integrated Devices 106 Integrated Devices 120 Dielectric layer 122 Interconnection 124 Solder Interconnects 144 Solder Interconnects 164 Solder Interconnects 200 packages 202 Substrate 204 First integrated device 206 Second Integrated Device 208 Encapsulation Layer 209 Cavity 210 Wirebond 210a Wirebond 210b wire bond 210c Wirebond 210d Wirebond 210e Wirebond 210f wire bond 220 Dielectric layer 222 Interconnection 224 First solder resist layer 226 Second solder resist layer 240 Pillar Interconnect 241 Pad 241a Pad 241b Pad 241c Pad 241d Pad 241e Pad 241f Pad 242 Multiple Solder Interconnects 244 Underfill 260 Pillar Interconnect 261 Pad 261a Pad 261b Pad 261c Pad 261d Pad 261e Pad 261f Pad 262 Multiple Solder Interconnects 264 Underfill 280 Multiple Solder Interconnects 700 packages 708 Encapsulation Layer 800 photoresist layers 801 Aperture 811 Seed Layer 830 Multiple Pillar Interconnects 832 Multiple Solder Interconnects 900 ways 1000 Carriers 1002 Interconnection 1010 Cavity 1012 Interconnect 1014 Interconnection 1016 Interconnection 1020 Dielectric layer 1022 Dielectric layer 1024 Dielectric layer 1030 Cavity 1040 Cavity 1100 methods 1400 devices 1402 Mobile Phone Device 1404 Laptop Computer Device 1406 Fixed Location Terminal Device 1408 Wearable Devices 1410 Motor Vehicles

Claims

1. a substrate including a cavity; a first integrated device coupled to the substrate through a first plurality of pillar interconnects and / or a first plurality of solder interconnects; a second integrated device coupled to the substrate through a second plurality of pillar interconnects and / or a second plurality of solder interconnects; a plurality of parallel wire bonds coupled to the first integrated device and the second integrated device, the plurality of parallel wire bonds overlying the cavity in the substrate; the first integrated device includes a first row of pads and a second row of pads; the second integrated device includes a first row of pads and a second row of pads; The plurality of parallel wire bonds include: (i) a first row of pads of the first integrated device, and (ii) a first plurality of wire bonds coupled to the first row of pads of the second integrated device; (i) the second row of pads of the first integrated device; and (ii) a second plurality of wire bonds coupled to the second row of pads of the second integrated device; the first row of pads from the first integrated device being offset relative to the second row of pads from the second integrated device; a second vertical distance between the second plurality of wire bonds and the first integrated device is different from a first vertical distance between the first plurality of wire bonds and the first integrated device; package.

2. 10. The package of claim 1, wherein the plurality of parallel wirebonds between the first integrated device and the second integrated device has a density of at least 40 wirebonds per millimeter.

3. 10. The package of claim 1, wherein each wire bond from the plurality of parallel wire bonds has a minimum diameter of 15 micrometers.

4. The package of claim 1 , further comprising an underfill disposed between (i) the first integrated device and the substrate, and (ii) the second integrated device and the substrate.

5. The package of claim 4, wherein the underfill comprises a viscosity of about 10 to 30 Pascal seconds (Pa·s).

6. The package of claim 4 , wherein the underfill comprises a capillary underfill and / or a molded underfill.

7. The package of claim 1 further comprising an encapsulation layer disposed over said substrate, said first integrated device, and said second integrated device.

8. The package of claim 7 , wherein the cavity in the substrate is at least partially filled with the encapsulation layer.

9. A package as described in any one of claims 1 to 8, wherein the first row of pads has a center-to-center pitch between pads of 40.5 micrometers, and / or the second row of pads has a center-to-center pitch between pads of 40.5 micrometers, and / or the first row of pads and the second row of pads have a row-to-row pitch of 61 micrometers.

10. An apparatus comprising a package according to any one of claims 1 to 9.

11. 1. A method for manufacturing a package, comprising: Providing a substrate including a cavity; coupling a first integrated device to the substrate through a first plurality of pillar interconnects and / or a first plurality of solder interconnects; coupling a second integrated device to the substrate through a second plurality of pillar interconnects and / or a second plurality of solder interconnects; forming a plurality of parallel wire bonds between the first integrated device and the second integrated device, the plurality of parallel wire bonds overlying the cavity in the substrate; the first integrated device includes a first row of pads and a second row of pads; the second integrated device includes a first row of pads and a second row of pads; The step of forming a plurality of parallel wire bonds comprises: (i) coupling a first plurality of wire bonds to the first row of pads of the first integrated device and (ii) to the first row of pads of the second integrated device; (i) coupling a second plurality of wire bonds to the second row of pads of the first integrated device, and (ii) to the second row of pads of the second integrated device; the first row of pads from the first integrated device being offset relative to the second row of pads from the second integrated device; a second vertical distance between the second plurality of wire bonds and the first integrated device is different from a first vertical distance between the first plurality of wire bonds and the first integrated device; method.

12. 12. The method of claim 11, wherein the plurality of parallel wire bonds between the first integrated device and the second integrated device are formed with a density of at least 40 wire bonds per millimeter.

13. 12. The method of claim 11, further comprising forming an underfill disposed between (i) the first integrated device and the substrate, and (ii) the second integrated device and the substrate.

14. The method of claim 11 , further comprising forming an encapsulation layer disposed over the substrate, the first integrated device, and the second integrated device.

15. The method of claim 14 , wherein the encapsulation layer is further formed at least partially within the cavity of the substrate.

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