Vertical transistor with gate connection grid

Abstract

In a general aspect, a semiconductor device (100) can include a plurality of vertical transistor segments (200, 300) disposed within an active area (110) of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes (206b, 306b). A first dielectric (415, 915, 1015) can be disposed on the active area. A conductive grid (130, 230, 330, 430, 630, 930, 1030) can be disposed on the first dielectric. The conductive grid can be electrically coupled to the respective gate electrodes using a plurality of conductive contacts (430a, 630a, 930a, 1030a) formed through the first dielectric. A second dielectric (925) can be disposed on the conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include portions (951) electrically coupled to the respective gate electrodes through the conductive grid using at least one conductive contact (930a) to the conductive grid formed through the second dielectric.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of and claims priority to U.S. patent application Ser. No. 17 / 194,846, entitled "VERTICAL TRANSISTORS WITH GATE CONNECTION GRID," filed March 8, 2021, the disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002] Vertical transistors, such as vertical power transistors implemented in semiconductor dies, are used in a wide variety of applications, including industrial applications, consumer electronics applications, etc. In some implementations, semiconductor devices that include power transistors may include metal tracks or metal runners that may be used to route control signals (e.g., gate signals) for the transistors.

[0003] However, there are some drawbacks associated with the use of such metal tracks. For example, the area of ​​the semiconductor die used to route the metal tracks may not be used to implement the active portion of the device, which in some implementations may reduce the active area of ​​the associated transistor by up to 15% relative to the available semiconductor die area. In some technologies, such as silicon carbide (SiC), gallium nitride (GaN), etc., such reduction in active area may significantly increase product cost due at least to the cost of the semiconductor wafers used to fabricate such transistors. Also, routing such metal tracks for gate connections may require interrupting metal routing for other transistor connections, such as source metal routing for vertical field effect transistors (FETs) and / or emitter metal routing for insulated gate bipolar transistors (IGBTs). Such interruption of metal routing may increase associated resistance and / or may make it difficult to form electrical connections, such as wire bonds or conductive clips, when packing the associated semiconductor die. Summary of the Invention

[0004] In a general aspect, the semiconductor device may include a vertical transistor having a first transistor segment and a second transistor segment. The first transistor segment may include a first body region, a first source region, and a first gate electrode. The second transistor segment may include a second body region, a second source region, and a second gate electrode. The semiconductor device may further include a first dielectric layer disposed on the vertical transistor and a conductive grid disposed on the first dielectric layer. The conductive grid may be electrically coupled to the first gate electrode and the second gate electrode using at least a first conductive contact formed through the first dielectric layer. The semiconductor device may also include a second dielectric layer disposed on the conductive grid and the first dielectric layer, and a conductive metal layer disposed on the second dielectric layer. The conductive metal layer may include a first portion and a second portion. The first portion may be electrically coupled to the first body region, the first source region, the second body region, and the second source region using at least a second conductive contact formed through the first dielectric layer and the second dielectric layer. The second portion may be electrically coupled to the conductive grid using at least a third conductive contact formed through the second dielectric layer.

[0005] In another general aspect, the semiconductor device can include a semiconductor region, an active region disposed within the semiconductor region, and an isolation region disposed within the semiconductor region. The isolation region can at least partially surround the active region. The semiconductor device can also include a plurality of vertical transistor segments disposed within the active region. The plurality of vertical transistor segments can include respective gate electrodes. The semiconductor device can also include a first dielectric layer disposed on the active region, and a conductive grid disposed on the first dielectric layer. The conductive grid can be electrically coupled to the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric layer. The semiconductor device can further include a second dielectric layer disposed on the conductive grid and the first dielectric layer, and a conductive metal layer disposed on the second dielectric layer. The conductive metal layer can include portions electrically coupled to the respective gate electrodes through the conductive grid using at least one conductive contact to the conductive grid formed through the second dielectric layer.

[0006] In another general aspect, a method of fabricating a semiconductor device can include forming a vertical transistor in a semiconductor region. The vertical transistor can include a first transistor segment and a second transistor segment. The first transistor segment can have a first body region, a first source region, and a first gate electrode. The second transistor segment can have a second body region, a second source region, and a second gate electrode. The method can further include forming a first dielectric layer on the vertical transistor and forming a conductive grid on the first dielectric layer. The conductive grid can be electrically coupled to the first gate electrode and the second gate electrode using at least a first conductive contact formed through the first dielectric layer. The method can also include forming a second dielectric layer on the conductive grid and the first dielectric layer, and forming a conductive metal layer on the second dielectric layer. The conductive metal layer can include a first portion that can be electrically coupled to the first body region, the first source region, the second body region, and the second source region using at least a second conductive contact formed through the first dielectric layer and the second dielectric layer. The conductive metal layer can also include a second portion that can be electrically coupled to the conductive grid using at least a third conductive contact formed through the second dielectric layer. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 1 illustrates a schematic diagram of a semiconductor device including a gate connection grid. [Figure 1B] FIG. 1 illustrates a schematic diagram of a semiconductor device including a gate connection grid. [Diagram 2] FIG. 2A is a schematic diagram illustrating a cross-sectional view of a vertical transistor segment having a planar gate electrode coupled to a gate connection grid. [Diagram 3] FIG. 2A shows a schematic cross-sectional view of a vertical transistor segment having a trench gate electrode coupled to a gate connection grid. [Figure 4] FIG. 1 shows a portion of a semiconductor device implementing a vertical transistor including a gate connection grid. [Diagram 5] FIG. 2 shows a schematic diagram of a gate electrode and associated bulk / body and source / emitter regions of a vertical transistor. [Figure 6] 1A-1D are schematic diagrams illustrating various configurations of a vertical transistor planar gate electrode and associated bulk / body and source / emitter regions. [Figure 7] 1A-1D are schematic diagrams illustrating various configurations of a vertical transistor planar gate electrode and associated bulk / body and source / emitter regions. [Figure 8] 1A-1D are schematic diagrams illustrating various configurations of a vertical transistor planar gate electrode and associated bulk / body and source / emitter regions. [Figure 9A] 1A to 1C are cross-sectional views illustrating a manufacturing process for a vertical transistor having a planar gate electrode. [Figure 9B] 1A to 1C are cross-sectional views illustrating a manufacturing process for a vertical transistor having a planar gate electrode. [Figure 9C] 1A to 1C are cross-sectional views illustrating a manufacturing process for a vertical transistor having a planar gate electrode. [Figure 9D] 1A to 1C are cross-sectional views illustrating a manufacturing process for a vertical transistor having a planar gate electrode. [Figure 9E] 1A to 1C are cross-sectional views illustrating a manufacturing process for a vertical transistor having a planar gate electrode. [Figure 9F] 1A to 1C are cross-sectional views illustrating a manufacturing process for a vertical transistor having a planar gate electrode. [Figure 9G] 1A to 1C are cross-sectional views illustrating a manufacturing process for a vertical transistor having a planar gate electrode. [Figure 10] FIG. 10 is a cross-sectional view that illustrates a schematic of a vertical device having a trench gate electrode that can be fabricated using a process similar to that of FIGS. 9A-9G.

[0008] In the drawings, which are not necessarily drawn to scale, the same reference numbers in different figures may refer to the same and / or similar components (elements, structures, etc.). The drawings generally illustrate various implementations discussed in the present disclosure, by way of example, but not by way of limitation. A reference number shown in one drawing may not be repeated for the same and / or similar elements in related figures. A reference number that is repeated in multiple figures may not be specifically discussed with respect to each of those drawings, but is provided for context between the related figures. Also, when multiple examples of an element are shown in a given figure, not all the same elements in the drawings are specifically referenced with one reference number. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The present disclosure is directed to vertical transistor implementations. For illustrative and discussion purposes, the examples shown herein are generally described with respect to n-channel vertical transistors implemented with planar gate electrodes. However, in some implementations, such as the implementations of Figures 3 and 10, the techniques described herein can be implemented in vertical transistors that include trench gate electrodes. Also, in some implementations, the semiconductor conductivity types discussed herein can be reversed (e.g., n-type and p-type conductivity types can be reversed to create a p-channel vertical transistor).

[0010] Implementations described herein may address at least some of the shortcomings of current implementations discussed above. For example, implementations described herein include a gate connection grid that provides a low resistance electrical connection to a gate electrode to a doped polysilicon gate electrode of an associated transistor, such as, for example, a vertical power transistor. Utilizing such a gate connection grid allows metal tracks or metal runners for carrying gate control signals to be removed or omitted from a power transistor implemented within a semiconductor die. Thus, the active area of ​​the associated transistor may be increased by 1 percent compared to the available semiconductor die area, or up to nearly 100 percent of the available semiconductor die area. In some implementations, the available semiconductor die area may be a semiconductor area within an isolation or termination region of a corresponding semiconductor die. Such an isolation or termination region may be disposed around at least a portion of the perimeter of the corresponding semiconductor die and may help tune the breakdown voltage of the associated power transistor. For example, such an isolation region may prevent breakdown from occurring below the rated voltage of the transistor, for example, by terminating high electric fields during operation of the transistor.

[0011] Also, because no metal tracks or metal runners are used in the exemplary implementations described herein to carry electrical signals, e.g., gate control signals, for the power transistors, the signal metal for other connections to the transistors, such as source and / or emitter connections, can be continuous. That is, because no such metal runners are used, the implementations described herein avoid discontinuities in the signal metal to accommodate the routing of such metal tracks. This allows the associated area of ​​the source and / or emitter signal metal to be increased, which in turn can improve the performance of the associated transistors, e.g., increasing the current carrying capacity for the same die size as current implementations, and can simplify electrical connections to the signal metal, such as electrical clips or wirebond connections, when the device is implemented for use.

[0012] The approaches described herein may also provide other advantages. For example, in some implementations, the resistance of the gate connection within the associated semiconductor may be easily adjusted or tuned with milliohm range precision. Such adjustment may be achieved as a result of the number of electrical contacts made between the gate connection grid (e.g., tungsten or other metal grid) and the gate electrode (e.g., doped polysilicon gate electrode) of the transistor segments. Also, by using the gate connection grid and omitting the gate metal track or metal runner, it may be possible to eliminate the formation of field oxide in the associated semiconductor processing. Such field oxide may be used for electrical isolation of the metal gate track in the current approach. For the purposes of this disclosure, the gate connection grid may also be referred to as an electrically conductive grid or a conductive grid.

[0013] 1A and 1B are schematic diagrams of a semiconductor device 100 including a gate connection grid 130. In this example, the semiconductor device 100 includes an active area 110 and an isolation or termination region 120. In this example, the termination region 120 surrounds the active area 110. That is, the termination region 120 defines the periphery of the active area 110. In some implementations, the termination region 120 can include implants and / or trench structures for terminating electric fields associated with the operation of transistors implemented in the active area 110 of the semiconductor device 100.

[0014] As shown in FIG. 1A, the semiconductor device 100 includes a gate connection grid 130 and a gate pad area 140 disposed within the active area 110. In this example, the gate connection grid 130 includes regularly arranged rows and columns of conductive material and may be implemented with tungsten or other metallic materials. That is, in the implementations described herein, the gate connection grid (conductive grid) may include a matrix of rows and columns of conductive material. In some implementations, the gate connection grid may have other configurations. For example, the rows and columns may be irregularly spaced or segmented. The specific configuration of a gate connection grid, such as the gate connection grid 130, depends on the particular implementation. As shown in FIG. 1A, the gate connection grid 130 may extend across all or nearly all of the active area 110 with an appropriate spacing from the active area 110 for the associated semiconductor processing. The configuration of the gate connection grid 130 allows for a low resistance connection from the gate connection grid 130 to the gate electrodes of the transistor segments. The gate electrodes of the transistor segments are disposed below the gate connection grid 130 of the associated transistors included in the active area 110. For example, as mentioned above, the gate connection grid 130 may be implemented using tungsten, which has approximately 100 times less resistivity than doped polysilicon.

[0015] The semiconductor device 100 also has a gate pad area 140 and a gate pad connection area 140a. As shown in FIG. 1A, the gate pad connection area 140a can have a smaller area than the gate pad area 140. In this example, a gate pad metal 150, which may be part of a signal distribution layer of the semiconductor device 100, may be disposed in the gate pad area 140, as shown in FIG. 1B. The gate pad metal 150 may be electrically coupled to the gate connection grid 130 in the gate pad connection area 140a, for example, using another metal layer, conductive vias, and / or conductive contacts, as in the manner described herein. Thus, in this example, the gate pad metal 150 may be electrically coupled to the gate electrode of the associated transistor of the semiconductor device 100 through the gate connection grid 130 and through electrical connections between the gate connection grid 130 and the gate electrode, and between the gate pad metal 150 and the gate connection grid 130. Also in this example, as shown in FIG. 1B , a source pad metal 160, which may be part of a distribution layer that includes the gate pad metal 150, may be disposed on or over the portions of the active area 110 that are not covered by the gate pad metal 150, with the source pad metal 160 being appropriately spaced from the gate pad metal 150 and the termination region 120.

[0016] In such an approach, since the metal gate tracks are omitted, the entire active area 110 of the semiconductor device 100, appropriately spaced from the termination region 120, can contain active transistor segments. Thus, the area previously used to implement the metal gate tracks can be omitted or used for the active transistor area. Thus, a semiconductor die having a smaller area can be used to create a semiconductor device having a transistor active area equal to the transistor active area of ​​the semiconductor device including the metal gate tracks. That is, the area for implementing the gate metal tracks can be omitted and the corresponding die size can be reduced by the amount of area used to implement such gate metal tracks (e.g., up to 15% of the associated active area). In other words, in some implementations, a gate connection grid, such as the exemplary implementations described herein, can not reduce the active area in the active area of ​​a corresponding semiconductor device, such as the vertical transistors described herein.

[0017] FIG. 2 is a schematic diagram illustrating a cross-sectional view of a vertical transistor segment 200 having a planar gate coupled with a gate connection grid 230. The vertical transistor segment 200 can extend into and out of the page in the third dimension. In some implementations, a plurality of the vertical transistor segments 200 shown in FIG. 2 may be included in a semiconductor die, and the gate connection grid 230 may be used to electrically couple the respective gate electrodes to each other to implement a vertical transistor including a plurality of vertical transistor segments. Depending on the particular configuration of the elements of the vertical transistor segment 200 and / or the doping profile of the elements of the vertical transistor segment 200, the vertical transistor segment 200 can implement a vertical field effect transistor (FET) or an insulated gate bipolar transistor (IGBT). By way of example, the vertical transistor segment 200 is generally described as a vertical FET.

[0018] In the exemplary implementation of FIG. 2, the vertical transistor segment 200 includes a substrate 201, which may be a heavily doped n-type substrate, such as a SiC substrate, or another semiconductor substrate. The vertical transistor segment 200 also includes an epitaxial layer 202, which may be an n-type epitaxial layer with a doping concentration lower than that of the substrate 201. In this exemplary implementation, the substrate 201 may include or implement the drain terminal (or the collector terminal in an IGBT implementation) of the vertical transistor segment 200. The epitaxial layer 202 may implement the drift region of the vertical transistor segment 200. The line 270 in FIG. 2 indicates the direction of majority carrier flow in the vertical transistor segment 200 when in operation and in an on-state. In this example, the majority carrier flow is electrons, but would be holes if the conductivity type of the vertical transistor segment 200 were reversed to switch between n-type and p-type conductivity.

[0019] As also shown in FIG. 2, the vertical transistor segment 200 may include a body region 203, which may be a p-type well region, which may also be referred to as a bulk region. The source regions 204 (or emitter regions in case of IGBT implementations) may be disposed respectively within the body region 203. In this example, the source regions 204 may be heavily doped n-type implants. The vertical transistor segment 200 may further include heavy body regions 205 (or sub-contact regions) disposed respectively within the body region 203. The heavy body regions 205 may be heavily doped p-type implants that facilitate the formation of an ohmic contact from a source signal metal layer (or emitter signal metal layer in case of IGBT implementations) to the body region 203, which may also form an ohmic contact to the source region 204.

[0020] The vertical transistor segment 200 also includes a gate structure 206. The gate structure 206 includes a gate dielectric 206a and a gate electrode 206b. The gate structure 206 extends between and partially over each of the source regions 204, as shown in FIG. 2. In operation, application of an appropriate bias to the gate electrode 206b of the gate structure 206 forms a conductive channel from the source region 204 through the body region 203 to the epitaxial layer 202 (e.g., to the drift region of the vertical transistor segment 200). As mentioned above, the gate structure 206, specifically the gate electrode 206b, can be electrically coupled to a gate connection grid 230, examples of which are described herein. The gate connection grid 230 can also be coupled to the gate structure of additional vertical transistor segments, for example, to the gate structure of a replicated instance of the vertical transistor segment 200.

[0021] In some implementations, instances of the vertical transistor segments 200 may be replicated throughout the active area 110 of the semiconductor device 100, such that all or nearly all of the active area 110 is occupied by replicated vertical transistor segments. In this example, the replicated transistor segments closest to the termination region 120 may be appropriately spaced from the termination region 120. Electrical interconnection between such vertical transistor segments may be implemented using the techniques described herein. For example, the gate structures (gate structures 206) of such transistor segments may be interconnected via a gate connection grid 230, while the body regions 203, source regions 204, and heavy body regions 205 may be interconnected via a conductive metal layer.

[0022] FIG. 3 is a schematic diagram illustrating a cross-sectional view of a vertical transistor segment 300 having a trench gate coupled with a gate connection grid 330. The vertical transistor segment 300 can extend into and out of the page in the third dimension, similar to the vertical transistor segment 200. In some implementations, multiple vertical transistor segments 300 shown in FIG. 3 may be included in a semiconductor die, and the gate connection grid 330 can be used to electrically couple the respective gate electrodes to each other to implement a vertical transistor including multiple vertical transistor segments. Depending on the specific configuration of the elements of the vertical transistor segment 300 and / or the doping profile of the elements of the vertical transistor segment 300, the vertical transistor segment 300 can implement a vertical field effect transistor (FET) or an insulated gate bipolar transistor (IGBT). By way of example, the vertical transistor segment 300 is generally described as a vertical FET.

[0023] In the exemplary implementation of FIG. 3, the vertical transistor segment 300 includes a substrate 301, which may be a heavily doped n-type substrate, such as a SiC substrate, or another semiconductor substrate. The vertical transistor segment 300 also includes an epitaxial layer 302, which may be an n-type epitaxial layer with a doping concentration lower than that of the substrate 301. In this exemplary implementation, the substrate 301 may include or implement the drain terminal (or the collector terminal in an IGBT implementation) of the vertical transistor segment 300. The epitaxial layer 302 may implement the drift region of the vertical transistor segment 300. The line 370 in FIG. 3 indicates the flow direction of majority carriers in the vertical transistor segment 300 when in operation and in an on-state. In this example, the flow of majority carriers is electrons, but would be holes if the conductivity type of the vertical transistor segment 300 were reversed and switched between n-type and p-type conductivity.

[0024] As also shown in FIG. 3, the vertical transistor segment 300 may further include a body region 303, which may be a p-type well region formed in the epitaxial layer 302. The body region 303 may also be referred to as a bulk region. The source regions 304 (or emitter regions in case of IGBT implementations) may be disposed in the body region 303 and adjacent to the trench gate structure 306, respectively. In this example, the source regions 304 may be heavily doped n-type implants. The vertical transistor segment 300 may further include heavy body regions 305 (or sub-contact regions) disposed in the body region 303 and adjacent to the source regions 304, respectively. The heavy body regions 305 may be heavily doped p-type implants that facilitate the formation of an ohmic contact from a source signal metal layer (or emitter signal metal layer in case of IGBT implementations) to the body region 303, and the source signal metal may also form an ohmic contact to the source region 304.

[0025] As mentioned above, the vertical transistor segment 300 also includes a trench gate structure 306. The trench gate structure 306 includes a gate dielectric 306a and a gate electrode 306b, where the gate dielectric 306a lines the trench 306c and 306b is disposed within the gate dielectric 306a. The gate structure 306, e.g., trench 306c, extends through the body region 303 into the n-type portion of the epitaxial layer 302, as shown in FIG. 3. In some implementations, the trench may extend into the substrate 301. In operation, by applying an appropriate bias to the gate electrode 306b of the gate structure 306, a conductive channel is formed from the source region 304 through the body region 303 to the n-type portion of the epitaxial layer 302 (e.g., to the drift region of the vertical transistor segment 300). As mentioned above, the gate structure 306, specifically the gate electrode 306b, may be electrically coupled to the gate connection grid 330, examples of which are described herein. The gate connection grid 330 may also be coupled to gate structures of additional vertical transistor segments, for example, gate structures of replicated instances of the vertical transistor segment 300.

[0026] In some implementations, instances of the vertical transistor segments 300 may be replicated throughout the active area 110 of the semiconductor device 100, such that all or nearly all of the active area 110 is occupied with replicated vertical transistor segments. In this example, the replicated transistor segments closest to the termination region 120 may be appropriately spaced from the termination region 120. Electrical interconnection between such vertical transistor segments may be implemented using the techniques described herein. For example, the gate structures (gate structures 306) of such transistor segments may be interconnected via a gate connection grid 330, while the body regions (body regions 303), source regions 304, and heavy body regions 305 may be interconnected via a conductive metal layer.

[0027] FIG. 4 is an isometric view of a portion of a semiconductor device 400 implementing a vertical transistor including a gate connection grid 430. The portion of the semiconductor device 400 shown in FIG. 4 is provided as an example to illustrate an exemplary configuration of the gate connection grid 430 and the connection of the gate connection grid 430 to the gate structure 406 of the corresponding vertical transistor segment. In the example of FIG. 4, underlying semiconductor regions, such as a substrate and / or epitaxial layers, are not specifically shown. Furthermore, other elements of the semiconductor device 400 are not shown in FIG. 4 so as not to obscure the illustrated structure. Such elements may include dielectric layers, metal layers, vias, etc., which may be used to implement interconnections between the vertical transistor segments of the semiconductor device 400, and may be disposed on the top surface of the portion of the semiconductor device 400 as shown in FIG. 4. Also, in FIG. 4, for illustrative purposes, the body region, the heavy body region, and the source (or emitter) region are each shown as a single region, and are referred to herein as source / body regions 405. The configuration of each source (or emitter) region in source / body region 405 can be similar to the configuration shown in FIG. 2 for source region 204 in body region 203.

[0028] As shown in FIG. 4, the semiconductor device 400 includes a gate structure 406, which may be similar to the gate structure 206 shown in FIG. 2 and may be disposed on a semiconductor region in which the source / body region 405 is disposed. In the semiconductor device 400, a dielectric layer 415 may be disposed on the gate structure 406. The dielectric layer 415 may electrically insulate the gate structure 406 from the gate connection grid 430, except where a contact 430a is formed between the gate structure 406 and the gate connection grid 430. In some implementations, all of the gate structures 406 may be electrically coupled to each other either through the gate connection grid 430 and the contact 430a, and / or through doped polysilicon used to form the gate electrodes of the gate structures 406. In such implementations, the gate structures 406 may function as a single transistor gate for the transistors that include the corresponding transistor segments.

[0029] In this example, the gate connection grid 430 may be disposed on the dielectric layer 415 (e.g., on the top surface of the dielectric layer 415) or in a recess formed in the dielectric layer 415. Such a recess pattern may be formed using photolithography techniques. Also, as shown in FIG. 4, contacts 430a may be formed through the dielectric layer 415 to electrically couple the gate connection grid 430 to one or more of the gate structures 406. As discussed above, in some implementations, the gate connection grid 430 and the contacts 430a may be formed using tungsten and / or other conductive low resistance metal materials. As with other elements of the transistor segments of the semiconductor device 400, the contacts 430a may extend into and out of the page. Furthermore, the contacts 430a between the gate connection grid 430 and the gate structures 406 may be formed in different locations of the gate connection grid 430, for example, at locations located into or out of the page of FIG. 4. Thus, such contacts are not visible in FIG. 4.

[0030] 4, electrical contacts 465 to the source / body regions 405 can be made through the dielectric layer 415, with the contacts 465 extending through openings in the gate-connection grid 430 and spaced apart from the gate-connection grid 430. In the semiconductor device 400, the electrical contacts 465 can extend upward from the illustrated portion of the semiconductor device 400, for example, through the second dielectric layer. For example, the electrical contacts 465 can electrically couple the source / body signal metal layer with the body regions 405, as shown for electrical contact 965 in FIGS. 9E-9G.

[0031] FIG. 5 is a cross-sectional view that illustrates a schematic of a gate electrode 506 and associated bulk / body and source / emitter regions, referred to as source / body regions 505, of a vertical transistor. As with FIG. 4, the underlying semiconductor regions (e.g., substrate and / or epitaxial layers) are not shown in the figure. Also, as with source / body regions 405, body regions 203, source regions 204, and heavy body regions 205 are arranged with gate structure 206 of vertical transistor segment 200, source / body regions 505 in FIG. 5 may be similarly arranged with gate electrode 506. The cross-sectional view of FIG. 5 also illustrates schematic cross-sectional views of the gate electrodes and source / body regions of the exemplary implementations of FIGS. 6-8 along section lines 5-5 shown in each of these figures, each of which is described below.

[0032] In particular, Figures 6-8 are schematic diagrams illustrating various configurations of vertical transistor planar gate electrodes and associated bulk / body and source / emitter regions that may be included in a vertical transistor. In each of Figures 6-8, similar to Figures 4 and 5, the body region 203, source region 204, and heavy body region 205 of 200 are shown disposed relative to the gate electrode 206, and similarly, the source / body regions are shown that may be disposed with the corresponding gate electrode.

[0033] For example, FIG. 6 illustrates a portion of the gate electrode 606 (a waffle-shaped gate electrode) that includes an opening through which the source / body region 605 is exposed. The gate electrode 606 of FIG. 6 may be referred to as a fully connected gate electrode because the gate electrode 606 may be formed from a continuous doped polysilicon feature. Electrical contact to the source / body region 605 may be made through the opening in the gate electrode 606. Section line 5-5 in FIG. 6 illustrates a portion of the source / body region 605 and the gate electrode 606 that corresponds to the cross-sectional view of FIG. 5. Also illustrated in FIG. 6 is a portion of the gate connection grid 630 and a contact 630a from the gate connection grid 630 to the gate electrode 606. Thus, the segments of the gate electrode 606 may be electrically coupled to each other through both the doped polysilicon of the gate electrode 606 and the gate connection grid 630 in this exemplary implementation.

[0034] FIG. 7 illustrates a gate electrode 706 of a portion of a vertical transistor. As shown in FIG. 7, the gate electrode 706 is generally arranged in stripes, with some adjacent stripes interconnected. That is, some adjacent stripes of the gate electrode 706 in FIG. 7 can be formed using continuous doped polysilicon features, while other adjacent stripes of the gate electrode 706 can be formed as independent doped polysilicon features. As shown in FIG. 7, the source / body regions 705 are exposed through the spaces between the adjacent stripes, and electrical contacts to the source / body regions 605 can be made along the spaces between the gate electrodes 706. Similar to section line 5-5 in FIG. 6, section line 5-5 in FIG. 7 illustrates portions of the source / body regions 705 and the gate electrode 706 that correspond to the cross-sectional view of FIG. 5. Although not specifically shown in FIG. 7, the gate electrode 706 can be coupled to a gate connection grid, for example, using techniques described herein.

[0035] 8 illustrates a portion of a gate electrode 806 that includes fully connected hexagonal polysilicon features, e.g., interconnected hexagons, with hexagonal openings through which source / body regions 805 are exposed. Electrical contact to source / body regions 805 can be made through the openings in gate electrode 806. Section line 5-5 in FIG. 8 illustrates portions of source / body regions 805 and gate electrode 806 that correspond to the cross-sectional view of FIG.

[0036] 9A-9G are cross-sectional views that are schematic illustrations of operations of a manufacturing process for fabricating a vertical transistor having a planar gate electrode. In FIGS. 9A-9G, similar to FIGS. 4 and 5, the underlying semiconductor region is not specifically shown. Also, the sequence of processing operations illustrated by FIGS. 9A-9G may be referred to as back-of-line (BOL) processing operations. That is, the processing operations of FIGS. 9A-9G show the interconnection of segments of a vertical transistor disposed within a semiconductor region, and the processing operations for fabricating the transistor segments may be referred to as front-of-line (FOL) processing. Specifically, with reference to FIG. 9A, the source / body regions 905 and corresponding gate electrodes 906 (as discussed above with respect to FIGS. 4-8) are already present, for example as a result of FOL processing operations. In some implementations, the transistors of FIGS. 9A-9G may be implemented using transistor segments, such as vertical transistor segment 200. The transistor segment 200 is included in an active area, such as active area 110 of semiconductor device 100. For example, as discussed above with respect to FIG. 2, the gate electrode 906 may have an underlying gate dielectric layer, not specifically shown in FIGS. 9A-9G.

[0037] With reference to FIG. 9A, the BOL process may begin by first including forming a dielectric layer 915 on the vertical transistor segments created during the FOL process, e.g., forming a dielectric layer 915. The dielectric layer 915 (as well as other dielectric layers discussed herein) may include a glass material, such as borophosphosilicate glass (BPSG), a deposited oxide, or other dielectric material. As shown in FIG. 9B, after forming the dielectric layer 915, at least one electrical contact 930a to one or more of the corresponding gate electrodes 906 may be formed through the dielectric layer 915. Although only a single electrical contact 930a is visible in FIG. 9B (and related figures), as discussed above, other electrical contacts 930a to the gate electrodes 906 may be made elsewhere within the associated transistor device, e.g., either further into or further from the page in the third dimension, or to the side of the view of FIG. 9B, e.g., in transistor segments implemented to the left and / or right of the depicted segment.

[0038] 9C, after forming the electrical contacts 930a and other such contacts, a gate connection grid 930 may be formed on the dielectric layer 915 and associated electrical contacts, such as the electrical contacts 930a, to electrically couple the gate connection grid 930 to the gate electrode 906. Moving to FIG. 9D, a dielectric layer 935 may be formed on the gate connection grid 930 and the dielectric layer 915. In some implementations, such as this example, the dielectric layer 935 may be planarized (as it may be planarized along with the dielectric 915 prior to forming the electrical contacts 930a and the gate connection grid 930). Such planarization may include a chemical mechanical polishing operation.

[0039] 9E, after planarizing the dielectric layer 935, electrical contacts 930b to the gate connection grid 930 and electrical contacts 965 to the body regions 905 can be formed. Again, while only a single electrical contact 930b and electrical contact 965 are shown in FIG. 9E and one or more associated representations, other such electrical contacts can be formed at other locations within the associated transistor device, for example, either further into or further from the page in the third dimension, or to the side of the representation in FIG. 9E. In some implementations, the contacts can be formed using the same photolithography mask, or can be formed using different photolithography masks. In an implementation, the order in which the electrical contacts 930b and electrical contacts 965 are formed depends on the particular processing implementation.

[0040] As shown in FIG. 9F, after forming the contacts 930b and 965, a signal metal layer (first signal metal layer) can be formed that includes a first portion 951 electrically coupled to the electrical contact 930b, and can also be electrically coupled to other such contacts to electrically couple the first portion 951 of the first signal metal layer to the gate connection grid 930. Thus, the first portion 951 is electrically coupled to the gate electrode 906 via the electrical contact 930b, the gate connection grid 930, and the electrical contact 930a. The first signal metal layer can also include a second portion 961 electrically coupled to the electrical contact 965, and can also be electrically coupled to other such contacts. Thus, the second portion 961 is electrically coupled to the source / body region 905 via the electrical contact 965.

[0041] 9G, after forming the first signal metal layer, a dielectric layer 945 can be formed on the first signal metal layer and the dielectric layer 935, and a second signal metal layer can be formed on the first signal metal layer and the dielectric layer 945. As shown in FIG. 9G, the second signal metal layer includes a first portion 950 electrically coupled to the first signal metal layer first portion 951. In this example, the second signal metal layer first portion 950 is electrically coupled to the first signal metal layer first portion 951 through a conductive via 950a, although other approaches are possible. For example, the second signal metal layer first portion 950 can be disposed at least in part directly on the first signal metal layer first portion 951. In this example, the second signal metal layer first portion 950 can be referred to as a gate pad metal, and is electrically coupled to the gate electrode 906 through an interconnect structure including the gate connection grid 930, as shown in FIG. 9G and described above.

[0042] 9G, the second signal metal layer includes a second portion 960 electrically coupled to the first portion 961 of the first signal metal layer. In this example, the second portion 960 of the second signal metal layer is electrically coupled to the second portion 961 of the first signal metal layer as a result of being at least partially disposed directly on the second portion 961 of the first signal metal layer. In this example, the second portion 960 of the second signal metal layer may be referred to as a source pad metal (or emitter pad metal) and is electrically coupled to the body region 905 via the interconnect structure shown in FIG. 9G and described above.

[0043] In FIG. 9G, a second replicated transistor cell fabricated during FOL processing is shown to the left or side of the cell shown in FIGS. 9A-9F. FIG. 9F thus illustrates the replication of the vertical transistor cell in the active area of ​​an associated semiconductor device. As shown in FIG. 9G, the replicated cell is not shown as including a contact 930b to the gate signal metal since the portion of the gate connection grid 930 in the replicated cell is disposed below the source metal, e.g., the second portion 961 of the first signal metal layer. However, as described herein, the gate connection grid 930 can extend across the associated active area, as shown in FIG. 1, so that the gate electrode 906 included in the replicated cell can be electrically coupled to the first portion 951 of the first signal metal layer through the gate connection grid 930.

[0044] 9G, the first portion 951 of the first signal metal layer can extend under the first portion 950 of the second signal metal layer, which can increase the amount of source signal metal (or emitter signal) metal and increase the current carrying capability of the associated transistor. As mentioned above, the second signal metal layer (including the first portion 950 and the second portion 960) can be referred to as a signal distribution layer or redistribution layer.

[0045] FIG. 10 is a cross-sectional view that shows a schematic of a vertical device having a trench gate electrode that can be fabricated using a BOL process similar to that of FIGS. 9A-9G. The process of fabricating the vertical transistor of FIG. 10 is similar to that of FIGS. 9A-9G, so the details of the process will not be described again in detail here. Instead, the differences in the structure of the transistor of FIG. 10 compared to that of FIG. 9G are described below. Briefly, the transistor of FIG. 10 includes a source / body region 1005 (or emitter / body region), a trench gate structure 1006, a dielectric layer 1015, a gate connection grid 1030, a contact 1030a, a contact 1030b, a contact 1065, a first portion 1051 of a first signal metal layer, a second portion 1061 of a first signal metal layer, a first portion of a second signal metal layer 1050, a conductive via 1050a, and a second portion 1060 of a second signal metal layer 1061. The transistor shown in Figure 10 also includes other elements similar to the transistor of Figure 9G, and these elements are not specifically referenced in Figure 10. Additionally, elements referenced with 1000 series numbers in Figure 10 correspond to similar elements referenced with 900 series numbers in Figure 9, respectively.

[0046] Referring to Figure 10 and further to Figure 9G, the gate structure 1006 of Figure 10 is a trench gate structure as compared to the planar gate structure including the gate electrode 906 shown in Figures 9A-9G. Also, in Figure 10, the dielectric layer 1015 has a flat upper surface which may be the result of the implementation of the trench gate structure 1006 and / or planarization of the dielectric layer 1015. Thus, the gate connecting grid 1030 is flat as compared to the conformal shape of the gate connecting grid 930 to the surface of the dielectric layer 915.

[0047] As also shown in Fig. 10, the semiconductor substrate or semiconductor region on which the semiconductor device 1000 is implemented may be arranged along a plane P. In the example of Fig. 10, at least a portion of the gate connection grid 1030 and a portion of the active area A (e.g., a portion of each of one or more segments of a vertical transistor) may be arranged along a line L perpendicular to the plane P. That is, the conductors included in the gate connection grid 1030 may be arranged along the line L directly above the active parts of the vertical transistors of the semiconductor device 1000.

[0048] In a general aspect, the semiconductor device may include a vertical transistor having a first transistor segment and a second transistor segment. The first transistor segment may include a first body region, a first source region, and a first gate electrode. The second transistor segment may include a second body region, a second source region, and a second gate electrode. The semiconductor device may further include a first dielectric layer disposed on the vertical transistor and a conductive grid disposed on the first dielectric layer. The conductive grid may be electrically coupled to the first gate electrode and the second gate electrode using at least a first conductive contact formed through the first dielectric layer. The semiconductor device may also include a second dielectric layer disposed on the conductive grid and the first dielectric layer, and a conductive metal layer disposed on the second dielectric layer. The conductive metal layer may include a first portion and a second portion. The first portion may be electrically coupled to the first body region, the first source region, the second body region, and the second source region using at least a second conductive contact formed through the first dielectric layer and the second dielectric layer. The second portion may be electrically coupled to the conductive grid using at least a third conductive contact formed through the second dielectric layer.

[0049] Implementations can include one or more of the following features. For example, the first gate electrode can be a first planar gate electrode and the second gate electrode can be a second planar gate electrode. The first gate electrode can be a first trench gate electrode and the second gate electrode can be a second trench gate electrode.

[0050] The vertical transistor may be included in a semiconductor substrate. The semiconductor substrate may be arranged in a plane. At least a portion of the gate connection grid and a portion of the first segment of the vertical transistor may be arranged along a line perpendicular to the plane.

[0051] The metal layer may be a first metal layer, and the semiconductor device may include a third dielectric layer disposed on the first metal layer and the second dielectric layer, and a second metal layer disposed on the third dielectric layer. The second metal layer may include a first portion electrically coupled to the first portion of the first metal layer through the third dielectric layer. The second metal layer may include a second portion electrically coupled to the second portion of the first metal layer through the third dielectric layer. The first portion of the second metal layer may be disposed on the first portion of the first metal layer. The second portion of the second metal layer may be electrically coupled to the second portion of the first metal layer using at least one conductive via formed through the third dielectric layer.

[0052] The conductive grid and the first conductive contact may comprise tungsten.The first gate electrode and the second gate electrode may comprise doped polysilicon.

[0053] The vertical transistor may be included in a silicon carbide (SiC) semiconductor region. The first body region and the second body region may be of a first conductivity type and may be disposed within the SiC semiconductor region. The SiC semiconductor region, the first source region, and the second source region may be of a second conductivity type opposite the first conductivity type. The first source region may be disposed within the first body region, and the second source region may be disposed within the second body region.

[0054] The vertical transistor may include a vertical field effect transistor (FET). The SiC semiconductor region may include a drift region of the vertical FET and a drain region of the vertical FET.

[0055] The vertical transistor may include a vertical insulated gate bipolar transistor (IGBT). The first source region may be a first emitter region of the vertical IGBT, and the second source region may be a second emitter region of the vertical IGBT. The SiC semiconductor region may include a drift region of the vertical IGBT and a collector region of the vertical IGBT.

[0056] The first gate electrode can be a first portion of a doped polysilicon gate electrode and the second gate electrode can be a second portion of a doped polysilicon gate electrode. The first gate electrode can be a first doped polysilicon gate electrode and the second gate electrode can be a second doped polysilicon gate electrode. The first doped polysilicon gate electrode can be electrically coupled to the second doped polysilicon gate electrode via the conductive grid and respective electrical contacts to the conductive grid.

[0057] The at least a first conductive contact formed through the first dielectric layer can include a first plurality of conductive contacts formed through the first dielectric layer. The at least a second conductive contact formed through the first and second dielectric layers can include a second plurality of conductive contacts formed through the first and second dielectric layers. The at least a third conductive contact formed through the second dielectric layer can include a third plurality of conductive contacts formed through the second dielectric layer.

[0058] In another general aspect, the semiconductor device can include a semiconductor region, an active region disposed within the semiconductor region, and an isolation region disposed within the semiconductor region. The isolation region can at least partially surround the active region. The semiconductor device can also include a plurality of vertical transistor segments disposed within the active region. The plurality of vertical transistor segments can include respective gate electrodes. The semiconductor device can also include a first dielectric layer disposed on the active region, and a conductive grid disposed on the first dielectric layer. The conductive grid can be electrically coupled to the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric layer. The semiconductor device can further include a second dielectric layer disposed on the conductive grid and the first dielectric layer, and a conductive metal layer disposed on the second dielectric layer. The conductive metal layer can include portions electrically coupled to the respective gate electrodes through the conductive grid using at least one conductive contact to the conductive grid formed through the second dielectric layer.

[0059] Implementations can include one or more of the following features. For example, the metal layer can be a first metal layer. The semiconductor device can include a third dielectric layer disposed on the first metal layer and the second dielectric layer, and the second metal layer can include a portion electrically coupled to a portion of the first metal layer through the third dielectric layer.

[0060] The respective gate electrodes may include respective planar gate electrodes. The respective gate electrodes may include respective trench gate electrodes. The plurality of vertical transistor segments may include one of a plurality of vertical field effect transistor segments or a plurality of vertical insulated gate bipolar transistor segments. The gate connection grid may not require reducing an active area of ​​the active region.

[0061] In another general aspect, a method of fabricating a semiconductor device can include forming a vertical transistor in a semiconductor region. The vertical transistor can include a first transistor segment and a second transistor segment. The first transistor segment can have a first body region, a first source region, and a first gate electrode. The second transistor segment can have a second body region, a second source region, and a second gate electrode. The method can further include forming a first dielectric layer on the vertical transistor and forming a conductive grid on the first dielectric layer. The conductive grid can be electrically coupled to the first gate electrode and the second gate electrode using at least a first conductive contact formed through the first dielectric layer. The method can also include forming a second dielectric layer on the conductive grid and the first dielectric layer, and forming a conductive metal layer on the second dielectric layer. The conductive metal layer can include a first portion that can be electrically coupled to the first body region, the first source region, the second body region, and the second source region using at least a second conductive contact formed through the first dielectric layer and the second dielectric layer. The conductive metal layer can also include a second portion that can be electrically coupled to the conductive grid using at least a third conductive contact formed through the second dielectric layer.

[0062] Implementations can include one or more of the following features. For example, the metal layer can be a first metal layer. The method can include forming a third dielectric layer on the first metal layer and the second dielectric layer, and forming a second metal layer on the third dielectric layer. The second metal layer can include a first portion electrically coupled to the first portion of the first metal layer through the third dielectric layer and a second portion electrically coupled to the second portion of the first metal layer through the third dielectric layer.

[0063] For purposes of this disclosure, when an element such as a layer, region, or substrate is referred to as being on, disposed on, connected to, electrically connected to, bonded to, or electrically coupled to another element, it will be understood that the element may be directly on, connected to, or bonded to the other element, or there may be one or more intervening elements. On the other hand, when an element is referred to as being directly on, disposed on, connected to, or bonded to another element or layer, there are no intervening elements or layers. Although the terms directly on, directly connected, or directly bonded may not be used throughout the detailed description of the present invention, elements illustrated as being directly on, directly connected, or directly bonded may be referred to as such. The claims of this application may be amended to recite the exemplary relationships described or illustrated herein.

[0064] As used herein, the singular can include the plural unless the context clearly indicates otherwise in a particular instance. Spatially relative terms (e.g., over, above, above, below, just below, below, under, etc.) are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. In some implementations, the relative terms above and below can include vertically above and vertically below, respectively. In some implementations, the term adjacent can include laterally adjacent, vertically adjacent, or horizontally adjacent.

[0065] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or the like.

[0066] Although several features of various exemplary implementations have been described as described herein, those skilled in the art will find many variations, substitutions, changes, and equivalents thereto. It will therefore be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It will be understood that these are presented by way of example only, and not by way of limitation, and that various changes in form and details may be made. Any part of the apparatus and / or method described herein may be combined in any combination, except in mutually exclusive combinations. The implementations described herein may include various combinations and / or subcombinations of the functions, components, and / or features of the different implementations described.

Claims

1. 1. A semiconductor device comprising: A vertical transistor, a first transistor segment having a first body region, a first source region, and a first gate electrode; a second transistor segment having a second body region, a second source region, and a second gate electrode; a first dielectric layer disposed over the vertical transistor; a conductive grid disposed on the first dielectric layer, the conductive grid being electrically coupled to the first gate electrode and the second gate electrode using at least a first conductive contact formed through the first dielectric layer; a second dielectric layer disposed on the conductive grid and the first dielectric layer; a metal layer disposed on the second dielectric layer, a first portion electrically coupled to the first body region, the first source region, the second body region, and the second source region using at least a second conductive contact formed through the first dielectric layer and the second dielectric layer; a second portion electrically coupled to the conductive grid using at least a third conductive contact formed through the second dielectric layer; and A semiconductor device comprising:

2. the metal layer is a first metal layer, and the semiconductor device comprises: a third dielectric layer disposed on the first metal layer and the second dielectric layer; a second metal layer disposed on the third dielectric layer, a first portion electrically coupled to the first portion of the first metal layer through the third dielectric layer; a second portion electrically coupled to the second portion of the first metal layer through the third dielectric layer; Further comprising: the first portion of the second metal layer is disposed on the first portion of the first metal layer; the second portion of the second metal layer is electrically coupled to the second portion of the first metal layer using at least one conductive via formed through the third dielectric layer. The semiconductor device of claim 1 .

3. the at least a first conductive contact formed through the first dielectric layer is included in a first plurality of conductive contacts formed through the first dielectric layer; the at least second conductive contact formed through the first dielectric layer and the second dielectric layer is included in a second plurality of conductive contacts formed through the first dielectric layer and the second dielectric layer; the at least third conductive contact formed through the second dielectric layer is included in a third plurality of conductive contacts formed through the second dielectric layer. The semiconductor device of claim 1 .

4. 1. A semiconductor device comprising: A semiconductor region; an active region disposed within the semiconductor region; an isolation region disposed within the semiconductor region and at least partially surrounding the active region; a plurality of vertical transistor segments disposed in the active region, the plurality of vertical transistor segments including respective gate electrodes; a first dielectric layer disposed over the active region; a conductive grid disposed on the first dielectric layer, the conductive grid being electrically coupled to each of the gate electrodes using a plurality of conductive contacts formed through the first dielectric layer; a second dielectric layer disposed on the conductive grid and the first dielectric layer; a metal layer disposed on the second dielectric layer, the metal layer including a portion electrically coupled to the respective gate electrode through the conductive grid using at least one conductive contact to the conductive grid formed through the second dielectric layer; A semiconductor device comprising:

5. The semiconductor device of claim 4 , wherein the conductive grid does not reduce an active area of ​​the active region.

6. 1. A method of fabricating a semiconductor device, the method comprising: Forming a vertical transistor in a semiconductor region, the vertical transistor comprising: a first transistor segment having a first body region, a first source region, and a first gate electrode; forming a vertical transistor including a second transistor segment having a second body region, a second source region, and a second gate electrode; forming a first dielectric layer over the vertical transistor; forming a conductive grid on the first dielectric layer, the conductive grid being electrically coupled to the first gate electrode and the second gate electrode using at least a first conductive contact formed through the first dielectric layer; forming a second dielectric layer over the conductive grid and the first dielectric layer; forming a metal layer on the second dielectric layer, the metal layer comprising: a first portion electrically coupled to the first body region, the first source region, the second body region, and the second source region using at least a second conductive contact formed through the first dielectric layer and the second dielectric layer; a second portion electrically coupled to the conductive grid using at least a third conductive contact formed through the second dielectric layer; and forming a metal layer comprising: The method includes:

7. The metal layer is a first metal layer, and the method includes: forming a third dielectric layer on the first metal layer and the second dielectric layer; forming a second metal layer on the third dielectric layer; and wherein the second metal layer comprises: a first portion electrically coupled to the first portion of the first metal layer through the third dielectric layer; a second portion electrically coupled to the second portion of the first metal layer through the third dielectric layer; The method of claim 6, comprising:

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