Method for filling recessed features in semiconductor devices with low resistivity metal - Patents.com
Patent Information
- Application Number
- JP2023557010
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-03-16
- Filing Date
- 2022-03-07
- Publication Date
- 2025-02-26
- Estimated Expiration
- 2042-03-07
AI Technical Summary
Existing methods for filling recessed features in semiconductor devices with metal face issues of insufficient metal nucleation on dielectric materials, leading to high electrical resistance and void formation due to the use of liners like TiN or TaN, which reduce the amount of metal deposition.
A method involving the formation of a nucleation-promoting layer on the sidewalls of recessed features, followed by vapor deposition of low resistivity metals like Ru, Co, or W, without the need for conventional liners, ensuring void-free filling.
This approach allows for complete and void-free filling of recessed features with low resistivity metals, reducing electrical resistance and enhancing the overall performance of semiconductor devices.
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Abstract
Description
[Technical field]
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of the filing date of U.S. Provisional Patent Application No. 63 / 161,909, filed March 16, 2021, the entirety of which is incorporated herein by reference.
[0002] The present invention relates to semiconductor processing and semiconductor devices, and more particularly to a method for filling recessed features in semiconductor devices with a low resistivity metal. [Background technology]
[0003] Semiconductor devices contain filled recessed features, including trenches and vias formed in dielectric materials such as interlayer dielectrics (ILDs). During metal chemical vapor deposition (CVD), metal nucleation on the dielectric material is typically poor. This problem can be addressed by depositing a liner, such as TiN or TaN, having a thickness of 1-1.5 nm in the recessed feature prior to metal CVD. While the liner provides a good nucleation surface and good adhesion to the metal, the presence of the liner also reduces the amount of metal that can be deposited in the recessed feature, resulting in a high electrical resistance layer at the bottom of the recessed feature. Thus, new methods for void-free metal filling of recessed features that further reduce the liner thickness or do not require the use of a liner are needed. Summary of the Invention [Means for solving the problem]
[0004] An embodiment of the present invention describes a method for filling recessed features of a semiconductor device with a low resistivity metal. According to one embodiment, the method includes providing a patterned substrate including a recessed feature formed in a first layer and a second layer exposed in the recessed feature, forming a nucleation promotion layer on sidewalls of the first layer in the recessed feature, and depositing a metal layer in the recessed feature by vapor deposition, where the metal layer is deposited on the second layer and on the nucleation promotion layer.
[0005] According to another embodiment, the method includes providing a patterned substrate including a recessed feature formed in a first layer and a second layer exposed in the recessed feature, selectively forming an initial metal layer on the second layer in the recessed feature, then forming a nucleation promotion layer on sidewalls of the first layer in the recessed feature, and depositing a metal layer in the recessed feature by vapor deposition, wherein the metal layer is deposited on the initial metal layer and on the nucleation promotion layer.
[0006] According to another embodiment, the method includes providing a patterned substrate including a recessed feature formed in a dielectric material and a second layer exposed in the recessed feature; depositing a contact metal on the dielectric material and on the second layer, where the contact metal reacts to form a metal oxide layer on the dielectric material; removing the metal oxide layer from sidewalls of the dielectric material in the recessed feature, forming a nucleation promotion layer on the sidewalls; and depositing a metal layer in the recessed feature by vapor deposition, where the metal layer is deposited on the contact metal and on the nucleation promotion layer.
[0007] A more detailed understanding of the present invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description, when considered in conjunction with the accompanying drawings, in which: [Brief description of the drawings]
[0008] [Figure 1A]1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 1B] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 1C] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 1D] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 2A] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 2B] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 2C] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 2D] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 2E] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 3A] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 3B] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 3C] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 3D] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 3E] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 3F] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 4A] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 4B] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 4C] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 4D] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 4E] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Figure 4F] 1A-1C are schematic diagrams illustrating a method of metal formation in recessed features according to one embodiment of the present invention; [Diagram 5] 1 shows a transmission electron microscope (TEM) image of Ru metal filling of recessed features in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] An embodiment of the present invention describes a method for depositing a low resistivity metal in recessed features of a semiconductor device. The recessed features may include simple and complex features found in semiconductor devices, such as vias, trenches, and combinations thereof. The method provides good void-free metal filling of fine recessed features that are difficult to fill without forming voids during metal filling. Using the method, the recessed features may be partially or completely filled with a low resistivity metal. The deposited low resistivity metal may include, for example, Ru metal, Co metal, W metal, or combinations thereof. However, other metals may also be used.
[0010] 1A-1D show a schematic of a method of metal formation in a recessed feature according to an embodiment of the present invention. Patterned substrate 1 includes a field region 101 around a recessed feature 110 (e.g., a via hole) formed in a first layer 100. In one example, recessed feature 110 may be formed by anisotropic dry etching using an overlying patterned mask (not shown). Recessed feature 110 includes a second layer 102 having sidewalls 103 and an exposed surface 104 at the bottom of recessed feature 110. Patterned substrate 1 further includes an etch stop layer 109.
[0011] According to one embodiment, the first layer 100 includes a dielectric material and the second layer 102 includes a metal layer. The dielectric material may include any other suitable dielectric material including, for example, SiO2, SiN, SiCO, SiCN, fluorinated silicon glass (FSG), or other low-k materials, carbon-doped oxides, polymers, SiCOH-containing low-k materials, non-porous low-k materials, porous low-k materials, CVD low-k materials, spin-on dielectric (SOD) low-k materials, or high-k materials. In some examples, the width (critical dimension (CD)) of the recessed feature 110 may be about 10 nm to about 100 nm, about 10 nm to about 20 nm, about 20 nm to about 90, or about 40 nm to about 80 nm. In some examples, the depth of the recessed feature 110 may be about 40 nm to about 200 nm, or about 50 nm to about 150 nm. However, the method may also be used for void-free metal filling of recessed features with smaller or larger CDs. In some examples, the recessed feature 110 may have an aspect ratio (depth / width) of about 2 to about 20 or about 4 to about 6. The second layer 102 may include a low resistivity metal such as Cu metal, Ru metal, Co metal, W metal, or combinations thereof. In one example, the second layer 102 may include two or more stacked metal layers. Examples of stacked metal layers include Co metal on Cu metal (Co / Cu) and Ru metal on Cu metal (Ru / Cu). In one example, the first layer 100 contains SiO2, and the second layer 102 includes a W metal layer, a structure commonly found in the middle-of-the-line (MOL) region of semiconductor devices.
[0012] According to one embodiment, the method further includes a cleaning step of exposing the patterned substrate 1 to a H2-containing gas to chemically reduce the exposed surface 104 of the second layer 102 and remove any remaining etch residues from the recessed features 110. For example, the H2-containing gas can consist of H2 gas or can contain H2 gas and Ar gas. The cleaning step can be performed with or without plasma excitation of the H2-containing gas. In one example, the cleaning step includes exposing the patterned substrate 1 to H2 gas and Ar gas at a substrate temperature of about 250° C. to about 400° C. and a gas pressure of about 250 mTorr to about 7 Torr for a period of about 30 seconds to about 60 seconds. In some examples, the second layer 102 contains Cu metal or W metal and the cleaning step includes removing CuO x Or WO x The surface species are chemically reduced to the corresponding elemental metal, thereby reducing the electrical resistance in the final device.
[0013] The method further comprises forming a nucleation promotion layer on the patterned substrate 1. The nucleation promotion layer converts the otherwise poor growth surface on the sidewalls 103 and field regions 101 of the first layer 100 into a good growth surface for subsequent metal deposition by vapor deposition. This has the effect that metal deposition proceeds effectively both on the nucleation promotion layer and on the second layer 102 in the recessed features 110. This allows for void-free metal filling of the recessed features 110. The nucleation promotion layer is thinner than conventional deposition liners of TiN and TaN, and therefore the amount of metal that can be deposited in the recessed features is higher when using a nucleation promotion layer. Furthermore, the absence of a liner avoids the formation of a high electrical resistance layer at the bottom of the recessed features 110.
[0014] According to one embodiment, the nucleation promotion layer is formed by first forming a nucleation inhibition layer and then converting the nucleation inhibition layer into a nucleation promotion layer. Forming the nucleation promotion layer may include treating the patterned substrate 1 with a reactive gas that forms a nucleation inhibition layer 120 on the sidewalls 103 and on the field regions 101 of the first layer 100. This is shown diagrammatically in FIG. 1B. The reactive gas contains a surface modifier that has properties that prevent the deposition of metal on the first layer 100, while the second layer 102 is not modified.
[0015] According to one embodiment, the reaction gas contains molecules capable of forming a self-assembled monolayer (SAM) on the substrate. A SAM is a molecular assembly that spontaneously forms on the substrate surface by adsorption and organizes into more or less large ordered domains. A SAM may include molecules with a head group, a tail group and a functional end group, and the SAM is generated by chemisorption of the head group onto the substrate from the gas phase at room temperature or above room temperature, followed by slow organization of the tail group. Initially, when the molecular density on the surface is low, the adsorbate molecules either form a disordered molecular mass or form an ordered two-dimensional "lying phase", and when the molecular coverage increases, they start to form a three-dimensional crystalline or semi-crystalline structure on the substrate surface over a period of minutes to hours. The head group assembles on the substrate, while the end group assembles away from the substrate. According to one embodiment, the head group of the molecules that form the SAM may include thiols, silanes or phosphonates. Examples of silanes include molecules containing C, H, Cl, F and Si atoms or C, H, Cl and Si atoms. Non-limiting examples of molecules include perfluorodecyltrichlorosilane (CF3(CF2)7CH2CH2SiCl3), perfluorodecanethiol (CF3(CF2)7CH2CH2SH), chlorodecyldimethylsilane (CH3(CH2)8CH2Si(CH3)2Cl), and tert-butyl(chloro)dimethylsilane ((CH3)3CSi(CH3)2Cl)).
[0016] According to some embodiments of the present invention, the reaction gas may contain a silicon-containing gas including alkylamine silane, alkyl silane, alkoxy silane, alkyl alkoxy silane, alkyl siloxane, alkoxy siloxane, alkyl alkoxy siloxane, aryl silane, acyl silane, aryl siloxane, acyl siloxane, silazane, or any combination thereof. According to some embodiments of the present invention, the reaction gas may be selected from dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA), bis(dimethylamino)dimethylsilane (BDMADMS) and other alkylamine silanes. According to other embodiments, the reaction gas may be selected from N,O bistrimethylsilyl trifluoroacetamide (BSTFA) and trimethylsilylpyrrole (TMS-pyrrole).
[0017] According to some embodiments of the present invention, the reaction gas may contain a silazane compound. Silazanes are saturated silicon-nitrogen hydrides. They are similar in structure to siloxanes with --NH- instead of --O--. The organosilazane precursor may further contain at least one alkyl group bonded to the Si atom. The alkyl group may be, for example, a methyl group, an ethyl group, a propyl group, or a butyl group, or a combination thereof. Furthermore, the alkyl group may be a cyclic hydrocarbon group, such as a phenyl group. Additionally, the alkyl group may be a vinyl group. Disilazanes are compounds having 1-6 methyl groups or 1-6 ethyl groups bonded to the silicon atom, or disilazane molecules having a combination of methyl and ethyl groups bonded to the silicon atom. Examples of disilazanes include hexamethyldisilazane (HMDS) and trimethyldisilazane (TMDS).
[0018] In one example, the first layer 100 includes a SiO2 layer, and the reactant gas containing TMSDMA reacts with hydrophilic hydroxyl groups (-OH) on the SiO2 layer to form a nucleation inhibition layer 120 containing hydrophobic -SiMe3 groups on the SiO2 layer.
[0019] The method further includes treating the patterned substrate 1 with plasma excited H2 gas to modify the nucleation inhibition layer 120. In one example, the H2 gas can further include Ar gas. In the case of -SiMe3 groups on the SiO2 layer, exposure to plasma excited H2 gas removes one or more of the Me groups, thereby forming -SiMe x It is speculated that this creates new adsorption sites near or at the groups (x<3).
[0020] Thereafter, the method further includes treating the patterned substrate 1 with H2O vapor, which adds hydroxyl groups (-OH) to the modified nucleation inhibition layer, thereby forming a nucleation promotion layer 122, as shown diagrammatically in FIG. 1C. In one example, the H2O vapor exposure may be performed at a substrate temperature of about 160° C. The -SiMe on the SiO2 layer x In the case of the group, exposure to H2O vapor is believed to form -SiCOH or -SiCOOH surface species on the SiO2 layer.
[0021] After exposure to HO vapor, * A radical cleaning step may optionally be performed to remove residual H2O from the patterned substrate 1 and the process chamber. In one example, the cleaning step may be performed at a substrate temperature of about 400°C.
[0022] 1B and 1C, according to another embodiment, the nucleation promotion layer 122 may be formed by treating the nucleation inhibition layer 120 with a plasma excited nitrogen-containing gas that modifies the sidewalls 103 of the first layer 100 in the recessed feature 110. Non-limiting examples of nitrogen-containing gases include NH3 gas, N2 gas, or N2 gas and H2 gas. The nitrogen-containing gas may further include a chemically inert gas such as Ar.
[0023] After forming the nucleation promotion layer 122, the method further includes depositing a metal layer 106 in the recessed feature 110 by vapor deposition, the metal layer 106 being deposited on the second layer 102 and on the nucleation promotion layer 122. According to one embodiment, the recessed feature 110 may be completely filled without voids by the metal layer 106, as shown generally in FIG. 1D. In one example, the metallization layer on the field region 101 may be removed by etching or chemical mechanical polishing (CMP).
[0024] The metal layer 106 may be selected from the group consisting of, for example, Ru metal, Co metal, and W metal. According to one embodiment of the present invention, Ru metal may be deposited by CVD or atomic layer deposition (ALD). An example of a Ru-containing precursor is triruthenium dodecacarbonyl (Ru(CO) 12 ), (2,4-dimethylpentadienyl)(ethylcyclopentadienyl)ruthenium (Ru(DMPD)(EtCp)), bis(2,4-dimethylpentadienyl)ruthenium (Ru(DMPD)2), 4-dimethylpentadienyl)(methylcyclopentadienyl)ruthenium (Ru(DMPD)(MeCp)), and bis(ethylcyclopentadienyl)ruthenium (Ru(EtCp)2) and combinations of these with other Ru precursors.
[0025] In one example, Ru metal can be prepared by precipitation of Ru(CO) in a CO carrier gas at a substrate temperature of about 120° C. to about 250° C., a gas pressure of about 5 mTorr to about 500 mTorr, and a gas exposure time of about 100 seconds to about 1000 seconds. 12 The precursors may be used to deposit by CVD.
[0026] 5 shows a TEM image of Ru metal filling of a recessed feature according to one embodiment of the invention. The recessed feature was formed in a dielectric material 500 and had a width of about 24.7 nm near the top above a metal layer 502 and a width of about 11.5 nm near the bottom. A nucleation inhibition layer was formed on the sidewalls and on the field region using a reaction gas containing TMSDMA, and a nucleation promotion layer was formed by exposing the nucleation inhibition layer to plasma excited H gas, followed by exposure to H O vapor. Ru metal 506 was formed by deposition of Ru3(CO) in a CO carrier gas at a substrate temperature of about 155° C., a gas pressure of about 20 mTorr, and a gas exposure time of about 600 seconds. 12 It was deposited by CVD using precursors.
[0027] Figures 2A-2E show a schematic of a method of metal formation in recessed features according to an embodiment of the invention. Patterned substrate 1 from Figure 1B is reproduced in Figure 2A as patterned substrate 2. Patterned substrate 2 includes a nucleation inhibition layer 120 on the sidewalls 103 of the first layer 100 and on the field regions 101.
[0028] The method includes depositing an initial metal layer 106a on a patterned substrate 2 by vapor deposition, the initial metal layer 106a being preferentially deposited on the second layer 102 in the recessed features 110, the initial metal layer 106a not completely filling the recessed features 110. As shown diagrammatically in FIG. 2B, the metal deposition may not be completely selective to the second layer 102, and the metal nuclei 107a may be deposited on the sidewalls 103 and the field regions 101. The deposition of the metal nuclei 107a is delayed in time compared to the second layer 102 due to the lack of suitable nucleation sites on the sidewalls 103 and the field regions 101. Unlike the initial metal layer 106a, the metal nuclei 107a may form a non-continuous layer in which the total amount of deposited metal in the metal nuclei 107a is less than the amount of metal in the initial metal layer 106a. According to one embodiment, metal deposition may be stopped before metal nuclei 107 a form on the sidewalls 103 and on the field regions 101 .
[0029] The method further includes removing the metal nuclei 107a from the patterned substrate 2 to selectively form the initial metal layer 106a on the second layer 102 in the recessed features 110. This is shown diagrammatically in FIG. 2C. It may be preferable to interrupt the metal deposition and perform the removal of the metal nuclei 107a before the metal nuclei 107a become too large and become more difficult to remove effectively. In one example, the Ru metal nuclei 107a were removed by etching with an etching gas containing ozone (O3) and a carrier gas. Analysis of the patterned substrate 2 after exposure to the etching gas containing O3 showed little or no damage to the dielectric material of the first layer 100. The etching gas containing O3 can be generated by plasma excitation in the process chamber containing the patterned substrate 2, or the etching gas containing O3 can be generated remotely using an ozone generator and O3 can be flowed into the process chamber exposed to the patterned substrate 2.
[0030] Thereafter, following exposure to an etching gas to remove the metal nuclei 107a, a heat treatment step can be performed that includes exposing the patterned substrate 2 to an H2-containing gas to chemically reduce the exposed surfaces of the initial metal layer 106a. For example, the H2-containing gas can consist of H2 gas or can contain H2 gas and Ar gas. The optional heat treatment step can be performed with or without plasma excitation of the H2-containing gas. In one example, the heat treatment includes exposing the patterned substrate 2 to H2 gas and Ar gas at a substrate temperature of about 300° C. to about 350° C. and a gas pressure of about 250 mTorr to about 7 Torr for a period of about 30 seconds to about 60 seconds. In one example, the initial metal layer 106a contains Ru metal, and the optional second heat treatment step can include ... an H2 gas and Ar gas for a period of about 30 seconds to about 60 seconds. x The surface species are chemically reduced to the corresponding elemental Ru metal.
[0031] According to one embodiment, the steps of depositing the initial metal layer 106a and the metal cores 107 and removing the metal cores 107a may be repeated at least once to increase the thickness of the initial metal layer 106a within the recessed feature 110.
[0032] The method further includes treating the patterned substrate 2 with plasma excited H2 gas which modifies the nucleation inhibition layer 120 on the sidewalls 103 above the initial metal layer 106a in the recessed feature 110. In one example, the H2 gas may further include Ar gas. The method then further includes treating the patterned substrate 2 with H2O vapor which adds hydroxyl groups (-OH) to the modified nucleation inhibition layer. This forms a nucleation promotion layer 122 above the initial metal layer 106a in the recessed feature 110. This is shown diagrammatically in FIG. 2D. The -SiMe on the SiO2 layer x In the case of the group, exposure to H2O vapor is believed to form -SiCOH or -SiCOOH species on the SiO2 layer.
[0033] After exposure to HO vapor, * A radical cleaning step may be performed to remove residual H2O from the patterned substrate 2 and the process chamber. In one example, the cleaning step may be performed at a substrate temperature of about 400°C.
[0034] The method further includes depositing a metal layer 106b in the recessed feature 110 by vapor deposition, the metal layer 106b being deposited on the initial metal layer 106a and on the nucleation promotion layer 122 on the sidewalls 103. According to one embodiment shown in Figure 2E, the recessed feature 110 may be completely filled with the metal layers 106a and 106b. In one example, the metallization layer may be removed by etching or CMP.
[0035] 2A-2E may provide improved void-free metal filling of narrow, high aspect ratio recessed features than the method described in Figures 1A-1D. This is due to the fact that the nucleation promotion layer 122 of Figure 2D is formed on the sidewall surface 103 after a portion of the volume of the recessed feature 110 has already been filled with metal layer 106a, thereby reducing the amount of additional metal required and reducing the likelihood of voids when completely filling the recessed feature 110.
[0036] 3A-3F show a schematic of a method of metal formation in recessed features according to another embodiment of the present invention. Patterned substrate 3 is similar to patterned substrate 1 of FIG. 1A, but includes a dual damascene structure including a field region 301 around recessed features 314 including recessed features 310 (e.g., vias) and 312 (e.g., trenches) formed in a first layer 300. Recessed feature 312 includes sidewalls 303 and bottom 313, and recessed feature 310 includes a second layer 302 having sidewalls 305 and exposed surface 304. Patterned substrate 3 further includes an etch stop layer 309. In one example, first layer 300 includes a low-k material and second layer 302 includes a Cu metal layer. This structure is commonly found in the back-end-of-line (BEOL) region of a semiconductor device.
[0037] The method may further include a cleaning step including exposing the patterned substrate 3 to an H2-containing gas to chemically reduce the exposed surface 304 of the second layer 302. For example, the H2-containing gas may consist of H2 gas or may contain H2 gas and Ar gas. The cleaning step may be performed with or without plasma excitation of the H2-containing gas. In one example, the cleaning includes exposing the patterned substrate 3 to H2 gas and Ar gas at a substrate temperature of about 250° C. to about 400° C. and a gas pressure of about 250 mTorr to about 7 Torr for a period of about 30 seconds to about 60 seconds. In some examples, the second layer 302 includes Cu metal or W metal and the cleaning step includes removing CuO x Or WO x The surface species are chemically reduced to the corresponding elemental metal, resulting in reduced electrical resistance in the final device.
[0038] The method further comprises treating the patterned substrate 3 with a reactive gas that forms a nucleation stop layer 320 on the sidewalls 303 and 305, bottom 313 and field region 301 of the first layer 300. This is shown diagrammatically in Figure 3B. The formation of the nucleation stop layer is described above with reference to Figure 1B.
[0039] The method further comprises depositing an initial metal layer 306a on the patterned substrate 3 by vapor deposition, the initial metal layer 306a being preferentially deposited on the second layer 302 in the recessed features 310. As shown diagrammatically in Figure 3C, the metal deposition may not be completely selective and the metal nuclei 307a may be deposited on the sidewalls 303 and 305, the bottom 313 and the field regions 301. Unlike the initial metal layer 306a, the metal nuclei 307a may form a non-continuous layer where the total amount of metal in the metal nuclei 307a is less than the amount of metal in the initial metal layer 306a.
[0040] The method further includes removing the metal nuclei 307a from the patterned substrate 3 to selectively form the initial metal layer 306a on the second layer 302 in the recessed features 310. This is shown diagrammatically in FIG. 3D. It may be preferable to interrupt the metal deposition and perform the removal of the metal nuclei 307a before the metal nuclei 307a become too large and become more difficult to remove efficiently. In one example, the Ru metal nuclei 307a were removed by etching with an etching gas containing ozone (O3) and a carrier gas. The etching gas containing O3 can be generated by plasma excitation in the process chamber containing the patterned substrate 3, or the etching gas containing O3 can be generated remotely using an ozone generator and flowed into the process chamber exposed to the patterned substrate 3.
[0041] Thereafter, following exposure to an etching gas to migrate the metal nuclei 307a, a heat treatment step can be performed that includes exposing the patterned substrate 3 to an H2-containing gas to chemically reduce the exposed surfaces of the initial metal layer 306a. For example, the H2-containing gas can consist of H2 gas or can contain H2 gas and Ar gas. The optional heat treatment step can be performed with or without plasma excitation of the H2-containing gas. In one example, cleaning includes exposing the patterned substrate 3 to H2 gas and Ar gas at a substrate temperature of about 300° C. to about 350° C. and a gas pressure of about 250 mTorr to about 7 Torr for a period of about 30 seconds to about 60 seconds. In one example, the initial metal layer 306a contains Ru metal, and the optional second heat treatment step can include ... an H2 gas and Ar gas for a period of about 30 seconds to about 60 seconds. x The surface species are chemically reduced to the corresponding elemental Ru metal.
[0042] According to one embodiment, the steps of depositing a metal layer and removing the metal nuclei may be repeated at least once to increase the thickness of the initial metal layer 306a within the recessed feature 310. In one example, the steps of depositing a metal layer and removing the metal nuclei may be repeated until the recessed feature 310 is completely filled.
[0043] The method further includes treating the patterned substrate 3 with plasma excited H2 gas which modifies the nucleation inhibition layer 320 on the sidewalls 305 above the initial metal layer 306a in the recessed feature 110, on the sidewalls 303 and bottom 313 in the recessed feature 312, and on the field region 301. Thereafter, the method further includes treating the patterned substrate 3 with H2O vapor which adds hydroxyl groups (-OH) to the modified nucleation inhibition layer. This forms a nucleation promotion layer 322 above the initial metal layer 306a, as shown diagrammatically in Figure 3E. The -SiMe on the SiO2 layer x In the case of the group, exposure to H2O vapor is believed to form the -SiCOH or -SiCOOH species.
[0044] After exposure to HO vapor, *A radical cleaning step may be performed to remove residual H2O from the patterned substrate 3 and the process chamber. In one example, the cleaning step may be performed at a substrate temperature of about 400°C.
[0045] The method further includes depositing a metal layer 306b in the recessed feature 310 by vapor deposition, the metal layer 306b being deposited on the initial metal layer 306a and on the nucleation promotion layer 322. According to one embodiment shown in Figure 3F, the recessed features 310 and 312 may be completely filled with the metal layers 306a and 306b. In one example, the metal overlayer may be removed by etching or CMP.
[0046] 4A-4F show a schematic diagram of a method of metal formation in a recessed feature according to another embodiment of the present invention. In FIG. 4A, a patterned substrate 4 includes a field region 401 around a recessed feature 410 formed in a first layer 400. The recessed feature 410 includes sidewalls 403 and a second layer 402 at the bottom of the recessed feature 410. The second layer 402 includes an oxide layer 415 thereon. In one example, the first layer 300 includes a low-k material, the second layer 402 includes an epitaxial Si or SiGe layer, and the oxide layer 415 includes a SiO x or SiGeO x Includes.
[0047] The method includes a cleaning step that includes performing a chemical oxide removal (COR) to remove the oxide layer 415. The oxide removal forms a clean surface 404 on the second layer 402, as shown generally in Figure 4B. In one example, the COR includes a gas exposure to NH3 and HF, followed by a thermal treatment to remove volatile reaction by-products from the patterned substrate 4.
[0048] The method further includes conformally depositing a contact metal on the patterned substrate 4. For example, the contact metal may include titanium (Ti) metal or cobalt (Co) metal. In the example of Ti metal, the Ti metal reacts with oxygen on the surface of the first layer 400 to form TiO 2 on the sidewalls 403 and in the field regions 401. xForming layer 423, a Ti metal layer 425 is deposited on the clean surface 404. This is shown diagrammatically in Figure 4C. In one example, the Ti metal layer can be deposited by plasma enhanced chemical vapor deposition.
[0049] The method then removes TiO from the sidewalls 403 and field region 401 by a dry etching process. x It further includes selectively removing layer 423. This is shown diagrammatically in Figure 4D.
[0050] A nucleation promotion layer 427 is then formed by treating the patterned substrate 4 with a plasma excited nitrogen-containing gas that modifies the sidewalls 403 and the field regions 401. Non-limiting examples of nitrogen-containing gases include NH3 gas, N2 gas, or N2 gas and H2 gas. The nitrogen-containing gas may further include a chemically inert gas such as Ar.
[0051] According to another embodiment, the nucleation promotion layer 427 may be formed as described above with reference to the nucleation promotion layer 122 of FIG. 1C.
[0052] The method further includes depositing a metal layer 406 in the recessed feature 410 by vapor deposition, the metal layer 406 being deposited on the Ti metal layer 425 and on the nucleation promotion layer 427. According to one embodiment, the recessed feature 410 may be completely filled without voids by the metal layer 406, as shown generally in Figure 4F. In one example, the metal overlayer may be removed by etching or CMP.
[0053] A method for filling recessed features of a semiconductor device with a low resistivity metal has been disclosed in various embodiments. The above description of the embodiments of the invention has been presented for purposes of illustration and explanation. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. This specification and the following claims include terms that are used for descriptive purposes only and should not be construed as limiting. Those skilled in the relevant art will appreciate that many modifications and variations are possible in light of the above teachings. Those skilled in the art will recognize various equivalent combinations and substitutions of the various components shown in the drawings. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Claims
1. 1. A method of forming a semiconductor device, comprising: providing a patterned substrate including a recessed feature formed in a first layer and a second layer exposed in the recessed feature; forming a nucleation promotion layer on sidewalls of the first layer within the recessed feature but not on the second layer, the nucleation promotion layer including forming a nucleation inhibition layer on the sidewalls and converting the nucleation inhibition layer to the nucleation promotion layer; depositing a metal layer in the recessed feature by vapor deposition, the metal layer being deposited on the second layer and on the nucleation promotion layer; Including, The forming of the nucleation promotion layer includes exposing the patterned substrate to a reactive gas that forms the nucleation inhibition layer on the sidewalls; treating the patterned substrate with plasma-excited H2 gas to modify the nucleation inhibition layer; adding hydroxyl groups to the modified nucleation inhibition layer; A method comprising:
2. Adding hydroxyl groups to the modified nucleation inhibition layer comprises: The patterned substrate is 2 Exposure to O vapor The method of claim 1 , comprising:
3. The method of claim 1 , wherein the nucleation blocking layer comprises a self-assembled monolayer (SAM).
4. 10. The method of claim 1, wherein the reactive gas contains an alkylamine silane, an alkyl silane, an alkoxy silane, an alkyl alkoxy silane, an alkyl siloxane, an alkoxy siloxane, an alkyl alkoxy siloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, or a combination thereof.
5. The method of claim 1 , wherein the first layer comprises a dielectric material and the second layer comprises a metal.
6. The method of claim 1 , wherein the recessed feature includes a via hole and a trench above the via hole, and the metal layer fills less than entirely of the via hole.
7. 2. The method of claim 1, wherein the second layer is selected from the group consisting of Ru metal, Co metal, and W metal, and the metal layer is selected from the group consisting of Cu metal, Ru metal, Co metal, W metal, and combinations thereof.
8. 1. A method of forming a semiconductor device, comprising: providing a patterned substrate including a recessed feature formed in a first layer and a second layer exposed in the recessed feature; selectively forming an initial metal layer on the second layer within the recessed feature; thereafter, forming a nucleation promotion layer on sidewalls of the first layer within the recessed feature but not on the second layer, the nucleation promotion layer including forming a nucleation inhibition layer on the sidewalls and converting the nucleation inhibition layer to the nucleation promotion layer; depositing a metal layer in the recessed feature by vapor deposition, the metal layer being deposited on the initial metal layer and on the nucleation promotion layer; Including, The forming of the nucleation promotion layer includes exposing the patterned substrate to a reactive gas that forms the nucleation inhibition layer on the sidewalls; treating the patterned substrate with plasma-excited H2 gas to modify the nucleation inhibition layer; adding hydroxyl groups to the modified nucleation inhibition layer; A method comprising:
9. 9. The method of claim 8, wherein depositing the initial metal layer further comprises depositing metal nuclei on the sidewalls of the first layer, the method further comprising removing the metal nuclei from the sidewalls.
10. 10. The method of claim 9, further comprising repeating the depositing of the metal layer and removing the metal nuclei at least once to increase a thickness of the initial metal layer within the recessed feature.
11. The method of claim 10, further comprising the steps of: adding hydroxyl groups to the modified nucleation inhibition layer; The patterned substrate is 2 Exposure to O vapor The method of claim 8 , comprising:
12. The method of claim 8 , wherein the nucleation blocking layer comprises a self-assembled monolayer (SAM).
13. 9. The method of claim 8, wherein the reactive gas contains an alkylamine silane, an alkyl silane, an alkoxy silane, an alkyl alkoxy silane, an alkyl siloxane, an alkoxy siloxane, an alkyl alkoxy siloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, or a combination thereof.
14. The method of claim 8 , wherein the first layer comprises a dielectric material and the second layer comprises a metal.
15. The method of claim 8 , wherein the recessed feature includes a via hole and a trench above the via hole, and the initial metal layer partially fills the via hole.
16. 1. A method of forming a semiconductor device, comprising: providing a patterned substrate including a recessed feature formed in a dielectric material and a second layer exposed in the recessed feature; depositing a contact metal on the dielectric material and on the second layer, the contact metal reacting to form a metal oxide layer on the dielectric material; removing the metal oxide layer from sidewalls of the dielectric material in the recessed feature; forming a nucleation promotion layer on the sidewalls but not on the second layer, the forming including forming a nucleation inhibition layer on the sidewalls and converting the nucleation inhibition layer to the nucleation promotion layer; depositing a metal layer in the recessed feature by vapor deposition, the metal layer being deposited on the contact metal and on the nucleation promotion layer; The method includes:
17. The method of claim 16 , wherein the metal layer completely fills the recessed feature.
18. The method of claim 16 , wherein the contact metal comprises Ti or Co.
19. The forming of the nucleation promotion layer includes exposing the patterned substrate to a reactive gas that forms a nucleation blocking layer on the sidewalls; treating the patterned substrate with a plasma-excited nitrogen-containing gas to modify the sidewalls of the first layer of dielectric material within the recessed features; 17. The method of claim 16, comprising:
20. 20. The method of claim 19, wherein the nucleation inhibition layer comprises a self-assembled monolayer (SAM).
21. 20. The method of claim 19, wherein the reactive gas contains an alkylamine silane, an alkyl silane, an alkoxy silane, an alkyl alkoxy silane, an alkyl siloxane, an alkoxy siloxane, an alkyl alkoxy siloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, or a combination thereof.