Shield Contact Layout for Power MOSFET

Abstract

The method includes defining a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of a first type extending vertically in a semiconductor substrate, and defining trenches (105, 105-1, 105-2, 105-3, 105-4) of a second type extending laterally and intersecting the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type. The second type of trenches (105, 105-1, 105-2, 105-3, 105-4) are in fluid communication with each of the plurality of intersecting trenches (101, 101-1, 101-2, 102-3, 102-4, 101-c, 101-L, 101-M, 101-U) of the first type. The method further includes disposing a shield poly layer (111) within the plurality of trenches of the first type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the plurality of trenches of the second type (105, 105-1, 105-2, 105-3, 105-4); and disposing an interpoly dielectric layer (112) and a gate poly layer (108) over the shield poly layer (111) in the first type of trenches (105, 105-1, 105-2, 105-3, 105-4) and the second type of trenches (105, 105-1, 105-2, 105-3, 105-4), and forming electrical contacts to the shield poly layer (111) through the openings (106, 16) in the interpoly dielectric layer (112) and the gate poly layer (108) disposed in the second type of trenches.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 166,242, filed March 26, 2021, which was filed on March 2, 2022. 3 Filed on date international application Number: PCT / US2022 / 071278 of This is a national phase application.

[0002] FIELD OF THEINVENTION This description relates to contacts in shielded gate trench MOSFETs. [Background technology]

[0003] The buried polysilicon shield electrode balances the charge and reduces the drain-source on resistance (RDS on Polysilicon shield electrodes are used in shielded gate trench MOSFETs to reduce gate bounce and poor avalanche capability. However, the resistance and stray capacitance associated with the polysilicon shield electrode can affect the electrical performance of the device or affect application efficiency, for example, by causing undesirable gate bounce or poor avalanche capability during unclamped inductive switching (UIS) in the device circuitry. As semiconductor devices (e.g., device cell dimensions) and lithographic design rules shrink, it becomes increasingly difficult to fabricate low resistance buried polysilicon shield electrodes in semiconductor devices (e.g., shielded gate trench MOSFETs) to avoid or reduce gate bounce and poor avalanche capability, for example. Summary of the Invention

[0004] In a general aspect, the device includes a plurality of trenches of a first direction type extending vertically in a semiconductor substrate and a plurality of trenches of a second direction type extending transversely and intersecting the plurality of trenches of the first direction type. The vertical direction is orthogonal to the transverse direction. The trenches of the second direction type are in fluid communication with each of the plurality of intersecting trenches of the first direction type.

[0005] The device further includes a shield poly layer disposed within the plurality of trenches of the first directional type and the trenches of a second directional type, an inter-poly dielectric layer (IPL) and a gate poly layer disposed over the shield poly layer within the plurality of trenches of the first directional type and the trenches of the second directional type, and an electrical contact to the shield poly layer disposed within an opening in the inter-poly dielectric layer and the gate poly layer disposed in the trenches of the second directional type.

[0006] In a general aspect, the device includes a plurality of vertical trenches and mesas of a first direction type extending parallel to a vertical direction across a semiconductor substrate, and a lateral trench of a second direction type extending in a transverse direction perpendicular to the vertical direction and perpendicularly intersecting the plurality of vertical trenches and mesas of the first direction type. The lateral trench is in fluid communication with the plurality of vertical trenches of the first direction type. The lateral trench divides each of the plurality of vertical trenches and mesas into a first section vertical trench and a first section mesa on a first side of the lateral trench and a second section vertical trench and a second section mesa on a second side opposite the first side of the lateral trench, the lateral trench being in fluid communication with each of the plurality of first section vertical trenches and second section vertical trenches.

[0007] The device includes a shield poly layer disposed within the plurality of vertical and lateral trenches, an interpoly dielectric layer (IPL) and a gate poly layer disposed over the shield poly layer within the plurality of vertical and lateral trenches, and extending through the interpoly dielectric layer and the gate poly layer disposed within the lateral trenches. Extreme Covered with rim At least oneand electrically contacting the shield poly layer with a conductive plug.

[0008] In a general aspect, the method includes defining a first type of trench in a semiconductor substrate. The first type of trenches extend vertically. The method further includes defining a second type of trench that extends laterally and intersects the first type of trenches. The second type of trench is in fluid communication with each of the first type of intersecting trenches. The method further includes disposing a shield poly layer within the first type of trenches and the second type of trenches, disposing an interpoly dielectric layer (IPD) and a gate poly layer over the shield poly layer within the first type of trenches and the second type of trenches, and forming an electrical contact to the shield poly layer through an opening in the interpoly dielectric layer and the gate poly layer disposed in the second type of trench. [Brief description of the drawings]

[0009] [Figure 1] 1 illustrates a portion of an example device mask layout. [Figure 2A] 1 illustrates a portion of an exemplary shielded gate trench MOSFET device. [Figure 2B] FIG. 2B is an illustration of a cross-sectional view of a portion of the device of FIG. 2A. [Figure 2C] FIG. 2B illustrates another cross-sectional view of a portion of the device of FIG. 2A. [Diagram 3] 1 illustrates another exemplary shielded gate trench MOSFET device. [Figure 4] FIG. 1 illustrates yet another exemplary shielded gate trench MOSFET device. [Diagram 5] FIG. 1 illustrates a further exemplary shielded gate trench MOSFET device. [Figure 6] FIG. 1 illustrates yet another exemplary shielded gate trench MOSFET device. [Figure 7]FIG. 1 illustrates an additional exemplary shielded gate trench MOSFET device. [Figure 8] FIG. 1 illustrates yet another additional exemplary shielded gate trench MOSFET device. [Figure 9] FIG. 2 is an illustration of an exemplary method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Metal oxide semiconductor field effect transistor (MOSFET) devices are used in many power switching applications. In a typical MOSFET device, a gate electrode provides turn-on and turn-off control of the device in response to an applied gate voltage. For example, in an N-type enhancement mode MOSFET, turn-on occurs when a conductive N-type inversion layer (i.e., channel region) forms in the p-type body region in response to a positive gate voltage that exceeds a characteristic threshold voltage. The inversion layer connects the N-type source region to the N-type drain region and allows majority carrier conduction between these regions.

[0011] In a trench MOSFET device, a gate electrode is formed in a trench that extends downward (e.g., vertically downward) from a major surface of a semiconductor material (which may also be referred to as a semiconductor region), such as silicon. Additionally, a shield electrode may be formed below the gate electrode in the trench (and may be insulated via an inter-electrode or inter-poly dielectric). Current flow in a trench MOSFET device is primarily vertical (e.g., in an N-doped drift region), resulting in more densely packed device cells. A device cell may include, for example, a trench containing the gate electrode and shield electrode, and an adjacent mesa containing the drain, source, body, and channel regions of the device.

[0012] The current handling capability of a trench MOSFET device is determined by its gate channel width. To minimize cost, it may be important to keep the transistor die area size as small as possible and increase the width of the channel surface area (i.e., increase the "channel density") by creating cell structures that are repeated across the entire area of ​​the MOSFET die. A way to increase channel density (and thus increase channel width) is to reduce the size of the device cells and pack more device cells with a smaller pitch within a given surface area.

[0013] An exemplary trench MOSFET device may include an array of hundreds or thousands of device cells, each including a trench and an adjacent mesa. The device cells may be referred to herein as trench-mesa cells, since each device cell geometrically includes a trench and a mesa (or two half-mesa) structure. The shield and gate electrodes may be formed inside a linear trench (e.g., trench 101) that extends along (e.g., aligned with) a mesa (e.g., mesa 102). The shield and gate electrodes may be made of polysilicon (e.g., “n+ shield polysilicon” and “n+ gate polysilicon”) and isolated from each other by a dielectric layer (e.g., inter-poly dielectric (IPD) layer 112, FIG. 2B). The IPD layer may be, for example, an oxide layer. The shield and gate electrodes are also isolated from the silicon in the mesa by a dielectric layer (e.g., shield dielectric and gate dielectric layers).

[0014] To ensure proper electrical contact of all cells, a "planar stripe" structure is often used for trench MOSFETs fabricated on a semiconductor die surface. In a planar stripe structure, a gate electrode ("gate") and a shield electrode ("shield poly") in a trench (e.g., a linear trench) are arranged to extend (e.g., be aligned) along the length of the trench in a vertical stripe. The trench containing the gate electrode and shield electrode can be referred to as an active trench, with the gate electrode (e.g., made of gate poly) being arranged on (or above) the shield electrode (e.g., made of shield poly) along the length of the active trench. The gate poly in the active trench is exposed and contacted at the stripe ends by a gate runner (e.g., gate metal), and the shield electrode (shield poly) in the trench is exposed at locations along the length of the active trench for contact by a source metal and may be raised to the surface (using a masking step).

[0015] In modern trench MOSFET devices (e.g., with narrow line widths), shield resistance is a factor that affects device efficiency and performance. Lower shield resistance can be obtained by making multiple contacts to the shield poly in the active trench (e.g., by vertically lifting the shield poly through the gate poly to the surface in multiple locations to make multiple shield contacts with the source metal).

[0016] Lifting the shield poly perpendicular to the surface (from directly below the gate poly) interrupts or breaks the continuity of the gate poly that runs along the length of the active trench. The gate poly is split into two discontinuous segments along the length of the active trench by each instance of the shield poly that is lifted perpendicular to the surface. In an exemplary implementation, two separate gate runners or gate metal strips (e.g., gate metal 710-1, 710-2 shown in Figures 6 and 7) at the ends of the stripe may be required to contact the two discontinuous gate poly segments created by a single instance of the shield poly that is lifted perpendicular to the surface through the active trench. Multiple instances of shield poly that are lifted perpendicular to the surface through the gate poly along the length of the active trench may result in several isolated gate poly segments that are floating (i.e., not connected by two separate gate runners), and therefore multiple gate runners are required to contact each gate poly segment, which takes up die area.

[0017] The disclosure herein describes an exemplary device configuration or layout for making contact to a shield electrode buried under a gate electrode in an active trench of a MOSFET device fabricated in a semiconductor substrate. A contact (e.g., metal, metal alloy, metal silicide, conductive poly, or other conductive material contact) is made to a shield poly buried under the gate poly in a shield connection trench perpendicular to and transverse to the active trench. The shield connection trench may be a trench portion on the side of the active trench. The contact is made through a vertical insulator-lined (e.g., oxide-lined) opening that extends from the top surface through the gate poly (and other dielectrics, e.g., interlayer dielectrics) overlying the shield electrode to reach the buried shield poly. The buried shield poly is left in place beneath the gate poly and is not raised to the surface. Instead, the contact to the shield poly is made by depositing a conductive material (e.g., metal, tungsten) in the opening. The gate poly is routed in the horizontal plane around the opening in the shield connection trench to maintain continuity of the gate electrode in a portion of the active trench on one side of the contact and a corresponding portion of the active trench on the opposite side of the contact.

[0018] 1 shows a portion of an example device mask layout 100 for a shielded gate trench MOSFET device (e.g., device 200 of FIGS. 2A, 2B, and 2C) in which multiple contacts may be made to shield electrodes within the device. FIG 1 shows the device mask layout 100, for example, in the xy plane (the xy plane may be aligned along the plane of a silicon wafer or semiconductor substrate of the transistor device).

[0019] For ease of explanation, the relative orientation or coordinates of the features (e.g., trenches 101 and 105, mesa 102, etc.) of the disclosed trench MOSFET devices may be described herein with reference to the x and y axes shown on the page, for example, in FIG. 1. The direction perpendicular to the xy plane of the page (e.g., the z axis) may be referred to as the vertical direction or axis. The z direction may be a direction downward into the depth of the semiconductor substrate, for example, aligned with the direction of the depth of the trench in a MOSFET device fabricated in the semiconductor substrate. Furthermore, for visual clarity, a limited number of trenches / device cells (e.g., 3-5 trenches / device cells) of the array of trenches / device cells in the device mask layout 100 are shown in FIG. 1. As previously mentioned, an actual MOSFET device may include hundreds or thousands of arrays of trenches / device cells, which may be obtained, for example, by repeating (e.g., in the x direction) the limited array structure shown in the exemplary device mask layout 100.

[0020] The device mask layout 100 includes several active trenches (i.e., vertical trenches 101) of a device that run parallel (e.g., substantially parallel) to each other (e.g., in the y-direction) as shown in FIG. 1 . Mesas 102 may be formed between pairs of the vertical trenches 101. The trenches 101 and mesas 102 may be linear trenches and linear mesas (e.g., extending in the y-direction), respectively. The trenches 101 and mesas 102 may have uniform widths Wt and Wm (e.g., horizontal widths in the x-direction), respectively. Device elements (e.g., source and body regions (not shown)) may be formed in the mesas 102 and contacted, for example, by a source metal (not shown) in source contact regions 103. The device elements (e.g., source and body regions) may be formed, for example, by n-type source and drain (NSD) implants in sections 104 of the device mask layout 100.

[0021] It should be noted that while FIG. 1 (and other figures herein) shows only a small number of trenches 101 and mesas 102 (e.g., four trenches and three mesas), an actual MOSFET device may include an array of hundreds or thousands of trenches / device cells, which may be obtained, for example, by repeating (e.g., in the x-direction) the trench and mesa structures or patterns shown in the figures.

[0022] A horizontal or lateral trench (e.g., shield connection trench 105) (side trench) may extend laterally (e.g., in the x-direction) to intercept and traverse (i.e., cross) the trenches 101 and mesas 102 at a distance Y along the y-axis. The shield connection trench 105 may have, for example, a vertical width Wv in the y-direction. The shield connection trench 105 may effectively divide each vertical trench 101 and each mesa 102 into two sections (e.g., at an upper section of the vertical trench 101 in an upper region (e.g., region 10U) of the device mask layout 100 above the shield connection trench 105 in the y-direction, and at a lower section of the trench 101 in a lower region (e.g., region 10L) of the device mask layout 100 below the shield connection trench 105 in the y-direction). The trenches (ie, trench 101 and trench 105) may have, for example, approximately the same depth (not shown) referenced from the top surface of mesa 102.

[0023] In an exemplary implementation, the two sections of the vertical trench 101 above the shield connection trench 105 on either side (i.e., above and below) (i.e., the upper section of the vertical trench 101 in the upper region 10U and the lower section of the corresponding trench 101 in the lower region 10L) may be aligned in the horizontal x-direction (i.e., share or lie on a common y-axis Yt, as illustrated in FIG. 1 for the second vertical trench from the right of the page).

[0024] The shield connection trench 105 is in fluid communication with each of the split sections of trench 101 (in other words, the shield connection trench 105 has physical openings in each of the split sections of trench 101 such that a fluid (i.e., a gas or liquid that is not fixed in shape) can easily flow through the openings from the shield connection trench 105 to each of the split sections of trench 101, or vice versa). The shield and gate electrodes (not shown) of the device can be formed in trench 101, for example, by depositing shield poly and gate poly in trenches 101 and 105. The shield poly and gate poly can be separated by an inter-poly dielectric (IPD) layer (not shown in FIG. 1).

[0025] The shield poly in shield connection trench 105 may be exposed for contacting the shield electrode in trenches 101 and 105 through one or more openings (e.g., opening 106) made from the top surface of the gate poly (through the gate poly and IPD layers in shield connection trench 105 to reach the underlying shield poly). In an exemplary implementation, an insulator-covered conductive plug (e.g., insulator-covered conductive plug 116 shown at least in FIGS. 2A, 2B, and 2C) may be fabricated in opening 106. Insulator-covered conductive plug 116 may include, for example, a conductive central portion made of conductive material 109 (FIG. 2A) surrounded by a concentric insulating outer portion (made of oxide 110 (FIG. 2A)).

[0026] In an example implementation, referring again to device mask layout 100 (FIG. 1), opening 106 may first be filled with an oxide (e.g., oxide 110, FIG. 2A) or other insulator, and then another opening may be made through the oxide or other insulator fill to form an insulator-covered opening (e.g., opening 16) back to the underlying shield poly. In device mask layout 100 shown in FIG. 1, this another insulator-covered opening (i.e., opening 16) is shown as a rectangle in dashed line format within opening 106.

[0027] A metal or other conductive material (e.g., conductive material 109, FIG. 2A) may be deposited in the oxide-covered opening 16 to establish electrical contact with the underlying shield poly, for example, for connection to the source metal of the device (e.g., source metal 720, FIGS. 6-9).

[0028] In an exemplary implementation, gate poly deposited in the shield connection trench 105 along the sides or periphery of the insulator-covered conductive plug 116 formed in the opening 106 may provide structural and electrical continuity of the gate electrode in the trench 101 across the shield connection trench 105 (in other words, the gate poly in a section of the trench 101 in the upper region 10U is continuous with the gate poly in a corresponding section of the trench 101 in the lower region 10U).

[0029] In an exemplary implementation, the openings 106 and 16 (and the insulator-covered conductive plug 116) can have a square, rectangular, circular, elliptical, or any other shape in the xy plane. In an exemplary implementation, the opening 106 can have, for example, a rectangular shape having a width Wo in the x-direction and a length Lo in the y-direction, as shown in FIG. 1. In an exemplary implementation, the width Wo can be greater than, the same as, or less than the width Wm of the mesa 102.

[0030] In an exemplary implementation, for a MOSFET having a breakdown voltage BVDSS of 25V to 30V, trench 101 can have a width Wt, for example, in the range of about 0.2 μm to 1.0 μm (e.g., 0.3 μm), mesa 102 can have a width Wm, for example, in the range of about 0.2 μm to 1.0 μm (e.g., 0.3 μm), and shield contact trench 105 can have a width Wt, for example, in the range of about 0.5 μm to 2.0 μm (e.g., 1.0 μm). The insulator-covered conductive plug 116 may have a width Wv in the range of about 0.3 μm to 2.0 μm (e.g., 1.4 μm) and a length Lo in the range of about 0.3 μm to 1.2 μm (e.g., 0.6 μm), and the contact opening 16 may have a width in the x-direction in the range of about 0.1 μm to 1.8 μm (e.g., 1.0 μm) and a length in the y-direction of about 0.1 μm to 1.0 μm (e.g., 0.2 μm).

[0031] For MOSFETs with breakdown voltages BVDSS exceeding 30V, the dimensions of the features described above (e.g., width Wt of trench 101, width Wm of mesa 102, width Wv of shield contact trench 105, width Wo and length Lo of insulator-covered conductive plug 116, and width and length of contact opening 16) may be larger than the example values ​​given above for MOSFETs with breakdown voltages BVDSS between 25V and 30V.

[0032] In an exemplary implementation, an array of several openings 106 (e.g., array 106A) may be arranged along the x-axis within the shield connection trench 105 to form a corresponding array 116A (FIG. 2A) of insulator-covered conductive plugs 116.

[0033] In an exemplary implementation, as shown in FIG. 2A, the insulator-covered conductive plugs 116 in the shield connection trenches 105 may be aligned in the y-direction with the mesas 102 in the upper region 10U and the corresponding mesas 102 in the lower region 10L (in other words, , absolute Covered with rim eachThe conductive plug 116, the mesa 102 in the upper region 10U, and the corresponding mesa 102 in the lower region 10L may all lie along a common axis in the y-direction (eg, axis Ym in FIG. 2A).

[0034] FIG. 2A illustrates an exemplary shielded gate trench MOSFET device 200 having a gate electrode that is continuous around its periphery and uninterrupted (i.e., uninterrupted) by a shield contact fabricated in a shield poly below the gate electrode. In an exemplary implementation, the device 200 may be fabricated using, for example, the device mask layout 100. In the example illustrated in FIG. 2A, the device 200 includes an active trench 101 and a mesa 102 extending in the y-direction, and a horizontal shield connection trench 105 (a side trench) extending laterally (e.g., in the x-direction) across the trench 101 and the mesa 102. Corresponding sections of the active trench 101 (and mesa 102) extending in the y-direction above and below the horizontal shield connection trench 105 may be aligned with each other in the x-direction (in other words, the section of the trench 101 above and the corresponding section of the trench 101 below may share a common y-axis (e.g., axis Yt) and may not be offset from each other in the x-direction). 2A, for example, shows section 101-U of trench 101 above and section 101-L of the corresponding trench 101 below horizontal shield connecting trench 105 aligned on a common y-axis (i.e., Yt). Similarly, adjacent sections of mesa 102 above and below horizontal shield connecting trench 105 are aligned on a common y-axis (i.e., Ym).

[0035] In an exemplary implementation, the gate poly deposited in the shield connection trench 105 along the side or periphery of the insulator-covered conductive plug 116 may provide structural and electrical continuity of the gate electrode in the trench 101 across the shield connection trench 105 (in other words, the gate poly in a section of the trench 101 in the upper region 10U is continuous with the gate poly in a corresponding section of the trench 101 in the lower region 10U through the shield connection trench 105).

[0036] Gate oxide 107 may be grown or deposited on the sidewalls of mesa 102 adjacent to active trench 101 and shield connection trench 105. A layer of gate poly 108 may be deposited in active trench 101 and shield connection trench 105 to form a gate electrode on top of a layer of shield poly (shield poly layer 111, FIG. 2B) and interpoly dielectric (IPD) layer 112 (IPD layer 112, FIG. 2B) previously deposited in the trench. The layer of shield poly and the layer of IPD are not visible in FIG. 2A because they are buried under gate poly 108.

[0037] In device 200, the buried shield poly layer is contacted by an array of vertical insulator-covered conductive plugs 116 (e.g., array 116A) fabricated through the gate poly 108 and IPD 112 layers in the shield connection trench 105. Absolute Covered with rim each The conductive plug 116 may include a conductive central portion surrounded by an insulating liner. In an exemplary implementation, the insulating liner may be made of an insulating material such as oxide 110, and the conductive central portion may be made of a conductive material 109 (e.g., tungsten). Absolute Covered with rim each The conductive material 109 (e.g., tungsten) of the conductive plug may electrically contact the gate poly 108 and the shield poly buried under the IPD layer 112 in the device 200. The gate poly 108 along and around the vertical insulator covered conductive plug 116 may maintain electrical continuity of the gate electrode formed in the active trench 101 across the shield connection trench 105.

[0038] Electrical contact to the buried shield poly layer is made through the interpoly dielectric layer 112 and the gate poly layer 108 disposed within the shield connection trench 105 to reach the buried shield poly layer. The ultimate Covered with rim At least one It is made by a conductive plug 116 .

[0039] In an exemplary implementation, the number of vertical insulator-covered conductive plugs 116 in the shield connection trench 105 may be equal (or approximately equal) to the number of active trenches 101 (or mesas 102) intersected by the shield connection trench 105. Further, in an exemplary implementation, as shown in FIG. , Absolute Covered with rim each A conductive plug 116 may be disposed in a space between a section of the mesa 102 in the upper region 10A and a corresponding section of the mesa 102 in the lower region 10L. Absolute Covered with rim each The conductive plug 116 can have a rectangular shape with a width Wo in the x-direction and a length Lo in the y-direction. In an exemplary implementation, as described above, the width Wo can be greater than, the same as, or less than the width Wm of the mesa 102. For example, in the exemplary implementation shown in FIG. 2A, the width Wo can be about 2-3 times larger than the length Lo.

[0040] 2B and 2C show cross-sectional views of a portion of the device 200. FIG. 2B shows, for example, a cross-sectional view (taken at the zy plane along line AA in FIG. 2A) across a portion of a section of the mesa 102 in the upper region 10A, a portion of a corresponding section of the mesa 102 in the lower region 10L, the shield connection trench 105, and the insulator-covered conductive plug 116 (disposed between the mesas 102). The insulator-covered conductive plug 116 includes a conductive central portion (e.g., conductive material 109) surrounded by a concentric insulating outer portion (e.g., oxide 110). FIG. 2B shows the insulator-covered conductive plug 116 penetrating the gate poly 108 and IPD 112 to the buried shield poly layer 111 in the shield connection trench 105. The conductive material 109 (e.g., tungsten) in the conductive central portion of the insulator-covered conductive plug 116 electrically contacts the buried shield poly layer 111 in the shield connection trench 105. The buried shield poly layer 111 may be isolated from the bottom and sides of the shield connection trench 105 by a dielectric layer (e.g., oxide layer 113).

[0041] FIG. 2C shows, for example, the shield connection trench 105 and Amazing Covered with rim Two A portion of the conductive plug 116 of FIG. 2C shows a cross-sectional view (taken in the zx plane along line BB in FIG. 2A) of a buried shield poly layer 111 in the shield connection trench 105, for example, through the gate poly 108 and IPD 112. Absolutely Covered with rim Two 2B, each of the two insulator-covered conductive plugs 116 includes a conductive central portion (e.g., conductive material 109) surrounded by a concentric insulating outer portion (e.g., oxide 110). The conductive material 109 (e.g., tungsten) electrically contacts the buried shield poly layer 111 in the shield connection trench 105.

[0042] As previously mentioned, in the exemplary implementation shown in Figure 2A, corresponding sections of the active trenches 101 (and mesas 102) extending in the y-direction above and below the horizontal shield-connecting trenches 105 are aligned with each other in the x-direction and are not offset with respect to each other in the x-direction. The intersection of the shield-connecting trenches 105 with the vertical trenches 101 having non-offset sections can create a four-way (xy) cross of trenches, as depicted by arrows 11 in Figure 2A.

[0043] 3 shows another exemplary shielded gate trench MOSFET device 300 having a gate electrode that is continuous around the periphery and uninterrupted (e.g., uninterrupted) by a shield contact made in the shield poly below the gate electrode in the horizontal shield connection trench. In the device 300, corresponding sections of the active trench 101 (and mesa 102) that extend in the y direction above and below the horizontal shield connection trench 105 are offset relative to each other in the x direction, e.g., by a distance DS in the x direction. The shield connection trench 105 may serve as a termination trench for the offset section of the vertical trench 101, creating a three-way (xxy) crossing of trenches, as depicted by arrows 12 in FIG. 3. Processing a three-way crossing of trenches may be preferable to processing a four-way crossing of trenches (arrows 11 in FIG. 2A) under some processing conditions.

[0044] 4 and 5 show other exemplary shielded gate trench MOSFET devices (i.e., devices 400 and 500, respectively) having a gate electrode that is continuous around the periphery and uninterrupted by a shield contact fabricated in the shield poly below the gate electrode in the horizontal shield connection trench. In devices 400 and 500, similar to device 200, corresponding sections of active trenches 101 (and mesas 102) that extend in the y-direction above and below the horizontal shield connection trench 105 are aligned with each other in the x-direction and are not offset relative to each other in the x-direction. However, the number of vertical insulator-covered conductive plugs 116 in the shield connection trench 105 may be less than the number of active trenches 101 (or mesas 102) that are crossed by the shield connection trench 105.

[0045] In an exemplary implementation, the number of vertical insulator-covered conductive plugs 116 in the shield connection trench 105 may be equal to approximately half the number of active trenches 101 (or mesas 102) that the shield connection trench 105 intersects.

[0046] In the example implementation shown in FIG. , absolute Covered with rim each The conductive plug 116 may have a width Wo (in the x-direction) that is greater than Wm of the mesa 102 (e.g., Wo may be about twice as large as Wm). In an exemplary implementation, Wo may be approximately equal to or greater than the sum of the width (Wm) of the mesa 102 and the width (Wt) of the trench 101. Furthermore, in an exemplary implementation, as shown in FIG. , Absolute Each conductive plug 116 covered with an edge may be disposed in a shield connection trench 105 in a space between a section of a pair of mesas 102 in the upper region 10U and a corresponding pair of sections of a pair of mesas 102 in the lower region 10L. Absolute Covered with rim each The conductive plug 116 may have a rectangular shape with a width Wo in the x-direction and a length Lo in the y-direction. In an exemplary implementation, as described above, the width Wo may be greater than the width Wm of the mesa 102. For example, in the exemplary implementation shown in FIG. 4, the width Wo may be approximately equal to the width of two mesas (2Wm) and the width of the trench (Wt), i.e., Wo may be approximately equal to 2*Wm+Wt.

[0047] FIG. 5 illustrates another exemplary implementation of a device in which the number of vertical contact insulator-covered conductive plugs 116 in the shield connection trenches 105 is equal to approximately half the number of active trenches 101 in the device 500. , absolute Covered with rim eachThe conductive plugs 116 may have a width Wo (x-direction) that is smaller than the width Wm of the mesa 102. Furthermore, in an exemplary implementation, as shown in FIG. 5, each insulator-covered conductive plug 116 may be disposed in a shield connection trench 105 in a space between a section of the alternating mesa 102 in the upper region 10A and a corresponding section of the alternating mesa 102 in the lower region 10L. In other words, for a first mesa 102, an open insulator-covered conductive plug may be disposed in a shield connection trench 105 in a space between a section of the first mesa 102 in the upper region 10U and a corresponding section of the first mesa 102 in the lower region 10L, however, for a second (adjacent) mesa 102, the insulator-covered conductive plug 116 is not disposed between the upper and lower sections of the second mesa 102.

[0048] In the examples shown in Figures 1-5, the vertical active trenches and mesas (e.g., trench 101 and mesa 102) extend vertically (e.g., along the y-axis or y-direction) from the gate contact region (gate feed). The vertical active trenches and mesas may extend, for example, between two gate feeds (e.g., gate metal 710-1 and gate metal 710-2 in Figures 6-8). The multiple vertical active trenches and mesas may be intersected vertically, for example, by a single horizontal shield connection trench 105, and a single linear array (e.g., array 116A) of insulator-covered conductive plugs disposed within the shield connection trench 105 is used to make shield contact to the shield poly in the device.

[0049] 6, 7, 8, and 9 show another exemplary implementation in which a vertical active trench and mesa (e.g., trench 101 and mesa 102) between two gate feeds (e.g., gate metals 710-1 and 710-2 in FIGS. 6-8) is vertically crossed by two or more horizontal shield connection trenches, and two or more linear arrays (e.g., array 116A) of insulator-covered conductive plugs can be used to form shield contacts to the shield poly in the horizontal shield connection trenches of the device.

[0050] 6 illustrates another exemplary shielded gate trench MOSFET device 600 having a gate electrode that is continuous around its periphery and uninterrupted by a shield contact fabricated in the shield poly below the gate electrode. In the example illustrated in FIG. 6, the device 600 includes a first direction type active trench 101 and a mesa 102 that extend parallel vertically (e.g., along the y direction) between two gate feeds. The two gate feeds are formed by two sheets or strips of gate metal (e.g., gate metal 710-1 and gate metal 710-2) connected to gate electrode contacts (e.g., contact 702) at the end regions of the active trench 101.

[0051] A first horizontal shield connection trench 105-1 (side trench) of a second directional type extends laterally in a transverse direction (e.g., along the x-direction) and intersects with trench 101 and mesa 102 near location Y1 on the y-axis. A second horizontal shield connection trench 105-1 (side trench) of a second directional type extends laterally in a transverse direction (e.g., along the x-direction) perpendicular to the longitudinal direction and intersects with trench 101 and mesa 102 near location Y2 on the y-axis. The shield connection trenches 105-1 and 105-2 can effectively divide each vertical trench 101 and each mesa 102 into three sections (e.g., a first section of the vertical trench 101 in a first region (e.g., upper region 10U) on the side of the shield connection trench 105-1 (away from the side closer to the shield connection trench 105-2 in the y direction), a second section of the vertical trench 101 in a second region (e.g., middle region 10M) between the shield connection trenches 105-1 and 105-2 in the y direction, and a third section of the trench 101 in a third region (e.g., lower region 10L) on the side of the shield connection trench 105-2 (away from the side closer to the shield connection trench 105-1 in the y direction). The source contact regions 103 on the mesas 102 in all three regions can be contacted by, for example, a source metal 720.

[0052] Sections of trench 101 and mesa 102 extending in the y-direction above (e.g., in upper region 10U), between (e.g., in middle region 10M), and below (e.g., in lower region 10L) the horizontal shield connecting trenches 105-1 and 105-2, and corresponding sections of active trench 101 (and mesa 102) may be aligned with each other in the x-direction (in other words, a first section of trench 101 above horizontal shield connecting trench 105-1, a second section of trench 101 between horizontal shield connecting trenches 105-1 and 105-2, and a corresponding third section of trench 101 below horizontal shield connecting trench 105-2 may share a common y-axis (e.g., axis Yt) and may not be offset relative to each other in the x-direction). 6, for example, shows trench section 101-U of trench 101 above horizontal shield connecting trench 105-1, trench section 101-M of trench 101 between horizontal shield connecting trenches 105-1 and 105-2, and trench section 101-L of trench 101 below horizontal shield connecting trench 105-2, all aligned on a common y-axis (i.e., Yt). Similarly, adjacent sections of mesa 102 above, between, and below horizontal shield connecting trenches 105-1 and 105-2 are all aligned on a common y-axis (i.e., Ym). In device 600, as in device 200, corresponding sections of active trench 101 (and mesa 102) extending in the y-direction in the upper (e.g., trench section 10-U), between (e.g., trench section 10-M), and lower (e.g., trench section 10-L) horizontal shield connection trenches 105-1 and 105-2 are aligned with each other in the x-direction and are not offset with respect to each other in the x-direction.

[0053] In an exemplary implementation, both horizontal shield connection trenches 105-1 and 105-2 can be used as regions to contact the shield poly buried under the gate poly in the device. For example, an array 116A of insulator covered conductive plugs 116 can be placed in trench 105-1 and an array 116B of insulator covered conductive plugs 116 can be placed in trench 105-2 to create a shield poly contact. Having two horizontal shield connection trenches 105-1 and 105-2 can increase the number of shield contacts that can be created compared to the number of shield contacts that can be created in a device using only a single shield connection trench. In an exemplary implementation, a source metal 720 can be used to connect to the shield contacts formed in the two horizontal shield connection trenches 105-1 and 105-2.

[0054] In an exemplary implementation, as described above with reference to device 200 (Figures 2A-2C), in device 600, gate poly deposited in shield connection trenches 105-1 and 105-2 along the sides or periphery of insulator-covered conductive plug 116 may provide structural and electrical continuity of the gate electrode in trench 101 across shield connection trenches 105-1 and 105-2.

[0055] As previously described with reference to device 200, the buried shield poly layer in device 600 may be contacted by an array of vertical insulator-covered conductive plugs 116 (116A and 116B) fabricated through the layer of gate poly 108 (FIG. 2A) in shield connection trenches 105-1 and 105-2. Absolute Covered with rim eachThe conductive plug 116 may be covered with an insulator (e.g., oxide 110 in FIG. 2A) to form an inner opening 16. The inner opening 16 may be filled with a conductive material (e.g., conductive material 109 in FIGS. 2A-2C) to contact the shield poly buried under the gate poly 108 in the device 600. The gate poly 108 disposed along and around the vertical contact insulator covered conductive plug 116 maintains electrical continuity of the gate electrode formed in the active trench 101 across the shield connection trenches 105-1 and 105-2 in the device 600.

[0056] As discussed above with reference to FIG. 6, in device 600, corresponding sections of active trenches 101 (and mesas 102) extending in the y-direction of the top (e.g., trench section 10-U), between (e.g., trench section 10-M), and bottom (e.g., trench section 10-L) horizontal shield connection trenches 105-1 and 105-2 are aligned with each other in the x-direction and are not offset with respect to each other in the x-direction.

[0057] FIG. 7 illustrates an exemplary shielded gate trench MOSFET device 700 having two shield connection trenches 105-1 and 105-2 that vertically intersect the active trench 101 and mesa 102, similar to device 600. However, in device 700, unlike device 600, the two shield connection trenches 105-1 and 105-2 are configured as termination trenches for a section of the active trench 101. Furthermore, the section of the active trench 101 (and mesa 102) that extends in the y-direction between the two horizontal shield connection trenches 105-1 and 105-2 (e.g., trench section 10-M) is offset in the x-direction with respect to the trench sections above and below the two horizontal shield connection trenches 105-1 and 105-2 (e.g., trench sections 10-U and 10-L). In FIG. 7, the offset distance between different trench sections is indicated as a distance DS in the x-direction. In other words, the center section vertical trench (e.g., trench 101-M in trench section 10-M) is offset by a shift distance DS parallel to the first and second section vertical trenches (e.g., trenches 101-U and 101-L) and parallel to the first and second lateral trenches (e.g., horizontal shield connection trenches 105-1 and 105-2). Staggering the active trench sections eliminates the need to handle large (four-way) trench intersections.

[0058] In an exemplary implementation, a horizontal trench (e.g., shield connection trench 105) used to intercept and traverse (i.e., cross) the trenches 101 and mesas 102 to create an area for making shield poly contacts can include multiple short length, discontinuous trench segments, each traversing only a small number of trenches 101 and mesas 102 (e.g., 2-5 trenches 101). Furthermore, these short length horizontal trench segments can traverse a small number of trenches 101 at different locations in the device layout.

[0059] FIG. 8 illustrates an exemplary shielded gate trench MOSFET device 800 in which a short length of horizontal trench segment vertically intersects and traverses a small number of active trenches to create side regions for making shield poly contacts.

[0060] Device 800, like devices 600 and 700, can include an active trench 101 and a mesa 102 extending in the y-direction between two gate feeds. The two gate feeds are formed by two sheets or strips of gate metal (e.g., gate metal 710-1 and gate metal 710-2) connected to gate electrode contacts (e.g., contact 702) at end regions of active trench 101.

[0061] A first short length shield connection trench 105-3 extends laterally (e.g., in the x-direction) across trenches 101-1, 101-2, and 101-c (and mesas 102-1 and 102-2) at approximately location Y1 on the y-axis. A second short length shield connection trench 105-4 extends laterally (e.g., in the x-direction) across trenches 101-c, 101-3, and 101-4 (and mesas 102-3 and 102-4) at approximately location Y2 on the y-axis.

[0062] As shown in FIG. 8, the short length of the shield connection trench 105-3 effectively divides each of the vertical trenches 101-1 and 101-2 and each of the mesas 102-1 and 102-2 into two sections (e.g., an upper section of an upper region (e.g., region 12U) above the shield connection trench 105-3 in the y direction, and a lower section of a lower region (e.g., region 12L) below the shield connection trench 105-3 in the y direction). The short length of the shield connection trench 105-4 effectively divides each of the vertical trenches 101-3 and 101-4 and each of the mesas 102-3 and 102-4 into two sections (e.g., an upper section of an upper region (e.g., region 14U) above the shield connection trench 105-4 in the y direction, and a lower section of a lower region (e.g., region 14L) below the shield connection trench 105-4 in the y direction).

[0063] The short length shield connection trenches 105-3 and 105-4, due to their limited length or area, can accommodate only a limited number of insulator covered conductive plugs 116 for making shield poly contacts in the device 800. For example, each is dead Covered with rim Two Arrays 116C and 116D with conductive plugs 116 may be disposed in short length shield connection trenches 105-3 and 105-4, respectively. However, the variety of locations (e.g., locations Y1 and Y2) where short length shield connection trenches 105-3 and 105-4 can be used and the resulting variety of locations of insulator covered conductive plugs 116 for making shield poly contacts provides device design flexibility and processing robustness.

[0064] In an exemplary implementation, a MOSFET device includes a vertical trench and a set of vertical mesas extending longitudinally across a semiconductor substrate from a gate feed, the device further includes a first lateral trench perpendicularly intersecting at least one of the set of vertical trenches and mesas at a first distance from the gate feed, the first lateral trench being in fluid communication with at least one of the set of intersecting vertical trenches, and a second lateral trench perpendicularly intersecting at least one of the set of vertical trenches and mesas in the semiconductor substrate at a second distance from the gate feed, the second lateral trench being in fluid communication with at least one of the set of intersecting vertical trenches.

[0065] In a MOSFET device, a shield poly layer is disposed within the set of vertical trenches and the first and second lateral trenches, and an inter-poly dielectric layer (IPD) and a gate poly layer are disposed over the shield poly layer within the set of vertical and lateral trenches.

[0066] Furthermore, in the MOSFET device, a first electrical contact to the shield poly layer is made by a first insulator-covered conductive plug passing through the interpoly dielectric layer and the gate poly layer disposed in the first lateral trench, and a second electrical contact to the shield poly layer is made by a second insulator-covered conductive plug passing through the interpoly dielectric layer and the gate poly layer disposed in the second lateral trench.

[0067] In a MOSFET device, the gate poly disposed in at least one of the set of vertical trenches intersected by the first lateral trench forms a continuous gate electrode of the device uninterrupted by an electrical contact to a shield poly layer made by a first insulator-lined conductive plug passing through the interpoly dielectric layer and the gate poly layer disposed in the first lateral trench. The gate poly disposed in at least one of the set of vertical trenches intersected by the second lateral trench also forms a continuous gate electrode of the device uninterrupted by an electrical contact to a shield poly layer made by a first insulator-lined conductive plug passing through the interpoly dielectric layer and the gate poly layer disposed in the second lateral trench.

[0068] In some example implementations of the MOSFET device, at least one of the set of vertical trenches that the first lateral trench intersects at a first distance is one of a different set of vertical trenches from at least one vertical trench that the second lateral trench intersects at a second distance.

[0069] In some exemplary implementations of the MOSFET device, at least one of the set of vertical trenches that the first lateral trench intersects at a first distance is one of the same set of vertical trenches as at least one vertical trench that the second lateral trench intersects at a second distance.

[0070] In some exemplary implementations of the MOSFET device, at least one of the set of vertical trenches intersecting the first lateral trench at a first distance and intersecting the second lateral trench at a second distance is divided into a first section vertical trench on the side of the first lateral section, a middle section vertical trench between the first and second lateral trenches, and a third section vertical trench on the side of the second lateral trench. In some exemplary implementations of the device, the middle section vertical trench is offset with respect to the first section and second section vertical trenches by an offset distance parallel to the first and second lateral trenches.

[0071] FIG. 9 illustrates an exemplary method 900 for reducing shield electrode resistance in a shielded gate trench MOSFET device.

[0072] The method 900 includes defining (910) a first type of trench in a semiconductor substrate. The first type of trench extends vertically (e.g., from a gate feed region). The method 900 further includes intersecting (920) a second type of trench that extends laterally and intersects the first type of trench, the second type of trench being in fluid communication with each of the first type of intersecting trenches. The method 900 further includes disposing (930) a shield poly layer in the first type of trenches and the second type of trench, disposing (940) an interpoly dielectric layer (IPL) and a gate poly layer on the shield poly layer in the first type of trenches and the second type of trench, and forming (950) an electrical contact to the shield poly layer through an opening in the interpoly dielectric layer and the gate poly layer disposed in the second type of trench.

[0073] In method 900, forming an electrical contact to the shield poly layer through the opening includes covering the opening with an insulator (e.g., oxide) and disposing one of a metal (e.g., tungsten), a metal alloy, a metal silicide, or conductive polysilicon in the opening.

[0074] The method includes: defining a first type of trenches in a semiconductor substrate, the first type of trenches extending in a vertical direction; defining a second type of trenches extending in a horizontal direction and intersecting the first type of trenches, the second type of trenches being in fluid communication with each of the first type of intersecting trenches; disposing a shield poly layer in the first type of trenches and the second type of trenches; disposing an inter-poly dielectric layer (IPL) and a gate poly layer on the shield poly layer in the first type of trenches and the second type of trenches; and forming electrical contacts to the shield poly layer through openings in the inter-poly dielectric layer and the gate poly layer disposed in the second type of trenches.

[0075] In the above method, forming an electrical contact to the shield poly layer through the opening includes covering the opening with an insulator.

[0076] In the aforementioned method, forming an electrical contact to the shield poly layer through the opening includes disposing one of a metal, a metal alloy, a metal silicide, or conductive polysilicon in the opening.

[0077] In the aforementioned method, forming an electrical contact to the shield poly layer through the opening includes disposing tungsten in the opening.

[0078] In an exemplary implementation of the devices described herein, the insulator-covered conductive plug is an oxide-covered conductive plug.

[0079] In an exemplary implementation of the devices described herein, the conductive central portion of the insulator-covered conductive plug comprises one of a metal, a metal alloy, a metal silicide, or conductive polysilicon.

[0080] In an exemplary implementation of the devices described herein, the central portion of the insulator-covered conductive plug comprises tungsten.

[0081] In an exemplary implementation of the device described herein, at least one conductive plug covered with an insulator in the inter-poly dielectric layer and the gate poly layer disposed in the lateral trench is disposed in the space between the first section mesa and the second section mesa.

[0082] In some exemplary implementations of the devices described herein, the at least one conductive plug covered with an insulator includes a number of conductive plugs covered with an insulator disposed in the lateral trench, and the number of conductive plugs covered with an insulator is approximately the same as the number of vertical trenches in the plurality of vertical trenches.

[0083] In some exemplary implementations of the devices described herein, the at least one conductive plug covered with an insulator includes a number of conductive plugs covered with an insulator disposed in the lateral trench, and the number of conductive plugs covered with an insulator is approximately half the number of vertical trenches in the plurality of vertical trenches.

[0084] In an exemplary implementation of the devices described herein, at least one insulator-covered conductive plug in the interpoly dielectric layer and the gate poly layer is an oxide-covered opening.

[0085] In an exemplary implementation of the devices described herein, the electrical contact to the shield poly layer through at least one conductive plug covered with an insulator comprises one of a metal, a metal alloy, a metal silicide, or conductive polysilicon.

[0086] In an exemplary implementation of the devices described herein, the electrical contact to the shield poly layer through at least one conductive plug covered with an insulator comprises tungsten.

[0087] In an exemplary implementation of the device described herein, at least one conductive plug covered with an insulator, the first section vertical mesa, and the second section vertical mesa are aligned along a common axis perpendicular to the lateral trench.

[0088] In some exemplary implementations of the devices described herein, at least one conductive plug covered with an insulator, the first section vertical mesa, and the second section vertical trench are aligned along a common vertical axis perpendicular to the lateral trench.

[0089] In some example implementations of the devices described herein, each of the multiple vertical trenches and vertical mesas has a trench width and a mesa width, and the at least one conductive plug covered with an insulator has a width that is the same as or smaller than the mesa width.

[0090] In some example implementations of the devices described herein, each of the multiple vertical trenches and mesas has a trench width and a mesa width, and the at least one conductive plug covered with an insulator has a width greater than the mesa width.

[0091] In some exemplary implementations of the devices described herein, at least one insulator-covered conductive plug has a width approximately equal to the sum of two mesa widths and one trench width.

[0092] Specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments, however, example embodiments may be embodied in many alternative forms and should not be construed as being limited to only the embodiments set forth herein.

[0093] It will be understood that the particular number and geometric size and distribution of electrical contacts within the shield connection trenches is not limited to those shown in the figures herein.

[0094] For example, the representative embodiments shown in the figures herein may include a particular number and geometric size and alignment of electrical contacts (e.g., by insulator-covered conductive plugs 116) in the shield connection trench. The representative embodiments illustrated in the figures show, for example, one electrical contact in the shield connection trench per mesa or per two mesas, electrical contacts having a width comparable to the width of one mesa or the width of two mesas, and electrical contacts generally geometrically aligned with the mesas or the like. Other embodiments within the scope of the present disclosure need not be limited to the representative examples shown in the figures herein. Other embodiments can include, for example, electrical contacts aligned with the inter-mesa trenches, or partially aligned with the mesas and the inter-mesa trenches, or randomly positioned in the shield connection trenches without regard to alignment with the mesas or the inter-mesa trenches. Other embodiments can include, for example, electrical contacts of any width that need not be an integer multiple or fraction of the mesa width (or inter-mesa trench width). Similarly, other embodiments may include, for example, a number of contacts in the shield connection trenches that is not an integer multiple or fraction of the number of mesas (or inter-mesa trenches).

[0095] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including, but not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and / or others.

[0096] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the implementation. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0097] It will also be understood that when an element, such as a layer, region, or substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly disposed on, connected to, or coupled to the other element, or one or more intervening elements may be present. On the other hand, when an element is referred to as being directly disposed on, directly connected to, or directly coupled to another element or layer, no intervening elements or layers are present. Although the terms directly, directly connected, or directly coupled may not be used throughout the detailed description of the present invention, elements illustrated as being directly, directly connected, or directly coupled may be referred to as such. The claims of this application may be amended to recite the exemplary relationships described or illustrated herein.

[0098] As used herein, the singular can include the plural, unless in view of the context the specific instance clearly indicates. Spatially relative terms (e.g., throughout, above, above, below, lower, below, underneath, etc.) are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the drawings. In some implementations, the relative terms above and below can include vertically above and vertically below, respectively. In some implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

[0099] Exemplary implementations of the inventive concepts are described herein with reference to cross-sectional views that are schematic illustrations of idealized implementations (and intermediate structures) of the exemplary implementations. As such, variations from the shapes of the illustrated figures should be expected, for example, as a result of manufacturing techniques and / or tolerances. Thus, the exemplary implementations of the inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein, but should include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of a device, nor are they intended to limit the scope of the exemplary implementations.

[0100] Terms such as "first", "second", etc. may be used to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a "first" element can be called a "second" element without departing from the teachings of the present implementation.

[0101] Unless otherwise defined, all terms (technical and scientific) used herein have the same meaning as commonly understood by those skilled in the art to which the inventive concept pertains. Terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and it will be further understood that they are not interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

[0102] Although certain features of the described implementations have been illustrated as described herein, those skilled in the art will now conceive many modifications, substitutions, changes, and equivalents. It will therefore be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It will be understood that these are presented by way of example only, not limitation, and that various changes in form and details may be made. Any part of the apparatus and / or method described herein may be combined in any combination, except in mutually exclusive combinations. The implementations described herein may include various combinations and / or subcombinations of features, components and / or features of the different implementations described.

Claims

1. A device (200, 300, 400, 500, 600, 700, 800), a plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of a first direction type in a semiconductor substrate, the plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first direction type extending in a vertical direction; a trench (105, 105-1, 105-2, 105-3, 105-4) of a second direction type extending in a transverse direction and intersecting with the plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first direction type, the trench (105, 105-1, 105-2, 105-3, 105-4) being in fluid communication with each of the intersecting plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first direction type, the longitudinal direction being perpendicular to the transverse direction; a shield poly layer (111) disposed within the plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first directional type and the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second directional type; an interpoly dielectric layer (IPL) (112) and a gate poly layer (108) disposed on the shield poly layer (111) within the plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first directional type and the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second directional type; and an electrical contact (116) to the shield poly layer (111) disposed within an opening in the interpoly dielectric layer (112) and the gate poly layer (108) disposed within the trench (105, 105-1, 105-2, 105-3, 105-4) of the second directional type.

2. the electrical contact to the shield poly layer (111) being an insulator-covered conductive plug (116) disposed within an opening (106, 16) in the interpoly dielectric layer (112) and the gate poly layer (108); 2. The device of claim 1, wherein the gate poly layer (108) disposed in the plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first directional type forms a continuous gate electrode of the device, the continuous gate electrode being uninterrupted by the inter-poly dielectric layer (112) disposed in the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second directional type and the electrical contacts to the shield poly layer disposed in the openings (106, 16) in the gate poly layer (108).

3. A device (200, 300, 400, 500, 600, 700, 800), a plurality of vertical trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) and vertical mesas (102, 102-1, 102-2, 102-3, 102-4) of a first direction type extending in parallel in a vertical direction across a semiconductor substrate; A lateral trench (105, 105-1, 105-2, 105-3, 105-4) of a second direction type extending in a transverse direction perpendicular to the vertical direction and perpendicular to the vertical trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first direction type and the vertical mesas (102, 102-1, 102-2, 102-3, 102-4) of the first direction type. -4), wherein the lateral trenches (105, 105-1, 105-2, 105-3, 105-4) are in fluid communication with the plurality of vertical trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first direction type, and the lateral trenches (105, 105-1, 105-2, 105-3, 105-4) are in fluid communication with the plurality of vertical trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first direction type, a first section vertical trench (101-U, 101-L, 101-M) and a first section mesa (102, 102-1, 102-2, 102-3, 102-4) on a first side of the lateral trench (105, 105-1, 105-2, 105-3, 105-4) and a first section mesa (101-U, 101-L, 101-M) on a side opposite to the first side of the lateral trench (105, 105-1, 105-2, 105-3, 105-4); a second section vertical trench (101-U, 101-L, 101-M) and a second section vertical mesa on a second side of said first section vertical trench (101-U, 101-L, 101-M), said lateral trench (105, 105-1, 105-2, 105-3, 105-4) being in fluid communication with each of said first section vertical trench and said second section vertical trench; a shielding poly layer (111) disposed within the plurality of vertical trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) and the lateral trenches (105, 105-1, 105-2, 105-3, 105-4); an interpoly dielectric layer (IPL) (112) and a gate poly layer (108) disposed on the shield poly layer in the vertical trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) and the lateral trenches (105, 105-1, 105-2, 105-3, 105-4); and electrical contact to the shield poly layer (111) by at least one conductive plug (116) covered by an insulator, the conductive plug (116) extending through the inter-poly dielectric layer (112) and the gate poly layer (108) disposed in the lateral trench (105, 105-1, 105-2, 105-3, 105-4).

4. 4. The device of claim 3, wherein the gate poly layer (108) disposed within the plurality of vertical trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) and the lateral trenches (105, 105-1, 105-2, 105-3, 105-4) forms a continuous gate electrode of the device, the continuous gate electrode being uninterrupted by the electrical contact to the shield poly layer (111) by at least one insulator-covered conductive plug (116) through the interpoly dielectric layer (112) and the gate poly layer (108) disposed within the lateral trench.

5. 1. A method comprising: Defining a plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of a first type in a semiconductor substrate, the plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) extending in a vertical direction; defining a second type of trench (105, 105-1, 105-2, 105-3, 105-4) extending laterally and intersecting said plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of said first type, said second type of trench (105, 105-1, 105-2, 105-3, 105-4) being in fluid communication with each of said intersecting plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U); disposing a shield poly layer (111) within the plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first type and within the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second type; disposing an interpoly dielectric layer (IPD) (112) and a gate poly layer (108) over the shield poly layer (111) in the plurality of trenches (101, 101-1, 101-2, 101-3, 101-4, 101-c, 101-L, 101-M, 101-U) of the first type and in the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second type; forming electrical contacts to the shield poly layer (111) through openings (106, 16) in the interpoly dielectric layer (112) and the gate poly layer (108) disposed in the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second type.

6. 6. The method of claim 5, wherein forming the electrical contact to the shield poly layer (111) through the openings (106, 16) comprises covering the openings (106, 16) with an insulator.

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