Mask CD Control

Abstract

A method for controlling a critical dimension of a mask layer is described. The method includes receiving a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating a primary signal having the first primary parameter level and transitioning the primary signal from the first primary parameter level to the second primary parameter level. The method further includes generating a secondary radio frequency (RF) signal having a first secondary parameter level and transitioning the secondary RF signal from the first secondary parameter level to the second secondary parameter level. The method includes transitioning the secondary RF signal from the second secondary parameter level to the third secondary parameter level.

Description

[Technical field]

[0001] The present embodiments relate to a system and method for controlling the critical dimension (CD) of a mask layer. [Background technology]

[0002] The plasma tool includes a radio frequency (RF) generator, a match network, and a plasma reactor. The RF generator is coupled to the plasma reactor through the match network. A wafer is placed in the plasma chamber and etched.

[0003] An RF generator produces an RF signal that is fed into a match network. The match network reduces the reflected power back into the RF generator and feeds an output RF signal to a plasma reactor. The output RF signal is used to etch a wafer. However, in some cases, a different process result than desired may be achieved with the output RF signal.

[0004] The background description provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be regarded as prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0005] The embodiments of the present disclosure provide a system, an apparatus, a method, and a computer program for controlling a critical dimension (CD) of a mask layer of a substrate. It should be understood that the embodiments can be implemented in various ways, such as a process, an apparatus, a system, a device, or a method on a computer readable medium. Some embodiments are described below.

[0006] In one embodiment, in a high aspect ratio (HAR) contact etch, adequate process margin should be maintained while attempting to selectively etch stack layers compared to mask layers. As an example, the stack layers include alternating oxide and polysilicon layers, and the mask layers include carbon. Mask selectivity is related to polymeric species in close proximity to the mask layers. The polymeric species limit the size of the mask openings, thereby limiting the process margin. The method described herein improves the tradeoff between selectivity and process margin while controlling the etch rate of the mask.

[0007] In the case of two-level radio frequency (RF) pulsing, a process for turning both bias and flux power to low or off at a second level can increase mask selectivity when the low or off state is set long enough. However, this process may increase the risk of mask clogging due to increased passivation at the top of the mask. The low or off state is sometimes referred to herein as the low / off state.

[0008] Chemical attempts to extend process capping margins can worsen mask selectivity, ultimately reducing the mask selectivity benefits of two-level RF pulsing. Leaner chemistry, using less polymer source, is an effective knob to extend process margins and remove mask clogging. However, this chemistry approach has trade-offs with other parameters, such as worse profile due to larger maximum critical dimension (CD) and less mask remaining due to worse mask selectivity.

[0009] The methods described herein include multi-state pulsing, in which a third pulsing operation with no bias and low flux regime is added to the low level / off state. By adding the third pulsing operation, the tradeoff with mask clogging is addressed while significantly improving mask selectivity.

[0010] The no-bias and low-flux regime creates a plasma that can reach the top of the mask and remove the polymer deposited on the top and neck regions of the substrate during the low-level / off state. In multi-state pulsing, the no-bias and low-flux regime is implemented as a third state, which can be inserted before or after the low-level / off state, which is the neck-forming state. During each cycle, the no-bias and low-flux regime adjusts and corrects the neck, eliminating the cumulative effect of mask clogging and ultimately expanding the process capping margin. As a result, both the mask selectivity advantage gained from the low-level / off state and the advantage of expanding the process margin can be maintained. The no-bias and low-flux regime is offered as a way to remove mask clogging, which allows great flexibility for the choice of chemistry.

[0011] In one embodiment, a method for controlling a critical dimension of a mask layer is described. The method includes receiving, by a primary generator, a first primary parameter level and a second primary parameter level. The method further includes receiving, by a megahertz RF generator, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating, by the primary generator, a primary signal having a first primary parameter level. The method includes transitioning, by the primary generator, the primary signal from the first primary parameter level to the second primary parameter level during a clock cycle. The method further includes generating, by the secondary RF generator, a secondary RF signal having a first secondary parameter level. The method also includes transitioning, by the secondary RF generator, the secondary RF signal from the first secondary parameter level to the second secondary parameter level during a clock cycle. The method includes transitioning, by the secondary RF generator, the secondary RF signal from the second secondary parameter level to the third secondary parameter level during a clock cycle. A transition of the primary signal from a first primary parameter level to a second primary parameter level is synchronized with a transition of the secondary RF signal from a first secondary parameter level to a second secondary parameter level, the second secondary parameter level being generated to control a critical dimension of the mask layer.

[0012] In one embodiment, a controller for controlling a critical dimension of a mask layer is described. The controller includes a processor and a memory device. The processor receives a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The processor controls the primary generator to generate a primary signal having the first primary parameter level. The processor controls the primary generator to transition the primary signal from the first primary parameter level to the second primary parameter level during a clock cycle. The processor controls the secondary RF generator to generate a secondary RF signal having the first secondary parameter level. The processor controls the secondary RF generator to transition the secondary RF signal from the first secondary parameter level to the second secondary parameter level during a clock cycle. The processor further controls the secondary RF generator to transition the secondary RF signal from the second secondary parameter level to the third secondary parameter level during a clock cycle. The primary signal is controlled to transition from a first primary parameter level to a second primary parameter level in synchronization with a transition of the secondary RF signal from the first secondary parameter level to a second secondary parameter level, and the second secondary parameter level is generated to control a critical dimension of the mask layer. The memory device stores the first primary parameter level, the second primary parameter level, the first secondary parameter level, the second secondary parameter level, and the third secondary parameter level.

[0013] A plasma system for controlling critical dimensions of a mask is described. The plasma system includes a primary generator receiving a first primary parameter level and a second primary parameter level. The plasma system further includes a secondary RF generator receiving a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The primary generator generates a primary signal having a first primary parameter level. The primary generator also transitions the primary signal from the first primary parameter level to the second primary parameter level during a clock cycle. The secondary RF generator generates a secondary RF signal having a first secondary parameter level. The secondary RF generator also transitions the secondary RF signal from the first secondary parameter level to the second secondary parameter level during the clock cycle. The secondary RF generator transitions the secondary RF signal from the second secondary parameter level to the third secondary parameter level during the clock cycle. The transition of the primary signal from the first primary parameter level to the second primary parameter level is synchronous with the transition of the secondary RF signal from the first secondary parameter level to the second secondary parameter level. A second secondary parameter level is generated to control a critical dimension of the mask. The plasma system further includes an impedance match circuit coupled to the primary generator and the secondary RF generator. The impedance match circuit receives the primary and secondary RF signals and outputs a modified RF signal. The plasma system includes a plasma chamber coupled to the impedance match circuit. The plasma chamber receives the modified RF signal and controls a critical dimension of the mask layer.

[0014] Some advantages of the systems and methods described herein include reducing clogging in the mask layer. By introducing an intermediate state between two states of a high frequency (HF) RF generator, clogging in the mask layer is reduced. The HF RF signal generated by the HF RF generator transitions from a first state to a second state, such as an intermediate state, and then transitions from the intermediate state to a third state. The transition from the first state to the second state is synchronized with the transition of the low frequency (LF) RF signal from the first state to the second state. By pulsing the LF RF signal and the HF RF signal in this manner, clogging in the mask layer is reduced.

[0015] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0016] The embodiments can be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0017] [Figure 1] FIG. 1 is a diagram of one embodiment of a system illustrating an experimental routine for determining parameter levels and duty cycles of parameter states of an RF signal generated by a high frequency (HF) radio frequency (RF) generator.

[0018] [Figure 2A] FIG. 2A is an illustration of one embodiment of a graph illustrating a clock signal to which an RF signal is synchronized.

[0019] [Figure 2B] FIG. 2B illustrates an embodiment of a graph illustrating parameters of a low frequency (LF) RF signal generated by an LF RF generator and parameters of a HF RF signal generated by an HF RF generator.

[0020] [Figure 2C]FIG. 2C illustrates an embodiment of a graph illustrating parameters of an LF RF signal and a parameter of an HF RF signal.

[0021] [Figure 3A] FIG. 3A is a diagram of one embodiment of a system illustrating that, once an additional HF recipe is determined, the additional HF recipe is applied to one or more substrates during processing of the substrates.

[0022] [Figure 3B] FIG. 3B is an illustration of one embodiment of a desktop computer for selecting parameter levels and duty cycles.

[0023] [Figure 4] FIG. 4 is a diagram of an embodiment of an LF RF generator and an HF RF generator illustrating details of the RF generators.

[0024] [Figure 5A] FIG. 5A is a diagram of one embodiment of a substrate illustrating the effect of etching operations performed during states S1y and S1x on the substrate.

[0025] [Figure 5B] FIG. 5B is a diagram of one embodiment of a substrate illustrating the effect of states S2y and S0x on the substrate.

[0026] [Figure 5C] FIG. 5C is a diagram of one embodiment of a substrate illustrating the effect of states S0y and S0x on the substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The following embodiments describe systems and methods for controlling critical dimensions (CDs) of a mask layer of a substrate. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail so as not to unnecessarily obscure the embodiments.

[0028] In level-to-level RF pulsing, which is two-state pulsing, turning off both bias and flux in the s0 state may result in more passivation from the polymer. The s0 state may be referred to herein as the zero watt-s0 regime (0W-s0) regime. Passivation occurs primarily at the top of the mask, which can reduce the mask etch rate and increase mask selectivity. Further passivation results in a reduction in the CD of the top mask, which can lead to necking and mask clogging.

[0029] Chemical optimization or tuning may reduce mask clogging, but may also reduce selectivity benefits, such as etch rate. For example, if capping is caused by mask terracing and deposition in the neck region of the substrate, chemical optimization or tuning may reduce the risk of mask clogging. However, chemical tuning may reduce selectivity benefits. Chemical optimization or tuning may be referred to herein as a chemical approach.

[0030] The methods described herein for controlling CD include a no-bias / low-flux regime that creates a plasma that can reach the top of the mask and tune and correct the neck region by removing polymer deposited on the top and neck region. The methods for controlling CD reduce the risk of mask clogging and expand process margins. The no-bias / low-flux regime is implemented as a combination of the S0x and S2y states, which is the third state in multi-state pulsing. The expanded process margins provide the potential benefits of better mask selectivity or better maximum CD. In particular, the expanded process margins provide great value in implementing 0 watts as the S0x state, which significantly increases mask selectivity while maintaining healthy process margins. Thus, multi-state pulsing with 0 watts in the S0x state and the no-bias / low-flux regime as the third state eliminates the tradeoff of mask selectivity versus mask clogging. Multi-state pulsing simplifies the process of expanding process margins and adds further flexibility to the selection of chemical gases.

[0031] Depending on the level of mask clogging during S0x states, the no-bias / low-flux regime in multi-state pulsing can be controlled to minimize the trade-off while maintaining benefits in both process margin and mask selectivity. The force of the flux in the no-bias / low-flux regime can be used to control the CD at the neck and the shape of the neck. Controlling the CD increases the etch rate and improves the aspect ratio by widening the neck. The flux expansion factor is another knob to control quantities such as the duty cycle of the S2y states and the duty cycle of the S0x states. Such adjustability allows easy control of the balance between etch rate and mask selectivity.

[0032] The methods described herein for controlling CD provide a way to eliminate the trade-off of mask selectivity versus mask clogging. Chemical approaches to address mask clogging result in trade-offs such as worsening or degraded mask selectivity. Because the methods for controlling CD implement the no-bias / low-flux regime as a third state along with zero watts as state S0x, the mask selectivity advantage from state S0x and the healthy mask advantage from the no-bias / low-flux regime can be maintained during the same clock cycle. This control in removing mask clogging while maintaining high mask selectivity provides additional flexibility for mask type and mask thickness selection, further reducing substrate fabrication costs.

[0033] 1 is a diagram of an embodiment of a system 100 illustrating an experimental routine for determining parameter levels and duty cycles of a parameter state S1y of an RF signal 104 generated by a high frequency (HF) radio frequency (RF) generator. Examples of parameters include power and voltage. An example of a duty cycle of a parameter level includes a period of time that the parameter level is maintained.

[0034] The system 100 includes a low frequency (LF) RF generator, an HF RF generator, a match 104, a plasma chamber 106, a host computer 108, and an electron microscope 110. An example of an LF RF generator is an RF generator having a low operating frequency of 100 kilohertz (kHz), or 400 kHz, or 1 megahertz (MHz), or 2 MHz. An example of an HF RF generator is an RF generator having a high operating frequency of 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, or 120 MHz. To further illustrate, the HF RF generator has a higher frequency than the operating frequency of the LF RF generator. The LF RF generator is an example of a primary generator, and the HF RF generator is an example of a secondary RF generator.

[0035] The match 104 may be referred to herein as an impedance matching circuit or an impedance matching network. As an example, the match 104 includes a network of circuit components coupled together. Examples of circuit components are resistors, inductors, or capacitors.

[0036] Examples of the host computer 108 include a desktop computer, a laptop computer, a tablet, a smartphone, and a controller. The host computer 108 includes a processor 112 and a memory device 114. As an example, the processor 112 can be a central processing unit (CPU), a combination of a CPU and a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a microcontroller. Examples of the memory device 114 include a read only memory (ROM) and a random access memory (RAM). The processor 112 is coupled to the memory device 114.

[0037] The plasma chamber 106 includes a substrate support 116, such as an electrostatic chuck (ESC). The plasma chamber 106 further includes an upper electrode 118, which is positioned above the substrate support 116 and forms a gap 120 between the upper electrode 118 and the substrate support 116. A lower electrode embedded within the substrate support 116 is made of a metal, such as aluminum or an aluminum alloy. The substrate support 116 is made of a metal and aluminum oxide (Al 2 O 3 The upper electrode 118 is made of a ceramic such as a ceramic material. The upper electrode 118 is made of a metal and is coupled to a reference potential such as ground or a negative potential. One example of the plasma chamber 106 is a capacitively coupled plasma (CCP) chamber.

[0038] As an example, the electron microscope 110 uses electron beams and their wave-like properties to magnify an image of the substrate S. By way of example, the electron microscope 110 can resolve features of the substrate S smaller than one part in a million. Examples of the electron microscope 110 include a transmission electron microscope (TEM), a scanning electron microscope (SEM), and a scanning transmission electron microscope (STEM). An example of a substrate as used herein includes a semiconductor wafer having multiple layers. By way of example, the substrate includes multiple layers that form an integrated circuit such as an ASIC or PLD. The processor 112 is coupled to the LF RF generator, the HF RF generator, and the electron microscope 110.

[0039] An output O1 of the LF RF generator is coupled to an input I1 of the match 104 via an RF cable RFC1. An output OM of the match 104 is also coupled to a bottom electrode of the substrate support 116 via an RF transmission line RFT. An example of an RF transmission line RFT includes an RF cable surrounded by an RF sheath, with an insulator between the RF cable and the RF sheath.

[0040] The plasma chamber 106 has a sidewall 122, a top wall 124, and a bottom wall 126. The sidewall 122 is located between the top wall 124 and the bottom wall 126. The sidewall 122 is attached to the top wall 124 and the bottom wall 126. A slot 129 extends through the sidewall 122.

[0041] The processor 114 generates a recipe signal 128 and transmits the recipe signal 128 to the LF RF generator. The recipe signal 128 includes LF recipe information, such as the number of states of a parameter of an RF signal 130 generated by the LF RF generator, the parameter levels for each state of the RF signal 130, the duty cycle of each of the states, and the frequency of the RF signal 130. Similarly, the processor 114 generates a recipe signal 132 and transmits the recipe signal 132 to the HF RF generator. The recipe signal 132 includes the number of states of a parameter of an RF signal 102 generated by the HF RF generator, the parameter levels for each state of the RF signal 102, the duty cycle of each of the states, and the frequency of the RF signal 102.

[0042] After receiving recipe signal 128, the LF RF generator generates RF signal 130 based on the parameter level for the number of states received in recipe signal 128. For example, RF signal 130 has two states, each of the two states having a corresponding one of the parameter levels received in recipe signal 128. RF signal 130 also has a frequency received in recipe signal 128. Also, after receiving recipe signal 132, the HF RF generator generates RF signal 102 having a parameter level for the number of states received in recipe signal 132. For example, RF signal 102 has two states, each of the states having a corresponding one of the parameter levels received in recipe signal 132. RF signal 130 also has a frequency received in recipe signal 128.

[0043] The RF signal 130 is transmitted from output O1 via RF cable RFC1 and input I1 to the match 104. Also, the RF signal 102 is transmitted from output O2 to the match 104 via RF cable RFC2 and input I2.

[0044] The match 104 receives the RF signals 130 and 102 and matches the impedance of the load coupled to the output OM with the impedance of the source coupled to the inputs I1 and I2. The impedance matching modifies the impedance of the RF signals 130 and 102 and outputs a modified RF signal 134 at the output OM. An example of a load includes an RF transmission line RFT and a plasma chamber 106. An example of a source coupled to the inputs I1 and I2 includes an LF RF generator, an RF cable RFC1, an HF RF generator, and an RF cable RFC2. The modified RF signal 134 is transmitted from the output OM through the RF transmission line RFT to the lower electrode of the substrate support 116.

[0045] When one or more process gases are supplied to the gap 120 in the plasma chamber 106 in addition to the modified RF signal 134, a plasma is generated or maintained in the gap 134 to process the substrate S. Examples of processing the substrate S include depositing material on the substrate S, etching a layer of the substrate S, cleaning the substrate S, and sputtering the substrate S. Examples of the one or more process gases include an oxygen-containing gas, a fluorine-containing gas, and combinations thereof. Illustratively, the one or more process gases may be a gas that contains carbon and hydrogen, e.g., CHF 3 As another example, where the amount of carbon and hydrogen is reduced, hydrogen gas or nitrogen trifluoride (NF3) gas can be used as one or more process gases.

[0046] After processing the substrate S for a predetermined amount of time, e.g., 15 or 20 minutes, the substrate S is removed from the plasma chamber 106 via the slot 129. As an example, processing of the substrate S may take approximately one hour to complete. The substrate S is then placed under the electron microscope 110 and inspected ex-situ by a user. For example, once the substrate S is placed under the electron microscope 110, an image of the features of the substrate S generated or captured by the electron microscope 110 is displayed on a display device of the host computer 108 by the processor 112. Examples of display devices include a liquid crystal display (LCD), a light emitting diode (LED) display, and a plasma display. The display device of the host computer 108 is coupled to the processor 112 of the host computer 108.

[0047] Whether the clogging amount of the mask layer of the substrate S is greater than the predetermined clogging amount, or whether the shape of the profile of the mask layer is the predetermined shape, or a combination thereof, is determined by the user or by the processor 112. For example, the user measures a critical dimension (CD), such as a width at the neck of the substrate S, from the displayed image and determines whether the CD is less than the predetermined CD. In this example, the user provides the CD to the processor 112 via an input device of the host computer 108. Further, in this example, the processor 112 stores the CD in the memory device 114. Also, in this example, if the CD is less than the predetermined CD, the clogging amount of the mask layer is greater than the predetermined clogging amount. In this example, the predetermined CD is stored in the memory device 114. Further, in this example, on the other hand, if the CD is greater than the predetermined CD, the clogging amount of the mask layer is less than the predetermined clogging amount. In this example, the determination of whether the CD is greater than the predetermined CD is made by the user.

[0048] As another example, the processor 112 measures the CD at the neck of the substrate S from the captured image and determines whether the CD is less than the predetermined CD. Further, in this example, the processor 112 stores the CD in the memory device 114. Also, in this example, if the CD is less than the predetermined CD, the processor 112 determines that the clogging amount of the mask layer is greater than the predetermined clogging amount. Further, in this example, on the other hand, if the CD is greater than the predetermined CD, the processor 112 determines that the clogging amount of the mask layer is less than the predetermined clogging amount.

[0049] As yet another example, a user measures CDs at multiple locations on the neck of the substrate from a displayed image. In this example, the user measures a first CD at a first horizontal level on the neck and a second CD at a second horizontal level on the neck. The second horizontal level is lower than the first horizontal level. Continuing with this example, the user provides two CDs to the processor 112 via an input device. In this example, the processor 112 stores the two CDs in the memory device 114. Also in this example, if the first CD is outside a preset range from the first preset CD and the second CD is outside a preset range from the second preset CD, the shape of the profile of the mask layer is not a predetermined shape. In this example, on the other hand, if the first CD is within a preset range from the first preset CD and the second CD is within a preset range from the second preset CD, the shape of the profile of the mask layer is a predetermined shape. In this example, the first preset CD, the preset range, and the second preset CD are stored in the memory device 114. Further, in this example, the first preset CD, the preset range, and the second preset CD define a predetermined shape. Also, in this example, the determination of whether the first CD is within a preset range from the first preset CD and the second CD is within a preset range from the second preset CD is made by the user or by the processor 112. As another example, it should be noted that the CD can be measured at three or more horizontal levels at the neck to compare with the same number of preset CDs.

[0050] As yet another example, the processor 112 measures CDs at multiple locations on the neck of the substrate from the captured images. In this example, the processor 112 measures a first CD at a first horizontal level on the neck and a second CD at a second horizontal level on the neck. In this example, the processor 112 stores the two CDs in the memory device 114. Also in this example, if the first CD is outside a preset range from the first preset CD and the second CD is outside a preset range from the second preset CD, the processor 112 determines that the shape of the profile of the mask layer is not the predetermined shape. On the other hand, in this example, if the first CD is within a preset range from the first preset CD and the second CD is within a preset range from the second preset CD, the processor 112 determines that the shape of the profile of the mask layer is the predetermined shape.

[0051] Upon determining that the clogging amount is greater than the predetermined clogging amount or the shape of the mask layer profile is not the predetermined shape, or a combination thereof, the recipe of the RF signal 102 is modified by the user via the input device or by the processor 112 to provide a HF recipe. For example, the user or the processor 112 introduces an intermediate state between two states of the RF signal 102. To illustrate, if the two states of the RF signal 102 are S1y and S0y, the user provides HF recipe information regarding an intermediate state S2y between the two states S1y and S0y. To further illustrate, the user provides the parameter level and duty cycle of the intermediate state S2y to the processor 112 via the input device. In a further example, the remaining data is the same as the data in the recipe signal 132. Also, in a further example, by introducing the intermediate state, the duty cycle of the state S1y is reduced. In a further example, the user provides the duty cycle of the state S1y and the parameter level for the state S1y to the processor 112 via the input device. In a further example, a user provides parameter levels for state S0y to the processor 112 via an input device. In this example, the user provides an HF recipe to the processor 112 via an input device. Also in this example, the processor 112 stores the HF recipe in the memory device 114. As another example, the processor 112 introduces an intermediate state and sets parameter levels and duty cycles for the intermediate state S2y on behalf of the user. Also in this example, the processor 112 sets parameter levels for state S0y on behalf of the user.

[0052] Examples of input devices include a mouse, a stylus, a keyboard, and a keypad. The input devices are coupled to the processor 112 of the host computer 108.

[0053] Also, when changing the recipe of the RF signal 102 to provide an HF recipe, the LF recipe information used to generate the RF signal 130 is modified by the user or by the processor 112 to output the LF recipe. For example, the user modifies the duty cycle of state S1x of the RF signal 130 to be equal to the duty cycle of state S1y in the HF recipe. Also, in this example, the user does not modify other data, such as parameter levels, in the LF recipe information. In this example, the user provides the LF recipe to the processor 112 via an input device. Also, in this example, the processor 112 stores the LF recipe in the memory device 114. As another example, the processor 112 modifies the duty cycle of state S1x of the RF signal 130 on behalf of the user to be equal to the duty cycle of state S1y in the HF recipe. Also, in this example, the processor 112 does not modify other data, such as parameter levels, in the LF recipe information. Also, in this example, the processor 112 stores the LF recipe in the memory device 114.

[0054] In addition to modifying the recipe of RF signal 102 and modifying the recipe of RF signal 130, the substrate S is returned to the top of the substrate support 116 via slot 129. Upon receiving or generating an HF recipe, the processor 112 generates a recipe signal 136A based on the HF recipe and transmits the recipe signal 136A to the HF RF generator. Also, in response to receiving or generating an LF recipe, the processor 112 generates a recipe signal 137A and transmits the recipe signal 137A to the LF RF generator.

[0055] Upon receiving the recipe signal 136A, the HF RF generator generates an RF signal 138A based on the HF recipe. For example, the RF signal 138A has three parameter levels, one for each of the three states S1y, S2y, and S0y. The HF RF generator provides the RF signal 138A to the match 104 via output O2 and RF cable RFC2 and input I2.

[0056] Also upon receiving recipe signal 137A, the LF RF generator generates RF signal 139A based on the LF recipe. For example, state S1x of RF signal 139A has a duty cycle equal to the duty cycle of RF signal 138A. The LF RF generator provides RF signal 139A to match 104 via output O2 and RF cable RFC1 and input I1.

[0057] The match 104 receives the RF signals 138A and 139A and matches the impedance of the load coupled to the output OM with the impedance of the source coupled to the inputs I1 and I2. The impedance matching changes the impedance of the RF signals 138A and 139B and outputs a modified RF signal 140A at the output OM. The modified RF signal 140A is transmitted from the output OM through an RF transmission line RFT to the bottom electrode of the substrate support 116.

[0058] The substrate S is further processed in the plasma chamber 106 when one or more process gases are provided to the gap 120 in the plasma chamber 106 in addition to the modified RF signal 140A. Upon processing the substrate S for a preset amount of time, for example 15 or 20 minutes, the substrate S is removed from the plasma chamber 106 via the slot 129 and then placed under the electron microscope 110 and inspected ex-situ by a user. Once the substrate S is placed under the electron microscope 110, an image is captured or generated by the electron microscope 110 and displayed on a display device of the host computer 108 by the processor 112.

[0059] The user or the processor 112 determines whether the clogging amount of the mask layer of the substrate S is greater than the predetermined clogging amount, or whether the shape of the mask layer is a predetermined shape, or a combination thereof. For example, the user measures the CD at the neck of the substrate S again from the displayed image to determine whether the CD is less than the predetermined CD, and provides the CD to the processor 112 via the input device. In this example, if the CD measured again is less than the predetermined CD determined by the user, the clogging amount of the mask layer is greater than the predetermined clogging amount. Furthermore, in this example, on the other hand, if the CD measured again is greater than the predetermined CD determined by the user, the clogging amount of the mask layer is less than the predetermined clogging amount. In this example, the processor 112 stores the CD measured again in the memory device 114. As another example, the processor 112 measures the CD at the neck of the substrate S again from the captured image to determine whether the CD is less than the predetermined CD. In this example, if the CD measured again is less than the predetermined CD determined by the processor 112, the clogging amount of the mask layer is greater than the predetermined clogging amount. Further, in this example, if, on the other hand, the re-measured CD is greater than the predetermined CD determined by the processor 112, then the amount of blockage of the mask layer is less than the predetermined amount of blockage. In this example, the processor 112 stores the re-measured CD in the memory device 114.

[0060] As yet another example, the user again measures the CD at multiple locations on the neck of the substrate from the displayed image and determines whether the shape of the mask layer is the predetermined shape. As yet another example, the processor 112 measures the CD at multiple locations on the neck of the substrate from the captured image before determining whether the shape of the mask layer is the predetermined shape.

[0061] Upon determining that the clogging amount is greater than a predetermined clogging amount or the shape of the mask layer is not a predetermined shape, or a combination thereof, the HF recipe of the RF signal 138A is modified by the user via the input device or by the processor 112 to provide an additional HF recipe. For example, the user modifies the parameter level or the duty cycle, or both the parameter level and the duty cycle, of an intermediate state S2y between two states of the RF signal 138A. By way of example, the user increases or decreases the parameter level of the intermediate state S2y of the RF signal 138A. In the example, the remaining data is the same as the data in the HF recipe used to generate the recipe signal 136A. By way of further example, the user selects the parameter level of the intermediate state S2y to be between 100 and 1000 watts. By way of another example, the user increases or decreases the duty cycle of the intermediate state S2y of the RF signal 138A. In the example, the remaining data is the same as the data in the HF recipe used to generate the recipe signal 136A. As a further example, the user increases the duty cycle of the intermediate state S2y to be 1 to 3 times the duty cycle of the state S1y. As another further example, the user increases the duty cycle of the intermediate state S2y to be equal to the duty cycle of the state S1y or to be 3 times the duty cycle of the state S1y. As yet another further example, the user increases the duty cycle of the intermediate state S2y to be 4 to 5 times the duty cycle of the state S1y. As yet another further example, the user increases the duty cycle of the intermediate state S2y to be equal to 4 times the duty cycle of the state S1y or to be 5 times the duty cycle of the state S1y. The user provides additional HF recipes to the processor 112 via the input device. The processor 112 stores the additional HF recipes in the memory device 114.

[0062] As another example, the processor 112 modifies the parameter level or duty cycle, or both the parameter level and the duty cycle, of an intermediate state S2y between two states of the RF signal 138A. For example, the processor 112 increases or decreases the parameter level of the intermediate state S2y of the RF signal 138A. For example, the remaining data is the same as the data in the HF recipe used to generate the recipe signal 136A. For further example, the processor 112 sets the parameter level of the intermediate state S2y to be 100 to 300 watts. As another example, the processor 112 increases or decreases the duty cycle of the intermediate state S2y of the RF signal 138A. For example, the remaining data is the same as the data in the HF recipe used to generate the recipe signal 136A. For further example, the processor 112 increases the duty cycle of the intermediate state S2y to be 1 to 3 times the duty cycle of the state S1y. As another further example, the processor 112 increases the duty cycle of the intermediate state S2y to be equal to the duty cycle of the state S1y or to be three times the duty cycle of the state S1y. As yet another further example, the processor 112 increases the duty cycle of the intermediate state S2y to be four to five times the duty cycle of the state S1y. As yet another further example, the processor 112 increases the duty cycle of the intermediate state S2y to be equal to four times the duty cycle of the state S1y or to be five times the duty cycle of the state S1y. The processor 112 stores the additional HF recipe in the memory device 114.

[0063] Also, when changing the recipe of the RF signal 138A to provide the additional HF recipe, the LF recipe of the RF signal 139A is modified by the user or by the processor 112 to output the additional LF recipe. For example, the user modifies the duty cycle of state S1x of the RF signal 139A to be equal to the duty cycle of state S1y in the additional HF recipe. In this example, the parameter levels and frequencies in the additional LF recipe are the same as the parameter levels and frequencies in the LF recipe used to generate the RF signal 139A. Also, in this example, the user does not modify other data, such as parameter levels, in the LF recipe. In this example, the user provides the additional LF recipe to the processor 112 via an input device. In this example, the processor 112 stores the additional LF recipe in the memory device 114. As another example, the processor 112 modifies the duty cycle of state S1x of the RF signal 139A to be equal to the duty cycle of state S1y in the additional HF recipe. In this example, the parameter levels and frequencies in the additional LF recipe are the same as the parameter levels and frequencies in the LF recipe used to generate the RF signal 139A. Additionally, in this example, the processor 112 does not modify other data, such as parameter levels, in the LF recipe. In this example, the processor 112 stores an additional LF recipe in the memory device 114.

[0064] In addition to modifying the HF recipe of RF signal 138A and modifying the LF recipe of RF signal 139A, the substrate S is returned to the top of the substrate support 116 via slot 129. Upon receiving the additional HF recipe, the processor 112 generates a recipe signal 136B based on the additional HF recipe and transmits the recipe signal 136B to the HF RF generator. Similarly, in response to receiving the additional LF recipe, the processor 112 generates a recipe signal 137B based on the additional LF recipe and transmits the recipe signal 137B to the LF RF generator.

[0065] Upon receiving the recipe signal 136B, the HF RF generator generates an RF signal 138B based on the additional HF recipe. For example, the RF signal 138B has different parameter levels for state S2y, such as higher or lower parameter levels than the parameter levels for state S2y of the RF signal 138A. The HF RF generator provides the RF signal 138B to the match 104 via output O2 and RF cable RFC2 and input I2.

[0066] Similarly, upon receiving recipe signal 137B, the LF RF generator generates RF signal 139B based on an additional LF recipe. For example, RF signal 139B has a duty cycle for state S1x that is equal to the duty cycle of state S1y of RF signal 138B. The LF RF generator provides RF signal 139B to match 104 via output O1 and RF cable RFC1 and input I1.

[0067] The match 104 receives the RF signals 138B and 139B and matches the impedance of the load coupled to the output OM with the impedance of the source coupled to the input I2. The impedance matching modifies the impedance of the RF signals 138B and 139B and outputs a modified RF signal 140B at the output OM. The modified RF signal 140B is transmitted from the output OM through an RF transmission line RFT to the bottom electrode of the substrate support 116.

[0068] The substrate S is further processed in the plasma chamber 106 when one or more process gases are provided to the gap 120 in the plasma chamber 106 in addition to the modified RF signal 140B. Upon processing the substrate S for a precalculated amount of time, for example 15 or 20 minutes, the substrate S is removed from the plasma chamber 106 via the slot 129 and then placed under the electron microscope 110 and inspected ex-situ by a user. Once the substrate S is placed under the electron microscope 110, an image is generated or captured by the electron microscope 110 and displayed on a display device of the host computer 108 by the processor 112.

[0069] It is determined whether the clogging amount of the mask layer of the substrate S is greater than a predetermined clogging amount, or whether the shape of the profile of the mask layer is a predetermined shape, or a combination thereof. For example, the user determines whether the clogging amount of the mask layer of the substrate S is greater than a predetermined clogging amount from the displayed image. In this example, when the clogging amount is determined to be less than the predetermined clogging amount, the user does not modify the additional HF recipe of the RF signal 138B. Also, in this example, the processor 112 stores the additional HF recipe of the RF signal 138B in the memory device 118. On the other hand, in this example, when the clogging amount is determined to be not less than the predetermined clogging amount, for example, equal to or greater than the predetermined clogging amount, the user further modifies the additional HF recipe of the RF signal 138B. Thus, in this example, the user continues to modify the RF signal generated by the HF RF generator until the clogging amount is less than the predetermined clogging amount.

[0070] As another example, the user determines from the displayed image whether the shape of the profile of the mask layer of the substrate S is a predetermined shape. In this example, if the user determines that the shape of the profile is a predetermined shape, the user does not modify the additional HF recipe of the RF signal 138B. Also, in this example, the processor 112 stores the additional HF recipe of the RF signal 138B in the memory device 118. On the other hand, in this example, if the user determines that the shape of the profile is not a predetermined shape, the user further modifies the additional HF recipe of the RF signal 138B. Thus, in this example, the user continues to modify the recipe of the RF signal generated by the HF RF generator until the shape of the profile is a predetermined shape.

[0071] As yet another example, the processor 112 determines from the captured image whether the clogging amount of the mask layer of the substrate S is greater than a predetermined clogging amount. In this example, when the processor 112 determines that the clogging amount is less than the predetermined clogging amount, the processor 112 does not modify the additional HF recipe of the RF signal 138B. Also, in this example, the processor 112 stores the additional HF recipe of the RF signal 138B in the memory device 118. On the other hand, in this example, when the processor 112 determines that the clogging amount is not less than the predetermined clogging amount, for example, is equal to or greater than the predetermined clogging amount, the processor 112 further modifies the additional HF recipe of the RF signal 138B. Thus, in this example, the processor 112 continues to modify the RF signal generated by the HF RF generator until the clogging amount is less than the predetermined clogging amount.

[0072] As another example, the processor 112 determines from the captured image whether the shape of the profile of the mask layer of the substrate S is a predetermined shape. In this example, if the processor 112 determines that the shape of the profile is a predetermined shape, the processor 112 does not modify the additional HF recipe of the RF signal 138B. Also, in this example, the processor 112 stores the additional HF recipe of the RF signal 138B in the memory device 118. On the other hand, in this example, if the processor 112 determines that the shape of the profile is not a predetermined shape, the processor 112 further modifies the additional HF recipe of the RF signal 138B. Thus, in this example, the processor 112 continues to modify the recipe of the RF signal generated by the HF RF generator until the shape of the profile is a predetermined shape.

[0073] 2A is a diagram of one embodiment of a graph 200 illustrating a clock signal 202 to which RF signals, such as RF signals 102, 138A, 138B, 130, 139A, and 139B (FIG. 1), are synchronized. As an example, the clock signal 202 is generated by the processor 112 (FIG. 1) and transmitted to the LF RF generator and the HF RF generator. As another example, the clock signal 202 is generated by a digital signal processor (DSP) of the LF RF generator and transmitted from the DSP of the LF RF generator to the DSP of the HF RF generator. The DSP of the LF RF generator is coupled to the DSP of the HF RF generator. As yet another example, the clock signal 202 is generated by the DSP of the HF RF generator and transmitted from the DSP of the HF RF generator to the DSP of the LF RF generator.

[0074] Graph 200 plots logic levels of a clock signal 202 versus time t. Logic levels, such as voltage levels, are plotted on the y-axis and time t is plotted on the x-axis. The x-axis is divided into equal time intervals. For example, the x-axis is divided into equal time intervals between two consecutive times, such as times ta and t(a+1), where a is an integer equal to 0. To illustrate, the x-axis is divided into a first time interval between times t0 and t1, and a second time interval between times t1 and t2. The first time interval is equal to the second time interval.

[0075] During cycle 1 of clock signal 202, clock signal 202 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t6. Also during cycle 1 of clock signal 202, clock signal 202 transitions from logic level 1 to logic level 0 at time t6 and remains at logic level 0 from time t6 to time t12.

[0076] Similarly, during cycle 2 of clock signal 202, clock signal 202 transitions from logic level 0 to logic level 1 at time t12 and remains at logic level 1 from time t12 to time t18. Also, during cycle 2 of clock signal 202, clock signal 202 transitions from logic level 1 to logic level 0 at time t18 and remains at logic level 0 from time t18 to time t24.

[0077] Cycle 2 is consecutive to cycle 1. For example, there is no other cycle of clock signal 202 between cycle 1 and cycle 2.

[0078] 2B is one embodiment of a graph 210 illustrating a parameter 212 of an LF RF signal, such as RF signal 139A or 139B (FIG. 1), generated by an LF RF generator (FIG. 1), and a parameter 214 of an HF RF signal, such as RF signal 138A or 138B (FIG. 1), generated by an HF RF generator (FIG. 1). Graph 210 plots the parameter versus time, t. The parameter is plotted on the y-axis and time, t, is plotted on the x-axis. Parameter 212 is plotted as a solid line and parameter 214 is plotted as a dashed line.

[0079] During cycle 1, the parameter 212 transitions from parameter level 0 to parameter level P1x at time t0 and remains at parameter level P1x from time t0 to time t4. The parameter level P1x is an example of a state S1x of the LF RF signal. Also during cycle 1, the parameter 212 transitions from parameter level P1x to parameter level 0 at time t4 and remains at parameter level 0 from time t4 to time t12. The parameter level 0 of the LF RF signal is an example of a state S0x of the LF RF signal. The parameter level P1x is greater than the parameter level 0.

[0080] Furthermore, during cycle 1, the parameter 214 transitions from parameter level 0 to parameter level P2y at time t0 and remains at parameter level P2y from time t0 to time t4. The parameter level P2y is an example of a state S1y of the HF RF signal. Also during cycle 1, the parameter 214 transitions from parameter level P2y to parameter level P1y at time t4 and remains at parameter level P1y from time t4 to time t8. The parameter level P1y is less than or equal to the parameter level P2y. The parameter level P1y is an example of a state S2y of the HF RF signal.

[0081] The parameter 212 transitions from parameter level P1x to parameter level 0 simultaneously or synchronously with the transition of the parameter 214 from parameter level P2y to parameter level P1y. For example, the parameter 212 begins transitioning from parameter level P1x to parameter level 0 at the same time t4 that the parameter 214 begins transitioning from parameter level P2y to parameter level P1y. As another example, the parameter 212 transitions from parameter level P1x to parameter level 0 at the same time t4 that the parameter 214 transitions from parameter level P2y to parameter level P1y. As yet another example, the parameter 212 transitions from parameter level P1x to parameter level 0 during the same period that the parameter 214 transitions from parameter level P2y to parameter level P1y. As another example, the parameter 212 transitions from parameter level P1x to parameter level 0 at the same time that the parameter 214 transitions from parameter level P2y to parameter level P1y.

[0082] Additionally, during cycle 1, parameter 214 transitions from parameter level P1y to parameter level 0 at time t8 and remains at parameter level 0 from time t8 to time t12. Parameter level 0 of the HF RF signal is an example of state S0y of the HF RF signal.

[0083] The parameter 212 periodically transitions between parameter levels P1x and 0 during each cycle of the clock signal 202 (FIG. 2A). For example, during cycle 2, at time t12, the parameter 212 transitions from parameter level 0 to parameter level P1x, remains at parameter level P1x from time t12 to time t16, transitions from parameter level P1x to parameter level 0 at time t16, and remains at parameter level 0 from time t16 to time t24.

[0084] The parameter 214 periodically transitions between parameter levels P2y, P1y, and 0 during each cycle of the clock signal 202 (FIG. 2A). For example, during cycle 2, at time t12, the parameter 214 transitions from parameter level 0 to parameter level P2y, remains at parameter level P2y from time t12 to time t16, transitions from parameter level P2y to parameter level P1y at time t16, remains at parameter level P1y from time t16 to time t20, transitions from parameter level P1y to parameter level 0 at time t20, and remains at parameter level 0 from time t20 to time t24.

[0085] As an example, a parameter level of a parameter of an RF signal is a zero-to-peak envelope of the RF signal, and is distinct from another parameter level of the RF signal. By way of example, a first parameter level of a parameter of an RF signal includes one or more values, such as an amplitude or magnitude of the parameter, and a second parameter level of a parameter of an RF signal includes one or more values, such as an amplitude or magnitude of the parameter. The one or more values ​​of the first parameter level do not include the one or more values ​​of the second parameter level. By way of further example, if the first parameter level is greater than the second parameter level, the minimum value of the value of the first parameter level is greater than the maximum value of the value of the second parameter level.

[0086] Note that during cycle 1, during times t8-t12, a deposition operation is performed on the sidewall of the mask layer of the substrate S. Additionally, during cycle 1, during times t4-t8, a trade-off occurs between the CD of the mask layer and the clogging of the mask layer. For example, when parameter level P1y is applied, the amount of clogging decreases and the CD of the mask layer increases. Also, during times t0-t4, an etching operation to etch a feature in the substrate S is performed smoothly due to the trade-off that occurs during times t4-t8. Similarly, during cycle 2, the etching operation, the trade-off, and the deposition operation are repeated in this order.

[0087] In one embodiment, instead of transitioning to parameter level 0 during the time interval from time t8 to t12, parameter 214 transitions to a low parameter level different from 0. For example, the low parameter level of parameter 214 is within 5-10% of the 0 parameter level. The low parameter level of parameter 214 is lower than parameter level P1y. Similarly, parameter 214 transitions to a low parameter level from cycle 2 onwards.

[0088] In one embodiment, instead of transitioning to parameter level 0 during the time interval from time t4 to t12, parameter 212 transitions to a low parameter level different from 0. For example, the low parameter level of parameter 212 is within 5-10% of the 0 parameter level. The low parameter level of parameter 212 is lower than parameter level P1x. Similarly, parameter 212 transitions to a low parameter level from cycle 2 onwards.

[0089] 2C is an embodiment of a graph 216 illustrating a parameter 212 of an LF RF signal and a parameter 218 of an HF RF signal generated by the HF RF generator (FIG. 1). Graph 216 plots the parameter versus time t. In graph 216, the parameter is plotted on the y-axis and time t is plotted on the x-axis. Parameter 212 is plotted as a solid line and parameter 218 is plotted as a dashed line.

[0090] During cycle 1, parameter 218 transitions from parameter level 0 to parameter level P2y at time t0 and remains at parameter level P2y from time t0 to time t4. Parameter level P2y of parameter 218 is an example of state S1y of the HF RF signal. Also during cycle 1, parameter 218 transitions from parameter level P2y to parameter level 0 at time t4 and remains at parameter level 0 from time t4 to time t8. Parameter level 0 is an example of state S0y. State S0y is of parameter 218 of the HF RF signal.

[0091] Parameter 212 transitions from parameter level P1x to parameter level 0 simultaneously or synchronously with parameter 218 transitioning from parameter level P2y to parameter level 0. For example, parameter 212 begins transitioning from parameter level P1x to parameter level 0 at the same time t4 that parameter 218 begins transitioning from parameter level P2y to parameter level 0. As another example, parameter 212 transitions from parameter level P1x to parameter level 0 at the same time t4 that parameter 218 transitions from parameter level P2y to parameter level 0. As yet another example, parameter 212 transitions from parameter level P1x to parameter level 0 during the same time period that parameter 218 transitions from parameter level P2y to parameter level 0. As another example, parameter 212 transitions from parameter level P1x to parameter level 0 at the same time that parameter 218 transitions from parameter level P2y to parameter level 0.

[0092] Additionally, during cycle 1, parameter 218 transitions from parameter level 0 to parameter level P1y at time t8 and remains at parameter level P1y from time t8 to time t12. Parameter level P1y of the HF RF signal is an example of state S2y of parameter 218 of the HF RF signal.

[0093] The parameter 218 periodically transitions between parameter levels P2y, 0, and P1y during each cycle of the clock signal 202 (FIG. 2A). For example, during cycle 2, at time t12, the parameter 218 transitions from parameter level 0 to parameter level P2y, remains at parameter level P2y from time t12 to time t16, transitions from parameter level P2y to parameter level 0 at time t16, remains at parameter level 0 from time t16 to time t20, transitions from parameter level 0 to parameter level P1y at time t20, and remains at parameter level P1y from time t20 to time t24.

[0094] Note that during cycle 1, during times t4-t8, a deposition operation is performed on the sidewall of the mask layer of the substrate S. Additionally, during cycle 1, during times t8-t12, a trade-off occurs between the CD of the mask layer and the clogging of the mask layer. Also, during times t0-t4, an etching operation is performed smoothly due to the trade-off that occurs during times t8-t12. Similarly, during cycle 2, the etching operation, deposition operation, and trade-off are repeated in this order.

[0095] In one embodiment, a direct current (DC) generator is used instead of the LF RF generator. The DC generator generates a DC signal that pulses between two parameter levels. For example, the DC signal pulses between two power levels, such as power levels P1x and 0, in the same manner that the RF signal generated by the LF RF generator pulses between two power levels. The DC generator is another example of a primary generator.

[0096] In one embodiment, instead of transitioning to parameter level 0 during the time interval from time t4 to t8, parameter 218 transitions to a low parameter level different from 0. For example, the low parameter level of parameter 218 is within 5-10% of the 0 parameter level. The low parameter level of parameter 218 is lower than parameter level P1y. Similarly, parameter 218 transitions to a low parameter level from cycle 2 onwards.

[0097] 3A is a diagram of an embodiment of a system 300 illustrating that, once the additional HF recipe of recipe signal 136B is determined, the additional HF recipe is applied to one or more substrates during processing of the substrate. The system 300 includes a host computer 108, an LF RF generator, an HF RF generator, a match 104, and a plasma chamber 106. The substrate S1 is mounted on a substrate support 116 and is located in a gap 120 formed between an upper electrode 118 and the substrate support 116.

[0098] Processor 112 transmits recipe signal 137B to the LF RF generator and transmits recipe signal 136B to the HF RF generator, where the LF RF generator stores the additional LF recipe received in recipe signal 137B, and the HF RF generator stores the additional HF recipe received in recipe signal 136B.

[0099] After transmitting the recipe signals 137B and 136B, the processor 112 generates and transmits a trigger signal 302 to the LF RF generator and the HF RF generator. An example of the trigger signal 302 is a digital pulse. Illustratively, the trigger signal 302 has a single pulse.

[0100] Upon receiving the trigger signal 302, the LF RF generator generates an RF signal 137B based on the additional LF recipe, and in response to receiving the trigger signal 302, the HF RF generator generates an RF signal 138B based on the additional HF recipe.

[0101] The modified RF signal 140B is generated from the RF signals 138A and 139B in the same manner as described above with reference to Figure 1. The modified RF signal 140B, when supplied to the plasma chamber 106 along with one or more process gases, generates or sustains a plasma in the plasma chamber 106. The plasma processes the substrate S1. Similarly, when the substrate S1 is replaced with another substrate, the modified RF signal 140B is again supplied at the output OM to process the other substrate.

[0102] 3B is a diagram of one embodiment of a desktop computer 350, which is an example of host computer 108 (FIG. 1). Desktop computer 350 illustrates the selection or entry of an additional HF recipe that includes a power level P2y for state S1y, a power level P1y for state S2y, and a power level 0 for state S0y. Additionally, desktop computer 350 illustrates the selection of a duty cycle for state S1y and a duty cycle for state S2y.

[0103] Desktop computer 350 includes a monitor 352, a keyboard 354, and a mouse 356. Keyboard 354 and mouse 356 are coupled to monitor 352. For example, keyboard 354 and mouse 356 are coupled to a CPU of monitor 352 via a wireless connection.

[0104] A CPU, a graphics processing unit (GPU), and a memory device are located within the housing of monitor 352. An example of a CPU is processor 112 (FIG. 1), and an example of a memory device is memory device 114 (FIG. 1). Monitor 352 includes a display screen that is part of the display device referenced above.

[0105] The GPU displays row 358 with fields 362, 364, and 366 for receiving multiple power levels for states S1y, S2y, and S0y. Additionally, the GPU displays another row 360 with fields 368 and 370 for receiving duty cycles for states S1y and S2y.

[0106] A user selects an up / down button displayed next to field 362 to select a power level P2y for state S1y of RF signal 138B (FIG. 3A). For example, a user selects a button on an input device to select an up / down button displayed next to field 362. Similarly, a user selects another up / down button displayed next to field 364 to select a power level P1y for state S2y of RF signal 138B, and selects an up / down button appearing next to field 366 to select a power level 0 for state S0y of RF signal 138B. By way of example, a user selects power level P1y to be between 100 and 1000 watts. By way of further example, a user selects power level P1y to be 100 watts, or 200 watts, or 250 watts, or 300 watts.

[0107] In addition, the user selects an up / down button that appears next to field 368 to select a duty cycle DC1y for state S1y and selects another up / down button that appears next to field 370 to select a duty cycle DC2y for state S2y. As one example, the user selects duty cycle DC2y to be between 1 and 3 times the duty cycle DC1y. As another example, the user selects duty cycle DC2y to be equal to duty cycle DC1y, or to be twice the duty cycle DC1y, or to be three times the duty cycle DC1y.

[0108] Upon receiving the selection of the duty cycles DC1y and DC2y, the CPU of the desktop computer 350 calculates the duty cycle DC0y for the state S0y of the RF signal 138B. For example, the CPU determines the duty cycle DC0y as the difference between 100 percent and the sum of the duty cycles DC1y and DC2y. Each of the duty cycles DC1y and DC2y is a corresponding percentage of the total period of the cycle of the clock signal 202 (FIG. 2A). For example, the duty cycle DC1y is a first percentage of the total period, and the duty cycle DC2y is a second percentage of the total period. The duty cycles DC1y, DC2y, and D0y are part of the additional HF recipe. Also, upon receiving the selection of the duty cycle DC1y, the CPU of the desktop computer 350 matches the duty cycle for the state S1x of the RF signal 139B to be equal to the duty cycle DC1y of the RF signal 138B.

[0109] In one embodiment, the monitor 352 displays various recipes for processing substrates in the plasma chamber 106 (FIG. 3A), one of the recipes including an additional HF recipe. A user selects the additional HF recipe via an input device. Upon receiving the selection of the additional HF recipe, the CPU of the desktop computer 350 generates a trigger signal 302 (FIG. 3A) and sends the trigger signal 302 to the HF RF generator to execute the additional HF recipe.

[0110] 4 is a diagram of an embodiment of an LF RF generator and an HF RF generator illustrating details of the RF generator. The LF RF generator includes a digital signal processor (DSP) DSPx, a parameter controller PS1x, a parameter controller PS0x, a duty cycle controller DCC1x, a duty cycle controller DCC0x, a frequency controller Fx, a driver DRVRx, and a power supply PSx. The HF RF generator includes a digital signal processor DSPy, a number of parameter controllers PS1y, PS2y, and PS0y, and a number of duty cycle controllers DCC1y, DCC2y, and DCC0y. The HF RF generator further includes a frequency controller Fy, a driver DRVRy, and a power supply PSy. The frequency controller may be referred to herein as an automatic frequency tuner (AFT).

[0111] An example of a controller as used herein includes a processor and a memory device. The processor of the controller is coupled to the memory device of the controller. Illustratively, the controller is a microcontroller or an integrated controller integrated in an ASIC or PLD. An example of an automatic frequency tuner as used herein includes a processor and a memory device. The processor of the automatic frequency tuner is coupled to the memory device of the automatic frequency tuner. An example of a driver as used herein includes one or more transistors. The one or more transistors are coupled to each other. An example of an RF power source includes an electronic oscillator, which is an electronic circuit that generates a periodic oscillating electronic signal, such as a sine wave.

[0112] The digital signal processor DSPx is coupled to the processor 112. The digital signal processor DSPx is coupled to the frequency controller Fx, the duty cycle controllers DCC1x and DCC0x, and the parameter controllers PS1x and PS0x. Each duty cycle controller of the LF RF generator is coupled to a corresponding parameter controller of the LF RF generator. For example, the duty cycle controller DCC1x is coupled to the parameter controller PS1x, and the duty cycle controller DCC0x is coupled to the parameter controller PS0x. The controllers PS1x, PS0x, and Fx are coupled to the driver DRVRx, which is coupled to the RF power supply PSx. The RF power supply PSx is coupled to the RF cable RFC1 at the output O1. The duty cycle controller DCC1x is coupled to the duty cycle controller DCC0x.

[0113] Similarly, the digital signal processor DSPy is coupled to the processor 112. The digital signal processor DSPy is coupled to the parameter controllers PS1y, PS2y, and PS0y, the duty cycle controllers DCC1y, DCC2y, and DCC0y, and the frequency controller Fy.

[0114] Each duty cycle controller DCC1y, DC2y, and DC0y is coupled to a corresponding one of the parameter controllers PS1y, PS2y, and PS0y. For example, the duty cycle controller DCC1y is coupled to the parameter controller PS1y, the duty cycle controller DCC2 is coupled to the parameter controller PS2y, and the duty cycle controller DCC0y is coupled to the parameter controller PS0y. The parameter controllers PS1y, PS2y, and PS0y and the frequency controller Fy are coupled to the driver DRVRy, which is coupled to the RF power supply PSy. The RF power supply PSy is coupled to the RF cable RFC2 at the output O2. The duty cycle controller DCC1y is coupled to the duty cycle controller DCC2y, and the duty cycle controller DCC2y is coupled to the duty cycle controller DCC0y.

[0115] The processor 112 embeds recipe information for the three states S1y, S2y, and S0y in a recipe signal 402, such as recipe signal 136A or 136B (FIG. 1). For example, the processor 112 assigns an identifier to each of the three states S1y, S2y, and S0y. In this example, the identifier for each of the three states may be referred to herein as an HF state identifier. Also, in this example, the processor 112 identifies whether the recipe information for the three states S1y, S2y, and S0y is a parameter level, a frequency, or a duty cycle for the state. In this example, the processor 112 further includes an execution order (e.g., a sequence) of the duty cycles for the states S1y, S2y, and S0y in the recipe signal 402. Illustratively, the processor 112 assigns a first HF parameter identifier to the parameter level for state S1y, assigns a first HF duty cycle identifier to the duty cycle for state S1y, and assigns an HF frequency identifier to the frequency of the HF RF generator. Also, in the example, processor 112 assigns a second HF parameter identifier to the parameter level for state S2y and assigns a second HF duty cycle identifier to the duty cycle for state S2y. In the example, processor 112 assigns a third HF parameter identifier to the parameter level for state S0y and assigns a third HF duty cycle identifier to the duty cycle for state S0y. Further, in the example, the sequence includes state S1y being executed before state S2y being executed before state S0y.

[0116] The digital signal processor DSPy receives the recipe signal 402 and extracts recipe information from the recipe signal 402. For example, the digital signal processor DSPy determines from the three HF state identifiers that the recipe information in the recipe signal 402 includes information about three states S1y, S2y, and S0y. By way of example, the digital signal processor DSPy determines whether the recipe signal 402 includes information about a parameter level for each state S1y, S2y, and S0y, or a duty cycle for the state, or a frequency for the state. Continuing with the example, the digital signal processor DSPy determines that the recipe signal 402 includes a parameter level for the state based on the HF parameter identifier for the state. Similarly, in the example, the digital signal processor DSPy determines that the recipe signal 402 includes a duty cycle for the state based on the HF duty cycle identifier for the state. Also, in the example, the digital signal processor DSPy determines that the recipe signal 402 includes a frequency for the state based on the HF frequency identifier for the state. In the example, the digital signal processor DSPy identifies the execution order of the duty cycles for states S1y, S2y, and S0y from the recipe signal 402.

[0117] The digital signal processor DSPy transmits recipe information for each state to a corresponding one of the controllers PS1y, PS2y, PS0y, DCC1y, DCC2y, DCC0y, and Fcy. For example, the digital signal processor DSPy transmits a parameter level for state S1y to the parameter controller PS1y, a parameter level for state S2y to the parameter controller PS2y, and a parameter level for state S0y to the parameter controller PS0y. Also, in this example, the digital signal processor DSPy transmits a duty cycle for state S1y to the duty cycle controller DCC1y, a duty cycle for state S2y to the duty cycle controller DCC2y, and a duty cycle for state S0y to the duty cycle controller DCC0y. Furthermore, in this example, the digital signal processor DSPy transmits frequencies for the three states S1y, S2y, and S0y to the frequency controller Fy. In this example, the digital signal processor DSPy sends the execution order of the duty cycles for state S1y to the duty cycle controller DCC1y, the execution order of the duty cycles for state S2y to the duty cycle controller DCC2y, and the execution order of the duty cycles for state S0y to the duty cycle controller DCC0y.

[0118] Each controller in the HF RF generator stores a portion of the recipe information received from the digital signal processor DSPy. For example, the processor of the parameter controller PS1y stores a parameter level for state S1y in a memory device of the parameter controller PS1y. Continuing with this example, the processor of the parameter controller PS2y stores a parameter level for state S2y in a memory device of the parameter controller PS2y. Also in this example, the processor of the parameter controller PS0y stores a parameter level for state S0y in a memory device of the parameter controller PS0y. Further in this example, the processor of the duty cycle controller DCC1y stores a duty cycle and execution order for state S1y in a memory device of the duty cycle controller DCC1y. Further in this example, the processor of the duty cycle controller DCC2y stores a duty cycle and execution order for state S2y in a memory device of the duty cycle controller DCC2y. In this example, the processor of the duty cycle controller DCC0y stores the duty cycle and execution order for state S0y in a memory device of the duty cycle controller DCC0y, and in this example, the processor of the frequency controller FCy stores the frequencies for states S1y, S2y, and S0y in a memory device of the frequency controller FCy.

[0119] In response to receiving the trigger signal 302, the digital signal processor DSPy sends an instruction to each of the controllers DCC1y, DCC2y, DCC0y, and Fy at the beginning of each pulse of a cycle of the clock signal 202 (FIG. 2). Upon receiving the instruction, each duty cycle controller DCC1y, DCC2y, and DC0y sends a command to the corresponding parameter controller PS1y, PS2y, and PS0y according to an execution order to generate an instruction signal for a period in the duty cycle. For example, in response to receiving the instruction, the duty cycle controller DCC1y sends a command to the parameter controller PS1y at a first time T1 to generate an instruction signal based on a parameter level for the state S1y, and the instruction signal is generated for a period TP1y in the duty cycle for the state S1y. Similarly, in this example, upon receiving the command, the duty cycle controller DCC2y waits for a period TP1y and sends a command to the parameter controller PS2y at a second time T2 to generate a command signal based on the parameter level for state S2y, the command signal being generated for a period TP2y within the duty cycle for state S2y. In this example, the command is sent to the parameter controller PS2y to transition the HF RF signal from the parameter level for state S1y to the parameter level for state S2y. Also, in this example, the period TP1y is sent from the duty cycle controller DCC1y to the duty cycle controller DCC2y. Furthermore, in this example, upon receiving the command, the duty cycle controller DCC0y waits for a period TP2y and sends a command to the parameter controller PS0y at a third time T3 to generate a command signal based on the parameter level for state S0y, the command signal being generated for a period within the duty cycle for state S0y. In this example, a command is sent to parameter controller PS0y to transition the HF RF signal from the parameter level for state S2y to the parameter level for state S0y.In this example, the period TP2y is transmitted from the duty cycle controller DCC2y to the duty cycle controller DCC0y. In this example, the third period follows the second period, which follows the first period. The second period occurs immediately after the first period and the period TP1, and the third period occurs immediately after the second period and the period TP2.

[0120] In response to receiving an instruction from the digital signal processor DSPy, the frequency controller FCy generates an instruction signal based on the frequency of the states S1y, S2y, and S0y, and transmits the instruction signal to the driver DRVRy. Upon receiving an instruction signal for the states S1y, S2y, and S0y from the controllers PS1y, PS2y, and PS0y and FCy, the driver DRVRy generates a current signal based on the instruction signal, and transmits the current signal to the power supply PSy. When the current signal is received from the driver DRVRy, the power supply PSy generates an RF signal 404 based on the current signal. An example of the RF signal 404 is the RF signal 138A (FIG. 1). Another example of the RF signal 404 is the RF signal 138B (FIG. 1). The RF signal 404 is supplied by the power supply PSy at the output O2 for transmission via the RF cable RFC2.

[0121] It should be noted that when a recipe signal 132 having two states instead of three is sent from the processor 112 to the digital signal processor DSPy, the digital signal processor DSPy does not send the information in the recipe signal 132 regarding state S2y to the controllers PS2y and DCC2y: there is no parameter level for state S2y sent to the parameter controller PS2y, and there is no duty cycle for state S2y sent to the duty cycle controller DCC2y.

[0122] The processor 112 embeds recipe information for the two states S1x and S0x in the recipe signal 403, such as recipe signal 137A or 137b (FIG. 1). For example, the processor 112 assigns an identifier to each of the two states S1x and S0x. The identifier for each of the two states S1x and S0x may be referred to herein as an LF state identifier. Also, in this example, the processor 112 identifies whether the recipe information for the two states S1x and S0x is a parameter level, a frequency, or a duty cycle for the state. In this example, the processor 112 further includes an execution order (e.g., a sequence) of the duty cycles for the states S1x and S0x in the recipe signal 403. Illustratively, the processor 112 assigns a first LF parameter identifier to the parameter level for the state S1x, assigns a first LF duty cycle identifier to the duty cycle for the state S1x, and assigns an LF frequency identifier to the frequency of the LF RF generator. Also, in the example, processor 112 assigns a second LF parameter identifier to the parameter level for state S0x and assigns a second LF duty cycle identifier to the duty cycle for state S0x. In the example, the order includes state S1x being executed before state S0x.

[0123] The digital signal processor DSPx receives the recipe signal 403 and extracts recipe information from the recipe signal 403. For example, the digital signal processor DSPx determines from the two LF state identifiers that the recipe information in the recipe signal 403 includes information about two states S1x and S0x. In this example, upon such determination, the digital signal processor DSPx determines whether the recipe signal 403 includes information about a parameter level for each state S1x and S0x, or a duty cycle for the state, or a frequency for the state. Continuing with this example, the digital signal processor DSPx determines that the recipe signal 403 includes a parameter level for the state based on the LF parameter identifier for the state. Similarly, in this example, the digital signal processor DSPx determines that the recipe signal 403 includes a duty cycle for the state based on the LF duty cycle identifier for the state. Also, in this example, the digital signal processor DSPx determines that the recipe signal 403 includes a frequency for the state based on the LF frequency identifier for the state. In this example, the digital signal processor DSPx identifies the execution order of the duty cycles for states S1x and S0x from the recipe signal 403.

[0124] The digital signal processor DSPx sends recipe information for each state to a corresponding one of the controllers PS1x, PS2x, and Fx. For example, the digital signal processor DSPx sends parameter levels for state S1x to the parameter controller PS1x, parameter levels for state S0x to the parameter controller PS0x, and frequencies for the two states S1x and S0x to the frequency controller Fx. In this example, the digital signal processor DSPx sends the execution order of the duty cycle for state S1x to the duty cycle controller DCC1x, and the execution order of the duty cycle for state S0x to the duty cycle controller DCC0x.

[0125] Each controller in the LF RF generator stores a portion of the recipe information received from the digital signal processor DSPx. For example, the processor of the parameter controller PS1x stores the parameter levels for state S1x in a memory device of the parameter controller PS1x. Continuing with this example, the processor of the parameter controller PS0x stores the parameter levels for state S0x in a memory device of the parameter controller PS0x. Further, in this example, the processor of the duty cycle controller DCC1x stores the duty cycle and execution order for state S1x in a memory device of the duty cycle controller DCC1x. Further, in this example, the processor of the duty cycle controller DCC0x stores the duty cycle and execution order for state S0x in a memory device of the duty cycle controller DCC0x. Also, in this example, the processor of the frequency controller FCx stores the frequencies for states S1x and S0x in a memory device of the frequency controller FCx.

[0126] In response to receiving the trigger signal 302, the digital signal processor DSPx sends an instruction to each of the controllers PS1x, PS0x, DCC1x, DCC0x, and Fx at the beginning of each pulse of a cycle of the clock signal 202 (FIG. 2). Upon receiving the instruction, each duty cycle controller DCC1x and DC0x sends a command to the corresponding parameter controller PS1x and PS0x according to the execution order to generate an instruction signal for a period in the duty cycle. For example, in response to receiving the instruction, the duty cycle controller DCC1x sends a command to the parameter controller PS1x at a first time T1 to generate an instruction signal based on a parameter level for state S1x, and the instruction signal is generated for a period TP1y in the duty cycle for state S1x. Similarly, in this example, upon receiving the command, the duty cycle controller DCC0x waits for a period TP1y and sends a command to the parameter controller PS0x at a second time T2 to generate a command signal based on the parameter level for state S0x, the command signal being generated for a period within the duty cycle for state S0x. In this example, the period TP1y is sent from the duty cycle controller DCC1y to the duty cycle controller DCC0x. Also in this example, a command is sent to the parameter controller PS0x to transition the LF RF signal from the parameter level for state S1x to the parameter level for state S0x. In this example, when the command is sent to the parameter controller PS0x at the second time T2, the RF signal 405 generated by the LF RF generator transitions from the parameter level for state S1x to the parameter level for state S0x in synchronization with the transition of the RF signal 404 from the parameter level for state S1y to the parameter level for state S2y.

[0127] In response to receiving an instruction from the digital signal processor DSPx, the frequency controller FCx generates an instruction signal based on the frequency of the states S1x and S0x and sends the instruction signal to the driver DRVRx. Upon receiving the instruction signals for the states S1x and S0x from the controllers PS1x, PS0x, and FCy, the driver DRVRx generates a current signal based on the instruction signal and sends the current signal to the power supply PSx. When the current signal is received from the driver DRVRx, the power supply PSx generates an RF signal 405, such as the RF signal 139A or 139B (FIG. 1), based on the current signal. The RF signal 405 is supplied by the power supply PSx at the output O1 for transmission via the RF cable RFC1.

[0128] In one embodiment, the parameter 218 (FIG. 2C) is generated. In this embodiment, in response to receiving the trigger signal 302, the digital signal processor DSPy sends an instruction to each of the controllers DCC1y, DCC0y, DCC2y, and Fy at the beginning of each pulse of the cycle of the clock signal 202 (FIG. 2). Upon receiving the instruction, each duty cycle controller DCC1y, DCC0y, DCC2y sends a command to the corresponding parameter controller PS1y, PS0y, and PS2y according to the execution order to generate an instruction signal for a period in the duty cycle. For example, in response to receiving the instruction, the duty cycle controller DCC1y sends a command to the parameter controller PS1y at a first time T1.1 to generate an instruction signal based on the parameter level for the state S1y, and the instruction signal is generated for a period TP1.1y in the duty cycle for the state S1y. Similarly, in this example, upon receiving the command, the duty cycle controller DCC0y waits for a period TP1.1y and sends a command to the parameter controller PS0y at a second time T2.1 to generate a command signal based on the parameter level for state S0y, the command signal being generated for a period TP2.1y within the duty cycle for state S0y. In this example, the command is sent to the parameter controller PS0y to transition the HF RF signal from the parameter level for state S1y to the parameter level for state S0y. Also, in this example, the period TP1.1y is sent from the duty cycle controller DCC1y to the duty cycle controller DCC0y. Furthermore, in this example, upon receiving the command, the duty cycle controller DCC2y waits for a period TP2.1y and sends a command to the parameter controller PS2y at a third time T3.1 to generate a command signal based on the parameter level for state S2y, the command signal being generated for a period TP3.1y within the duty cycle for state S2y.In this example, a command is sent to parameter controller PS2y to transition the HF RF signal from the parameter level for state S0y to the parameter level for state S2y. In this example, a period TP2.1y is sent from duty cycle controller DCC0y to duty cycle controller DCC2y. In this example, the third time follows the second time, which follows the first time. Also in this example, the second time occurs immediately after the first time and period TP1.1, and the third time occurs immediately after the second time and period TP2.1.

[0129] In one embodiment, the duty cycle controller DCC1x is coupled to the duty cycle controller DCC1y. The processor of the duty cycle controller DCC1x accesses the duty cycle for the state S1y from the memory device of the duty cycle controller DCC1y. Upon accessing the duty cycle for the state S1y, the processor of the duty cycle controller DCC1x determines whether the duty cycle for the state S1x matches the duty cycle for the state DCC1y. Upon determining that the duty cycles for the states S1x and S1y do not match, the processor of the duty cycle controller DCC1x controls the duty cycle for the state S1x to match the duty cycle for the state S1y. On the other hand, upon determining that the duty cycles for the states S1x and S1y match, the processor of the duty cycle controller DCC1x does not control the duty cycle for the state S1x to match the duty cycle for the state S1y.

[0130] 5A is a diagram of an embodiment of a substrate 500 illustrating the effect of etching operations performed during states S1y and S1x on the substrate 500. The substrate 500 is an example of a substrate S (FIG. 1) or a substrate S1 (FIG. 3A). The substrate 500 has a stack layer 502, such as a NAND stack, and a mask layer 504.

[0131] The mask layer 504 has a profile 503. An example of a profile of a mask layer is a side view of the mask layer. The side view is a two-dimensional view that shows the shape of the mask layer. The shape can include a height along the y-axis and a width along the x-axis. The height is the vertical direction and the width is the horizontal direction.

[0132] A mask layer 504 is formed on top of the stack layer 502. As an example, the stack layer 502 includes an oxide-polysilicon-oxide-polysilicon (OPOP) layer at its bottom. The stack layer 502 further includes a drain side select gate (SGD) located on top of the OPOP layer and a nitride layer located on top of the SGD layer. The mask layer 504 is formed on top of the nitride layer.

[0133] Passivation layers 506A and 506B are formed on sidewalls SW1 and SW2 of the mask layer 504. For example, passivation layer 506A is adjacent to sidewall SW1 of the mask layer 504, and passivation layer 506B is adjacent to sidewall SW2 of the mask layer 504. Illustratively, there is no layer between passivation layer 506A and sidewall SW1, and there is no layer between passivation layer 506B and sidewall SW2. Passivation layer 506A faces passivation layer 506B through a gap between passivation layers 506A and 506B. Sidewalls SW1 and SW2 of the mask layer 504 may be referred to herein as a neck region or a neck of the substrate 500. The passivation layer includes a polymer material deposited on the sidewalls of the mask layer 504. For example, the passivation layers 506A and 506B may include material of the stack layer 502 sputtered from etching the stack layer 502, or material from the process gases, or a combination thereof.

[0134] States S1y and S1x etch stack layer 502 and play little role in reducing passivation layers 506A and 506B. If passivation layers 506A and 506B are not reduced, mask clogging occurs and the horizontal distance 508 between layers 506A and 506B decreases. For example, passivation layers 506A and 506B grow until there is no space between passivation layers 506A and 506B. Horizontal distance 508 is an example of the CD of mask layer 504. During application of states S1y and S1x, horizontal distance 508 is the minimum distance between passivation layers 506A and 506B.

[0135] 5B is a diagram of one embodiment of a substrate 500 illustrating the effect of states S2y and S0x on the substrate 500. While states S2y and S0x occur simultaneously or in parallel, a horizontal distance 510 between passivation layers 506A and 506B increases compared to horizontal distance 508 (FIG. 5A). Horizontal distance 510 is another example of a CD of the mask layer 504. During application of states S2y and S0x, horizontal distance 510 is the minimum distance between passivation layers 506A and 506B. Mask layer 504 has a profile 505.

[0136] FIG. 5C is a diagram of one embodiment of a substrate 500 illustrating the effect of states S0y and S0x on the substrate 500. During states S0y and S0x, a deposition operation is performed on the substrate 500. While states S0y and S0x occur, a horizontal distance 512 between the passivation layers 506A and 506B is reduced compared to horizontal distance 510 (FIG. 5B). The horizontal distance 512 is another example of a CD of the mask layer 504 having a profile 507. During the application of states S0y and S0x, the horizontal distance 512 is the minimum distance between the passivation layers 506A and 506B. By introducing states S2y and S0x, the horizontal distance 510 is achieved, thus increasing the CD of the mask layer 504. States S2y and S0x reduce the likelihood that the mask layer 504 will be clogged by the passivation layers 506A and 506B.

[0137] The embodiments described herein may be practiced with a variety of computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0138] In some embodiments, the controller is part of a system that may be part of the examples described above. Such systems include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics for controlling pre-, during, and post-processing operations of semiconductor wafers or substrates. Such electronics may be referred to as a "controller" and may control various components or subparts of one or more systems. The controller is programmed to control any of the processes disclosed herein depending on the processing requirements and / or type of system. Such processes include delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer loading and unloading from tools and other transfer tools coupled or interlocked with the system, and / or wafer loading and unloading from load locks.

[0139] Broadly, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors, i.e., microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, coefficients, variables, etc. for performing a particular process on or for a semiconductor wafer or in a system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or one or more processing steps in the fabrication of a wafer die.

[0140] The controller, in some embodiments, is part of a computer that is integrated or coupled with the system or otherwise networked to the system, or is coupled to such a computer, or a combination thereof. For example, the controller is in the "cloud" and is all or part of a fab host computer system. This allows remote access of wafer processing. The computer allows remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, change parameters of a current process, set up processing steps following the current process, or initiate a new process.

[0141] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a network. Such a network includes a local network or the Internet. The remote computer includes a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, which specifies parameters, coefficients, and / or variables of each of the processing steps to be performed during one or more operations. It should be understood that the parameters, coefficients, and / or variables are specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller is distributed, for example, by including one or more individual controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein). Examples of distributed controllers for such purposes include one or more integrated circuits on the chamber that communicate with one or more integrated circuits that are remotely located (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0142] In various embodiments, exemplary systems to which the methods may be applied include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0143] It is further noted that in some embodiments, the above operations apply to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are coupled to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome coil, a flat coil, etc.

[0144] As described above, depending on the process step or steps being performed by the tool, the host computer communicates with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to and from tool locations and / or load ports within the semiconductor manufacturing factory.

[0145] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0146] Some of the embodiments also relate to hardware units or devices for performing these operations. The device is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer is operable for its dedicated purpose while performing other processes, program execution or routines that are not part of its dedicated purpose.

[0147] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over a computer network. If data is obtained over a computer network, the data may be processed by other computers on the computer network (e.g., a cloud of computational resources).

[0148] One or more embodiments may also be fabricated as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit (e.g., memory device, etc.) that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disk ROM (CD-ROM), CD recordable (CD-R), CD rewriteable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, a non-transitory computer readable medium includes a computer readable tangible medium distributed over a network-coupled computer system such that the computer readable code is stored and executed in a distributed manner.

[0149] Although the method operations above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between each operation, or each method operation is coordinated to occur at slightly different times, or distributed across a system that allows each method operation to occur at various intervals, or performed in an order different than that described above.

[0150] It should further be noted that in one embodiment, one or more features of any embodiment described above may be combined with one or more features of any other embodiment also described above without departing from the scope described in the various embodiments described in this disclosure.

[0151] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Thus, the present embodiments should be considered as illustrative and not restrictive, and the embodiments should not be limited to the details set forth herein.

Claims

1. 1. A method for controlling a critical dimension of a mask layer of a substrate, comprising: receiving, by a primary generator, a first primary parameter level and a second primary parameter level; receiving, by a secondary radio frequency (RF) generator, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level; generating, by the primary generator, a primary signal having the first primary parameter level; transitioning the primary signal from the first primary parameter level to the second primary parameter level by the primary generator during a clock cycle; generating, by the secondary RF generator, a secondary RF signal having the first secondary parameter level; transitioning, by the secondary RF generator, the secondary RF signal from the first secondary parameter level to the second secondary parameter level during the clock cycle; transitioning, by the secondary RF generator, the secondary RF signal from the second secondary parameter level to the third secondary parameter level during the clock cycle; Including, the transition of the primary signal from the first primary parameter level to the second primary parameter level occurs synchronously with the transition of the secondary RF signal from the first secondary parameter level to the second secondary parameter level; the second secondary parameter level is generated to control the critical dimension of the mask layer. method.

2. 2. The method of claim 1 , The method, wherein the second secondary parameter level ranges from 100 watts to 1000 watts.

3. 2. The method of claim 1 , The method further comprising receiving a measurement of the critical dimension, wherein the second secondary parameter level is based on the measurement of the critical dimension.

4. 4. The method of claim 3, The measurement of the critical dimension is less than a predetermined critical dimension, and the method further comprises: modifying a fourth secondary parameter level to the second secondary parameter level after receiving an indication that the measurement of the critical dimension is less than the predetermined critical dimension. A method comprising:

5. 5. The method of claim 4, The method further comprising altering a duty cycle of the fourth secondary parameter level after receiving the indication that the measured value of the critical dimension is less than the predetermined critical dimension.

6. 2. The method of claim 1 , The method of claim 1, wherein the second secondary parameter level has a duty cycle that is between 1 and 3 times the duty cycle of the first secondary parameter level.

7. 2. The method of claim 1 , The method of claim 1, wherein the second secondary parameter level has a duty cycle that is between 4 and 5 times the duty cycle of the first secondary parameter level.

8. 2. The method of claim 1 , The method of claim 1, wherein the critical dimension comprises a distance between a first passivation layer adjacent to the mask layer and a second passivation layer adjacent to the mask layer, the first passivation layer facing the second passivation layer.

9. 2. The method of claim 1 , the transition of the primary signal from the first primary parameter level to the second primary parameter level is performed synchronously with the transition of the secondary RF signal from the first secondary parameter level to the second secondary parameter level when the transition of the primary signal from the first primary parameter level to the second primary parameter level is controlled to be initiated simultaneously with the transition of the secondary RF signal from the first secondary parameter level to the second secondary parameter level.

10. 2. The method of claim 1 , a deposition operation is performed on the mask layer during a first portion of the third secondary parameter level and the second primary parameter level, a trade-off between the critical dimension and blockage of the mask layer occurs during a second portion of the second secondary parameter level and the second primary parameter level, and the substrate is etched during the first primary parameter level and the first secondary parameter level.

11. 1. A controller for controlling a critical dimension of a mask layer, comprising: receiving a first primary parameter level and a second primary parameter level; receiving a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level; controlling a primary generator to generate a primary signal having the first primary parameter level; controlling the primary generator to transition the primary signal from the first primary parameter level to the second primary parameter level during a clock cycle; controlling a secondary radio frequency (RF) generator to generate a secondary RF signal having the first secondary parameter level; controlling the secondary RF generator to transition the secondary RF signal from the first secondary parameter level to the second secondary parameter level during the clock cycle; Controlling the secondary RF generator to transition the secondary RF signal from the second secondary parameter level to the third secondary parameter level during the clock cycle. It is configured as follows: the primary signal is controlled to transition from the first primary parameter level to the second primary parameter level synchronously with the transition of the secondary RF signal from the first secondary parameter level to the second secondary parameter level; The second secondary parameter level is generated to control the critical dimension of the mask layer. A processor; a memory device coupled to the processor, the memory device configured to store the first primary parameter level, the second primary parameter level, the first secondary parameter level, the second secondary parameter level, and the third secondary parameter level; A controller comprising:

12. 12. The controller of claim 11, The second secondary parameter level ranges from 100 watts to 1000 watts.

13. 12. The controller of claim 11, The processor is configured to receive a measurement of the critical dimension, and the second secondary parameter level is based on the measurement of the critical dimension.

14. 14. The controller of claim 13, The measurement of the critical dimension is less than a predetermined critical dimension, and the processor: modifying a fourth secondary parameter level to the second secondary parameter level after receiving an indication that the measurement of the critical dimension is less than the predetermined critical dimension; The controller is configured as follows:

15. 15. The controller of claim 14, The controller, wherein the processor is configured to alter a duty cycle of the fourth secondary parameter level after receiving the indication that the measured value of the critical dimension is less than the predetermined critical dimension.

16. 12. The controller of claim 11, The second secondary parameter level has a duty cycle that is between 1 and 3 times the duty cycle of the first secondary parameter level.

17. 1. A plasma system for controlling critical dimensions of a mask, comprising: a primary generator configured to receive a first primary parameter level and a second primary parameter level; a secondary radio frequency (RF) generator configured to receive a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level; the primary generator is configured to generate a primary signal having the first primary parameter level; the primary generator is configured to transition the primary signal from the first primary parameter level to the second primary parameter level during a clock cycle; the secondary RF generator configured to generate a secondary RF signal having the first secondary parameter level; the secondary RF generator is configured to transition the secondary RF signal from the first secondary parameter level to the second secondary parameter level during the clock cycle; the secondary RF generator is configured to transition the secondary RF signal from the second secondary parameter level to the third secondary parameter level during the clock cycle; the transition of the primary signal from the first primary parameter level to the second primary parameter level occurs synchronously with the transition of the secondary RF signal from the first secondary parameter level to the second secondary parameter level; The second secondary parameter level is generated to control the critical dimension of the mask. a secondary RF generator; an impedance matching circuit coupled to the primary generator and the secondary RF generator, the impedance matching circuit configured to receive the primary signal and the secondary RF signal and to output a modified RF signal; a plasma chamber coupled to the impedance matching circuit, the plasma chamber configured to receive the modified RF signal and control the critical dimension of the mask; A plasma system comprising:

18. 20. The plasma system of claim 17, The plasma system, wherein the second secondary parameter level ranges from 100 watts to 1000 watts.

19. 20. The plasma system of claim 17, 13. The plasma system, further comprising: a host computer coupled to the primary generator and the secondary RF generator, the host computer configured to receive a measurement of the critical dimension, and the second secondary parameter level is based on the measurement of the critical dimension.

20. 20. The plasma system of claim 19, the measurement of the critical dimension is less than a predetermined critical dimension, and the host computer modifying a fourth secondary parameter level to the second secondary parameter level after receiving an indication that the measurement of the critical dimension is less than the predetermined critical dimension; It is configured as follows: the host computer is configured to modify a duty cycle of the fourth secondary parameter level after receiving the indication that the measured value of the critical dimension is less than the predetermined critical dimension. Plasma system.

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