Contact structure for direct bonding

Abstract

A bonded structure is disclosed. The bonded structure can include a first element having a first conductive feature and a first non-conductive region. The first conductive feature can include a fine grain metal having an average grain size of 500 nm or less. The bonded structure can include a second element having a second conductive feature and a second non-conductive region. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the second non-conductive region is directly bonded to the second non-conductive region without an intervening adhesive.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 156,290, entitled "Contact Structure for Direct Bonding," filed March 3, 2021, the entire contents of which are incorporated herein by reference.

[0002] (Technical field) The present invention relates to contact structures for direct bonding. [Background technology]

[0003] Semiconductor devices, such as semiconductor wafers, can be stacked and directly bonded to one another without adhesives. For example, in some hybrid direct bond structures, the non-conductive field regions of the devices can be directly bonded to one another and the corresponding conductive contact structures can be directly bonded to one another. Summary of the Invention [Problem to be solved by the invention]

[0004] In some applications, it can be difficult to create a reliable electrical connection between opposing contact pads, and therefore there remains a continuing need for improved contact structures for direct bonding.

[0005] Specific implementations will now be described with reference to the following drawings, which are provided by way of example and not by way of limitation. [Brief description of the drawings]

[0006] [Figure 1A] 1A-1C are schematic cross-sectional side views of a structure at an intermediate stage in forming a first element. [Figure 1B] FIG. 2 is a schematic cross-sectional side view of a first element before bonding. [Diagram 2] 1 is a schematic cross-sectional side view of a junction structure having a first element and a second element. [Diagram 3] FIG. 2 is a schematic top view of coarse-grained copper showing the particles of the coarse-grained copper. [Figure 4] FIG. 2 is a schematic top view of fine-grain copper showing particles of fine-grain copper according to one embodiment. [Diagram 5] 4 is a graph showing average resistance versus temperature for fine grain copper pads and conventional copper pads. [Figure 6A] FIG. 2 is a schematic cross-sectional side view of a joint structure. [Figure 6B] 1 is a schematic cross-sectional side view of a joint structure according to one embodiment; [Figure 6C] 4 is a schematic cross-sectional side view of a joint structure according to another embodiment. [Figure 6D] 4 is a schematic cross-sectional side view of a joint structure according to another embodiment. [Figure 7A] 1A-1D are top-down electron backscatter diffraction (EBSD) images of conventional and coarse-grained copper pads. [Figure 7B] Top-down EBSD image of a nanotwinned copper pad. [Figure 7C] 1 is a top-down EBSD image of a fine grain copper pad according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present disclosure describes a method for directly bonding conductive pads in electronic devices using engineered metal grain structures. Such grain designs can be advantageous for direct metal bonding, such as direct hybrid bonding. For example, two or more semiconductor devices (integrated device dies, wafers, etc.) can be stacked or bonded together to form a bonding structure. The conductive contact pads of one device can be electrically connected to corresponding conductive contact pads of another device. Any suitable number of devices can be stacked in the bonding structure. The methods and bond pad structures described herein can be useful in other contexts as well.

[0008] In some embodiments, the elements are directly bonded to each other without adhesive. In various embodiments, the non-conductive (e.g., semiconductive or inorganic dielectric) material of the first element can be directly bonded to the corresponding non-conductive (e.g., semiconductive or inorganic dielectric) field area of ​​the second element without adhesive. In various embodiments, the conductive area (e.g., metal pad or contact structure) of the first element can be directly bonded to the corresponding conductive area (e.g., metal pad or contact structure) of the second element without adhesive. The non-conductive material may be referred to as the non-conductive bonding area or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element with adhesive-free bonding techniques using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference for all purposes. Additional examples of hybrid bonding can be found throughout U.S. Patent No. 11,056,390, the entire contents of which are incorporated herein by reference for all purposes. In another application, in a bonding structure, the non-conductive material of a first element can be directly bonded to the conductive material of a second element, so that the conductive material of the first element is intimately interlocked with the non-conductive material of the second element. Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or may include materials containing carbon, such as silicon carbide, silicon oxycarbonitride, low-K dielectric materials, SICOH, silicon carbonitride, or diamond-like carbon, or diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic, despite the carbon content.

[0009] In various embodiments, a direct bond can be formed without the aid of an adhesive. For example, the bonding surfaces of the semiconductor or dielectric can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the bonding surfaces. In some embodiments, the bonding surfaces can be terminated with a chemical species after or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces, and a termination process can provide additional chemical species at the bonding surfaces that improve the bond energy during direct bonding. In some embodiments, activation and termination treatments are provided in the same step, e.g., a plasma or wet etchant that activates and terminates the bonding surfaces. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination chemical species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, one or more fluorine peaks can be present near the layers and / or bonding interfaces, particularly the dielectric bonding interfaces. Thus, in a direct bond structure, the bond interface between two non-conductive materials can include a very smooth interface with a higher nitrogen content and / or fluorine peak at the bond interface. Further examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference for all purposes.

[0010] In various embodiments, the conductive contact pads of the first element can also be directly bonded to the corresponding conductive contact pads of the second element. For example, direct hybrid bonding techniques can be used to provide conductor-to-conductor direct bonds along a bonding interface that includes the covalently directly bonded dielectric-to-dielectric surfaces prepared as described above. In various embodiments, conductor-to-conductor (e.g., contact pad-to-contact pad) direct bonds and dielectric-to-dielectric hybrid bonds can be formed using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated herein by reference for all purposes. The bonding structures described herein can also be useful for direct metal bonding without bonding of non-conductive regions, or other bonding techniques.

[0011] In some embodiments, inorganic dielectric bonding surfaces can be prepared and bonded directly to each other without an adhesive as described above. The conductive contact pads (which can be surrounded by a field region of non-conductive dielectric) can also be bonded directly to each other without an adhesive. In some embodiments, each contact pad can be recessed below an outer surface (e.g., top surface) of the dielectric field region or non-conductive bonding region by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. The coefficient of thermal expansion (CTE) of the dielectric material can be, for example, in the range of 0.1 ppm / °C to 5 ppm / °C, and the CTE of the conductive material can be in the range of 6 ppm / °C to 40 ppm / °C, or in the range of 8 ppm / °C to 30 ppm / °C. The difference between the CTE of the dielectric material and the CTE of the conductive material inhibits subsequent lateral expansion of the conductive material. The non-conductive bonding regions can be bonded directly to each other without an adhesive at room temperature in some embodiments, and the bonded structure can then be annealed. When annealed, the contact pads can expand against the non-conductive bonding area to contact each other and form a direct metal-metal bond. Advantageously, hybrid bonding technologies such as Direct Bond Interconnect, or DBI®, available from Xperi, Inc., San Jose, Calif., allow for a high density of pads (e.g., small or fine pitch on a regular array) connected across the direct bond interface. In various embodiments, the conductive feature (e.g., contact pad) can include copper, although other metals may be suitable. Thus, when copper is used as a conductive feature material in this disclosure, copper is an example of a conductive feature material, and other suitable metals may be implemented.

[0012] Thus, in a direct bonding process, a first element can be directly bonded to a second element without an intervening adhesive. In some configurations, the first element can include a singulated element, such as a singulated integrated device die. In other configurations, the first element can include a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can include a singulated element, such as a singulated integrated device die. In other configurations, the second element can include a carrier or substrate (e.g., a wafer). In some embodiments, the singulated element can include a direct or indirect transition semiconductor material. In some embodiments, multiple dies with different CTEs can be bonded onto the same carrier. In some embodiments, the CTE of the substrate of the bonded dies is similar to the CTE of the substrate of the carrier. In another embodiment, the CTE of the substrate of the bonded dies is different from the CTE of the substrate of the carrier. The difference in CTE between the bonded dies, or between the bonded die and the carrier, may be in the range of 1 ppm / °C to 70 ppm / °C, and may be less than 30 ppm / °C, such as less than 12 ppm / °C.

[0013] As described herein, the first and second elements can be directly bonded to each other without an adhesive, which is different from a deposition process. Thus, the first and second elements can include non-deposited elements. Furthermore, unlike deposited layers, the direct bond structure can include defect areas with nanovoids present along the bond interface. The nanovoids can be formed due to activation (e.g., exposure to plasma) of the bonded surfaces. As described above, the bond interface can include concentrations of material from the activation and / or final chemical treatment process. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In embodiments utilizing oxygen plasma for activation, an oxygen peak or oxygen-rich layer can be formed at the bond interface. In some embodiments, the bond interface can include inorganic non-conductive materials terminated with nitrogen, such as nitrogen-terminated silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, etc. Thus, the surface of the bond layer can include silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, and the level of nitrogen present at the bond interface represents a nitrogen termination for at least one of the elements prior to direct bonding. Except for nitrogen-containing dielectrics, the nitrogen content of non-conductive materials typically has a gradient that peaks at or near the surface. In some embodiments, nitrogen and nitrogen-related moieties may be absent from the bond interface. As described herein, the direct bond may include a covalent bond that is stronger than a van der Waals bond. The bonding layer may also include a polished surface that has been planarized to a high degree of smoothness.

[0014] The grain size of the conductive features can affect the tendency of the conductive features to bond at relatively low temperatures and the bond strength between the bonded conductive features. In general, the grain size near the bond interface can be observed at the surface of the conductive features (before bonding) or in a cross-sectional view of the conductive features. One goal is to allow the grain boundaries of the conductive features on the opposing elements to cross each other to facilitate mobility and thus direct bonding, and the grain size can be measured relative to the lateral size of the conductive features to be bonded. The conductive features can include metallic features such as copper contact pads or lines. Conductive features with relatively small grains can be energetically unstable, and compared to larger grains, small grains can grow into larger grains with a much lower thermal budget for a given isothermal annealing condition or lower temperature for a given time. Thus, conductive features with relatively small grains can be bonded together with relatively high bond strength even with minimal heating, and lower annealing temperatures can be achieved for direct bonding with relatively small grains. The bond strength between such conductive features with relatively small grain sizes is greater than the bond strength between conductive features with single crystal or large grain sizes for a given annealing temperature. Excessive impurities within the grains and / or at the grain boundaries can impede or inhibit grain growth.

[0015] The conductive feature may include a fine-grain metal plating film, such as a fine-grain copper plating film. A fine-grain copper plating film is a film having an average grain size of 50 nm to 500 nm, e.g., an average grain size in the range of 10 nm to 500 nm, 10 nm to 300 nm, 10 nm to 150 nm, 10 nm to 100 nm, 10 nm to 75 nm, or 10 nm to 50 nm. Currently, copper plating films for standard wiring processes in integrated circuits have an average grain size in the range of 1 μm to 10 μm. The number of grains in a conductive feature may depend at least in part on the feature size of the conductive feature. For example, if a standard copper conductive feature has a feature size of 0.5 μm, the standard copper conductive feature will include 1 to 3 grains at the bond interface. If the feature size of the fine-grain metal conductive feature is 0.5 μm, the fine-grain metal conductive feature may include grains 5 to 10 times larger than a standard copper conductive feature of 0.5 μm.

[0016] The fastest diffusion path for atoms of the conductive features may depend on temperature, the nature of the microstructure, microstructural defects, hardness, grain size, impurity content of the film, film stress, interfacial adhesion, surface mobility of atoms, etc. Lattice diffusion may have the highest activation energy of about 2 eV for copper, for example. The activation energy of diffusion along grain boundaries and interfaces is significantly lower than that of lattice diffusion (e.g., about 0.7 eV for Cu, as an example). Thus, in some embodiments, lattice diffusion may be the slowest path of atomic mass transfer, and grain boundary diffusion may be the fastest diffusion path of atomic mass transfer. Also, the activation energy for creep of copper may be similar to the value of grain boundary diffusion. Furthermore, the creep rate may vary inversely as the cube of the grain size.

[0017] Smaller grains, because of their size, can have much larger grain boundary surface areas than larger grains. The grain boundary surface area of ​​a small grain conductive feature can be 10, 50, 250, or even 1000 times larger than the grain boundary surface area of ​​a large grain conductive feature. A conductive feature with a relatively small grain can have a higher creep rate than a conductive feature with a relatively large or coarse grain. A high creep rate can contribute to a higher tendency to bond compared to a low creep rate. A relatively small grain can be referred to as a fine grain. For example, a grain having a maximum width of less than 10 nm, less than 50 nm, less than 100 nm, less than 300 nm, or less than 500 nm can be defined as a fine grain. A coarse grain can typically have a maximum width of 1 μm to 2 μm or more. The higher creep rate of fine grains and the relatively large grain boundary surface area of ​​fine grains, which can contribute to a relatively large diffusion path with low activation energy, are particularly advantageous in relatively small conductive features or structures, such as microstructures with a maximum dimension of less than 5 μm (e.g., 1 μm), because such structures can be bonded at lower temperatures compared to structures with conductive features having larger grains. Conductive features, such as bond pads, vias (e.g., TSVs), traces, or through-substrate electrodes of embodiments described herein, can have a maximum lateral dimension in the range of about 0.01 μm to 25 μm, about 0.1 μm to 10 μm, about 0.5 μm to 8 μm, about 2 μm to 5 μm, about 1 μm to 3 μm, or about 0.01 μm to 1 μm. One example of a relatively small bond pad is, for example, about 100 μm. 2 Less than 50μm 2 Less than 20μm 2 Less than 10μm 2 Less than and 2μm 2 The conductive area to be bonded or the entire exposed area of ​​the conductive feature at the bond interface can be less than 100 μm.

[0018] In various embodiments, the metal-metal bond between the contact pads can be bonded such that grains of the conductive material (e.g., copper grains) grow into one another across the bond interface. In some embodiments, the copper can have grains oriented vertically along the (111) crystal plane to enhance diffusion of the copper across the bond interface. However, in some embodiments, other crystal planes of the copper can be oriented vertically to the contact pad surface. The non-conductive bond interface can extend substantially completely to at least a portion of the bonded contact pad, so that there is substantially no gap between the non-conductive bond regions at or near the bonded contact pads. In some embodiments having fine-grained direct bond interconnects, very small voids can nucleate along or close to the bond interface. The width of the voids in a cross section at or near the bond interface relative to the conductive features of the bonded elements can be, for example, less than 5%, less than 1%, or less than 0.1% of the cross-sectional width. In some embodiments, a barrier layer can be provided under the contact pads (which can include, for example, copper). However, in alternative embodiments, there may be no barrier layer underneath the contact pads, as described, for example, in U.S. Pat. No. 11,195,748, which is incorporated herein by reference in its entirety for all purposes.

[0019] Annealing temperatures and annealing times to form metal-metal direct bonds or thermal budgets are critical in the fabrication of direct bonded components. Ideally, it may be preferable to bond elements with very similar CTEs or small differences in CTEs to minimize stresses associated with CTE mismatches when cooling from the bonding temperature to room temperature. Assuming adequate adhesion between the bonded elements, the CTE-related stresses in the bonded elements may be proportional to the bonding temperature and to the difference in CTE for the individual elements in the bonded structure. Higher bonding temperatures may result in greater CTE-related stresses. Similarly, greater differences in CTE between elements may result in greater CTE-related stresses. High stresses in the bonded structure may be undesirable as they may induce defects such as microcracks, delamination, and / or large warpage in the bonded elements or stack of elements. To directly bond two elements, each having a non-conductive bonding surface and a conductive bonding region, the opposing non-conductive bonding surfaces may be bonded at temperatures below 120° C., for example. The opposing conductive bond regions may be bonded at a bonding temperature ranging from 250° C. to 450° C., and the bonding time may range from 15 minutes to 6 hours. In some circumstances, the bonding time may exceed 6 hours. Higher bonding temperatures may result in shorter bonding times in some applications. In general, the higher the bonding temperature used, the greater the likelihood of introducing defects into the bond structure. In view of the above, methods of directly forming conductor-to-conductor (e.g., metal-to-metal) bonds at relatively low temperatures may be desirable.

[0020] In some embodiments, in direct bonding of two substrates with CTE differences between elements, it may be desirable to reduce the annealing temperature and / or annealing time to minimize depletion of the thermal (energy) budget. Various embodiments disclosed herein can produce contact structures (e.g., copper contact pads) having fine copper grains with average grain sizes of 500 nm or less, 350 nm or less, 300 nm or less, or 50 nm or less, e.g., in the range of 10 nm to 500 nm, 10 nm to 300 nm, 10 nm to 150 nm, 10 nm to 100 nm, 10 nm to 75 nm, or 10 nm to 50 nm. The use of fine grain metals (e.g., fine grain copper or nano-copper) in conductive structures can advantageously provide high potential energy and high creep rates, thereby reducing the thermal budget available for the annealing process that creates the conductor-to-conductor (e.g., copper-to-copper) direct bonded connections. Furthermore, the increased potential energy can improve interdiffusion and strong metallurgical bonding at the copper-copper interface. Fine-grain copper can also have a more uniform pre-bond recess across the wafer due to its smaller grain size than coarse-grain copper. Fine-grain copper can be easier to control the recess uniformly than coarse-grain copper, since if the pad is made with coarse-grain copper, it may behave differently within the pad and affect the polishing rate. Subsequent wet and / or dry etching chemistry does not substantially compromise the uniformity of the recess size across the wafer, improving electrical yield after bonding.

[0021] FIG 1A is a schematic cross-sectional side view of a structure at an intermediate stage of forming an element (first element 1). FIG 1B is a schematic cross-sectional side view of element 1. FIG 2 is a schematic cross-sectional side view of a junction structure 2 with a first element 1 and a second element 3. In some embodiments, the first and second elements 1, 3 can have the same or substantially similar structure. In some embodiments, the first and second elements 1, 3 can include semiconductor elements.

[0022] The first device 1 may include a carrier 10, an insulating layer 12 on the carrier 10, a metallization layer 14 on the insulating layer 12, and a bonding layer 16 on the metallization layer 14. In some embodiments, the carrier 10 may include a substrate (e.g., a wafer) including a device region. In some embodiments, the carrier 10 may include a device layer or device structure. In some embodiments, the insulating layer 12 may include an oxide layer deposited on the carrier 10. The oxide layer may have a thickness of about 0.3 μm. For example, the thickness of the oxide layer may range from 0.1 μm to 20 μm, or from 0.1 μm to 10 μm. In some embodiments, the insulating layer 12 may include multiple dielectric layers including embedded interconnected conductive features (not shown). The embedded conductive features of the insulating layer 12 may be connected to conductive portions of the metallization layer 14. In some embodiments, the insulating layer 12 may include the metallization layer 14 and / or the bonding layer 16. In some applications, the flat top surface of the insulating layer 12 may include a bonding surface.

[0023] The metallization layer 14 may include a conductive portion 18 and a non-conductive portion 20. In some embodiments, the metallization layer 14 may include a back-end line (BEOL) metallization layer. In some embodiments, the conductive portion 18 may include laterally extending conductive traces and / or vertically extending conductive vias within the metallization layer 14 to function as a redistribution layer (RDL). The conductive portion 18 may include any suitable conductive material, such as copper (Cu). The copper may be formed by a conventional copper plating process. In some embodiments, the metallization layer 14 may define a bottom surface of a cavity 22 formed in the bonding layer 16.

[0024] In some embodiments, the bonding layer 16 can include a non-conductive layer that can define a non-conductive region 24, a barrier layer 26 disposed within the cavity 22, and a conductive feature 28 disposed within the cavity 22 over the barrier layer 26. The conductive feature 28 can include a contact structure configured to contact and electrically connect to an opposing contact structure on another element. The thickness of the conductive feature 28 can vary, for example, in the range of 0.3 μm to 6 μm, typically in the range of 0.5 μm to 4 μm. Similarly, the width of the conductive feature 28 can range, for example, from 0.3 μm to 60 μm, 0.5 μm to 40 μm, or 0.5 μm to 20 μm. As described herein, the conductive feature 28 can include a contact pad, a trace, a via, or any suitable combination thereof. In some embodiments, the via can include a through-substrate electrode. The width of the through-substrate conductive feature at the bonding surface can vary, for example, from 1 μm to 50 μm, 2 μm to 30 μm, or 2.5 μm to 15 μm. The conductive feature 28 and the metallization layer 14 can be electrically connected to each other. In some embodiments, a barrier layer 26 can be disposed between the conductive feature 28 and the metallization layer 14. Thus, in the illustrated embodiment, the conductive feature 28 includes a contact pad disposed on a metallization layer (such as a BEOL layer). In other configurations, the conductive feature 28 can include a conductive via that extends through (or mostly through) the device, such as in a through-substrate electrode or through-device electrode or through-silicon via TSV in the case of a silicon substrate.

[0025] The non-conductive region 24 may include a dielectric layer. In some embodiments, the non-conductive region 24 may include multiple layers of different dielectric materials. For example, the non-conductive region 24 may include silicon oxide. As shown in FIG. 1A, a cavity 22 may be formed in the non-conductive region 24. The cavity 22 may extend at least partially through the thickness of the non-conductive region 24. For example, the cavity 22 may extend completely through the thickness of the non-conductive region 24.

[0026] In some embodiments, the barrier layer 26 may include a diffusion barrier layer that prevents or reduces diffusion of the material of the conductive features 28 into the non-conductive regions 24. In some embodiments, the barrier layer 26 may include tantalum, titanium, cobalt, nickel, or tungsten, or any suitable compound, or combinations thereof. In some embodiments, the barrier layer 26 may include a multi-layer structure.

[0027] In some embodiments, the conductive feature 28 can include copper (Cu). For example, the conductive feature 28 can include a fine grain metal (e.g., fine grain copper). A fine grain metal or bond pad can be defined as a metal feature with a microstructure having an average grain width of less than 20 nm, less than 50 nm, less than 100 nm, less than 300 nm, or less than 500 nm. For example, the fine grain metal can have a maximum width within the microstructure in the range of 10 nm to 500 nm, 10 nm to 300 nm, 20 nm to 500 nm, 20 nm to 300 nm, 20 nm to 100 nm, 20 nm to 50 nm, 50 nm to 500 nm, 50 nm to 300 nm, or 100 nm to 300 nm. The grain size variation within the conductive feature 28 can be within about 10% among 95% or more of the grains within the conductive feature 28. In some embodiments, the average size of the grains in the conductive feature 28 may be less than 100 nm, less than 300 nm, or less than 500 nm. The grains of fine-grained metals may be significantly smaller than coarse-grained metals, including coarse grains, such as grains with a maximum width of 1 μm to 2 μm or more. In some embodiments, fine-grained metals may have higher stress than coarse-grained metals due to the deposition method. Fine-grained metals may have higher potential energy than coarse-grained metals.

[0028] In some embodiments, the conductive features 28 can be provided in the cavities 22 by plating. The conductive features 28 can be deposited in a suitable plating bath under a variety of high plating current densities. For example, plating current densities can range from 1 mA / cm to 100 mA / cm by direct current (DC) or pulse plating, or a combination of the two. 2 ~70mA / cm2 , or 40mA / cm 2 ~70mA / cm 2 For example, the range can be 1 mA / cm 2 ~70mA / cm 2 The conductive features 28 can be electroplated at current densities ranging from 0.5 seconds to 5 seconds at lower current densities and from 0.3 seconds to 2 seconds at higher current densities. In some embodiments, the conductive features 28 can include a metal coating that can be formed by plating copper from an acid copper bath or a copper fluoroborate bath, a copper sulfonate bath, or a copper pyrophosphate plating bath. In some embodiments, the acid plating bath can include 0.1M to 0.4M copper ions, 0.1M to 1M acid (e.g., 0.3M to 0.6M organic or inorganic acid), and 30 ppm to 70 ppm halide ions. In some embodiments, an atomizing agent can be used in the plating process to reduce the particle size of the conductive features 28. The atomizing agent can include thiourea, thiazine (sulfur-containing group), oxazine, or oxazine dye. The concentration of the grain refiner used in the plating process can range, for example, from 2 mg / L to 70 mg / L, from 2 mg / L to 50 mg / L, from 2 mg / L to 20 mg / L, from 10 mg / L to 70 mg / L, or from 20 mg / L to 50 mg / L. A higher concentration of grain refiner can be provided for smaller particle sizes of the conductive features 28.

[0029] Fine grain metals may contain relatively high concentrations of impurities (e.g., interstitial or non-interstitial impurities). Impurities may include, for example, sulfur, carbon, nitrogen, phosphorus, etc. Typically, the concentration of impurities may be greater than 30 ppm, or greater than 50 ppm, and preferably less than 5000 ppm. In some embodiments, relatively low concentrations of impurities may be desirable.

[0030] In some embodiments, conductive feature 28 can include a constituent. A constituent is an additive that can be added during a plating process or during formation of a seed layer to promote the formation of grains in conductive feature 28. In some embodiments, the average grain size of the grains in conductive feature 28 can be less than 100 nm, less than 300 nm, or less than 500 nm. The constituent can include boron, indium, phosphorous, gallium, nickel, cobalt, tin, manganese, titanium, vanadium, or selenium. In some embodiments, the amount of the constituent at the grain boundaries in conductive feature 28 can be less than 0.5% or less than 0.1% of conductive feature 28.

[0031] In some embodiments, the conductive feature 28 can include nanoparticles of an inert material, such as silicon oxide, aluminum, or titanium oxide, which can be plated together into the fine-grained metal of the conductive feature 28. An inert material is a material that does not form a major alloy with the fine-grained metal of the conductive feature 28 at annealing temperatures of 400° C. or less. In some embodiments, more than 90%, more than 95%, or more than 99% of the nanoparticles of the inert material do not form an alloy with the fine-grained metal of the conductive feature 28. The nanoparticles can be present at the grain boundaries of the conductive feature 28 as well as at the subgrain boundaries of the coating metal of the conductive feature 28. The nanoparticles can inhibit grain growth of the grains in the conductive feature 28 at temperatures below about 120° C. The concentration of the nanoparticles in the conductive feature 28 can be controlled so that the nanoparticles do not significantly change the conductivity of the conductive feature 28. For example, the concentration of the nanoparticles can be less than 1% or less than 0.1% of the conductive feature 28.

[0032] In some embodiments, plating can be performed at low temperatures, such as, for example, 5° C. to 15° C., or below 20° C. Conductive features 28 formed at low temperatures may tend to grow more rapidly than those formed at room temperature. In some embodiments, conductive features 28 formed at low temperatures, with low levels of impurities, for example, less than 30 ppm impurities, can be stored at low temperatures, preferably below 10° C., to inhibit grain growth, and can be further processed (e.g., chemical mechanical polishing (CMP)) at low temperatures. Conductive features 28 formed at low temperatures can be cleaned and bonded, for example, within 8 hours or within 4 hours after the CMP process.

[0033] In some embodiments, after plating the metal with any suitable process disclosed herein, the metal may be annealed to at least partially stabilize the microstructure of the metal, which may be referred to as a grain recovery process. The annealing may be performed prior to a CMP process. In some embodiments, the metal may be annealed at a temperature ranging from 80° C. to 150° C. For example, the metal may be annealed for 60 to 120 minutes. The grain size of the grains in the metal before and after the annealing process to induce the grain recovery process is generally smaller than the stabilized metal microstructure. The expected change in grain size is typically less than 10%, compared to conventional BEOL or packaging copper, where the difference between the as-plated grain size and the as-annealed grain size is typically more than 50% and even more than 100%.

[0034] As shown in Figure 2, the first element 1 can be bonded to the second element 3. The second element 3 can include a carrier 30, an insulating layer 32 on the carrier 30, a metallization layer 34 on the insulating layer 32, and a bonding layer 36 on the metallization layer 34. The metallization layer 34 can include a conductive portion 38 and a non-conductive portion 40. The bonding layer 36 can include a non-conductive region 44, a barrier layer 46 disposed in the cavity 42, and a conductive feature 48 disposed in the cavity 42 over the barrier layer 46.

[0035] In some embodiments, the first element 1 and the second element 3 can be directly bonded to each other without an adhesive along the bonding interface 49. For example, a conductive feature (e.g., conductive feature 28) of the first element 1 can be directly bonded to a corresponding conductive feature (e.g., conductive feature 48) of the second element 3 without an adhesive, and a non-conductive region 24 of the first element 1 can be directly bonded to a non-conductive region 44 of the second element 3 without an adhesive. For example, a bonding process according to one embodiment can include directly bonding the non-conductive region 24 of the first element 1 to the non-conductive region 44 of the second element 3 at room temperature, and directly bonding the conductive feature 28 to the conductive feature 48 by expanding the conductive feature 28 towards the conductive feature 48, e.g., by annealing at a temperature of 300° C. or less, 250° C. or less, 200° C. or less, or 180° C. or less. The first element 1 and the second element 3 can be directly bonded to each other at room temperature, typically 18-40° C. For example, the annealing temperature for bonding the conductive features 28 and 48 can range from 120° C. to 250° C., 120° C. to 200° C., or 120° C. to 180° C. In some embodiments, the conductive feature 28 of the first element 1 and / or the conductive feature 48 of the second element 3 can include a recess and a gap can exist between the non-conductive region 24 and the non-conductive region 44 when they are bonded together. The elements 1, 3 can be annealed at an elevated temperature to fill the gap or recess when a metallurgical bond is formed between the two opposing conductive features 28 and 48.

[0036] FIG. 3 is a schematic top view of coarse-grained copper showing grains 50 of the coarse-grained copper. FIG. 4 is a schematic top view of fine-grained copper showing grains 52 of the fine-grained copper according to an embodiment. Both the coarse-grained copper and the fine-grained copper of FIGS. 3 and 4 are annealed at a temperature between 80° C. and 150° C. for 120 minutes. The average grain size of the coarse-grained copper may range from 0.5 μm to 3 μm, and the average grain size of the fine-grained copper may range from 10 nm to 500 nm. As shown in FIG. 3, twins 54 may be formed within the grains of the copper. In some embodiments, the grains 52 of the fine-grained copper may include nanotwins (not shown) within the grain structure (e.g., within one or more of the grains 52). In some embodiments, the conductive feature 28 of FIG. 1B may include more than one type of microstructure. For example, the portion of the conductive feature 28 may include a top portion and a bottom portion positioned closer to the metallization layer 18 than the top portion (see FIG. 6D). In some embodiments, the top of the conductive feature 28 has a thickness in the range of 5% to 70% of the thickness of the conductive feature 28. In some embodiments, the top of the conductive feature 28 has a thickness in the range of, for example, 50 nm to 500 nm. The bottom can include a conductive feature having a highly oriented microstructure, for example, a nanotwinned copper microstructure. The top can include a bonding surface of the conductive feature 28 and a conductive region between the bonding surface and the bottom. The top can include a fine-grained metal, for example, fine-grained copper. In some embodiments, the bottom of the conductive feature 28 can include a material having a coarse-grained structure, for example, conventional BEOL or packaging copper with coarse grains. In some embodiments, the bottom can include another material other than pure copper, for example, a copper alloy, nickel, cobalt, tungsten, aluminum, and various alloys of each. In some applications, a barrier layer (not shown) can be disposed between the top and bottom of the conductive feature 28. The barrier layer can prevent or reduce intermixing of the top and bottom microstructures.

[0037] The activation energy of diffusion along grain boundaries and interfaces is significantly lower than that of lattice diffusion. For fine-grained microstructures with large grain boundary surface areas, grain boundary diffusion pathways dominate in metal-metal bonding. Fine-grained microstructures can also generally exhibit higher creep rates compared to nanotwinned copper as well as conventional coarse-grained copper with significantly larger grain sizes. The significantly higher density of extremely fast diffusion pathways and higher creep rates in fine-grained copper explain its low-temperature bonding propensity. Fine-grained metal microstructures are desirable for the faying surfaces of directly bonded interconnects because of their propensity for low-temperature bonding.

[0038] FIG. 5 is a graph showing the average resistance versus temperature for a fine-grain copper pad (FG) and a conventional copper pad (STD). The average resistance can give an indication of the degree of contact between opposing conductive features; a lower average resistance can mean a better connection compared to a higher average resistance. The graph shows that the fine-grain pad reaches a desired or nominal value for resistance at a lower temperature than the conventional copper pad. The results show that the fine-grain pad can be bonded to another pad at a lower annealing (bonding) temperature than the conventional copper pad.

[0039] 6A is a schematic cross-sectional side view of a bonding structure 4 with conductive features 70, 80 (e.g., conventional copper pads). The bonding structure includes a first element 5 and a second element 6 bonded to the first element 5 along a bonding interface 86. The first element 5 includes a conductive feature 70, a non-conductive region 72, and a metallization layer 74. The second element 6 includes a conductive feature 80, a non-conductive region 82, and a metallization layer 84. The conductive features 70, 80 include coarse grains, e.g., copper grains having an average grain size of greater than 1 μm. The conductive features 74, 84 include conventional coarse grain metal (e.g., coarse grain copper).

[0040] The bonding structure 4 is annealed at a temperature of more than 180° C. for bonding. As the annealing time or temperature increases, the metal-metal (e.g., copper-copper) bonding interface at the bonding interface 86 can develop. The longer the annealing, the more metal diffusion (e.g., copper diffusion) occurs at the bonding interface. The bonding interface 86 can extend along the x-direction, and the z-direction, which is approximately perpendicular to the x-direction, can be the film growth direction. In some embodiments of the bonding element 4, the number of grains of the conductive features 70, 80 that interrupt the bonding interface 86 can be 11 grains or less at its maximum width or diameter. Depending on the diameter or width of the conductive features 70, 80, the number of grains that interrupt the bonding interface can be less than 8 grains, or even less than 5 grains.

[0041] FIG. 6B is a schematic cross-sectional side view of a bonding structure 7 according to one embodiment. Unless otherwise noted, the components of FIG. 6B can be the same or substantially similar to the similar components of FIGS. 1A-2. The bonding structure 7 can include a first element 1′ and a second element 3′ bonded to the first element 1′ along a bonding interface 86′. The first element 1′ includes a conductive feature 28′, a non-conductive region 24′, a metallization layer 14′, and a carrier 10′. The second element 3′ includes a conductive feature 48′, a non-conductive region 44′, a metallization layer 34′, and a carrier 30′. The conductive features 28′, 48′ can include a fine-grained metal (e.g., fine-grained copper). The metallization layers 24′, 34′ can include a conventional coarse-grained metal (e.g., coarse-grained copper). In some embodiments of the bonding structure 7, one of the metallization layers 14′ or 34′ can include a layer having a fine-grained metal, such as fine-grained copper.

[0042] The bonded structure 7 is annealed at a temperature of more than 180° C. for bonding. The grain size of the conductive features 28′, 48′ before and after the annealing process for bonding the conductive features 28′, 48′ can be approximately similar. For example, the average grain size of the conductive features 28′, 48′ after the annealing process can be no more than twice the average grain size of the unannealed conductive features 28′, 48′. As the annealing time and / or temperature increases, the metal-metal (e.g., copper-copper) bond interface at the bonded interface 86′ can develop. After annealing for a sufficient time, more metal diffusion (e.g., copper diffusion) can occur at the metal-metal bonded interface. In some embodiments, the bonded interface 86′ can extend along the x-direction, and the z-direction, which is approximately perpendicular to the x-direction, can be the film growth direction. In some embodiments, as a result of the fine-grain structure of the joining structure 7, the number of grains of the joined conductive feature 28' or 48' that intersect the interface 86' in a linear lateral dimension may be greater than 12 grains at its maximum width or diameter. In some embodiments, the number of grains that intersect the interface 86' may be greater than 16 grains, or greater than 20 grains.

[0043] FIG. 6C is a schematic cross-sectional side view of a bonding structure 7′ according to one embodiment. Unless otherwise noted, the components of FIG. 6C can be the same or substantially similar to the like components of FIGS. 1A-2, 6A, and 6B. The bonding structure 7′ can include a first element 1′ including a conductive feature 28′ bonded directly to a conventional conductive feature 70, such as a conventional copper pad including a coarse-grained conductive metal along a bonding interface 86′. The first element 1′ can include a conductive feature 28′, a non-conductive region 24′, a metallization layer 14′, and a carrier 10′. The element 5 can include a conductive feature 70, a non-conductive region 72, a metallization layer 84, and a carrier 74. The conductive feature 70 is an example of a conductive feature, and the element 5 can include any suitable conductive feature. The conductive feature 28′ can include a fine-grained metal (e.g., fine-grained copper), and the conductive feature 70 can include a coarse-grained metal (e.g., coarse-grained copper). In some embodiments, the material of the conventional conductive feature 70 can be selected based at least in part on the material of the conductive feature 28'. For example, the material of the conventional conductive feature 70 can be selected to have the same or similar type of metal as the material of the conductive feature 28'. The metallization layers 14', 74 can include conventional coarse-grain copper. Other types of metals and metal microstructures may be used for the metallization layers 14', 74. In some embodiments of the joint structure 7', one of the metallization layers 14' or 74 can include a layer having a fine-grain conductive metal, such as fine-grain copper.

[0044] The bond structure 7' is annealed (e.g., at a temperature of 180° C.) for bonding. The grain size in the conductive feature 28' and the conductive pad 70 is different before and after the annealing process for bonding the conductive features 70', 80. As the annealing time and / or temperature increases, a metal-metal (e.g., copper-copper) bond interface at the bond interface 86'' can develop. After annealing for a sufficient time, more metal diffusion (e.g., copper diffusion) can occur at the bond interface of the interlocking conductive features 28' and 70. In some embodiments, the bond interface 86'' can extend along the x-direction, and a z-direction approximately perpendicular to the x-direction can be the film growth direction. In some embodiments, the number of grains intercepting the first conductive feature 28' of the first element 1' is 10% or more higher than the number of grains intercepting the conductive feature 70 of the element 5 at the bond interface 86'', measured in the linear lateral dimension of the bond interface 86'' at the diameter of the bond interface 86''. For example, bonding structure 7' can include 21 or more grains interrupting interface 86'' with conductive feature 28' and 12 or fewer grains interrupting interface 86'' with conductive feature 80. In some embodiments, the number of grains interrupting interface 86'' with conductive feature 28 of first element 1' is different from the number of grains interrupting bonding interface 86'' with conductive feature 80 of element 5.

[0045] FIG. 6C is a schematic cross-sectional side view of a bonding structure 7″ according to one embodiment. Unless otherwise noted, the components of FIG. 6D can be the same as or substantially similar to the like components of FIGS. 1A-2, 6A-6C. The bonding structure 7″ can be substantially similar to the bonding structure 7 of FIG. 6A, except that the element 3″ of the bonding structure 7″ includes a fine-grained portion 88 and a coarse-grained portion 89 in the conductive feature 48″. Although FIG. 6C shows one fine-grained portion and one coarse-grained portion, in some embodiments, there can be multiple fine-grained portions and / or multiple coarse-grained portions. The fine-grained portion 88 positioned closer to the bonding interface 86′″ can be referred to as a top portion, and the coarse-grained portion 89 closer to the metallization layer 34′ can be referred to as a bottom portion. In some embodiments, the fine-grained portion 88 of the conductive feature 48″ is located at a thickness T of the conductive feature 28. cf Thickness T in the range of 5% to 70% of fgFor example, the thickness T fg is the thickness T of the conductive feature 28 cf In some embodiments, the thickness T of the fine grain portion 88 may be in the range of 5% to 50%, 5% to 20%, 10% to 50%, or 10% to 20%. fg For example, the thickness T fg can be in the range of 50 nm to 400 nm, 50 nm to 300 nm, 100 nm to 500 nm, or 100 to 300 nm.

[0046] 7A-7C show top-down electron backscatter diffraction (EBSD) images of different types of copper features. FIG. 7A is a top-down EBSD image of a conventional or coarse-grained copper feature. FIG. 7B is a top-down EBSD image of a nanotwinned copper feature. FIG. 7C is a top-down EBSD image of a fine-grained copper feature according to one embodiment. FIGS. 7A-7C show grain orientation parallel to the z-direction (see FIGS. 6A-6D), which is the same direction as the film growth direction (e.g., perpendicular to the image plane in the images of FIGS. 7A-7C). For example, grain 90 has a grain orientation parallel to the z-direction of the grain. <111> The grains 92 have a crystal orientation that is approximately parallel to the z direction of the grains. <001> The grains 94 have a crystal orientation such that the z direction is approximately parallel to the grain <101> FIG. 7A shows a graph of the grains with different grain orientations (e.g., <111> , <001> , and <101> 7B shows an exemplary microstructure of a coarse-grained copper feature with grains having mostly or essentially a single metal grain orientation (e.g., <111> FIG. 1 shows an exemplary microstructure of a nanotwinned copper feature having highly oriented grains, including a lattice orientation. In another embodiment, the highly oriented grains include <111> direction, <100> direction, <110> The copper may have a high degree of orientation or a combination of these, such as a twinned microstructure and / or a highly oriented non-cubic structure, such as a tetragonal or hexagonal structure. Figure 7C shows an exemplary microstructure of a fine grain copper feature. The microstructure comprises fine grains with a grain size typically less than 100 nm, and the various grains of the fine grains are <111> , <110> , <100> The dark areas in Figure 7C are grains 96 with orientations that were not detected by electron backscatter diffraction.

[0047] In one embodiment, a bonded structure is disclosed. The bonded structure can include a first element having a first conductive feature and a first non-conductive region. The first conductive feature comprises a fine-grained metal having an average grain size of 500 nm or less. The bonded structure can include a second element having a second conductive feature and a second non-conductive region. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the second non-conductive region is directly bonded to the second non-conductive region without an intervening adhesive.

[0048] In one embodiment, the first conductive feature comprises copper.

[0049] In one embodiment, the particles of the first conductive feature have a maximum particle size of less than 500 nm. The particles of the first conductive feature can have a maximum particle size of less than 350 nm. The particles of the first conductive feature can have a maximum particle size of less than 50 nm.

[0050] In one embodiment, the particles of the second conductive feature have an average particle size of 500 nm or less.

[0051] In one embodiment, the particles of the second conductive feature have an average particle size greater than 1 μm.

[0052] In one embodiment, the fine grain metal of the first conductive feature has an average grain size of 350 nm or less. The fine grain metal of the first conductive feature can have an average grain size in the range of 10 nm to 300 nm.

[0053] In one embodiment, greater than 95% of the particles in the first conductive feature have a particle size variation of less than 10%.

[0054] In one embodiment, the first element further comprises a metallization layer having a conductive portion. The conductive portion of the metallization layer may comprise a metal having an average grain size in the range of 1 μm to 2 μm.

[0055] In one embodiment, the fine grain metal of the first conductive feature includes nanoparticles of an inert material. The concentration of the nanoparticles can be less than 1% of the first conductive feature. The concentration of the nanoparticles can be less than 0.1% of the first conductive feature. The nanoparticles can include one or more of silicon oxide, alumina, and titanium oxide.

[0056] In one embodiment, the fine grain metal comprises the constituents.

[0057] In one embodiment, a bonded structure is disclosed. The bonded structure can include a first element having a first conductive feature and a first non-conductive region. The first conductive feature can include a fine-grained metal having a composition. The bonded structure can include a second element having a second conductive feature and a second non-conductive region. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the second non-conductive region is directly bonded to the second non-conductive region without an intervening adhesive.

[0058] In one embodiment, the constituents include at least one of boron, indium, phosphorus, gallium, nickel, cobalt, tin, manganese, titanium, vanadium, and selenium. The first conductive feature can include a fine grain metal having an average grain size of 500 nm or less. The average grain size of the fine grain metal of the first conductive feature can be in the range of 10 nm to 300 nm.

[0059] In one aspect, an interconnect structure is disclosed. The interconnect structure can include an element including a bonding surface. The element has a conductive feature and a non-conductive region. The conductive feature is at least partially embedded in the non-conductive region. The conductive feature includes a bottom portion and a top portion disposed above the bottom portion. The top portion is positioned closer to the bonding surface of the element than the bottom portion. The top portion has an average grain size smaller than the average grain size of the bottom portion. The top portion has an average grain size of 500 nm or less.

[0060] In one embodiment, the junction structure includes an interconnect structure and a second element.

[0061] In one aspect, a method of forming a substrate is disclosed. The method can include providing a cavity in a non-conductive layer of a semiconductor device, providing a conductive contact structure in the cavity, and preparing the non-conductive layer and the conductive contact structure for direct bonding. The conductive contact structure has a fine grain structure including an average grain size of less than 500 nm.

[0062] In one embodiment, the conductive contact structures include copper.

[0063] In one embodiment, the average particle size is less than 350 nm. The average particle size can range from 10 nm to 300 nm.

[0064] In one embodiment, providing a conductive contact structure includes providing a copper electroplating bath having less than 0.5% additives, the additives including one or more of boron, indium, phosphorous, gallium, nickel, cobalt, tin, manganese, titanium, vanadium, and selenium, and electroplating the conductive contact structure into the cavity.

[0065] In one embodiment, providing a conductive contact structure includes providing a copper electroplating bath having electrically inactive nanoparticles therein. The electrically inactive nanoparticles may include one or more of silicon oxide, alumina, and titanium oxide. The concentration of the nanoparticles may be less than 1% by volume. The concentration of the nanoparticles may be less than 0.1% by volume.

[0066] In one embodiment, metal grain recovery of the conductive contact structure is inhibited at room temperature and at temperatures below 120°C.

[0067] In one embodiment, providing a conductive contact structure includes electroplating the cavity at a temperature less than 30° C. The method can further include electroplating the cavity at a temperature in the range of 5° C. to 15° C. The method can further include chemically mechanically polishing the non-conductive layer and the conductive contact structure at a temperature in the range of 5° C. to 15° C.

[0068] In one embodiment, the method further includes directly bonding the non-conductive layer of the semiconductor device to the second non-conductive layer of the second semiconductor device without an intervening adhesive. The method may further include annealing the semiconductor device and the second semiconductor device to contact the conductive contact structure to the second conductive contact structure of the second semiconductor device. The annealing may be performed at a temperature less than 300° C. The annealing may be performed at a temperature less than 250° C.

[0069] In one embodiment, the step of providing a conductive contact structure comprises applying a current of 0.1 mA / cm 2 ~70mA / cm 2 The method includes electroplating the cavity using a current density in the range of

[0070] In one embodiment, providing a conductive contact structure includes providing an electroplating bath having 0.1M to 0.4M copper ions and 0.1M to 1M acid.

[0071] In one embodiment, providing a non-conductive layer comprises depositing on the integrated circuit device. The method may further comprise lining at least sidewalls of the cavity with a barrier layer prior to filling the cavity with the conductive contact structure having a fine grain structure.

[0072] In one aspect, a method of forming a substrate is disclosed that can include providing a cavity in a non-conductive layer of a semiconductor device, providing a conductive contact structure in the cavity, and preparing the non-conductive layer and the conductive contact structure for direct bonding, the conductive contact structure having a fine grain structure.

[0073] In one embodiment, the conductive contact structures include copper.

[0074] In one embodiment, a majority of the particles of the conductive contact structure have a size of 500 nm or less. A majority of the particles have a size of 350 nm or less. A majority of the particles have a size in the range of 10 nm to 300 nm.

[0075] In one embodiment, the particles of the conductive contact structure have an average particle size of 500 nm or less. The average particle size may be 350 nm or less. The average particle size may be in the range of 10 nm to 300 nm.

[0076] In one embodiment, providing a conductive contact structure includes providing a copper electroplating bath having less than 0.5% additives and electroplating the conductive contact structure into the cavity. The copper electroplating bath may include less than 0.1% additives. The additives may include one or more of boron, indium, phosphorous, gallium, nickel, cobalt, tin, manganese, titanium, vanadium, and selenium.

[0077] In one embodiment, providing a conductive contact structure includes providing a copper electroplating bath having electrically inactive nanoparticles therein. The electrically inactive nanoparticles may include one or more of silicon oxide, alumina, and titanium oxide. The concentration of the nanoparticles may be less than 1% by volume. The concentration of the nanoparticles may be less than 0.1% by volume.

[0078] In one embodiment, metal grain recovery of the conductive contact structure is inhibited at room temperature and at temperatures below 120°C.

[0079] In one embodiment, providing a conductive contact structure includes electroplating the cavity at a temperature less than 30° C. The method may further include electroplating the cavity at a temperature in the range of 5° C. to 15° C. The method may further include chemically mechanically polishing the non-conductive layer and the conductive contact structure at a temperature in the range of 5° C. to 15° C.

[0080] In one embodiment, the method further includes directly bonding the non-conductive layer of the semiconductor device to the second non-conductive layer of the second semiconductor device without an intervening adhesive. The method may further include annealing the semiconductor device and the second semiconductor device to contact the conductive contact structure to the second conductive contact structure of the second semiconductor device. The annealing may be performed at a temperature less than 300° C. The annealing may be performed at a temperature less than 250° C.

[0081] In one embodiment, the step of providing a conductive contact structure comprises applying a current of 0.1 mA / cm 2 ~70mA / cm 2 Electroplating the cavity using a current density in the range of 40 mA / cm 2 ~70mA / cm 2 The range may be:

[0082] In one embodiment, providing a conductive contact structure includes providing an electroplating bath having 0.1 M to 0.4 M copper ions and 0.1 M to 1 M acid. The electroplating bath can have a halide ion range of 30 ppm to 70 ppm.

[0083] In one embodiment, providing the non-conductive layer comprises deposition on the integrated circuit device. The method may further comprise lining at least sidewalls of the cavity with a barrier layer prior to filling the cavity with the conductive contact structure having a fine grain structure. Providing the non-conductive layer may comprise deposition on a redistribution layer on the integrated circuit device.

[0084] In one embodiment, a joint structure is disclosed. The joint structure can include a first element having a first conductive feature and a first non-conductive region. The joint structure can include a second element having a second conductive feature and a second non-conductive region. The first conductive feature is directly bonded to the second conductive feature without an adhesive, thereby forming a joint interface. The grain count of the joint interface is greater than 40. The second non-conductive region is directly bonded to the second non-conductive region without an adhesive.

[0085] In one embodiment, the first conductive feature comprises a fine grain metal having an average grain size of 500 nm or less.

[0086] In one embodiment, the first conductive feature has a maximum lateral dimension in the range of about 0.01 μm to 25 μm. The first conductive feature may have a maximum lateral dimension of less than 1 μm.

[0087] In one embodiment, the total area of ​​the bond interface is about 100 μm 2 The total area of ​​the bonded interface is less than 2 μm 2 It can be smaller.

[0088] Unless the context clearly indicates otherwise, throughout this specification and claims, the words "comprise," "comprising," "include," "including," and the like, are to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to an exclusive or exhaustive sense. The word "coupled," as generally used herein, refers to two or more elements that are either directly connected or connected via one or more intermediate elements. Similarly, the word "connected," as generally used herein, refers to two or more elements that are either directly connected or connected via one or more intermediate elements. Additionally, the words "herein," "above," "below," and similar words of incorporation, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as being "on" or "above" a second element, the first element can be directly on or above the second element, such that the first and second elements are in direct contact, or the first element can be indirectly on or above the second element, such that there are one or more intervening elements between the first and second elements. Where the context permits, words using the singular or plural in the above Detailed Description can also include the plural or singular, respectively. The word "or" in connection with a list of two or more items encompasses all of the following interpretations of that word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0089] Additionally, conditional terms used herein, particularly those terms such as "can," "could," "might," "may," "eg," "for example," "such as," and the like, are generally intended to convey that certain embodiments include certain features, elements, and / or conditions while other embodiments do not, unless specifically stated otherwise or understood otherwise within the context in which they are used. Thus, such conditional terms are generally not intended to imply that features, elements, and / or conditions are in any way required for one or more embodiments.

[0090] Although specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and changes may be made in the form of the methods and systems described herein without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and operations of the various embodiments described above may be made to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the disclosure.

Claims

1. a first element having a first conductive feature and a first non-conductive region, the first conductive feature comprising a fine grain metal having an average grain size of 500 nm or less; a second element having a second conductive feature and a second non-conductive region; A joining structure comprising: A bonding structure, wherein the first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the first non-conductive region is directly bonded to the second non-conductive region without an intervening adhesive.

2. The joint structure of claim 1 , wherein the first conductive feature comprises copper.

3. The bond structure of claim 1 , wherein the particles of the first conductive feature have a maximum particle size of less than 500 nm.

4. The bond structure of claim 3 , wherein the particles of the first conductive feature have a maximum particle size of less than 350 nm.

5. The bond structure of claim 4 , wherein the particles of the first conductive feature have a maximum grain size of less than 50 nm.

6. The joint structure of claim 1 , wherein the average grain size of the second conductive feature is 500 nm or less.

7. The bond structure of claim 1 , wherein the second conductive feature comprises a coarse-grained metal.

8. The joint structure of claim 7 , wherein the average grain size of the second conductive feature is greater than 1 μm.

9. The joint structure of claim 1 , wherein the fine grain metal of the first conductive feature has an average grain size of 350 nm or less.

10. The joint structure of claim 9, wherein the fine grain metal of the first conductive feature has an average grain size in the range of 10 nm to 300 nm.

11. The bond structure of claim 1 , wherein greater than 95% of the grains of the first conductive feature have a grain size variation of less than 10%.

12. The junction structure of claim 1 , wherein the first element further comprises a metallization layer having a conductive portion.

13. The joint structure of claim 12, wherein the conductive portion of the metallization layer comprises a metal having an average grain size in the range of 1 μm to 2 μm.

14. The bond structure of claim 1 , wherein the fine grain metal of the first conductive feature comprises nanoparticles of an inert material.

15. The bond structure of claim 14 , wherein the concentration of the nanoparticles is less than 1% of the first conductive feature.

16. The bond structure of claim 15 , wherein the concentration of the nanoparticles is less than 0.1% of the first conductive feature.

17. The bonded structure according to claim 14 , wherein the nanoparticles include one or more of silicon oxide, alumina, and titanium oxide.

18. The bonded structure of claim 1 , wherein the fine grain metal comprises a constituent.

19. a first element having a first conductive feature and a first non-conductive region, the first conductive feature comprising a fine grain metal having a constituent; a second element having a second conductive feature and a second non-conductive region; A joining structure comprising: A bonding structure, wherein the first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the first non-conductive region is directly bonded to the second non-conductive region without an intervening adhesive.

20. 20. The bond structure of claim 19, wherein the constituent comprises at least one of boron, indium, phosphorous, gallium, nickel, cobalt, tin, manganese, titanium, vanadium, and selenium.

21. The bond of claim 19 , wherein the first conductive feature comprises a fine grain metal having an average grain size of 500 nm or less.

22. The joint structure of claim 21 , wherein the fine grain metal of the first conductive feature has an average grain size in the range of 10 nm to 300 nm.

23. 1. An interconnect structure comprising an element having a mating surface, the element has a conductive feature and a non-conductive region, the conductive feature being at least partially embedded in the non-conductive region, the conductive feature having a bottom portion and a top portion disposed above the bottom portion, the top portion being positioned closer to the joining surface of the element, the top portion having an average grain size smaller than the average grain size of the bottom portion; The average grain size of the upper portion is 500 nm or less. Interconnect structure.

24. A junction structure comprising the interconnect structure of claim 23 and a second element.

25. providing a cavity in a non-conductive layer of a semiconductor device; providing a conductive contact structure in the cavity, the conductive contact structure having a fine grain structure with an average grain size of less than 500 nm; preparing the non-conductive layer and the conductive contact structure for direct bonding.

26. 26. The method of claim 25, wherein the conductive contact structures comprise copper.

27. 26. The method of claim 25, wherein the average particle size is less than 350 nm.

28. The method of claim 27, wherein the average particle size is in the range of 10 nm to 300 nm.

29. 26. The method of claim 25, wherein the step of providing a conductive contact structure comprises providing a copper electroplating bath having an additive of less than 0.5%; and electroplating the conductive contact structure into the cavity.

30. 30. The method of claim 29, wherein the additive comprises one or more of boron, indium, phosphorous, gallium, nickel, cobalt, tin, manganese, titanium, vanadium, and selenium.

31. 26. The method of claim 25, wherein the step of providing a conductive contact structure comprises providing a copper electroplating bath having electrically inactive nanoparticles.

32. 32. The method of claim 31 , wherein the electrically inactive nanoparticles comprise one or more of silicon oxide, alumina, and titanium oxide.

33. 33. The method of claim 32, wherein the concentration of the nanoparticles is less than 1% by volume.

34. 34. The method of claim 33, wherein the concentration of the nanoparticles is less than 0.1% by volume.

35. 26. The method of claim 25, wherein metal grain recovery of the conductive contact structure is inhibited at room temperature and at temperatures below 120°C.

36. 26. The method of claim 25, wherein the step of providing a conductive contact structure comprises electroplating the cavity at a temperature less than 30 degrees Celsius.

37. 37. The method of claim 36, further comprising electroplating the cavity at a temperature in the range of 5°C to 15°C.

38. 38. The method of claim 37, further comprising chemically mechanically polishing the non-conductive layer and the conductive contact structures at a temperature in the range of 5°C to 15°C.

39. 26. The method of claim 25, further comprising directly bonding the non-conductive layer of the semiconductor element to a second non-conductive layer of a second semiconductor element without an intervening adhesive.

40. 40. The method of claim 39, further comprising annealing the semiconductor device and the second semiconductor device to contact the conductive contact structure to a second conductive contact structure of the second semiconductor device.

41. 41. The method of claim 40, wherein the annealing step is performed at a temperature less than 300°C.

42. 42. The method of claim 41, wherein the annealing step is performed at a temperature less than 250°C.

43. The step of providing a conductive contact structure comprises providing a current of 0.1 mA / cm 2 ~70mA / cm 2 26. The method of claim 25, comprising electroplating the cavity using a current density in the range of

44. 26. The method of claim 25, wherein the step of providing a conductive contact structure comprises providing an electroplating bath having 0.1M to 0.4M copper ions and 0.1M to 1M acid.

45. 25. The method of claim 24, wherein the step of providing a non-conductive layer comprises deposition on an integrated circuit device, and further comprises lining at least sidewalls of the cavity with a barrier layer prior to filling the cavity with the conductive contact structure having the fine grain structure.

46. providing a cavity in a non-conductive layer of a semiconductor device; providing a conductive contact structure within the cavity, the conductive contact structure having a fine-grain structure; preparing the non-conductive layer and the conductive contact structure for direct bonding.

47. 47. The method of claim 46, wherein the conductive contact structures comprise copper.

48. 47. The method of claim 46, wherein a majority of the particles of the conductive contact structure have a particle size of 500 nm or less.

49. 49. The method of claim 48, wherein the majority of the particles have a particle size of 350 nm or less.

50. 50. The method of claim 49, wherein the majority of the particles have a particle size in the range of 10 nm to 300 nm.

51. 47. The method of claim 46, wherein the conductive contact structure has an average grain size of 500 nm or less.

52. 52. The method of claim 51, wherein the average particle size is less than 350 nm.

53. 53. The method of claim 52, wherein the average particle size is in the range of 10 nm to 300 nm.

54. 47. The method of claim 46, wherein the step of providing a conductive contact structure comprises providing a copper electroplating bath having an additive of less than 0.5%; and electroplating the conductive contact structure into the cavity.

55. 55. The method of claim 54, wherein the copper electroplating bath has less than 0.1% additives.

56. 56. The method of claim 55, wherein the additive comprises one or more of boron, indium, phosphorous, gallium, nickel, cobalt, tin, manganese, titanium, vanadium, and selenium.

57. 47. The method of claim 46, wherein the step of providing a conductive contact structure comprises providing a copper electroplating bath having electrically inactive nanoparticles.

58. 58. The method of claim 57, wherein the electrically inactive nanoparticles comprise one or more of silicon oxide, alumina, and titanium oxide.

59. 59. The method of claim 58, wherein the concentration of the nanoparticles is less than 1% by volume.

60. 60. The method of claim 59, wherein the concentration of the nanoparticles is less than 0.1% by volume.

61. 47. The method of claim 46, wherein metal grain recovery of the conductive contact structure is inhibited at room temperature and at temperatures below 120 degrees Celsius.

62. 47. The method of claim 46, wherein the step of providing a conductive contact structure comprises electroplating the cavity at a temperature less than 30 degrees Celsius.

63. 63. The method of claim 62, further comprising electroplating the cavity at a temperature in the range of 5°C to 15°C.

64. 64. The method of claim 63, further comprising chemically mechanically polishing the non-conductive layer and the conductive contact structures at a temperature in the range of 5°C to 15°C.

65. 47. The method of claim 46, further comprising directly bonding the non-conductive layer of the semiconductor element to a second non-conductive layer of a second semiconductor element without an intervening adhesive.

66. 66. The method of claim 65, further comprising annealing the semiconductor device and the second semiconductor device to contact the conductive contact structure to a second conductive contact structure of the second semiconductor device.

67. 67. The method of claim 66, wherein the annealing step is performed at a temperature less than 300°C.

68. 68. The method of claim 67, wherein the annealing step is performed at a temperature less than 250°C.

69. The step of providing a conductive contact structure comprises providing a current of 0.1 mA / cm 2 ~70mA / cm 2 47. The method of claim 46, comprising electroplating the cavity using a current density in the range of

70. The current density is 40 mA / cm 2 ~70mA / cm 2 70. The method of claim 69, in the range of

71. 47. The method of claim 46, wherein the step of providing a conductive contact structure comprises providing an electroplating bath having 0.1M to 0.4M copper ions and 0.1M to 1M acid.

72. 72. The method of claim 71, wherein the electroplating bath has a range of 30 ppm to 70 ppm of halide ions.

73. 47. The method of claim 46, wherein the step of providing a non-conductive layer comprises deposition on an integrated circuit device, and further comprises lining at least sidewalls of the cavity with a barrier layer prior to filling the cavity with the conductive contact structure having the fine grain structure.

74. 74. The method of claim 73, wherein the step of providing a non-conductive layer comprises depositing in a redistribution layer on the integrated circuit device.

75. a first element having a first conductive feature and a first non-conductive region; a second element having a second conductive feature and a second non-conductive region; A joining structure comprising: A bonding structure, wherein the first conductive feature is directly bonded to the second conductive feature without an adhesive to form a bonding interface, the particle count of the bonding interface being greater than 40, and the first non-conductive region is directly bonded to the second non-conductive region without an adhesive.

76. 76. The bond of claim 75, wherein the first conductive feature comprises a fine grain metal having an average grain size of 500 nm or less.

77. 76. The junction of claim 75, wherein the first conductive feature has a maximum lateral dimension in the range of about 0.01 μm to 25 μm.

78. 78. The junction of claim 77, wherein the first conductive feature has the maximum lateral dimension of less than 1 μm.

79. The total area of ​​the bonded interface is about 100 μm 2 The joint structure of claim 75, wherein the joint structure is smaller than

80. The total area of ​​the bonding interface is 2 μm 2 80. The joint structure of claim 79, wherein said joint structure is smaller than

Images