Multiple functional blocks on a system-on-chip (SOC)

JP2024516123A5Pending Publication Date: 2025-03-19QUALCOMM INC
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Patent Information

Application Number
JP2023562285
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2021-04-19
Filing Date
2022-03-24
Publication Date
2025-03-19

AI Technical Summary

Technical Problem

Current integrated circuit (IC) manufacturing techniques lack flexibility to accommodate different resistance (R) and capacitance (C) standards for functional blocks on a system-on-chip (SOC), leading to inefficiencies in performance and heat management.

Method used

The use of multiple metals during the back-end-of-line (BEOL) process to create customized interconnects for individual functional blocks on an SOC, where each block can have different metal layers tailored to its specific requirements, such as copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), or aluminum (Al), to optimize resistance and capacitance.

Benefits of technology

This approach allows for customized resistance and capacitance criteria to be met for each functional block, enhancing performance by reducing heat buildup and increasing throughput, thereby optimizing the operation of the SOC.

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Abstract

In one aspect, a system on a chip (SOC) includes a plurality of functional blocks including a first functional block and a second functional block co-located on the SOC. The SOC includes a first metal layer, a first dielectric layer disposed on a top surface of the first metal layer, and a first via disposed in the first dielectric layer and used in the first functional block. The SOC includes a second via disposed in the first dielectric layer and used in the second functional block, and a second metal layer disposed on the first dielectric layer. The second metal layer includes a first set of connections used in the first functional block and a second set of connections used in the second functional block. The first set of connections is different from the second set of connections. The SOC includes a second dielectric layer disposed on the first dielectric layer.
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