Manufacturing method and power semiconductor device

Abstract

In at least one embodiment, the power semiconductor device (1) comprises: - a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, the well region (22) including a channel region (220) directly in the source region (21); a gate insulator (4) directly between the semiconductor body (2) and the gate electrode (31), The channel region (220) has a non-uniform channel doping profile (6) along the gate insulator (4), resulting in a doping concentration N A is maximum in the first section (61) remote from the source region (21).

Description

[Technical field]

[0001] statement A manufacturing method for a power semiconductor device is provided. Additionally, a corresponding power semiconductor device is provided. [Background technology]

[0002] The document US Pat. No. 6,573,561 B1 refers to a vertical MOSFET having an asymmetric graded channel profile.

[0003] The document US Pat. No. 6,664,594 B2 discloses a power MOS device having an asymmetric channel structure for improving the linear operating capability.

[0004] The document US Pat. No. 8,067,797 B2 describes a variable threshold trench IGBT with offset emitter contacts.

[0005] The document US Patent Application Publication No. 2016 / 0064550A1 refers to a power device.

[0006] The documents US Patent Application Publication No. 2021 / 0111279A1 and US Patent Application Publication No. 2005 / 0133833A1 refer to electronic devices. Summary of the Invention [Problem to be solved by the invention]

[0007] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to power semiconductor devices and corresponding manufacturing methods that exhibit improved electrical behavior. [Means for solving the problem]

[0008] This object is achieved, inter alia, by a manufacturing method and a power semiconductor device as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0009] In at least one embodiment, a method for manufacturing a power semiconductor device includes, for example in the order listed, providing a semiconductor substrate; - epitaxially growing at least one semiconductor layer on a semiconductor substrate; - providing a gate insulator and a gate electrode, the gate insulator (4) being located directly between the at least one semiconductor layer and the gate electrode; Including, the semiconductor substrate and / or the at least one semiconductor layer constitute a semiconductor body having a source region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type, the well region including a channel region directly in the source region; The channel region has a non-uniform channel doping profile along the gate insulator, resulting in a doping concentration N A is greatest in a first section remote from the source region, and the non-uniform channel doping profile is formed completely or partially by epitaxial growth of the at least one semiconductor layer.

[0010] A power semiconductor device is further provided. A method for manufacturing a power semiconductor module is provided, as illustrated in relation to at least one of the embodiments described below. Accordingly, features of the power semiconductor device are also disclosed for the method and vice versa.

[0011] In at least one embodiment, the power semiconductor device comprises: a semiconductor body having a source region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type, the well region including a channel region starting directly from the source region; at least one gate electrode arranged in the semiconductor body and assigned to at least one channel region; at least one gate insulator located directly between the semiconductor body and at least one assigned gate electrode; Equipped with The channel region has an intentionally non-uniform channel doping profile along the gate insulator such that the doping concentration in the channel region is greatest in a first section away from the source region.

[0012] The gate electrode is insulated from the semiconductor body by a gate insulator. For example, the at least one source region is in direct contact with the assigned gate insulator and / or directly in the assigned channel region. The first conductivity type is, for example, an n-conductivity type, and thus the at least one source region is n-doped.

[0013] The at least one well region, and therefore the at least one channel region, is of a second conductivity type different from the first conductivity type. The second conductivity type is, for example, a p-conductivity type, and therefore the at least one channel region is p-doped. The maximum doping concentration of the at least one well region and / or the at least one channel region can be lower than the maximum doping concentration of the at least one source region.

[0014] According to at least one embodiment, the semiconductor body further comprises a drift region, which may be of the first conductivity type. For example, the drift region is in direct contact with the gate insulator and / or is directly in the channel region. The drift region may be located, for example, between the channel region and the drain or collector region of the semiconductor body in a direction perpendicular to the top surface of the semiconductor body. For example, the optional trench may terminate in the drift region.

[0015] Optionally, the semiconductor body may comprise an enhancement layer. For example, the enhancement layer may be located directly between the well region and the drift region and have a higher maximum doping concentration than the drift region. The enhancement layer may also be of the first conductivity type. The enhancement layer may function as a hole blocking layer, i.e., E off Improved Vce-sat In addition, the reinforcing layer also helps to control the length of the channel region and minimizes the variations due to the manufacturing process. For example, the thickness of the reinforcing layer is at least 1 μm and / or at most 5 μm.

[0016] According to at least one embodiment, the doping concentration N A is maximum at a depth from the top surface of the semiconductor body of at least 0.5 μm or at least 1.5 μm. A may also be at a distance of at least 0.5 μm or at least 1.5 μm from the source region along the gate insulator. The maximum may be located within a well region. Thus, the maximum is achieved by epitaxial growth rather than ion implantation.

[0017] According to at least one embodiment, the power semiconductor device is a Metal-Insulator-Semiconductor Field Effect Transistor, MISFET, Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET, or an Insulated Gate Bipolar Transistor, IGBT or Reverse Conducting Insulated Gate Bipolar Transistor, RC-IGBT.

[0018] According to at least one embodiment, the well region extends from a top surface of the semiconductor body to the drift region. The channel region is part of the well region and may have the same doping concentration. In operation, electrons flow in the channel region from the source region along the gate insulator to the drift region. The channel region has a thickness in the nanometer range, illustratively between 1 nm and 50 nm, in a direction perpendicular to the interface between the gate insulator and the well region.

[0019] For example, the semiconductor body is made of silicon, or Si for short. However, the semiconductor body may alternatively be made of SiC, Ga 2 O 3 , or may be made of a wide bandgap semiconductor material such as GaN.

[0020] The gate insulator is made of any insulating material, which may be an oxide. For example, the gate insulator may be made of the following material: SiO 2 , Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , ZrO 2 , HfO 2 , La 2 O 3 , Ta 2 O 5 , TiO 2 The gate insulator is therefore sometimes called a gate oxide.

[0021] According to at least one embodiment, the power semiconductor device is a power device, for example configured for a maximum voltage of at least 0.2 kV, or at least 0.6 kV, or at least 1.2 kV.

[0022] The power semiconductor device is intended for a power module in a vehicle, for example in a hybrid or plug-in electric vehicle, that converts direct current from a battery or fuel cell into alternating current for an electric motor. Additionally, the power semiconductor device may be a fuse in a vehicle, such as an automobile.

[0023] For simplicity, in the following only one channel region and assigned components are referred to. If multiple channel regions and assigned components are present, the features described below may apply to only one, multiple, or all of the channel regions and assigned components.

[0024] According to at least one embodiment, in the channel region, the doping concentration increases monotonically or strictly monotonically along the gate insulator, e.g., towards the drift region, where monotonically means that the doping concentration is constant or increasing, and strictly monotonically means that the doping concentration increases continuously towards the drift region.

[0025] According to at least one embodiment, the non-uniform channel doping profile along the gate insulator has a first section away from the source region and adjacent to the drift region, the doping concentration being highest in the first section.

[0026] Otherwise, the doping concentration is highest in an intermediate section of the channel region between the first section and the second section, the second section being closer to the assigned source region and farther from the drift region.

[0027] If no such intermediate section is present, the channel region may consist of a first section having the highest doping concentration and a second section adjacent to the source region.

[0028] According to at least one embodiment, the length of the first section and / or the intermediate section is at least 5%, or at least 10%, or at least 15% of the total length of the channel region along the gate insulator. Alternatively or additionally, said length is at most 40%, or at most 30%, or at most 25% of said total length. The same may apply to the second section, if present.

[0029] According to at least one embodiment, the doping concentration is constant along the gate insulator in the second section and / or the middle section. Constant means, for example, that there is no intentional variation in the doping concentration so that variations due to manufacturing tolerances can be ignored. For example, constant may mean that there is no change in the doping concentration in the second section and / or the middle section that is more than 5%, or more than 10%, or more than 15% of the maximum doping concentration present in the channel region.

[0030] According to at least one embodiment, the doping concentration varies along the channel region by at least 50%, or at least 65%, or at least 80% of the maximum doping concentration of the non-uniform channel doping profile, for example, the second section has a maximum doping concentration that is at most 50%, or at most 35%, or at most 20% of the maximum doping concentration of the first section, or of the middle section if the maximum doping concentration is in the middle section.

[0031] According to at least one embodiment, the channel doping profile is configured in a stepped manner such that there are one or more steps in the channel doping profile along the gate insulator in the channel region, or the channel doping profile along the gate insulator may vary continuously and without steps.

[0032] According to at least one embodiment, the gate electrode is partially or completely disposed in at least one trench formed in the semiconductor body. The at least one trench, and thus the assigned gate electrode, extends, for example, in a direction away from the top surface of the semiconductor body through the well region into the drift region. As a result, the gate insulator is also partially or completely located in the assigned trench. The power semiconductor device may therefore be a trench-based device.

[0033] Otherwise, the gate electrode and gate insulator are applied to the top surface of the semiconductor body, which may therefore be planar.

[0034] According to at least one embodiment, the well region is of multi-layer type, so that it includes at least two sublayers. For example, the sublayers may be epitaxially grown or may be produced by ion implantation and / or thermal treatment. It is possible that the sublayers are of the same material, but their doping concentrations are different. Thus, there may be clear jumps in doping concentration between the sublayers, and within each sublayer, the doping concentration may be constant, for example, with a tolerance of at most 5% of the maximum doping concentration of the respective layer. For example, in at least some planes parallel to the top surface, the doping concentration may be constant in this case throughout the well region. In other words, there may be an intentional doping gradient only along the depth of the well region, and no intentional doping gradient in the lateral direction parallel to the top surface.

[0035] Otherwise, the well region is of single layer type and includes only one layer in which a doping profile is established. Such a doping profile may be continuous and rectangular without steps and may be produced, for example, by ion implantation and / or thermal processing.

[0036] If multiple sublayers are present, the sublayers may be created by applying different dopants and / or may be grown in different epitaxial growth steps where the respective doping concentrations are added during the epitaxial growth. The application of the dopants may be done in a single step or by two or more application steps, for example by using different implantation energies or different dopants. In the case of planar devices, a mask may be used to apply the dopants to achieve a non-uniform channel doping profile. A heat treatment step may follow the application of the dopants or the epitaxial growth.

[0037] According to at least one embodiment, outside the channel region and along the depth of the well region, i.e. perpendicular to the top surface, the well region has at least some constant doping concentration. Thus, along at least some vertical intersections, the doping concentration may be constant within the well region. Thus, within the well region, the non-uniform channel doping profile may be limited to the region adjacent to the gate insulator. For example, the non-uniform channel doping profile may be limited to the channel region with a tolerance of, for example, at most 0.5 μm.

[0038] According to at least one embodiment, the gate insulator has a non-uniform thickness along the channel region, for example, along the channel region, the gate insulator is thickest in a first section.

[0039] According to at least one embodiment, the gate electrode has a non-uniform gate electrode work function profile along the channel region such that a threshold voltage of the gate electrode is highest in the first section. Thus, the work function Φ of the gate electrode in the first section away from the source region is m is maximum for devices having p-type doped well regions and correspondingly p-type doped channel regions, and is minimum for devices having n-type doped well regions and correspondingly n-type doped channel regions.

[0040] According to at least one embodiment, the gate insulator has a non-uniform gate insulator thickness profile along the channel region. In other words, the thickness of the gate insulator varies along the channel region. The thickness variation can be continuous or non-continuous, i.e., stepped. For example, along the channel region, the gate insulator can be thickest in a first section and, consequently, thinnest in a second section.

[0041] In accordance with at least one embodiment, the gate insulator has a non-uniform gate dielectric constant profile along the channel region such that the dielectric constant of the gate insulator is lowest in a first portion of the channel region away from the source region.

[0042] According to at least one embodiment, there is a non-uniform thickness profile, as well as a non-uniform channel doping profile and / or a non-uniform gate electrode work function profile and / or a non-uniform gate dielectric constant profile, i.e., the non-uniform channel doping profile can be combined with a non-uniform gate insulator thickness, a non-uniform gate electrode work function profile, or a non-uniform gate dielectric constant profile, or with two of the non-uniform channel doping profile, the non-uniform gate electrode work function profile, and the non-uniform gate dielectric constant profile, or with all three other non-uniform profiles.

[0043] According to at least one embodiment, the power semiconductor device has a collector-emitter saturation voltage V ce-sat , thus both saturation current and short circuit current are reduced while on-state losses can remain unaffected. This is true for a non-uniform channel doping profile, which may be compared to a similarly set up reference semiconductor device having a uniform doping profile with the same integral doping concentration as the non-uniform channel doping profile of the channel region along the gate insulator.

[0044] The power semiconductor device is described in more detail below by way of exemplary embodiments with reference to the drawings, in which the same elements in the individual figures are indicated by the same reference numerals, however the relationships between the elements are not shown to scale, rather the individual elements may be shown exaggerated in size to aid understanding. [Brief description of the drawings]

[0045] [Figure 1] 2 is a schematic cross-sectional view of a reference semiconductor device; [Diagram 2] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Diagram 3] FIG. 3 is a top view of the power semiconductor device of FIG. 2. [Figure 4] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Diagram 5] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 6] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 7] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 8] FIG. 2 is a schematic diagram of doping profiles of a power semiconductor device and a reference semiconductor device described herein. [Figure 9] FIG. 1 illustrates simulation results of electrical data for a power semiconductor device described herein and a reference semiconductor device. [Figure 10] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 11] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 12] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 13] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 14] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 15] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 16] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] 1 shows a reference semiconductor device 9 which corresponds to the exemplary embodiment of the power semiconductor device 1 described herein, except for the channel doping profile 6, 69 in a channel region 220 contained in a well region 22. Like the power semiconductor device 1, the reference semiconductor device 9 comprises a semiconductor body 2, e.g. made of Si.

[0047] The semiconductor body 2 also comprises a source region 21 at a top surface 20 of the semiconductor body 2. A trench penetrates both the well region 22 and the source region 21. The source region 21 is of a first conductivity type, such as n-conductivity, and the well region 22, and therefore the channel region 220 contained by the well region 22, is of a second, different conductivity type, such as p-conductivity. Within the trench is a gate electrode 31 separated from the semiconductor body 2 by an electrically insulating gate insulator 4. The trench, and therefore the gate electrode 31, terminates in a drift region 23 of the semiconductor body 2. The drift region 23 is also of the first conductivity type.

[0048] In the reference semiconductor device 9, the channel region 220 is doped with a uniform reference doping profile 69, i.e., a constant doping concentration N AFor example, adjacent to the gate insulator 4, where the source region 21 and the channel region 220 are in direct contact, x=0. For example, adjacent to the gate insulator 4, where the channel region 220 and the drift region 23 are in direct contact, x=L. That is, L corresponds to the channel length of the channel region 220. For example, x extends perpendicularly to the upper surface 20 of the semiconductor layer body 2. Thus, the length L may correspond to the distance between the source region 21 and the drift region 23 directly at the gate insulator 4. Thus, the length L may be defined as the length of the layer of the first conductivity type, i.e., the layer of the second conductivity type between the source region 21 and the drift region 23, and the drift region 23 may include a layer of low doping concentration not shown.

[0049] The shape of the channel region 220 is only very diagrammatically depicted and is drawn along only one side of the gate electrode 31 for simplicity of the drawing.

[0050] According to the exemplary embodiment of the power semiconductor device 1 shown in Figures 2 and 3, the well region includes a non-uniform channel doping profile 6, which may be present throughout the well region 22 or may be limited to the channel region 220 or adjacent regions of the channel region 220 and the well region 22. Thus, the doping concentration N A varies stepwise such that the doping profile 6 has a step 53. The step 53 does not have to strictly follow a theta function or a unit step function, but there may be a transition section 62. Compared to the channel length L, the length of the transition section 62 is small, for example at most 2% or at most 5% of the channel length L.

[0051] As a result, the doping concentration N A is highest adjacent to the drift region 23 in a first section 61 of the doping profile 6. The length of the first section 61 is, for example, ¼ or ⅓ of the channel length L. For example, the length of the first section 61 is 20% to 40% of the channel length L. The doping concentration NA The variation in is only diagrammatically shown in FIG.

[0052] For example, the maximum doping concentration N A is the maximum doping concentration N A In the second section 64, the doping concentration N A may be substantially constant. Both the source region 21 and the well region 22 may be electrically connected by at least one source electrode 32 located on the top surface 20.

[0053] Optionally, there may be at least one plug 25 in the top surface 20 of the semiconductor body 2 to electrically contact the channel region 220. The plug 25 may have a different thickness than the well region 22 such that the plug 25 may extend deeper or shallower into the semiconductor body 2 than the well region 22. Furthermore, the thicknesses of the source region 21 and the plug 25 may be the same or different.

[0054] Furthermore, between the drift region 23 and the well region 22 there is a reinforcement layer 27. The reinforcement layer 27 is also of the first conductivity type.

[0055] Both the source region 21 and the at least one plug 25 may be electrically connected by at least one source electrode 32 located on the top surface 20. Illustratively, the plug 25 has a higher maximum doping concentration than the well region 22 or the channel region 220. The depth of the plug may be lower, deeper or the same as the depth of the well region / channel region.

[0056] 2 and 3, the source regions 21 and the optional at least one plug 25 are located along only one side of the gate electrode 31. However, the source regions 21 and the optional at least one plug 25 can also be located along both sides of the gate electrode 31 or all around the gate electrode 31, for example, as compared to FIG.

[0057] For example, the power semiconductor device 1 is an insulated gate bipolar transistor, IGBT for short. Therefore, on the side of the drift region 23 remote from the well region 22, there is also a collector region 26 of the second conductivity type. In the collector region 26, a collector electrode 34 is present. Furthermore, as a further option, there may be a buffer region of the first conductivity type between the drift region 23 and the collector region 26. The doping concentration of such a buffer region, not shown, may be higher than the doping concentration of the drift region 26.

[0058] When viewed in top view on the top surface 20, the trench housing the gate electrode 31 and the gate insulator 4 may be elongated. The source region 21, the at least one plug 25, and the channel region 220 may be symmetrically disposed on either side of the trench, see FIG.

[0059] For example, instead of the source region 21, the collector region 26 or the drain region 24, and at least one plug 25 has a maximum doping concentration of at least 1×10 18 cm -3 Or at least 5×10 18 cm -3 Or at least 1×10 19 cm -3 and / or at most 5 × 10 20 cm -3 Or at most 2×10 20 cm -3 Or at most 1×10 20 cm -3 Furthermore, the maximum doping concentration of the well region 22, and therefore the channel region 220, is at least 5×1016 cm -3 Or at least 1×10 17 cm -3 and / or at most 5 × 10 19 cm -3 Or at most 5 x 10 18 cm -3 For example, the maximum doping concentration in the first section 61 can be at least 1.5×10 17 cm -3 and / or at most 3 × 10 18 cm -3 For example, the maximum doping concentration present in the non-uniform channel doping profile 6 is at least 5×10 16 cm -3 and at most 3 × 10 18 cm -3 and / or the minimum doping concentration present in the non-uniform channel doping profile 6 is at most 2×10 17 cm -3 Or at most 1×10 17 cm -3 For example, the maximum doping concentration of the enhancement layer 27 is at least 10 15 cm -3 and / or at most 10 18 cm -3 It is.

[0060] Depending on the voltage class of the power semiconductor device 1, the maximum doping concentration of the drift region 23 is at least 1×10 11 cm -3 Or at least 1×10 12 cm -3 Or at least 1×10 13 cm -3 and / or at most 1 × 10 17 cm -3 Or at most 5 x 10 16 cm -3 Or at most 1×10 16 cm -3 It could be.

[0061] For example, the semiconductor body 2 is at least partially produced by epitaxial growth, i.e. the doping concentration of the respective layers of the semiconductor body 2 may be generated during growth and not after growth, for example by ion implantation. This applies, for example, at least to the enhancement layer 27 and to the well region 22, which may thus be doped by epitaxial growth. Optionally, the drift region 23 may be partly or completely part of the growth substrate. The same applies to all other examples.

[0062] If not, the same may be true for Figures 2 and 3 as for Figure 1 . The concept behind the channel region 220 having a non-uniform channel doping profile 6 is explained below.

[0063] For power semiconductor device 1, illustratively for low frequency applications, it may be desirable to have as low an on-state loss as possible in order to minimize total electrical losses. Furthermore, from a device reliability standpoint, it may be advantageous to have a low short circuit current. Thus, a power semiconductor device 1 with minimized on-state losses and improved short circuit capability may be desired.

[0064] However, for example, decreasing the channel length L or increasing the channel width W can reduce the on-state voltage drop V ce-sat Several means of reducing the output characteristic I c Against V ce As shown diagrammatically using the undesirable higher saturation current I sat See Figure 4. High I sat is a high short circuit current I sc This directly relates to the short circuit capability of the power semiconductor device 1 and adversely affects the short circuit capability of the power semiconductor device 1. On the other hand, the I sat In order to reduce the threshold voltage V th As shown in Figure 5, increasing V ce-satTherefore, Figures 4 and 5 are schematic diagrams of typical output characteristics of an IGBT with a uniform threshold profile along the entire channel region. th and different channel resistances. In Fig. 5, different threshold voltages V th This is the case.

[0065] a) Increasing the channel length L; b) Reducing the anode injection efficiency by reducing the anode implant dose; c) reducing the channel width by reducing the source coverage along the trench; and d) Reducing the channel width by increasing the cell pitch Other techniques for reducing the short circuit current, such as d), also undesirably result in higher on-state losses. Moreover, techniques such as d) may also adversely affect the breakdown capability of the power semiconductor device 1. Reducing the gate bias to reduce the short circuit current may also lead to unstable dynamic behavior and may be undesirable, as it is primarily dictated by the application requirements.

[0066] Thus, in conventional MISFET or IGBT devices, there is a trade-off between minimizing on-state losses and reducing short-circuit current. For applications requiring improved short-circuit capability, V ce-sat Without affecting the short circuit current I sc It may be desirable to be able to reduce

[0067] In the power semiconductor device 1 described herein, the tradeoff between on-state losses and short circuit current is improved by improving the latter without adversely affecting the former. Unlike other approaches, the described design provides a ce-satThe non-uniform threshold voltage profile proposed in the power semiconductor device 1 described herein is characterized by a non-uniform threshold voltage profile along the channel region 220 adjacent to the gate insulator 4 in order to reduce the saturation current for V th is realized by implementing a non-uniform channel doping profile 6 in the channel region 220. The described power semiconductor device 1 does not adversely affect the breakdown capability and even more so the turn-off losses of the power semiconductor device 1. In addition, the described concept is applicable to generally any MOS device such as a power MOSFET or an IGBT or a reverse conducting IGBT and is even compatible with both planar and trench architectures.

[0068] In the power semiconductor device 1 described herein, improved MISFET, MOSFET, or IGBT or RC-IGBT devices are introduced that have improved short circuit capability without detrimentally affecting the on-state losses. The improved design also relaxes the design constraints of the IGBT, allowing the possibility to independently explore other methods mentioned above to minimize the on-state losses that are usually limited by the short circuit capability of the respective device.

[0069] In the following, some theoretical background to the conception of the semiconductor device 1 described herein is presented.

[0070] For standard long channel MOS devices, high V ce It is known that the channel pinch-off at V causes current saturation in the output characteristic, which ultimately determines the short circuit current. pinch-off is the threshold voltage V th Exemplarily, the applied bias V ce is the pinch-off voltage V pinch-off ≒(V g -V th ), the channel begins to pinch off near its drain end at x=L, where V gis the applied gate voltage and L is the channel length. ce The voltage drop perpendicular to the channel is V th It is smaller and therefore the channel can no longer persist near the drain end.

[0071] However, for a more detailed understanding of the device, channel pinch-off should be considered as a rather local phenomenon, occurring specifically near the drain end of the channel. More precisely, it is the local threshold voltage V that determines the pinch-off point, and hence the saturation current. th (x). This is because in the first section 61 near the channel end, i.e., the drift region 23, V th By locally increasing (L), V pinch-off This means that it is possible to reduce

[0072] Additionally, it preserves the overall channel resistance, thereby reducing V ce-sat To avoid affecting V th (x) can be reduced.

[0073] This is because the curve pointing to the reference semiconductor device 9 has a uniform threshold voltage V th-1 6 including the profile. On the other hand, the curve for the power semiconductor device 1 shows a non-uniform V along the channel. th It consists of a profile, V th is V to lower the pinch-off point. th-2 (L)>V th-1 and in the remainder of the channel, V is increased to keep the overall channel resistance the same. th-2 ' <V th-1 In this way, the saturation current, and therefore the short circuit current, can be significantly reduced without affecting the on-state losses, as shown in the schematic output of Figure 7. thVariation holds the key to improving the short circuit capability of MISFET or MOSFET or IGBT devices.

[0074] Channel V th is a function of various other MOS cell design parameters as shown in the following equation:

[0075]

number

[0076] Here, V t is the threshold voltage, V fb is the flat band voltage, V fb =(φ m -φ s ), where φ m and φ s are the gate metal work function and the semiconductor work function, respectively. N A is the doping of the channel body, and ε s is the dielectric constant of the semiconductor, and C ox is the gate insulator capacitance, and φ B is the semiconductor surface potential,

[0077]

number

[0078] where k is the Boltzmann constant, T is the temperature, and n i is the intrinsic carrier concentration of the semiconductor.

[0079] Therefore, the relatively high V th The non-uniform V required across the channel th The profile can be achieved by introducing non-uniformity in one or any combination of the following MOS design parameters:

[0080] 1. Channel doping profile as detailed herein, NA (x), 2. Gate oxide thickness, Tox(x), 3. Gate dielectric constant, ε ox (y), and / or 4.V fb =(φ m -φ s ), so the gate metal work function φ m (x).

[0081] In the following, we focus on varying the channel doping profile, however, said doping concentration variations can of course be combined with varying gate insulator thickness, varying gate dielectric constant, and / or varying gate metal work function.

[0082] 1 and 2 above show schematic cross-sectional views of a reference semiconductor device 9 with a uniform doping profile 69 and a power semiconductor device 1 with a non-uniform channel doping profile 6, which are implemented in the simulations presented below. Three different doping profiles A, B, C were investigated, see FIG. 8.

[0083] That is, the non-uniform channel doping profile N A (x) is a locally varied V th To obtain the profile, a technical computer-aided design, TCAD, and simulation were implemented. In these designs A, B, and C, the boron concentration N along the channel region 220 is A (x) was varied such that its peak position shifted from x=0 at the top of the channel region 220 to x=L at the bottom, as shown in FIG. 8. For comparison, the uniform doping profile 69 of the reference semiconductor device 9 is also shown. However, for all four of these designs A, B, C, 69, the total integrated doping concentration along the channel was the same V ce-sat was kept the same to maintain

[0084] The output characteristic, see FIG. 9, is due to the local V th 4 shows the expected effect due to the variation. The design having a boron peak in the first section 61 of the channel region 220, i.e., Design A, exhibits a reduced I compared to Design C having a peak doping concentration in the second section 64 adjacent to the source region 21. sat Design A also exhibits the same reason, i.e., a higher local V at the channel region edge. th , which is better compared to the reference uniform doping profile 69. Furthermore, it is noted that design C may not be desirable for applications where the short circuit current needs to be reduced. The short circuit problem, i.e., to reduce the current between the source and the collector, is solved in the power semiconductor device 1 described herein by introducing a non-uniform channel doping profile 6 having a higher doping near the channel ends, i.e., a higher doping concentration in the middle section 63 or the first section 61 adjacent to the drain region as in designs B and A.

[0085] V ce-sat The overall channel resistance is kept the same by lowering the doping in other parts of the channel that fixes I. In design B, the peak doping concentration in the middle section 63 between the second section 64 and the first section 61, and I sat is already reduced compared to the reference semiconductor device 9.

[0086] The breakdown characteristics of the device remain unaffected by having a non-uniform channel doping profile 6. The switching losses E off remains almost unaffected by having a non-uniform channel doping profile 6, the following list summarizing the simulation results for designs A, B, and C compared with the different doping profiles shown in Figure 8.

[0087] Design C of a semiconductor device having a doping peak in a first section 64 adjacent to the source region 21: V at -150A ce-sat :1.667V V at -10mA th :7.12V -E off :13.76mJ -I sc :=100% Design B of an exemplary power semiconductor device 1 with a doping peak in the middle section 63: V at -150A ce-sat :1.676V V at -10mA th :7.12V -E off :13.58mJ -I sc :=Design C I sc Approximately 73% of Design A of an exemplary power semiconductor device 1 with a doping peak in the first section 61: V at -150A ce-sat :1.688V V at -10mA th :7.08V -E off :13.72mJ -I sc :=Design C I sc Approximately 62% of For example, the channel length L is in each case 1 μm to 10 μm or 1 μm to 5 μm. In the exemplary devices 9, A, B, C, the channel length L is in each case 2.5 μm, and the first section 61 of design A has a length of 0.5 μm.

[0088] In the exemplary embodiment of the power semiconductor device 1 of Fig. 10, the doping profile 6 again has one step 53. Optionally, the channel region 220 is produced, for example grown, with a first sublayer 51 and a second sublayer 52 which may be doped during growth, so that in this exemplary embodiment there is substantially no transition region.

[0089] In all other illustrative embodiments, the trench housing the gate electrode 31 need not have rounded ends in the drift region 23, but may be rectangular in shape or other shapes when viewed in cross section; see also FIG. 10.

[0090] As is possible in all other exemplary embodiments of the power semiconductor device 1 , the outer side of the gate insulator 4 facing the semiconductor body 2 may be planar at least along the channel region 220 .

[0091] Moreover, the power semiconductor device 1 in Fig. 10 is shown to be a MISFET or MOSFET, not an IGBT. As a result, the power semiconductor device 1 comprises a drain region 24 instead of a collector region 26. Thus, on the side of the drift region 23 remote from the well region 22, there is also a drain region 24 of the first conductivity type, but with, for example, a higher maximum doping concentration than the drift region 23. In the drain region 24, a drain electrode 33 is present.

[0092] Of course, all gate insulator designs for IGBT power semiconductor devices 1 can be applied to MOSFET and MISFET power semiconductor devices 1, and vice versa.

[0093] If this is not the case, the same may be true for FIG. 10 as for FIG. 2-FIG. 9, and vice versa.

[0094] 11, the doping profile 6 includes multiple steps 53, for example two steps 53. For example, the second step closer to the drift region 23 is larger than the first step closer to the source region 21. The first step may define the start of a first section 61.

[0095] Optionally, a non-uniform channel doping profile 6 can be combined with a varying thickness of the gate insulator 4. For example, in a first section along the channel region outside the edge, the thickness of the gate insulator 4 is ≧20 nm and ≦80 nm, or ≧40 nm and ≦80 nm.

[0096] As in all other exemplary embodiments, these two ideas, namely having an asymmetric non-uniform gate insulator thickness and a non-uniform channel doping profile 6, can be combined with each other. In this case, the gate insulator 4 may be thickest in the first section 61. The thickness of the gate insulator 61 is determined by the doping concentration N A The progression of the non-uniform channel doping profile 6 described herein may therefore also be applied to a non-uniform gate insulator thickness, and the progression of the non-uniform channel doping profile 6 and the non-uniform gate insulator thickness may be the same or different.

[0097] Alternatively or additionally, in the section adjacent to the drift region 23, thus in the first section 61, said thickness may be ≧120 nm and ≦250 nm or ≧120 nm and ≦180 nm. For example, these two thicknesses of the gate insulator 4 differ by at least a factor of 1.5 and / or at most a factor of 5. A jump position J in the gate insulator thickness is, for example, in the first section 61. For example, said position J is between two steps 53 of the doping profile 6.

[0098] If this is not the case, the same may be true for FIG. 11 as for FIG. 2-FIG. 10, and vice versa.

[0099] In Figure 12, the doping concentration N A is shown not to be formed in a step shape but to vary continuously at the beginning of the first section 61. The doping concentration N AThe transition section 62 where the length L changes may be, for example, at least 2% and / or at most 15% or at most 10% or at most 5% of the length L. As in FIG. 11, there may be two or more such transition sections 61.

[0100] If this is not the case, the same may be true for FIG. 12 as for FIG. 2-FIG. 11, and vice versa.

[0101] According to FIG. 13, the doping concentration N A does not increase monotonically. Therefore, the higher doping concentration N A and the original doping concentration N A , adjacent to the drift region 23. A There is a large third step to the doping concentration N A The smaller peak may be located in the middle section 63.

[0102] If this is not the case, the same may be true for FIG. 13 with respect to FIGS. 2-12, and vice versa.

[0103] In the exemplary embodiment of FIG. A increases continuously in a linear fashion from the second section 64 to the first section 61. Thus, a clearly defined interface or dividing line between the first section 61 and the second section 64 is not necessary.

[0104] If this is not the case, the same may be true for FIG. 14 as for FIG. 2-FIG. 13, and vice versa.

[0105] According to FIG. 15, the power semiconductor device 1 is of planar design, and not of trench design, as for example the power semiconductor device 1 of FIG. 2 and FIG. 3. Thus, the top surface 20 is planar, and the gate insulator 4 and the gate electrode 31 are applied to the top surface 20. As a result, the length L between the source region 21 and the drift region 23 is parallel to the top surface 20, unlike the other exemplary embodiments which are perpendicular to the top surface 20. The doping concentration N A The same applies to the direction x in which changes.

[0106] 15, the well regions 22 protrude laterally, i.e. parallel to the top surface 20, from the source regions 21 and extend below the gate insulator 4. The source regions 21 may also extend below the gate insulator 4, but to a lesser extent.

[0107] All the above mentioned different designs of the doping profile 6 can be applied equally to the planar concept of Fig. 15, both in case of MISFET or MOSFET as well as in case of IGBT. Thus, the same may be applied to Fig. 14 as for Figs. 2-13.

[0108] 16 shows that there is a non-uniform channel doping profile of the gate insulator 4 due to the optionally present at least two different materials 81, 82 of which the gate insulator 4 is composed, as well as a non-uniform gate insulator thickness profile and a non-uniform gate dielectric constant profile, i.e. the thickness of the gate insulator 4 varies along the channel region 220.

[0109] For example, the difference in dielectric constant along the channel region 220 due to the at least two different materials 81, 82 is at least 2.0, or at least 3.0, or at least 3.5. Alternatively or additionally, said difference is at most 50, or at most 25. When comparing the respective dielectric constants, textbook values ​​of the respective materials at room temperature, i.e. 300K, and at a frequency of the alternating electric field of at most 1 kHz may be used.

[0110] For example, the thickness of the first material 81 in the first section 61 exceeds the thickness of the second material 82 in the second section 64, and vice versa. For example, the thickness difference between the first material 81 and the second material 82 is at least 20% or at least 40% of the maximum thickness of the gate insulator 4 along the channel region 220. When only a non-uniform gate insulator thickness profile and a uniform gate dielectric constant profile are present, the gate insulator 4 may be made of a single material.

[0111] For example, the thickness of the gate insulator 4 in the second section 64 is 50 nm to 100 nm, and / or the thickness of the gate insulator 4 in the first section 61 is 100 nm to 240 nm. However, other than as shown in FIG. 16 , the thickness of the gate insulator 4 in the first section 61 may alternatively be smaller than in the second section 64, and the maximum thickness may be in the second section 64 instead.

[0112] Thus, there is a step in the non-uniform gate channel doping profile 6 at the interface between the first section 61 and the second section 64, see the inset of FIG.

[0113] In addition to or instead of a non-uniform gate dielectric constant profile and / or a non-uniform gate insulator thickness profile, there may be a non-uniform gate electrode work function profile 72. Thus, the gate electrode 31 may include a first gate material 84 adjacent to the source region 21 and a second gate material 85 adjacent to the drain region 23. The gate materials 84, 85 may vary where the materials 81, 82 of the gate insulator 4 vary. Thus, the work function Φ of the gate electrode 31 in the first section 61 away from the source region 21 m is maximum for device 1 with p-doped well region 22 and is minimum for device 1 with n-doped well region 22.

[0114] For example, the work function difference of the gate electrode along the channel region 220 is at least 0.7 eV, or at least 1.0 eV, or at least 1.1 eV. This is the case, for example, when the gate electrode 31 is based on polysilicon. If metals such as Li, Zn, Hf for low work functions or Pt, Pd, or Au for high work functions are also considered, the work function difference can be at least 1.3 eV or at least 1.4 eV. For example, the work function difference is at most 2.0 eV or at most 1.5 eV.

[0115] For example, the second gate material 85 has a work function Φ of about 5.22 eV. m p + For example, the first gate material 84 is doped polysilicon having a work function Φ of about 4.1 eV. m n + Although based on silicon, these first gate material 84 and second gate material 85 are sometimes referred to as different gate electrode metals.

[0116] Such at least one of a non-uniform gate insulator thickness profile, a non-uniform gate insulator dielectric constant profile, and a non-uniform gate insulator thickness profile may also be present in all other exemplary embodiments similarly.

[0117] If this is not the case, the same may be true for FIG. 16 as for FIG. 2-FIG. 15, and vice versa.

[0118] Components depicted in the figures exemplarily follow one another directly in the specified order, unless otherwise indicated. Components that are not in contact in the figures are exemplarily spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of depicted components relative to one another are accurately reproduced in the drawings.

[0119] The power semiconductor device described herein is not limited by the description based on the exemplary embodiments, but rather includes any novel feature and any combination of features, including any combination of features in the claims, even if this feature or this combination itself is not explicitly specified in the claims or exemplary embodiments.

[0120] This patent application claims priority to European Patent Application No. 21186114.1, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0121] List of References 1. Power Semiconductor Devices 2. Semiconductor body 20 Top side 21 Source Area 22 Well Area 220 Channel Area 23 Drift Region 24 Drain Region 25 Plug 26 Collector Region 27 Reinforcement layer 31 Gate electrode 32 Source electrode 33 Drain electrode 34 Collector electrode 4 Gate insulator 51 First sublayer of channel region 52 Second sublayer of channel region 53 Doping concentration steps 6 Non-uniform channel doping profile 61 First Section 62 Transition Section 63 Mid Section 64 Second Section 69 Uniform Reference Doping Profile 72 Non-uniform gate electrode work function profile 81 First Ingredient 82 Second Ingredient 84 First Gate Material 85 Second Gate Material 9 Reference Semiconductor Device A First Exemplary Power Semiconductor Device B. Second Exemplary Power Semiconductor Device C. Third Exemplary Power Semiconductor Device J Gate insulator thickness jump position I sat saturation current L is the length of the channel region along the gate insulator N A Doping Concentration V th Threshold Voltage x is the length along the channel region

Claims

1. A method for manufacturing a power semiconductor device (1), comprising: - providing a semiconductor substrate; - epitaxially growing at least one semiconductor layer on the semiconductor substrate; - providing a gate insulator (4) and a gate electrode (31), wherein the gate insulator (4) is directly positioned between the at least one semiconductor layer and the gate electrode (31); - wherein - the semiconductor substrate and / or the at least one semiconductor layer form a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, and the well region (22) directly includes a channel region (220) in the source region (21); - the channel region (220) has a non-uniform channel doping profile (6) along the gate insulator (4), such that the doping concentration N in the channel region (220) A is maximum in a first section (61) away from the source region (21), and the non-uniform channel doping profile (6) is formed completely or partially by the epitaxial growth of the at least one semiconductor layer a method.

2. The method according to claim 1, wherein the semiconductor body (2) further comprises a strengthening layer (27) of the first conductivity type directly on a side of the well region (22) away from the source region (21). The doping concentration N within the channel region (220) A is maximum at a depth from the upper surface (20) of the semiconductor body (2) of at least 0.5 μm The method according to claim 1.

3. The doping concentration N A includes a plurality of steps (53), The method according to claim 1 or 2.

4. The doping concentration N A increases linearly or substantially linearly from the source region (21) to the drift region (23), Substantially linear, meaning that the actual doping concentration deviates by at most 0.1 from the maximum doping concentration of the non-uniform channel doping profile (6) along the gate insulator (4) in the well region (22) from a linear fit of the non-uniform channel doping profile (6). The method according to claim 1 or 2.

5. - A semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, wherein the well region (22) directly includes a channel region (220) in the source region (21); - a gate insulator (4) directly between the semiconductor body (2) and the gate electrode (31); A power semiconductor device (1) comprising: The channel region (220) has a non-uniform channel doping profile (6) along the gate insulator (4), such that the doping concentration N A is maximum in a first section (61) away from the source region (21), wherein one of the following - the doping concentration N A includes a plurality of steps (53), or - the doping concentration N A increases linearly or substantially linearly from the source region (21) to the drift region (23). applies. A power semiconductor device (1).

6. - the source region (21) is in direct contact with the gate insulator (4) and the channel region (220); - the semiconductor body (2) is in direct contact with the gate insulator (4) and further comprises a drift region (23) of the first conductivity type directly in the channel region (220). - the power semiconductor device (1) is a metal-insulator-semiconductor field effect transistor, MISFET, metal-oxide-semiconductor field effect transistor, MOSFET, insulated gate bipolar transistor, IGBT, or reverse conducting insulated gate bipolar transistor, RC-IGBT, The power semiconductor device (1) according to claim 5.

7. Along the gate insulator (4), the doping concentration N in the channel region (220) A is directly the highest in the drift region (23), The power semiconductor device (1) according to claim 5 or 6.

8. The doping concentration N A increases monotonically or strictly monotonically in the channel region (220) along the gate insulator (4) in a direction away from the source region (21). The power semiconductor device (1) according to claim 5 or 6.

9. The doping concentration N A increases linearly, The power semiconductor device (1) according to claim 8.

10. The doping concentration N A does not monotonically increase from the source region (21) to the drift region (23), and as a result, the doping concentration N A includes a peak within the intermediate section (63) of the channel region (220). The power semiconductor device (1) according to claim 5 or 6.

11. the length of the first section (61) is at least 10% and at most 40% of the total length L of the channel region (220) along the gate insulator (4), The power semiconductor device (1) according to claim 5 or 6.

12. The non-uniform channel doping profile (6) has a second section (64) extending along the gate insulator (4) to the source region (21), and the doping concentration N A is constant along the gate insulator (4) within the second section (64), The power semiconductor device (1) according to claim 5 or 6.

13. The doping concentration N A varies along the channel region (220) by at least 50% of the maximum doping concentration of the non-uniform channel doping profile (6). The power semiconductor device (1) according to claim 5 or 6.

14. - the maximum doping concentration of the non-uniform channel doping profile (6) is at least 5×10 １６ cm －３ and at most 3×10 １８ cm －３ or - The minimum doping concentration of the non-uniform channel doping profile (6) is at most 2×10 １７ cm －３ or at most 1×10 １７ cm －３ is is at least one of The power semiconductor device (1) according to claim 13.

15. the non-uniform channel doping profile (6) is configured in a stepped manner such that at least one step (53) exists in the non-uniform channel doping profile (6) along the gate insulator (4), The power semiconductor device (1) according to claim 5 or 6.

16. the gate electrode (31) is at least partially disposed in a trench formed through the well region (22) in the semiconductor body (2), The power semiconductor device (1) according to claim 5 or 6.

17. the gate electrode (31) and the gate insulator (4) are disposed on the flat upper surface (20) of the semiconductor body (2), The power semiconductor device (1) according to claim 5 or 6.

18. the well region (22) is in a multi-layer form such that the well region (22) includes at least two sub-layers (51, 52) having different maximum doping concentrations, The power semiconductor device (1) according to claim 5 or 6.

19. along the depth of the well region (22) outside the channel region (220), the well region (22) has a constant doping concentration at least in some places, The power semiconductor device (1) according to claim 5 or 6.

20. The gate insulator (4) has a non-uniform thickness along the channel region (220), and as a result, along the channel region (220), the gate insulator (4) is thickest in the first section (61). The power semiconductor device (1) according to claim 5 or 6.

21. The following - the channel region (220) has a non-uniform channel doping profile along the gate insulator (4), such that the doping concentration N A is maximum in the first section (61), or - The gate insulator (4) has a non-uniform gate dielectric constant profile along the channel region (220), and as a result, the relative dielectric constant of the gate insulator (4) is lowest in the first section (61) of the channel region (220) away from the source region (21). At least one of which is true. The power semiconductor device (1) according to claim 5 or 6.

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