Power semiconductor device and manufacturing method

Abstract

In at least one embodiment, the power semiconductor device (1) comprises: - a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, the well region (22) including a channel region (220) starting directly from the source region (21); a gate insulator (4) directly between the semiconductor body (2) and the gate electrode (31), The gate insulator (4) has a relative dielectric constant (ε ox The gate dielectric constant profile is non-uniform along the channel region (220) such that the dielectric constant (D) is lowest in a first section (61) of the channel region (220) away from the source region (21).

Description

[Technical field]

[0001] statement A power semiconductor device is provided, as well as a manufacturing method for such a power semiconductor device. [Background technology]

[0002] The document US Pat. No. 6,225,669 B1 refers to a non-uniform gate / dielectric field effect transistor.

[0003] The document US Pat. No. 6,503,786 B2 refers to a power MOS device having an asymmetric channel structure for improving the linear operating capability.

[0004] The document US Patent Application Publication No. 2016 / 0064550A1 refers to a power device.

[0005] Chinese Patent Application Publication No. 109087951, US Patent Application Publication No. 2015 / 0214362A1, US Patent Application Publication No. 2016 / 0104794A1, and J. Robertson, "High dielectric constant oxides" in THE EUROPEAN PHYSICAL JOURNAL APPLIED PHYSICS, Vol. 28, No. 3, Dec. 1, 2004, pp. 265-291, refer to electronic devices. Summary of the Invention [Means for solving the problem]

[0006] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to power semiconductor devices that exhibit improved electrical behavior. This object is achieved, inter alia, by a power semiconductor device and a manufacturing method for such a power semiconductor device as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0007] In at least one embodiment, the power semiconductor device comprises: a semiconductor body having a source region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type, the well region including a channel region starting directly from the source region; - a gate insulator directly between the semiconductor body and the gate electrode; Equipped with The gate insulator has a non-uniform gate dielectric constant profile along the channel region such that the dielectric constant of the gate insulator is lowest in a first section of the channel region away from the source region.

[0008] For example, the gate insulator is made of at least two different materials having different dielectric constants, with the material with the smaller dielectric constant being located in the first section or being predominantly located in the first section.

[0009] Therefore, a threshold voltage V th can be made to be the highest.

[0010] The gate electrode is insulated from the semiconductor body by a gate insulator. For example, the at least one source region is in direct contact with the assigned gate insulator and / or directly in the assigned channel region. The first conductivity type is, for example, an n-conductivity type, and thus the at least one source region is n-doped.

[0011] The at least one well region, and therefore the at least one channel region, is of a second conductivity type different from the first conductivity type. The second conductivity type is, for example, a p-conductivity type, and therefore the at least one channel region is p-doped. The maximum doping concentration of the at least one well region and / or the at least one channel region can be lower than the maximum doping concentration of the at least one source region.

[0012] According to at least one embodiment, the semiconductor body further comprises a drift region, which may be of the first conductivity type. For example, the drift region is in direct contact with the gate insulator and / or is directly in the channel region. The drift region may be located, for example, between the channel region and the drain or collector region of the semiconductor body in a direction perpendicular to the top surface of the semiconductor body. For example, the optional trench may terminate in the drift region.

[0013] Optionally, the semiconductor body may comprise an enhancement layer. For example, the enhancement layer may be located directly between the well region and the drift region and have a higher maximum doping concentration than the drift region. The enhancement layer may also be of the first conductivity type. The enhancement layer may function as a hole blocking layer, i.e., E off Improved V ce-sat In addition, the reinforcing layer also helps to control the length of the channel region and minimizes the variations due to the manufacturing process. For example, the thickness of the reinforcing layer is at least 1 μm and / or at most 5 μm.

[0014] According to at least one embodiment, the power semiconductor device is a Metal-Insulator-Semiconductor Field Effect Transistor, MISFET, Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET, or an Insulated Gate Bipolar Transistor, IGBT or Reverse Conducting Insulated Gate Bipolar Transistor, RC-IGBT.

[0015] According to at least one embodiment, the well region extends from a top surface of the semiconductor body to the drift region. The channel region is part of the well region and may have the same doping concentration. In operation, electrons flow in the channel region from the source region along the gate insulator to the drift region. The channel region has a thickness in the nanometer range, illustratively between 1 nm and 50 nm, in a direction perpendicular to the interface between the gate insulator and the well region.

[0016] For example, the semiconductor body is made of silicon, or Si for short. However, the semiconductor body may alternatively be made of a wide bandgap semiconductor material, such as SiC, Ga2O3, or GaN.

[0017] For example, the difference in dielectric constant along the channel region is at least 2.0, or at least 3.0, or at least 3.5. Alternatively or additionally, said difference is at most 50, or at most 25. When comparing the respective dielectric constants, textbook values ​​of the respective materials at room temperature, i.e., 300K, and at a frequency of the fluctuating electric field of at most 1 kHz may be used. Here and below, the term "along the channel region" may refer to the direction of current flow in the channel region in the intended use of the power semiconductor device.

[0018] The gate insulator is made of any combination of insulating materials, which may be oxides. For example, the gate insulator may include at least one or at least two of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2. Therefore, the gate insulator may also be referred to as a gate oxide.

[0019] For example, the gate insulator includes a high-k material, which is a material that has a dielectric constant greater than that of silicon oxide, which is about 3.9. The gate insulator may also include a low-k material, which has a dielectric constant less than that of silicon oxide, i.e., less than 3.9. For example, the gate insulator includes a high-k material as well as a low-k material.

[0020] According to at least one embodiment, the power semiconductor device is a power device, for example configured for a maximum voltage of at least 0.2 kV, or at least 0.6 kV, or at least 1.2 kV.

[0021] The power semiconductor device is intended for a power module in a vehicle, for example in a hybrid or plug-in electric vehicle, that converts direct current from a battery or fuel cell into alternating current for an electric motor. Additionally, the power semiconductor device may be a fuse in a vehicle, such as an automobile.

[0022] For simplicity, in the following only one channel region and assigned components are referred to. If multiple channel regions and assigned components are present, the features described below may apply to only one, multiple, or all of the channel regions and assigned components.

[0023] According to at least one embodiment, the gate insulator includes a first material in a first section and a second material in a second section adjacent the source region, the first material having a lower dielectric constant than the second material.

[0024] The gate insulator can be comprised of a first section and a second section. Alternatively, there can be at least one additional section, such as an intermediate section located between the first section and the second section along the channel region. If there is at least one additional section, there can be at least one additional material having a dielectric constant different from the dielectric constants of the first material and the second material.

[0025] According to at least one embodiment, the length of the first section is at least 5%, or at least 10%, or at least 15% of the total length of the channel region along the gate insulator. Alternatively or additionally, said length is at most 40%, or at most 30%, or at most 25% of said total length. The same may apply to at least one additional section, if present.

[0026] According to at least one embodiment, the gate insulator has a uniform thickness profile along the channel region, in other words, the thickness of the gate insulator is constant across the entire channel region.

[0027] According to at least one embodiment, the gate insulator has a non-uniform gate insulator thickness profile along the channel region. In other words, the thickness of the gate insulator varies along the channel region. The thickness variation can be continuous or non-continuous, i.e., stepped. For example, along the channel region, the gate insulator can be thickest in a first section and, consequently, thinnest in a second section.

[0028] According to at least one embodiment, the channel region has a non-uniform channel doping profile along the gate insulator. For example, a doping concentration N A can be largest in the first section and, consequently, smallest in the second section. For example, the doping concentration N A is maximum at a depth from the top surface of the semiconductor body of at least 0.5 μm or at least 1.5 μm. A may also be at a distance of at least 0.5 μm or at least 1.5 μm from the source region along the gate insulator. The maximum may be located within a well region. Thus, the maximum is achieved by epitaxial growth rather than ion implantation.

[0029] According to at least one embodiment, the gate electrode has a non-uniform gate electrode work function profile along the channel region such that a threshold voltage of the gate electrode is highest in the first section. Thus, the work function Φ of the gate electrode in the first section away from the source region is m is largest for devices with p-type doped well regions and therefore p-type doped channel regions, and is smallest for devices with n-type doped well regions and therefore n-type doped channel regions.

[0030] According to at least one embodiment, the work function difference of the gate electrode along the channel region is at least 0.7 eV, or at least 1.0 eV, or at least 1.1 eV. This is the case, for example, when the gate electrode is based on polysilicon. If metals such as Li, Zn, Hf for low work functions or metals such as Pt, Pd, or Au for high work functions are also considered, the work function difference can be at least 1.3 eV or at least 1.4 eV. For example, the work function difference is at most 2.0 eV or at most 1.5 eV.

[0031] For example, the gate electrode may include a first gate material in a first section and a second gate material in a second section, the first gate material having a higher work function Φ 1 in the case of device 1 having a p-doped well region 22 than the second gate material. m and vice versa for device 1 having n-doped well region 22.

[0032] According to at least one embodiment, the thickness of the gate insulator varies significantly along the channel region, meaning, for example, that the minimum thickness of the gate insulator is at most 70%, or at most 50% of the maximum thickness of the gate insulator, in this respect only the gate insulator along the channel region may be relevant.

[0033] According to at least one embodiment, the minimum doping concentration of the channel region along the gate insulator is at most 50%, or at most 20%, or at most 10% of the maximum doping concentration of the channel region.

[0034] According to at least one embodiment, there is a non-uniform gate dielectric constant profile, and at least one of a non-uniform gate insulator thickness profile, a non-uniform channel doping profile, and a non-uniform gate electrode work function profile. Thus, the relative dielectric constant of the gate insulator and the gate electrode work function Φ m, the thickness of the gate insulator, and the doping concentration in the channel region N A may vary along the channel region.

[0035] According to at least one embodiment, at least one of the non-uniform gate dielectric constant profile, the non-uniform gate insulator thickness profile, the non-uniform channel doping profile, and the non-uniform gate electrode work function profile extends continuously and step-free, and thus, each of the at least one profiles may be represented by a differentiable function.

[0036] According to at least one embodiment, at least one of the non-uniform gate dielectric constant profile, the non-uniform gate insulator thickness profile, the non-uniform channel doping profile, and the non-uniform gate electrode work function profile extends in a step-like manner, and thus at least one respective profile includes one or more steps and may not be represented by a differentiable function.

[0037] Any combination of stepwise and continuous profiles can be used, for example a stepwise non-uniform gate dielectric constant profile can be combined with at least one of a stepwise non-uniform gate insulator thickness profile, a continuous non-uniform channel doping profile, and a stepwise non-uniform gate electrode work function profile.

[0038] According to at least one embodiment, the non-uniform gate dielectric constant profile and at least one of the non-uniform gate electrode work function profile, the non-uniform gate insulator thickness profile, and the non-uniform channel doping profile extend in the same direction, e.g., at least one step in the non-uniform gate dielectric constant profile and at least one step in the non-uniform gate electrode work function profile, the non-uniform gate insulator thickness profile, and the non-uniform channel doping profile are at the same position along the channel region.

[0039] According to at least one embodiment, the gate electrode is partially or completely disposed in at least one trench formed in the semiconductor body. The at least one trench, and thus the assigned gate electrode, extends, for example, in a direction away from the top surface of the semiconductor body through the well region into the drift region. As a result, the gate insulator is also partially or completely located in the assigned trench. The power semiconductor device may therefore be a trench-based device.

[0040] Otherwise, the gate electrode and gate insulator are applied to the top surface of the semiconductor body, which may therefore be planar.

[0041] According to at least one embodiment, the power semiconductor device has a collector-emitter saturation voltage V ce-sat , thus configuring both saturation current and short circuit current to be reduced while on-state losses may remain unaffected. This may be true for a non-uniform gate dielectric constant profile, optionally supported by at least one of a non-uniform gate electrode workfunction profile, a non-uniform gate insulator thickness profile, and a non-uniform channel doping profile, and compared to a reference semiconductor device having a similarly set but uniform gate dielectric constant profile, as well as optionally at least one of a uniform gate electrode workfunction profile along the gate insulator, a uniform gate insulator thickness profile, and a uniform channel doping profile.

[0042] There is further provided a method for manufacturing a power semiconductor device, by which a power semiconductor device is manufactured as shown in relation to at least one of the above-described embodiments, and therefore features of the power semiconductor device are also disclosed for the method and vice versa.

[0043] In at least one embodiment, a method for manufacturing a power semiconductor device includes the following steps, specifically in the order listed: providing a semiconductor substrate; - epitaxially growing at least one semiconductor layer on a semiconductor substrate;

[0044] For example, the semiconductor substrate comprises at least a portion of the drift region. For example, at least one epitaxially grown semiconductor layer comprises a well region and a source region.

[0045] The power semiconductor device and the manufacturing method are described in more detail below by way of exemplary embodiments with reference to the drawings. The same elements in the individual figures are indicated by the same reference numerals. However, the relationship between the elements is not shown to scale, rather the individual elements may be shown exaggerated in size to facilitate understanding. [Brief description of the drawings]

[0046] [Figure 1] 2 is a schematic cross-sectional view of a reference semiconductor device; [Diagram 2] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Diagram 3] FIG. 3 is a top view of the power semiconductor device of FIG. 2. [Figure 4] FIG. 4 is a schematic diagram of a non-uniform gate dielectric constant profile of the power semiconductor device of FIGS. 2 and 3. [Diagram 5] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 6] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 7] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 8]FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 9] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 10] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 11] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 12] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 13] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] 1 shows a reference semiconductor device 9 which corresponds to the exemplary embodiment of the power semiconductor device 1 described herein, except for the gate dielectric constant profile of the gate insulator 4 in a channel region 220 contained in a well region 22. Like the power semiconductor device 1, the reference semiconductor device 9 comprises a semiconductor body 2, e.g. made of Si.

[0048] The semiconductor body 2 also comprises a source region 21 at a top surface 20 of the semiconductor body 2. A trench penetrates both the well region 22 and the source region 21. The source region 21 is of a first conductivity type, such as n-conductivity, and the well region 22, and therefore the channel region 220 contained by the well region 22, is of a second, different conductivity type, such as p-conductivity. Within the trench is a gate electrode 31 separated from the semiconductor body 2 by an electrically insulating gate insulator 4. The trench, and therefore the gate electrode 31, terminates in a drift region 23 of the semiconductor body 2. The drift region 23 is also of the first conductivity type.

[0049] In the reference semiconductor device 9, the gate insulator 4 consists of only one material, so that in the region of the gate insulator 4 facing the well region 22, a constant relative dielectric constant ε ox That is, there is a uniform gate dielectric constant profile along the length direction x of the channel region 220 away from the source region 21 towards the drift region 23.

[0050] For example, x=0 where the source region 21 and the channel region 220 directly contact adjacent to the gate insulator 4. For example, x=L where the channel region 220 and the drift region 23 directly contact adjacent to the gate insulator 4, where L corresponds to the channel length of the channel region 220. It should be noted that the shape of the channel region 220 is only very roughly drawn.

[0051] For example, x extends perpendicular to the top surface 20 of the semiconductor layer body 2. The length L may therefore correspond to the distance between the source region 21 and the drift region 23 directly at the gate insulator 4. The length L may therefore be defined as the length of the layer of the first conductivity type, i.e. the layer of the second conductivity type, between the source region 21 and the drift region 23. Optionally, the drift region 23 may comprise a layer of lower doping concentration towards the back side of the device, not shown. x may be considered as the direction of current flow in the intended use of the reference semiconductor device 9.

[0052] 2 and 3, the gate insulator 4 comprises a first material 81 and a second material 82. Along a length direction x, the first material 81 directly follows the second material 82. As a result, the gate insulator 4 has a non-uniform gate dielectric constant profile along the channel region 220.

[0053] The dielectric constant of the first material 81 is smaller than the dielectric constant of the second material 82. Thus, in the first section 61, away from the source region 21, there is a minimum in the non-uniform gate dielectric constant profile. The remainder of the channel region 220 is referred to as the second section 62. The dielectric constant does not change in the first section 61 and in the second section 62, respectively.

[0054] Thus, along the channel region 220, the gate insulator 4 may be composed of a second section 62 and a first section 61 having a second material 82 and a first material 81, respectively. In a direction perpendicular to the length direction x, the gate insulator 4 may include only one material, i.e., either the first material 81 or the second material 82.

[0055] The gate insulator 4 may be of constant thickness throughout the channel region 220. For example, an inner side 43 of the gate insulator 4 facing the gate electrode 31 and / or an outer side 42 of the gate insulator 4 facing the semiconductor body 2 may be planar throughout the channel region 22. For example, when viewed in cross section, the inner side 43 and / or the outer side 42 may appear as straight lines. Thus, along the channel region 220, the inner side 43 and / or the outer side 42 may not include any steps.

[0056] For example, the first material 81 has a relative dielectric constant ε of 2.6. ox2 and the second material 82 is a low-k material having a relative dielectric constant ε ox1 4. The thickness of the gate insulator 4 is, for example, 100 nm over the entire channel region 220. For example, the low-k material can be silica-based, silsesquioxane (SSQ)-based, or polymer-based, and the high-k material can be an oxide such as HfO2 or ZrO2. The low dielectric constant in the first section 61 allows the threshold voltage V th-1 is the threshold voltage V in the second section 62 th-2 The threshold voltage V along the channel region 220 is thThe effect on is described in more detail below in conjunction with FIGS.

[0057] Optionally, there may be at least one plug 25 in the top surface 20 of the semiconductor body 2 to electrically contact the channel region 220. The plug 25 may have a different thickness than the well region 22 such that the plug 25 may extend deeper or shallower into the semiconductor body 2 than the well region 22. Furthermore, the thicknesses of the source region 21 and the plug 25 may be the same or different.

[0058] Furthermore, between the drift region 23 and the well region 22 there is a reinforcement layer 27. The reinforcement layer 27 is also of the first conductivity type.

[0059] Both the source region 21 and the at least one plug 25 or well region 22 may be electrically connected, for example, by at least one source electrode 32 located on the top surface 20. Illustratively, the plug 25 has a higher maximum doping concentration than the well region 22 or the channel region 220. The depth of the plug may be lower, deeper or the same as the depth of the well region 22 and the channel region 220.

[0060] For example, the power semiconductor device 1 is an insulated gate bipolar transistor, IGBT for short. Thus, on the side of the drift region 23 remote from the well region 22, there is also a collector region 26 of the second conductivity type. In the collector region 26, a collector electrode 34 is present. Furthermore, there may be a buffer region of the first conductivity type between the drift region 23 and the collector region 26. The doping concentration of such a buffer region may be higher than the doping concentration of the drift region 23.

[0061] For example, the semiconductor body 2 is at least partially produced by epitaxial growth, i.e. the doping concentration of the respective layers of the semiconductor body 2 may be generated during growth and not after growth, for example by ion implantation. This applies, for example, at least to the enhancement layer 27 and to the well region 22, which may thus be doped by epitaxial growth. Optionally, the drift region 23 may be partly or completely part of the growth substrate. The same applies to all other examples.

[0062] When viewed in top view on the top surface 20, the trench housing the gate electrode 31 and the gate insulator 4 may be elongated. The source region 21, the at least one plug 25, and the channel region 220 may be symmetrically disposed on either side of the trench, see FIG.

[0063] For example, the maximum doping concentration of the source region 21, the collector region 26 (or instead of the drain region 24 if the device is a MISFET or MOSFET), and the at least one plug 25 is at least 1×10 18 cm -3 Or at least 5×10 18 cm -3 Or at least 1×10 19 cm -3 and / or at most 5 × 10 20 cm -3 Or at most 2×10 20 cm -3 Or at most 1×10 20 cm -3 Furthermore, the maximum doping concentration of the well region 22, and therefore the channel region 220, is at least 5×10 16 cm -3 Or at least 1×10 17 cm -3 and / or at most 5 × 10 19 cm -3 Or at most 5 x 10 18 cm -3For example, the maximum doping concentration of the enhancement layer 27 can be at least 10 15 cm -3 and / or at most 10 18 cm -3 It is.

[0064] Depending on the voltage class of the power semiconductor device 1, the maximum doping concentration of the drift region 23 is at least 1×10 11 cm -3 Or at least 1×10 12 cm -3 Or at least 1×10 13 cm -3 and / or at most 1 × 10 17 cm -3 Or at most 5 x 10 16 cm -3 Or at most 1×10 16 cm -3 It could be.

[0065] For example, the thickness of the gate insulator 4 is 50 nm to 250 nm, or 80 nm to 150 nm. 2 and 3, the source region 21 and the at least one plug 25 are arranged along only one side of the gate electrode 31, so that the channel region 220 is present only along one outer side 42 of the gate insulator 4. However, the source region 21 as well as the at least one plug 25 can also be arranged along two sides of the gate electrode 31, or all around the gate electrode 31 when viewed from a top view, as compared to, for example, FIG.

[0066] If not, the same may be true for Figures 2-4 as for Figure 1. The concept behind the gate insulator 4 having a non-uniform gate dielectric constant profile is explained in some detail below.

[0067] For power semiconductor device 1, illustratively for low frequency applications, it may be desirable to have as low an on-state loss as possible in order to minimize total electrical losses. Furthermore, from a device reliability standpoint, it may be advantageous to have a low short circuit current. Thus, a power semiconductor device 1 with minimized on-state losses and improved short circuit capability may be desired.

[0068] However, for example, decreasing the channel length L or increasing the channel width W can reduce the on-state voltage drop V ce-sat Several means of reducing the output characteristic I c Against V ce As shown diagrammatically using the undesirable higher saturation current I sat See Figure 5. High I sat is a high short circuit current I sc This directly relates to the short circuit capability of the power semiconductor device 1 and adversely affects the short circuit capability of the power semiconductor device 1. On the other hand, the I sat In order to reduce the threshold voltage V th As shown in Figure 6, increasing V ce-sat 5 and 6 are schematic diagrams of typical output characteristics of an IGBT having a uniform threshold voltage profile along the entire channel region 220, and in FIG. th and different channel resistances. In Fig. 6, different threshold voltages V th This is the case.

[0069] a) increasing the channel length L; b) Reducing the anode injection efficiency by reducing the anode implant dose; c) reducing the channel width by reducing the source coverage along the trench; and d) Reducing the channel width by increasing the cell pitch Other techniques for reducing the short circuit current, such as d), also undesirably result in higher on-state losses. Moreover, techniques such as d) may also adversely affect the breakdown capability of the power semiconductor device 1. Reducing the gate bias to reduce the short circuit current may also lead to unstable dynamic behavior and may be undesirable, as it is primarily dictated by the application requirements.

[0070] Thus, in conventional MISFET or IGBT devices, there is a trade-off between minimizing on-state losses and reducing short-circuit current. For applications requiring improved short-circuit capability, V ce-sat Without affecting the short circuit current I sc It may be desirable to be able to reduce

[0071] In the power semiconductor device 1 described herein, the tradeoff between on-state losses and short circuit current is improved by improving the latter without adversely affecting the former. Unlike other approaches, the described design provides a ce-sat The semiconductor laser features a non-uniform threshold voltage profile along the channel region 220 adjacent the gate insulator 4 to reduce the saturation current for the gate insulator 4 .

[0072] The non-uniform V th is achieved by implementing a non-uniform gate dielectric constant profile of the gate insulator 4 along the channel region 220. In addition, the described concept is applicable to generally any MOS device such as power MOSFETs or IGBTs or reverse conducting IGBTs and is even compatible with both planar and trench architectures.

[0073] The power semiconductor device 1 described herein introduces improved MISFET, MOSFET, IGBT, or RC-IGBT devices with improved short circuit capability without detrimentally affecting on-state losses. The improved design also relaxes the design constraints of the IGBT or RC-IGBT, allowing the possibility to independently explore other methods mentioned above to minimize on-state losses that are typically limited by the short circuit capability of the respective device.

[0074] In the following, some theoretical background to the conception of the semiconductor device 1 described herein is presented.

[0075] For standard long channel MOS devices, high V ce It is known that the channel pinch-off at V causes current saturation in the output characteristic, which ultimately determines the short circuit current. pinch-off is the threshold voltage V th Exemplarily, the applied bias V ce is the pinch-off voltage V pinch-off ≒(V g -V th ), the channel begins to pinch off near its drain end at x=L, where V g is the applied gate voltage and L is the channel length. ce The voltage drop perpendicular to the channel is V th It is smaller and therefore the channel can no longer persist near the drain end.

[0076] However, for a more detailed understanding of the device, channel pinch-off should be considered as a rather local phenomenon, occurring specifically near the drain end of the channel. More precisely, it is the local threshold voltage V that determines the pinch-off point, and hence the saturation current. th (x). This is because in the first section 61 near the channel end, i.e., the drift region 23, V thBy locally increasing (L), V pinch-off This means that it is possible to reduce

[0077] Additionally, it preserves the overall channel resistance, thereby reducing V ce-sat To avoid affecting V th (x) can be reduced.

[0078] This is because the curve referring to the reference semiconductor device 9 has a uniform threshold voltage V th-1 7 including the channel profile. On the other hand, the curve for the power semiconductor device 1 shows a non-uniform V th It consists of a profile, V th is V to lower the pinch-off point. th-2 (L)>V th-1 and in the remainder of the channel, V is increased to keep the overall channel resistance the same. th-2 ' <V th-1 In this way, the saturation current, and therefore the short circuit current, can be significantly reduced without affecting the on-state losses, as shown in the schematic output of Figure 8. th Variation holds the key to improving the short circuit capability of MISFET or MOSFET or IGBT devices.

[0079] Channel V th is a function of various other MOS cell design parameters as shown in the following equation:

[0080]

number

[0081] Here, V th is the threshold voltage, V fb is the flat band voltage, V fb =(Φ m -Φ s), where Φ m and Φ s are the gate electrode work function and the semiconductor work function, respectively. N A is the doping of the channel body, and ε s is the dielectric constant of the semiconductor, and C ox is the gate insulator capacitance, and φ B is the semiconductor surface potential,

[0082]

number

[0083] where k is the Boltzmann constant, T is the temperature, and n i is the intrinsic carrier concentration of the semiconductor.

[0084] Therefore, the relatively high V th The non-uniform V required across the channel th The profile can be achieved by introducing non-uniformity in one or any combination of the following MOS design parameters:

[0085] 1. Channel doping profile, N A (x), 2. Gate oxide thickness, Tox(x), 3. Gate dielectric constant, ε, as detailed herein ox (y), and / or 4.V fb =(Φ m -Φ s ), so the gate metal work function φ m (x).

[0086] In the following, we focus on changing the gate dielectric constant profile, however, said change in dielectric constant can of course be combined with a varying gate insulator thickness, a varying gate electrode work function, and / or a varying channel doping concentration.

[0087] Lower ε near the channel ends ox It should be noted that two or more combinations of dielectric constants or even gradients of dielectric constants can achieve the same purpose, such as having a higher ε ox area and lower ε ox Even the physical length of the regions can be adjusted to suit purposes and overcome manufacturing challenges.

[0088] Therefore, by employing different gate dielectric materials 81, 82 along the channel region 220, the V th It is possible to introduce non-uniformity in the profile. This is because both th ×C ox is related to ε ox / t ox Instead, the gate oxide thickness t ox , see above. Thus, the relative permittivity ε ox The gate oxide thickness t ox The same effect as observed can be obtained by increasing or decreasing . For example, for a uniform gate oxide thickness of 100 nm, t ox In the case of a constant relative dielectric constant ε ox Assuming that the change in thickness from 60 nm in the second section 62 to 150 nm in the first section 61 corresponds to a change in ε ox is increased to 6.5, and ε ox This effectively replicates the case when is set to 2.6.

[0089] According to Fig. 9, on both sides of the gate electrode 31, there are source regions 21 and at least one plug 25, so that the channel region 220 is also along the two outer sides 42. Furthermore, as an option, the gate insulator 4 is shown in Fig. 9 to be composed of a first material 81, a second material 82 and a third material 83 located in the intermediate section 63 between the first section 61 and the second section 62 when viewed along the channel region 220. The dielectric constant of the third material 83 is between the dielectric constants of the first material 81 and the second material 82.

[0090] In FIG. 9, there are three materials 81, 82, 83 in the gate insulator 4, however, the gate insulator 4 may comprise more than two different materials.

[0091] Moreover, the power semiconductor device 1 in Fig. 9 is shown to be a MISFET or MOSFET, rather than an IGBT. As a result, the power semiconductor device 1 comprises a drain region 24 instead of a collector region 26. Thus, on the side of the drift region 23 remote from the well region 22, there is also a drain region 24 which is of the first conductivity type but has, for example, a higher maximum doping concentration than the drift region 23. In the drain region 24, a drain electrode 33 is present.

[0092] Of course, all gate insulator designs for IGBT power semiconductor devices 1 can be applied to MOSFET and MISFET power semiconductor devices 1, and vice versa.

[0093] If this is not the case, the same may be true for FIG. 9 as for FIG. 2-FIG. 8, and vice versa.

[0094] FIG. 10 shows that the trench in which the gate insulator 4 and gate electrode 31 are housed need not have rounded ends in the drift region 23, but may also be rectangular or trapezoidal in shape when viewed in cross section.

[0095] Moreover, in FIG. 10, it is shown that there exists not only a non-uniform gate dielectric constant profile due to at least two different materials 81, 82, but also a non-uniform gate insulator thickness profile. That is, the thickness of the gate insulator 4 varies along the channel region 220. For example, the thickness of the first material 81 in the first section 61 exceeds the thickness of the second material 82 in the second section 62, and vice versa. For example, the thickness difference between the first material 81 and the second material 82 is at least 20% or at least 40% of the maximum thickness of the gate insulator 4 along the channel region 220. When only a non-uniform gate insulator thickness profile and a uniform gate dielectric constant profile exist, the gate insulator 4 may be made of a single material.

[0096] For example, the thickness of the gate insulator 4 in the second section 62 is 50 nm to 100 nm, and / or the thickness of the gate insulator 4 in the first section 61 is 100 nm to 240 nm. However, other than as shown in FIG. 10 , the thickness of the gate insulator 4 in the first section 61 may alternatively be smaller than in the second section 62, and the maximum thickness may be in the second section 62 instead.

[0097] In addition to or instead of a non-uniform gate insulator thickness profile, there may be a non-uniform gate electrode work function profile 72 of the gate electrode 31. Thus, the gate electrode 31 may include a first gate material 84 adjacent to the source region 21 and a second gate material 85 adjacent to the drain region 23. The gate materials 84, 85 may vary where the materials 81, 82 of the gate insulator 4 vary. Thus, the work function Φ of the gate electrode 31 in the first section 61 away from the source region 21 m is maximum for device 1 with p-doped well region 22 and is minimum for device 1 with n-doped well region 22.

[0098] For example, the second gate material 85 has a work function Φ of about 5.22 eV. mp + For example, the first gate material 84 is doped polysilicon having a work function Φ of about 4.1 eV. m n + Although based on silicon, these first gate material 84 and second gate material 85 are sometimes referred to as different gate electrode metals.

[0099] Thus, there is a step in the non-uniform gate electrode work function profile 72 at the interface between the first section 61 and the second section 62, see the inset of FIG.

[0100] In addition to or instead of a non-uniform gate insulator thickness profile and / or a non-uniform gate electrode work function profile 72, there may be a non-uniform channel doping profile 71. That is, the doping concentration N A varies along the channel region 220.

[0101] For example, the maximum doping concentration present in the non-uniform channel doping profile 71 is at least 5×10 16 cm -3 and at most 5 × 10 19 cm -3 and / or the minimum doping concentration present in the non-uniform channel doping profile 71 is at most 2×10 17 cm -3 Or at most 1×10 17 cm -3 The maximum doping concentration may be present in the first section 61 and the minimum doping concentration may be present in the second section 62. The doping concentration N A For example, the doping concentration N A However, the doping concentration N AThe steps in do not have to follow exactly a theta function or a unit step function, but there can be sinusoidal steps, see the inset in Figure 10. The steps can be at the locations where the material 81, 82 of the gate insulator 4 changes.

[0102] At least one such non-uniform gate electrode work function profile 72, non-uniform gate insulator thickness profile, and non-uniform channel doping profile 71 may also be present in all other exemplary embodiments similarly.

[0103] If this is not the case, the same may be true for FIG. 10 as for FIG. 2-FIG. 9, and vice versa.

[0104] According to Fig. 11, the power semiconductor device 1 is a planar design, not a trench design like, for example, the power semiconductor device 1 of Fig. 2 and Fig. 3. Thus, the top surface 20 is planar, and the gate insulator 4 and the gate electrode 31 are applied to the top surface 20. As a result, the length direction x runs parallel to the top surface 20 from the source region 21 to the drift region 23, unlike other exemplary embodiments that are perpendicular to the top surface 20. The power semiconductor device 1 of Fig. 11 can be any MISFET device or any IGBT device.

[0105] 11 , the well region 22 protrudes laterally, i.e., parallel to the top surface 20, from the source region 21 and extends below the gate insulator 4. The source region 21 may also extend below the gate insulator 4, but to a lesser extent. The change from the second material 82 to the first material 81 occurs at the top surface 20 of the well region 22. As a result, the channel region 220 extends along the top surface 20.

[0106] If this is not the case, the same may be true for FIG. 11 as for FIG. 2-FIG. 10, and vice versa.

[0107] According to FIG. 12, as in FIG. 2, the non-uniform gate dielectric profile also has a step, but the first material 81 and the second material 82 do not have a planar interface perpendicular to the length direction x. Instead, the interface may have a ramp-like shape due to the manufacturing process. Thus, a transition section 64 is formed. In the transition section 64, the materials 81, 82 can be stacked one above the other, so that, for example, there is an unintended slight thickness variation of the gate insulator 4. For example, such a thickness variation is at most 50% or at most 10% of the maximum thickness of the gate insulator 4 along the channel region 220.

[0108] Compared to the total channel length L, the length of the transition section 64 along the length direction x is small, e.g. at most 2% or at most 5% of the total channel length L. The same may apply to all other exemplary embodiments. Such a transition section 62 or multiple such transition sections may also be present at an interface between different materials 81, 82, 83 of the gate insulator 4 in all other exemplary embodiments. Such at least one transition section 64, if present, may also be present in a non-uniform gate electrode work function profile 72, a non-uniform gate insulator thickness profile, and / or a non-uniform channel doping profile 71.

[0109] If this is not the case, the same may be true for FIG. 12 with respect to FIGS. 2-11, and vice versa.

[0110] 13, the second material 82 is shown applied to the first material 81. The overall thickness of the gate insulator 4 may remain constant throughout the channel region 220. Thus, the thicknesses of the materials 81, 82 may vary linearly along the channel region 220, such that the effective dielectric constant of the gate insulator 4 may vary continuously, e.g., linearly, along the channel region 220.

[0111] If this is not the case, the same may be true for FIG. 13 with respect to FIGS. 2-12, and vice versa.

[0112] Components depicted in the figures exemplarily follow one another directly in the specified order, unless otherwise indicated. Components that are not in contact in the figures are exemplarily spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of depicted components relative to one another are accurately reproduced in the drawings.

[0113] The power semiconductor device described herein is not limited by the description based on the exemplary embodiments, but rather includes any novel feature and any combination of features, including any combination of features in the claims, even if this feature or this combination itself is not explicitly specified in the claims or exemplary embodiments.

[0114] This patent application claims priority to European Patent Application No. 21186132.3, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0115] Reference sign 1. Power Semiconductor Devices 2. Semiconductor body 20 Top side 21 Source Area 22 Channel Area 23 Drift Region 24 Drain Region 25 Plug 26 Collector Region 27 Reinforcement layer 31 Gate electrode 32 Source electrode 33 Drain electrode 34 Collector electrode 4 Gate insulator 42 Outside of the gate insulator 43 Inside the gate insulator 61 First Section 62 Second Section 63 Mid Section 64 Transition Section 71 Non-uniform channel doping profile 72 Non-uniform gate electrode work function profile 81 First Ingredient 82 Second Ingredient 83 The third ingredient 84 First Gate Material 85 Second Gate Material ε ox Dielectric constant L is the length of the channel region along the gate insulator V th Threshold Voltage x lengthwise along the channel region

Claims

1. - A semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, wherein the well region (22) includes a channel region (220) starting directly from the source region (21), the semiconductor body (2); - A gate insulator (4) directly between the semiconductor body (2) and a gate electrode (31); A power semiconductor device (1) comprising: The gate insulator (4) has a gate dielectric constant profile that is non-uniform along the channel region (220) such that the relative dielectric constant (ε ox ) is lowest in a first section (61) of the channel region (220) remote from the source region (21). One of the following: - The channel region (220) has a non-uniform channel doping profile (71) along the gate insulator (4), or - The threshold voltage (V th ) of the gate electrode (31) is the highest in the first section (61), and the gate electrode (31) has a non-uniform gate electrode work function profile (72) along the channel region (220), or - The gate insulator (4) has a non-uniform thickness along the channel region (220), such that along the channel region (220), the gate insulator (4) is thickest in the first section (61) away from the source region (21); At least one of which applies, A power semiconductor device (1).

2. The difference in the relative permittivity (ε ox ) along the channel region (220) is at least 2.0, The semiconductor body (2) further comprises a strengthening layer (27) of the first conductivity type directly on the side of the well region (22) away from the source region (21), The power semiconductor device (1) according to claim 1.

3. One of the following: - The length of the first section (61) is at least 10% and at most 40% of the total length (L) of the channel region (220) along the gate insulator (4), - The thickness of the gate insulator (4) is constant throughout the channel region (220); At least one of which applies, the power semiconductor device (1) according to claim 1 or 2.

4. The thickness of the gate insulator (4) varies along the channel region (220), The power semiconductor device (1) according to claim 1 or 2.

5. The gate insulator (4) includes a first material (81) and a second material (82), the second material (82) is applied to the first material (81), and the overall thickness of the gate insulator (4) remains constant throughout the channel region (220), The power semiconductor device (1) according to claim 1 or 2.

6. The thicknesses of the first material (81) and the second material (82) vary linearly, The power semiconductor device (1) according to claim 5.

7. The non-uniform gate dielectric constant profile of the gate insulator (4) along the channel region (220) is such that the relative dielectric constant (ε ox ) changes stepwise such that there is at least one step (43). The power semiconductor device (1) according to claim 1 or 2.

8. When looking along the channel region (220), the gate insulator (4) has a second section (62) located adjacent to the source region (21). The relative permittivity (ε ox ) has a specific first value in the first section (61) and a specific second value in the second section (62), The power semiconductor device (1) according to claim 7.

9. Perpendicular to the channel region (220), the relative permittivity (ε ox ) changes within the gate insulator (4), The power semiconductor device (1) according to claim 1 or 2.

10. The inner side (43) of the gate insulator (4) facing the gate electrode (31) is planar along the channel region (220). The power semiconductor device (1) according to claim 1 or 2.

11. The outer side (42) of the gate insulator (4) facing the semiconductor body (2) is planar along the channel region (220). The power semiconductor device (1) according to claim 1 or 2.

12. The work function difference of the gate electrode (31) along the channel region (220) is at least 1.0 eV. The power semiconductor device (1) according to claim 1 or 2.

13. Along the gate insulator (4), the minimum doping concentration of the channel region (220) is at most 50% of the maximum doping concentration of the channel region (220). The power semiconductor device (1) according to claim 1 or 2.

14. The gate electrode (31) is at least partially disposed in a trench formed through the well region (22) in the semiconductor body (2). The power semiconductor device (1) according to claim 1 or 2.

15. The gate electrode (31) and the gate insulator (4) are disposed on the flat upper surface (20) of the semiconductor body (2). The power semiconductor device (1) according to claim 1 or 2.

16. At least one of the non-uniform gate dielectric constant profile, and the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform gate electrode work function profile has at least one step, The steps in at least one of the non-uniform gate dielectric constant profile, and the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform gate electrode work function profile are located at the same position along the channel region (220). The power semiconductor device (1) according to claim 1 or 2.

17. The non-uniform gate dielectric profile, and at least one of the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform gate electrode work function profile has at least one step, the step in at least one of the non-uniform gate dielectric profile, and the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform gate electrode work function profile is located at a different position along the channel region (220), or at least two of the non-uniform gate electrode work function profile, the non-uniform thickness profile, the non-uniform channel doping profile, or the non-uniform gate dielectric profile are of different shapes, The power semiconductor device (1) according to claim 1 or 2.

18. - The source region (21) is in direct contact with the gate insulator (4) and the channel region (220), - The semiconductor body (2) further includes a drift region (23) of a first conductivity type that is in direct contact with the gate insulator (4) and is directly located in the channel region (220), - The power semiconductor device (1) is a metal-insulator-semiconductor field effect transistor, MISFET, metal-oxide-semiconductor field effect transistor, MOSFET, insulated gate bipolar transistor, IGBT, or reverse conducting insulated gate bipolar transistor, RC-IGBT. The power semiconductor device (1) according to claim 1 or 2.

19. A method for manufacturing the power semiconductor device (1) according to claim 1 or 2, comprising: - Providing a semiconductor substrate; - Epitaxially growing at least one epitaxial growth semiconductor layer on the semiconductor substrate The method includes.

20. The power semiconductor device (1) according to claim 18 is manufactured, the semiconductor substrate includes at least a part of the drift region (23), the at least one epitaxial growth semiconductor layer includes the well region (22) and the source region (21), The method according to claim 19.

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