Power semiconductor device and manufacturing method

Abstract

In one embodiment, the power semiconductor device (1) comprises: - a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, the well region (22) including a channel region (220) directly in the source region (21); a gate electrode (31) arranged in the semiconductor body (2) and assigned to the channel region (220); a gate insulator (4) directly between the semiconductor body (2) and the gate electrode (31), The gate insulator (4) has a non-uniform thickness Tox along the channel region (220) such that the gate insulator (4) is thickest along the channel region (220) in a first portion (44) away from the source region (21).

Description

[Technical field]

[0001] statement A power semiconductor device is provided, as well as a manufacturing method for such a power semiconductor device. [Background technology]

[0002] The document US Pat. No. 6,503,786 B2 refers to a power MOS device having an asymmetric channel structure for improving the linear operating capability.

[0003] Document WO 2017 / 112276 A1 discloses a non-uniform gate oxide thickness for a DRAM device.

[0004] Document US 2007 / 0063269 A1 describes a trench IGBT with increased short circuit capability.

[0005] The document US Patent Application Publication No. 2016 / 0064550A1 refers to a power device.

[0006] The documents EP 1248300 A2, US 2008 / 0166846 A1 and US 2016 / 0093719 A1 refer to electronic devices. Summary of the Invention [Means for solving the problem]

[0007] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to power semiconductor devices that exhibit improved electrical behavior. This object is achieved, inter alia, by a power semiconductor device and a manufacturing method for such a power semiconductor device as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0008] In at least one embodiment, the power semiconductor device comprises: a semiconductor body having a source region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type, the well region including a channel region starting directly from the source region; a gate electrode arranged in the semiconductor body and assigned to the channel region; - a gate insulator directly between the semiconductor body and the gate electrode; Equipped with The gate insulator has a non-uniform thickness Tox along the channel region such that the gate insulator is thickest at a first portion along the channel region, away from the source region.

[0009] The gate electrode is insulated from the semiconductor body by a gate insulator. According to at least one embodiment, the at least one gate electrode is partially or completely disposed in at least one trench formed in the semiconductor body. The at least one trench, and therefore the assigned gate electrode, may extend, for example, in a direction away from the top surface of the semiconductor body through the well region into the drift region. As a result, the at least one gate insulator is also partially or completely located in the assigned trench. Thus, the power semiconductor device may be a trench-based device.

[0010] Alternatively, the at least one gate electrode and the at least one gate insulator are applied to a top surface of the semiconductor body, which may therefore be planar.

[0011] For example, the at least one source region is in direct contact with the assigned gate insulator and / or directly in the assigned channel region. The first conductivity type is, for example, an n-conductivity type, and thus the at least one source region is n-doped.

[0012] According to at least one embodiment, the at least one channel region is also of a second conductivity type different from the first conductivity type. The second conductivity type is, for example, a p-conductivity type, and therefore the at least one channel region is p-doped. The maximum doping concentration of the at least one channel region can be lower than the maximum doping concentration of the at least one source region.

[0013] According to at least one embodiment, the semiconductor body further comprises a drift region, which may be of the first conductivity type. For example, the drift region is in direct contact with the gate insulator and / or directly in the channel region. Along a direction away from the top surface of the semiconductor body, the drift region may be located between the channel region and the drain or collector region of the semiconductor body. For example, the optional trench may terminate in the drift region.

[0014] Optionally, the semiconductor body may comprise an enhancement layer. For example, the enhancement layer may be located directly between the well region and the drift region and have a higher maximum doping concentration than the drift region. The enhancement layer may also be of the first conductivity type. The enhancement layer may function as a hole blocking layer, i.e., E off Improved V ce-sat In addition, the reinforcing layer also helps to control the length of the channel region and minimizes the variations due to the manufacturing process. For example, the thickness of the reinforcing layer is at least 1 μm and / or at most 5 μm.

[0015] According to at least one embodiment, the well region extends from a top surface of the semiconductor body to the drift region. The channel region is part of the well region and may have the same doping concentration. In operation, electrons flow in the channel region from the source region along the gate insulator to the drift region. The channel region has a thickness in the nanometer range, illustratively between 1 nm and 50 nm, in a direction perpendicular to the interface between the gate insulator and the well region.

[0016] According to at least one embodiment, the power semiconductor device is a metal-insulator-semiconductor field effect transistor, MISFET, metal-oxide-semiconductor field effect transistor, MOSFET, insulated gate bipolar transistor, IGBT, or reverse conducting insulated gate bipolar transistor, RC-IGBT.

[0017] For example, the semiconductor body is made of silicon, or Si for short. However, the semiconductor body may alternatively be made of a wide bandgap semiconductor material, such as SiC, Ga2O3, or GaN.

[0018] The gate insulator is made of any electrically insulating material, which may be an oxide. For example, the gate insulator is made of at least one of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2. Therefore, the gate insulator may also be called a gate oxide.

[0019] According to at least one embodiment, the power semiconductor device is a power device, for example configured for a maximum voltage of at least 0.2 kV, or at least 0.6 kV, or at least 1.2 kV.

[0020] The power semiconductor device is intended for a power module in a vehicle, for example in a hybrid or plug-in electric vehicle, that converts direct current from a battery or fuel cell into alternating current for an electric motor. Additionally, the power semiconductor device may be a fuse in a vehicle, such as an automobile.

[0021] For simplicity, in the following only one channel region and assigned components are referred to. If multiple channel regions and assigned components are present, the features described below may apply to only one, multiple, or all of the channel regions and assigned components.

[0022] According to at least one embodiment, the thickness of the gate insulator along the channel region increases monotonically or strictly monotonically towards the drift region, where monotonically means that the thickness is constant or increasing, and strictly monotonically means that the thickness always increases towards the drift region.

[0023] According to at least one embodiment, along the channel region, the gate insulator has a first portion. The first portion may be remote from the source region and thus adjacent to the drift region. For example, the first portion is the thickest portion of the gate insulator along the channel region.

[0024] According to at least one embodiment, the length of the first portion is at least 5%, or at least 10%, or at least 15% of the total length of the channel region along the gate insulator. Alternatively or additionally, said length is at most 40%, or at most 30%, or at most 25% of said total length.

[0025] According to at least one embodiment, the gate insulator has a second portion located next to the source region along the channel region, and the gate insulator may be comprised of the second portion and the first portion along the channel region.

[0026] According to at least one embodiment, the gate insulator has a constant thickness along the channel region within the second portion, i.e., the only intentional thickness variation of the gate insulator may be within the first portion or at the boundary between the first and second portions.

[0027] According to at least one embodiment, the thickness of the gate insulator along the channel region varies by at least 10%, or at least 20%, or at least 30% of the maximum thickness of the gate insulator, for example, the remaining portion of the gate insulator has a thickness that is at most 70%, or at most 80%, or at most 90% of the thickness of the first portion.

[0028] According to at least one embodiment, the thickness of the gate insulator along the channel region varies stepwise such that there are one or more steps in the thickness of the gate insulator along the channel region, or the thickness of the gate insulator may vary continuously and without steps.

[0029] According to at least one embodiment, the gate insulator is of multi-layer type, such that it comprises at least two sub-layers. Otherwise, the gate insulator is of single-layer type and comprises only one layer. If multiple sub-layers are present, the sub-layers can be made of different materials and / or have different dielectric constants. The sub-layers may directly follow each other. The sub-layers can have different sizes, so that the sub-layers can be arranged mismatched. The sub-layers can also have different thicknesses, or they are all the same thickness.

[0030] According to at least one embodiment, the channel region has a non-uniform channel doping profile along the gate insulator. For example, a doping concentration N A may be largest in the first portion and, as a result, smallest in the second portion. For example, the doping concentration N A is maximum at a depth from the top surface of the semiconductor body of at least 0.5 μm or at least 1.5 μm. A may also be at a distance of at least 0.5 μm or at least 1.5 μm from the source region along the gate insulator. The maximum may be located within a well region. Thus, the maximum is achieved by epitaxial growth rather than ion implantation.

[0031] According to at least one embodiment, the gate electrode has a non-uniform gate electrode work function profile along the channel region such that a threshold voltage of the gate electrode is highest in a first portion. Thus, the work function Φ of the gate electrode in the first portion away from the source region is mis largest for devices with p-type doped well regions and therefore p-type doped channel regions, and is smallest for devices with n-type doped well regions and therefore n-type doped channel regions.

[0032] In accordance with at least one embodiment, the gate insulator has a non-uniform gate dielectric constant profile along the channel region such that the dielectric constant of the gate insulator is lowest in a first portion of the channel region away from the source region.

[0033] According to at least one embodiment, there is a non-uniform thickness profile, as well as a non-uniform channel doping profile and / or a non-uniform gate electrode work function profile and / or a non-uniform gate dielectric constant profile, i.e., the non-uniform gate insulator thickness profile can be combined with a non-uniform channel doping profile, a non-uniform gate electrode work function profile, or a non-uniform gate dielectric constant profile, or with two of the non-uniform channel doping profile, the non-uniform gate electrode work function profile, and the non-uniform gate dielectric constant profile, or with all three other non-uniform profiles.

[0034] According to at least one embodiment, the power semiconductor device has a collector-emitter saturation voltage V ce-sat , thus reducing both saturation current and short circuit current while on-state losses may remain unaffected. This may be true due to the non-uniform thickness profile of the gate insulator, which increases in thickness in a first portion while decreasing in thickness in the remainder of the gate insulator along the channel region, when compared to a similarly set up reference semiconductor device having a constant thickness of the gate insulator along the channel region.

[0035] There is further provided a method for manufacturing a power semiconductor device, by which a power semiconductor device is manufactured as shown in relation to at least one of the above-described embodiments. Accordingly, features of the power semiconductor device are also disclosed for the method and vice versa.

[0036] In at least one embodiment, a method for manufacturing a power semiconductor device includes the following steps, specifically in the order listed: providing a semiconductor substrate; - epitaxially growing at least one semiconductor layer on a semiconductor substrate;

[0037] For example, the semiconductor substrate comprises at least a portion of the drift region. For example, at least one epitaxially grown semiconductor layer comprises a well region and a source region.

[0038] The power semiconductor device and the manufacturing method are described in more detail below by way of exemplary embodiments with reference to the drawings. The same elements in the individual figures are indicated by the same reference numerals. However, the relationship between the elements is not shown to scale, rather the individual elements may be shown exaggerated in size to facilitate understanding. [Brief description of the drawings]

[0039] [Figure 1] 2 is a schematic cross-sectional view of a reference semiconductor device; [Diagram 2] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Diagram 3] FIG. 3 is a top view of the power semiconductor device of FIG. 2. [Figure 4] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Diagram 5] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 6]FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 7] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 8] FIG. 2 is a schematic diagram of gate insulator thickness for a power semiconductor device and a reference semiconductor device described herein. [Figure 9] FIG. 1 illustrates simulation results of electrical data for a power semiconductor device described herein and a reference semiconductor device. [Figure 10] FIG. 1 illustrates simulation results of electrical data for a power semiconductor device described herein and a reference semiconductor device. [Figure 11] FIG. 1 illustrates simulation results of electrical data for a power semiconductor device described herein and a reference semiconductor device. [Figure 12] FIG. 1 illustrates simulation results of electrical data for a power semiconductor device described herein and a reference semiconductor device. [Figure 13] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 14] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 15] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 16] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 17] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 18] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 19] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] 1 shows a reference semiconductor device 9 which corresponds to an exemplary embodiment of the power semiconductor device 1 described herein, except for the design of the gate insulator 4. Like the power semiconductor device 1, the reference semiconductor device 9 comprises a semiconductor body 2, for example made of Si.

[0041] The semiconductor body 2 comprises a source region 21 and a well region 22 through which a trench passes. In the well region 22 there is a channel region 220. When the reference semiconductor device 9 is in the on-state, electrons flow from the source region 21 through the channel region 220, which is located directly on the gate insulator 4, to the drift region 23.

[0042] The source region 21 is of a first conductivity type, such as n-conductivity, and the well region, and therefore the channel region 220, is of a second, different conductivity type, such as p-conductivity. Within the trench is a gate electrode 31 separated from the semiconductor body 2 by an electrically insulating gate insulator 4. The trench, and therefore the gate electrode 31, terminates in a drift region 23 of the semiconductor body 2. The drift region 23 is also of the first conductivity type.

[0043] In the reference semiconductor device 9, the gate insulator 4 is of constant thickness at least throughout the channel region 220. In contrast, in the exemplary embodiment of the power semiconductor device 1, the gate insulator 4 has a non-uniform thickness along the channel region 220. It should be noted that the shape of the channel region 220 is only depicted very roughly.

[0044] According to the power semiconductor device 1 of Fig. 2 and Fig. 3, the gate insulator 4 comprises one step 43, where the thickness of the gate insulator 4 changes abruptly. Looking along the channel region 220, after the step, the gate insulator 4 comprises a first portion 44, where the gate insulator 4 has its maximum thickness Tmax. Here, the term "along the channel region 220" means, for example, from the point where the channel region 220 starts on the gate insulator 4 close to the source region 21 to the start of the drift region 23, i.e. from the source region 21 along the direction x, for example, to the drift region 23, which is directly on the gate insulator 4. The region of the gate insulator 4 of interest here and below therefore has a length L, which corresponds to the distance between the source region 21 and the drift region 23, which is directly on the gate insulator 4. The length L may therefore be defined as the length of a layer of a first conductivity type, for example a layer of a second conductivity type, between the source region 21 and the drift region 23, the drift region 23 may include a layer of low doping concentration, not shown in the figures.

[0045] Furthermore, between the drift region 23 and the well region 22 there is a reinforcement layer 27. The reinforcement layer 27 is also of the first conductivity type.

[0046] Both the source region 21 and the well region 22 may be electrically connected by at least one source electrode 32 located on the top surface 20 of the semiconductor body 2 .

[0047] Optionally, there may be at least one plug 25 in the top surface 20 of the semiconductor body 2 to electrically contact the channel region 220. The plug 25 may have a different thickness than the well region 22 such that the plug 25 may extend deeper or shallower into the semiconductor body 2 than the well region 22. Furthermore, the thicknesses of the source region 21 and the plug 25 may be the same or different.

[0048] Both the source region 21 and the at least one plug 25 may be electrically connected by at least one source electrode 32 located on the top surface 20. Illustratively, the plug 25 has a higher maximum doping concentration than the well region 22 or the channel region 220. The depth of the plug may be lower, deeper or the same as the depth of the well region / channel region.

[0049] For example, the power semiconductor device 1 is an insulated gate bipolar transistor, IGBT for short. Therefore, on the side of the drift region 23 remote from the well region 22, there is also a collector region 26 of the second conductivity type. Furthermore, as a further option, there may be a buffer region of the first conductivity type between the drift region 23 and the collector region 26, not shown. The doping concentration of the buffer region may be higher than the doping concentration of the drift region 23. In the collector region 26, a collector electrode 34 is present.

[0050] For example, the semiconductor body 2 is at least partially produced by epitaxial growth, i.e. the doping concentration of the respective layers of the semiconductor body 2 may be generated during growth and not after growth, for example by ion implantation. This applies, for example, at least to the enhancement layer 27 and to the well region 22, which may thus be doped by epitaxial growth. Optionally, the drift region 23 may be partly or completely part of the growth substrate. The same applies to all other examples.

[0051] When viewed in top view of the upper surface 20, the trench housing the gate electrode 31 may be elongated. The source region 21, the at least one plug 25, and the channel region 21 may be symmetrically disposed on either side of the trench, see FIG.

[0052] For example, the thickness of the gate insulator along the channel region outside the first portion is 20 nm to 80 nm, or 40 nm to 80 nm. Alternatively or additionally, in the first portion, the thickness is 120 nm to 250 nm, or 120 nm to 180 nm.

[0053] For example, instead of the source region 21, the collector region 26 or the drain region 24, and at least one plug 25 has a maximum doping concentration of at least 1×10 18 cm -3 Or at least 5×10 18 cm -3 Or at least 1×10 19 cm -3 and / or at most 5 × 10 20 cm -3 Or at most 2×10 20 cm -3 Or at most 1×10 20 cm -3 Furthermore, the maximum doping concentration of the well region 22, and therefore the channel region 220, is at least 5×10 16 cm -3 Or at least 1×10 17 cm -3 and / or at most 5 × 10 19 cm -3 Or at most 5 x 10 18 cm -3 For example, the maximum doping concentration of the enhancement layer 27 can be at least 10 15 cm -3 and / or at most 10 18 cm -3 It is.

[0054] Depending on the voltage class of the power semiconductor device 1, the maximum doping concentration of the drift region 23 is at least 1×10 11 cm -3 Or at least 1×10 12 cm -3 Or at least 1×10 13 cm -3and / or at most 1 × 10 17 cm -3 Or at most 5 x 10 16 cm -3 Or at most 1×10 16 cm -3 It could be.

[0055] 2 and 3, the source region 21 and the at least one plug 25 are arranged along only one side of the gate electrode 31, so that the channel region 220 is only along one outside of the gate insulator 4. However, the source region 21 as well as the at least one plug 25 can also be arranged along two sides of the gate electrode 31, or all around the gate electrode 31 when viewed from a top view, as compared to, for example, FIG.

[0056] If not, the same may be true for Figures 2 and 3 as for Figure 1 . The concept of a gate insulator 4 with non-uniform thickness is explained below.

[0057] For power semiconductor device 1, illustratively for low frequency applications, it may be desirable to have as low an on-state loss as possible in order to minimize total electrical losses. Furthermore, from a device reliability standpoint, it may be advantageous to have a low short circuit current. Thus, a power semiconductor device 1 with minimized on-state losses and improved short circuit capability may be desired.

[0058] However, for example, decreasing the channel length L or increasing the channel width W can reduce the on-state voltage drop V ce-sat Several means of reducing the output characteristic I c Against V ce As shown diagrammatically using the undesirable higher saturation current I sat See Figure 4. High I sat is a high short circuit current I sc This directly relates to the short circuit capability of the power semiconductor device 1 and adversely affects the short circuit capability of the power semiconductor device 1. On the other hand, the Isat In order to reduce the threshold voltage V th As shown in Figure 5, increasing V ce-sat Therefore, Figures 4 and 5 are schematic diagrams of typical output characteristics of an IGBT with a uniform threshold profile along the entire channel region. In Figure 4, th and different channel resistances. In Fig. 5, different threshold voltages V th This is the case.

[0059] a) Increasing the channel length L; b) Reducing the anode injection efficiency by reducing the anode implant dose; c) reducing the channel width by reducing the source coverage along the trench; and d) Reducing the channel width by increasing the cell pitch Other techniques for reducing the short circuit current, such as d), also undesirably result in higher on-state losses. Moreover, techniques such as d) may also adversely affect the breakdown capability of the power semiconductor device 1. Reducing the gate bias to reduce the short circuit current may also lead to unstable dynamic behavior and may be undesirable, as it is primarily dictated by the application requirements.

[0060] Thus, in conventional MISFET or IGBT devices, there is a trade-off between minimizing on-state losses and reducing short-circuit current. For applications requiring improved short-circuit capability, V ce-sat Without affecting the short circuit current I sc It is desirable to be able to reduce

[0061] Another possibility to affect the electrical behavior at the gate electrode in non-IGBT devices is to use a relatively thick gate oxide at the trench bottom, for example, mainly for protection against hot carrier injection. However, the extent of the thicker oxide may be limited to the n-base region and not extended to the p-doped regions, which would have influenced the MOS channel characteristics. Besides, asymmetries in the channel doping or gate oxide thickness may be introduced not within the channel region of the same cell, but for adjacent cells. Using a relatively thick gate oxide, for example with a thickness of 180 nm to 250 nm, uniformly along the trench sidewalls and trench bottom, may also be possible to improve the IGBT short circuit capability by raising its threshold voltage. However, this approach suffers from a higher on-state voltage drop. Another way to fabricate a non-uniform gate oxide for DRAM devices can use a relatively thick oxide at the top of the recess sidewalls.

[0062] In the power semiconductor device 1 described herein, the tradeoff between on-state losses and short circuit current is improved by improving the latter without adversely affecting the former. Unlike other approaches, the described design provides a ce-sat The non-uniform threshold voltage profile proposed in the power semiconductor device 1 described herein is characterized by a non-uniform threshold voltage profile along the channel region 220 adjacent to the gate insulator 4 in order to reduce the saturation current for V th is achieved by implementing a non-uniform gate insulator thickness along the channel region 220. The described power semiconductor device 1 does not adversely affect the breakdown capability and even more so the turn-off losses of the power semiconductor device 1. In addition, the described concepts are generally applicable to any MOS device such as a power MOSFET or IGBT or reverse conducting IGBT device and are even compatible with both planar and trench architectures.

[0063] The power semiconductor device 1 described herein introduces improved MISFET, MOSFET or IGBT devices with improved short circuit capability without detrimentally affecting on-state losses. The improved design also relaxes the design constraints of the IGBT, allowing the possibility to independently explore other methods mentioned above to minimize on-state losses that are typically limited by the short circuit capability of the respective device.

[0064] In the following, some theoretical background to the conception of the semiconductor device 1 described herein is presented.

[0065] For the reference long-channel MOS device 9, a high V ce It is known that the channel pinch-off at V causes current saturation in the output characteristic, which ultimately determines the short circuit current. pinch-off is the threshold voltage V th In detail, the applied bias V ce is the pinch-off voltage V pinch-off ≒(V g -V th ), the channel begins to pinch off near its drain end at x=L, where V g is the applied gate voltage and L is the channel length. ce The voltage drop perpendicular to the channel is V th It is smaller and therefore the channel can no longer persist near the drain end.

[0066] However, for a more detailed understanding of the device, channel pinch-off should be considered as a rather local phenomenon, occurring specifically near the drain end of the channel. More precisely, it is the local threshold voltage V that determines the pinch-off point, and hence the saturation current. th (x). This is because in the first portion 44 near the channel end, i.e., the drift region 23, V th By locally increasing (L), V pinch-offFurthermore, the overall channel resistance is preserved, thereby reducing V ce-sat To avoid affecting V th (x) can be reduced.

[0067] This is because the curve pointing to the reference semiconductor device 9 shows a uniform threshold voltage V along the entire channel. th-1 6 including the profile. On the other hand, the curve for the power semiconductor device 1 shows a non-uniform V along the channel. th It consists of a profile, V th is V to lower the pinch-off point. th-2 (L)>V th-1 and in the remainder of the channel, V th-2 ' <V th-1 In this way, the saturation current, and therefore the short circuit current, can be significantly reduced without affecting the on-state losses, as shown in the schematic output of Figure 7. th Variation holds the key to improving the short circuit capability of MISFET or MOSFET or IGBT devices.

[0068] Channel V th is a function of various other MOS cell design parameters as shown in the following equation:

[0069]

number

[0070] Here, V t is the threshold voltage, V fb is the flat band voltage, V fb =(φ m -φ s ), where φ m and φ s are the gate metal work function and the semiconductor work function, respectively. Na is the doping of the channel body, and ε s is the dielectric constant of the semiconductor, and C ox is the gate insulator capacitance, and φ B is the semiconductor surface potential,

[0071]

number

[0072] where k is the Boltzmann constant, T is the temperature, and n i is the intrinsic carrier concentration of the semiconductor.

[0073] Therefore, the relatively high V th The non-uniform V required across the channel th The profile can be achieved by introducing non-uniformity in one or any combination of the following MOS design parameters:

[0074] 1. Channel doping profile, N a (x), 2. The gate oxide thickness Tox(x) as detailed herein; 3. Gate dielectric constant, ε ox (y), and / or 4.V fb =(φ m -φ s ), so the gate metal work function φ m (x).

[0075] In the following, we focus on varying the gate insulator thickness, but said thickness variation can of course be combined with a varying channel doping profile, a varying gate dielectric constant, and / or a varying gate metal work function.

[0076] 1 and 2 above show schematic cross-sectional views of a reference semiconductor device 9 with a uniform gate insulator thickness profile and a power semiconductor device 1 with a non-uniform gate insulator thickness profile, which are implemented in the simulations presented below. Three different gate oxide profiles were investigated, see FIG. 8. The design referring to the reference semiconductor device 9 has a uniform gate oxide thickness Tox of 100 nm, which serves as a reference. For the design A of the power semiconductor device 1, the local V th To increase (L), Tox in the first portion 44 was increased to 140 nm, and Tox in the remaining portion of the channel region 220 was decreased to 40 nm to maintain the same on-state as the reference semiconductor device 9.

[0077] On the other hand, in the design B of the power semiconductor device 1, Tox in the first portion 44 is further increased to 150 nm, resulting in a higher local V th (L) and the thickness Tox of the remaining part of the gate insulator 4 is 60 nm. The effect of these gate oxide profiles can be clearly seen on the simulated output characteristics in FIG. 9, where V ce-sat Lowers the pinch-off point without sacrificing high local V th Due to (L), I sat A clear decrease in can be observed for designs A and B.

[0078] Design B, which has a larger Tox in the first portion 44, is sat shows a further improvement in, but a slightly higher V ce-sat 10. This is due to the relatively thick Tox in the remaining portion of the gate insulator 4 along the channel region 220.

[0079] As expected, a clear reduction in short circuit current, for example of 20% or 40%, can be observed for designs A and B, as shown in FIG. 11, compared to the reference semiconductor device 9.

[0080] As shown in FIG. 12, the breakdown characteristics of the device remain unaffected by the varying gate dielectric profile, as expected. The switching losses E off remains largely unaffected by changes in the Tox profile, compare the following list of simulation results for designs A and B with different Tox profiles.

[0081] Reference Semiconductor Device 9: -Gate oxide profile: uniform, 100nm V at -150A ce-sat :1.619V V at -10mA th :4.30V -E off :12.69mJ -I sc :=100% Power Semiconductor Device 1 Design A: -Gate oxide profile: non-uniform, 40nm and 140nm V at -150A ce-sat :1.633V V at -10mA th :5.56V -E off :13.10mJ -I sc :=I of reference semiconductor device 9 sc About 90% of Power Semiconductor Device 1 Design B: -Gate oxide profile: non-uniform, 60nm and 150nm V at -150A ce-sat :1.700V V at -10mA th :5.94V -E off :13.09mJ -I sc :=I of reference semiconductor device 9 sc About 70% of In these devices 9, A, B, the length L of the channel is in each case 2.5 μm, the first portion 44 of designs A, B having a length of 1.0 μm.

[0082] In the exemplary embodiment of the power semiconductor device 1 of Fig. 13, the thickness of the gate insulator 4 varies in two steps 43. The second step can be larger than the first step, so that the thickness increase is greater in the step 43 closer to the drift region 23, or vice versa. Thus, the thickness Tox of the gate insulator 4 increases monotonically towards the drift region 23.

[0083] As is possible in all other exemplary embodiments of the power semiconductor device 1, the outer side 40 of the gate insulator 4 facing the semiconductor body 2 may be planar at least along the channel region 220. Thus, a change in thickness of the gate insulator 4, such as a step 43, may only affect the inner side of the gate insulator 4, which faces the gate electrode 31.

[0084] Moreover, the power semiconductor device 1 in Fig. 13 is shown to be a MOSFET or MISFET, not an IGBT. As a result, the power semiconductor device 1 comprises a drain region 24 instead of a collector region 26. Thus, on the side of the drift region 23 remote from the well region 22, there is also a drain region 24 which is of the first conductivity type but has, for example, a higher maximum doping concentration than the drift region 23. In the drain region 24, a drain electrode 33 is present.

[0085] Of course, all gate insulator designs for IGBT power semiconductor devices 1 can be applied to MOSFET and MISFET power semiconductor devices 1, and vice versa.

[0086] Furthermore, all power semiconductor devices 1 may be configured as reverse conducting IGBTs, which comprise collector regions of a second conductivity type alternating with short circuits of a first conductivity type.

[0087] If this is not the case, the same may be true for FIG. 13 with respect to FIGS. 2-12, and vice versa.

[0088] 14, the gate insulator 4 includes multiple steps 43 and does not increase monotonically in thickness. Thus, there may be a small first step to a higher thickness near the source region 21 and a small second step back to the original thickness, and a larger third step to a higher final thickness adjacent the drift region 23.

[0089] If this is not the case, the same may be true for FIG. 14 as for FIG. 2-FIG. 13, and vice versa.

[0090] In Fig. 15, the thickness does not change in a step manner but is shown to change continuously from the beginning of the first portion 44. The transition region 46 in which the thickness Tox changes may be, for example, at least 2% and / or at most 15% or at most 10% or at most 5% of the length L. As in Fig. 13 or 14, there may be two or more such transition regions 46.

[0091] If this is not the case, the same may be true for FIG. 15 as for FIG. 2-FIG. 14, and vice versa.

[0092] In the previous exemplary embodiments, the gate insulator 4 is made of a single continuous layer of the same material with varying thickness. In contrast, referring to FIG. 16, the gate insulator 4 is of multi-layer type. For example, the gate insulator 4 includes a third sublayer 45 adjacent to the semiconductor body 2 and extending completely between the semiconductor body 2 and the gate electrode 31. In addition, there is a first sublayer 41 adjacent to the gate electrode 31 and reaching the drift region 23, as well as a second sublayer 42 between the first sublayer 41 and the third sublayer 45. The first sublayer 41 is only partially through the well region 22 and is not present near the source region 21.

[0093] For example, the first sublayer 41 is the thickest of the sublayers, and the second sublayer 42 or the third sublayer 45 is the thinnest. Each of the sublayers 41, 42, 45 may have a thickness that does not vary within the respective sublayer 41, 42, 45, such that the sublayers 41, 42, 45 may each be of constant thickness. Where the first sublayer 41 and the second sublayer 42 end, a step 43 exists. Thus, the sublayers 41, 42, 45 do not coincide. All of the sublayers 41, 42, 45 may be made from the same material or may be made from different materials.

[0094] Optionally, the length that second sub-layer 42 protrudes from first sub-layer 41 is at most 50% or at most 30% of the extent of first portion 44 along length L.

[0095] If this is not the case, the same may be true for FIG. 16 as for FIG. 2-FIG. 15, and vice versa.

[0096] 17, the thickness of the gate insulator 4 is shown to increase strictly monotonically, e.g. linearly, over the entire well region 22. It is also possible for said thickness to increase strictly monotonically, e.g. linearly, along the entire gate insulator 4, i.e. also in the source region 21 and / or the drain region 23.

[0097] According to Fig. 18, the power semiconductor device 1 has a planar design and not a trench design, for example, as the power semiconductor device 1 of Figs. 2 and 3. The top surface 20 is therefore planar, and the gate insulator 4 and the gate electrode 31 are applied to the top surface 20. As a result, the length L between the source region 21 and the drift region 23 is parallel to the top surface 20, unlike in the other exemplary embodiments, which is perpendicular to the top surface 20. The same applies to the direction x along which the thickness Tox varies.

[0098] 18, the channel region 220 protrudes laterally, i.e. parallel to the top surface 20, from the source region 21 and extends below the gate insulator 4. The source region 21 may also extend below the gate insulator 4, but to a lesser extent.

[0099] All the above mentioned different designs of the gate insulator 4 can be applied equally to the planar concept of Fig. 18, both for MISFET or MOSFET as well as for IGBT. Therefore, the same may be applied to Fig. 18 as for Figs. 2-17.

[0100] 19 shows that there is not only a non-uniform gate insulator thickness profile, but also a non-uniform gate dielectric constant profile due to the at least two different materials 81, 82 of which the gate insulator 4 is composed. That is, the thickness of the gate insulator 4 varies along the channel region 220.

[0101] For example, the difference in dielectric constant along the channel region 220 due to the at least two different materials 81, 82 is at least 2.0, or at least 3.0, or at least 3.5. Alternatively or additionally, said difference is at most 50, or at most 25. When comparing the respective dielectric constants, textbook values ​​of the respective materials at room temperature, i.e., 300K, and at a frequency of the fluctuating electric field of at most 1 kHz may be used. When there is only a non-uniform gate insulator thickness profile and a uniform gate dielectric constant profile, the gate insulator 4 may be made of a single material.

[0102] In addition to or instead of a non-uniform gate dielectric constant profile, there may be a non-uniform gate electrode work function profile 72 of the gate electrode 31. Thus, the gate electrode 31 may include a first gate material 84 adjacent to the source region 21 and a second gate material 85 adjacent to the drain region 23. The gate materials 84, 85 may vary where the materials 81, 82 of the gate insulator 4 vary. Thus, the work function Φ of the gate electrode 31 in the first portion 44 away from the source region 21 m is maximum for a device having a p-doped well region 22 and therefore a p-doped channel region 220 and is minimum for a device having an n-doped well region 22 and therefore an n-doped channel region 220.

[0103] For example, the work function difference of the gate electrode along the channel region 220 is at least 0.7 eV, or at least 1.0 eV, or at least 1.1 eV. This is the case, for example, when the gate electrode 31 is based on polysilicon. If metals such as Li, Zn, Hf for low work functions or Pt, Pd, or Au for high work functions are also considered, the work function difference can be at least 1.3 eV or at least 1.4 eV. For example, the work function difference is at most 2.0 eV or at most 1.5 eV.

[0104] For example, the second gate material 85 has a work function Φ of about 5.22 eV. m p + For example, the first gate material 84 is doped polysilicon having a work function Φ of about 4.1 eV. m n + Although based on silicon, these first gate material 84 and second gate material 85 are sometimes referred to as different gate electrode metals.

[0105] Thus, there is a step in the non-uniform gate electrode work function profile 72 at the interface between the first portion 44 and the second portion 47, see the inset of FIG.

[0106] In addition to or instead of a non-uniform gate dielectric constant profile and / or a non-uniform gate electrode work function profile 72, there may be a non-uniform channel doping profile 71. That is, the doping concentration N A varies along the channel region 220.

[0107] For example, the maximum doping concentration present in the non-uniform channel doping profile 71 is at least 5×10 16 cm -3 and at most 5 × 10 19 cm -3 and / or the minimum doping concentration present in the non-uniform channel doping profile 71 is at most 2×10 17 cm -3 Or at most 1×10 17 cm -3 The maximum doping concentration may be present in the first portion 44 and the minimum doping concentration may be present in the second portion 47. The doping concentration N A For example, the doping concentration N A However, the doping concentration N A The steps in do not have to follow exactly a theta function or a unit step function, but there can be sinusoidal steps, see the inset in Figure 19. The steps can be at the locations where the material 81, 82 of the gate insulator 4 changes.

[0108] At least one such non-uniform gate electrode work function profile 72, non-uniform gate insulator dielectric constant profile, and non-uniform channel doping profile 71 may also be present in all other exemplary embodiments similarly.

[0109] If this is not the case, the same may be true for FIG. 19 as for FIG. 2-FIG. 18, and vice versa.

[0110] Components depicted in the figures exemplarily follow one another directly in the specified order, unless otherwise indicated. Components that are not in contact in the figures are exemplarily spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces are exemplarily oriented parallel to one another. Similarly, unless otherwise indicated, the positions of depicted components relative to one another are accurately reproduced in the drawings.

[0111] The power semiconductor device described herein is not limited by the description based on the exemplary embodiments, but rather includes any novel feature and any combination of features, including any combination of features in the claims, even if this feature or this combination itself is not explicitly specified in the claims or exemplary embodiments.

[0112] This patent application claims priority to European Patent Application No. 21186089.5, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0113] List of References 1. Power Semiconductor Devices 2. Semiconductor body 20 Top side 21 Source Area 22 Well Area 220 Channel Area 23 Drift Region 24 Drain Region 25 Plug 26 Collector Region 27 Reinforcement layer 31 Gate electrode 32 Source electrode 33 Drain electrode 34 Collector electrode 4 Gate insulator 40 outside 41 First sublayer of gate insulator 42 Gate insulator second sublayer 43 Stairs 44 First Part 45 Gate insulator third sublayer 46 Transition region 47 Second Part 71 Non-uniform channel doping profile 72 Non-uniform gate electrode work function profile 81 First material of gate insulator 82 Second material for gate insulator 84 First Gate Material 85 Second Gate Material 9 Reference Semiconductor Device A First Exemplary Power Semiconductor Device B. Second Exemplary Power Semiconductor Device I sat saturation current L is the length of the channel region along the gate insulator Tmax Maximum thickness of the gate insulator Tox: The thickness of the gate insulator along the channel region. V th Threshold Voltage x is the length along the channel region

Claims

1. - A semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, wherein the well region (22) includes a channel region (220) directly above the source region (21), the semiconductor body (2); - A gate electrode (31) disposed on the semiconductor body (2) and assigned to the channel region (220); - A gate insulator (4) directly between the semiconductor body (2) and the gate electrode (31); A power semiconductor device (1) comprising: Along the channel region (220), the gate insulator (4) has a non-uniform thickness Tox along the channel region (220) such that the gate insulator (4) is thickest at a first portion (44) away from the source region (21); The following - The channel region (220) has a non-uniform channel doping profile (71) along the gate insulator (4), or -The threshold voltage (V th ) of the gate electrode (31) is the highest in the first portion (44), and the gate electrode (31) has a non-uniform gate electrode work function profile (72) along the channel region (220), or - The gate insulator (4) has a non-uniform gate dielectric constant profile along the channel region (220) such that the relative dielectric constant of the gate insulator (4) is lowest at the first portion (44) of the channel region (220) away from the source region (21); At least one of the above applies, Power semiconductor device (1).

2. The gate electrode (31) is at least partially disposed in a trench formed along the channel region (220) within the semiconductor body (2), The semiconductor body (2) further comprises a reinforcement layer (27) of the first conductivity type directly on the side of the well region (22) away from the source region (21), The power semiconductor device (1) according to claim 1.

3. The gate electrode (31) and the gate insulator (4) are disposed on a flat upper surface (20) of the semiconductor body (2), The semiconductor body (2) further comprises a reinforcement layer (27) of the first conductivity type directly on the side of the well region (22) away from the source region (21), The power semiconductor device (1) according to claim 1.

4. - The source region (21) is in direct contact with the gate insulator (4) and the channel region (220), - The semiconductor body (2) further includes a drift region (23) of the first conductivity type that is in direct contact with the gate insulator (4) and is directly in the well region (22). - The power semiconductor device (1) is a metal-insulator-semiconductor field effect transistor, MISFET, metal-oxide-semiconductor field effect transistor, MOSFET, insulated gate bipolar transistor, IGBT, or reverse conducting insulated gate bipolar transistor, RC-IGBT. The power semiconductor device (1) according to any one of claims 1 to 3.

5. Along the channel region (220), the gate insulator (4) is directly thickest in the drift region (23). The power semiconductor device (1) according to claim 4.

6. The thickness Tox of the gate insulator (4) along the channel region (220) increases monotonically or strictly monotonically away from the source region (21). The power semiconductor device (1) according to any one of claims 1 to 3.

7. The outer side (40) of the gate insulator (4) facing the semiconductor body (2) is planar along the channel region (220). The power semiconductor device (1) according to any one of claims 1 to 3.

8. The length of the first portion (44) is at least 10% and at most 40% of the total length (L) of the channel region (220) along the gate insulator (4). The power semiconductor device (1) according to any one of claims 1 to 3.

9. The gate insulator (4) has a second portion (47) disposed adjacent to the source region (21) as viewed along the channel region (220). The power semiconductor device (1) according to any one of claims 1 to 3.

10. The following - In the second portion (47), the gate insulator (4) has a constant thickness and is thinner than the first portion (44), or - The thickness Tox of the gate insulator (4) in the second portion (47) is 20 nm or more and 80 nm or less, and in the first portion (44) it is 120 nm or more and 250 nm or less At least one of which applies. The power semiconductor device (1) according to claim 9.

11. The thickness Tox of the gate insulator (4) along the channel region (220) varies by at least 20% of the maximum thickness (Tmax) of the gate insulator (4). The power semiconductor device (1) according to any one of claims 1 to 3.

12. The thickness Tox of the gate insulator (4) along the channel region (220) changes stepwise such that there is at least one step (43) in the thickness Tox of the gate insulator (4) along the channel region (220). The power semiconductor device (1) according to claim 4.

13. The gate insulator (4) includes a plurality of steps (43) in its thickness, and the thickness does not increase monotonically. The power semiconductor device (1) according to claim 12.

14. In the direction away from the source region (21), there is a first step to a higher thickness Tox, followed by a second step back to the original thickness Tox adjacent to the source region (21), and finally a third step to the highest final thickness Tox adjacent to the drift region (23). The power semiconductor device (1) according to claim 13.

15. The thickness Tox of the gate insulator (4) along the channel region (220) changes continuously without steps. The power semiconductor device (1) according to any one of claims 1 to 3.

16. The thickness Tox of the gate insulator (4) increases linearly across the entire well region (22). The power semiconductor device (1) according to claim 15.

17. The gate insulator (4) is in a multilayer form. The power semiconductor device (1) according to any one of claims 1 to 3.

18. The gate insulator (4) is in a single-layer form such that the gate insulator (4) is composed of exactly one continuous layer. The power semiconductor device (1) according to any one of claims 1 to 3.

19. A method for manufacturing the power semiconductor device (1) according to claim 4, comprising: - providing a semiconductor substrate; - epitaxially growing at least one epitaxial growth semiconductor layer on the semiconductor substrate. The method includes.

20. The semiconductor substrate includes at least a part of the drift region (23), and the at least one epitaxial growth semiconductor layer includes the well region (22) and the source region (21). The method according to claim 19.

Images