Power semiconductor device and manufacturing method

Abstract

In at least one embodiment, the power semiconductor device (1) comprises: - a semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, the well region (22) including a channel region (220) starting directly from the source region (21); a gate insulator (4) directly between the semiconductor body (2) and the gate electrode (31), The gate electrode (4) has a threshold voltage (V th The semiconductor device has a non-uniform work function profile (6) along the channel region (220) such that the work function peak-to-peak (Pt) is highest in a first section (61) remote from the source region (21).

Description

[Technical field]

[0001] A power semiconductor device is provided, as well as a manufacturing method for such a power semiconductor device. [Background technology]

[0002] The document US Pat. No. 10,468,407 B2 refers to a Fin Field Effect Transistor (FinFET) device structure having a non-planar gate structure.

[0003] The document US Pat. No. 7,141,858 B2 refers to a dual work function CMOS gate technology based on metal interdiffusion.

[0004] The document US Pat. No. 6,653,698 B2 describes the integration of dual workfunction metal gate CMOS devices.

[0005] The document US Patent Application Publication No. 2016 / 0064550A1 refers to a power device.

[0006] The documents US 2012 / 025874 A1, US 2015 / 0214362 A1, EP 1248300 A2, and US 2016 / 0104794 A1 refer to electronic devices. Summary of the Invention [Problem to be solved by the invention]

[0007] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to power semiconductor devices that exhibit improved electrical behavior. [Means for solving the problem]

[0008] This is achieved, inter alia, by a power semiconductor device and a manufacturing method for such a power semiconductor device as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0009] In at least one embodiment, the power semiconductor device comprises: a semiconductor body having a source region of a first conductivity type and a well region of a second conductivity type different from the first conductivity type, the well region including a channel region starting directly from the source region; - a gate insulator directly between the semiconductor body and the gate electrode; Equipped with The gate electrode has a non-uniform work function profile along the channel region such that a threshold voltage of the gate electrode is highest in a first section of the channel region away from the source region.

[0010] Therefore, the work function Φ of the gate electrode in the first section away from the source region m is largest for a device having a p-type doped well region with a p-type doped channel region and is smallest for a device having an n-type doped well region with an n-type doped channel region.

[0011] In the following, unless otherwise indicated, the work function Φ m is described for a device having p-doped well regions and therefore p-doped channel regions, but the converse also applies for devices having n-doped well regions.

[0012] The gate electrode is insulated from the semiconductor body by a gate insulator. For example, the at least one source region is in direct contact with the assigned gate insulator and / or directly in the assigned channel region. The first conductivity type is, for example, an n-conductivity type, and therefore the at least one source region is n-doped.

[0013] The at least one well region, and therefore the at least one channel region, is of a second conductivity type different from the first conductivity type. The second conductivity type is, for example, a p-conductivity type, and therefore the at least one channel region is p-doped. The maximum doping concentration of the at least one well region and / or the at least one channel region can be lower than the maximum doping concentration of the at least one source region.

[0014] According to at least one embodiment, the semiconductor body further comprises a drift region, which may be of the first conductivity type. For example, the drift region is in direct contact with the gate insulator and / or is directly in the channel region. The drift region may be located, for example, between the channel region and the drain or collector region of the semiconductor body in a direction perpendicular to the top surface of the semiconductor body. For example, the optional trench may terminate in the drift region.

[0015] Optionally, the semiconductor body may comprise an enhancement layer. For example, the enhancement layer may be located directly between the well region and the drift region and have a higher maximum doping concentration than the drift region. The enhancement layer may also be of the first conductivity type. The enhancement layer may function as a hole blocking layer, i.e., E off Improved V ce-sat Additionally, the reinforcing layer also helps control the length of the channel region, minimizing variations due to the manufacturing process.

[0016] For example, the maximum doping concentration of the enhancement layer is at least 10 15 cm -3 and / or at most 10 18 cm -3 Alternatively or additionally, the thickness of the reinforcing layer is at least 1 μm and / or at most 5 μm.

[0017] According to at least one embodiment, the power semiconductor device is a Metal-Insulator-Semiconductor Field Effect Transistor, MISFET, Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET, or an Insulated Gate Bipolar Transistor, IGBT or Reverse Conducting Insulated Gate Bipolar Transistor, RC-IGBT.

[0018] According to at least one embodiment, the well region extends from a top surface of the semiconductor body to the drift region. The channel region is part of the well region and may have the same doping concentration. In operation, electrons flow in the channel region from the source region along the gate insulator to the drift region. The channel region has a thickness in the nanometer range, illustratively between 1 nm and 50 nm, in a direction perpendicular to the interface between the gate insulator and the well region.

[0019] For example, the semiconductor body is made of silicon, or Si for short. However, the semiconductor body may alternatively be made of a wide bandgap semiconductor material, such as SiC, Ga2O3, or GaN.

[0020] The gate insulator is made of any insulating material, which may be an oxide. For example, the gate insulator is made of at least one of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2. Therefore, the gate insulator may also be called a gate oxide.

[0021] According to at least one embodiment, the power semiconductor device is a power device, for example configured for a maximum voltage of at least 0.2 kV, or at least 0.6 kV, or at least 1.2 kV.

[0022] The power semiconductor device is intended for a power module in a vehicle, for example in a hybrid or plug-in electric vehicle, that converts direct current from a battery or fuel cell into alternating current for an electric motor. Additionally, the power semiconductor device may be a fuse in a vehicle, such as an automobile.

[0023] For simplicity, in the following only one channel region and assigned components are referred to. If multiple channel regions and assigned components are present, the features described below may apply to only one, multiple, or all of the channel regions and assigned components.

[0024] According to at least one embodiment, the work function difference of the gate electrode along the channel region is at least 0.7 eV, or at least 1.0 eV, or at least 1.1 eV. This is the case, for example, when the gate electrode is based on polysilicon. If metals such as Li, Zn, Hf for low work functions or metals such as Pt, Pd, or Au for high work functions are also considered, the work function difference can be at least 1.3 eV or at least 1.4 eV. For example, the work function difference is at most 2.0 eV or at most 1.5 eV. Here and below, the term "along the channel region" may refer to the direction of current flow in the channel region in the intended use of the power semiconductor device.

[0025] According to at least one embodiment, the gate electrode includes a first material in a first section and a second material in a second section adjacent to the source region, the first material having a higher work function Φ (for devices having p-doped well regions) than the second material. m and vice versa for devices with n-doped well regions.

[0026] The gate electrode may be composed of a first section and a second section. Alternatively, there may be at least one additional section, such as an intermediate section, located between the first section and the third section along the channel region. If there is at least one additional section, it may have a work function Φ different from the work functions of the first and second materials. m There may be at least one additional material having the formula:

[0027] According to at least one embodiment, the first material is p-doped polysilicon and the second material is n-doped polysilicon. This applies, for example, to the n-type channel region.

[0028] According to at least one embodiment, the length of the first section is at least 5%, or at least 10%, or at least 15% of the total length of the channel region along the gate insulator. Alternatively or additionally, said length is at most 40%, or at most 30%, or at most 25% of said total length. The same may apply to at least one additional section, if present.

[0029] According to at least one embodiment, the gate insulator has a non-uniform thickness profile along the channel region, for example, along the channel region, the gate insulator may be thickest in a first section and, consequently, thinnest in a second section.

[0030] According to at least one embodiment, the channel region has a non-uniform channel doping profile along the gate insulator. For example, a doping concentration N A may be largest in the first section and, consequently, smallest in the second section.

[0031] According to at least one embodiment, there is a non-uniform thickness profile as well as a non-uniform channel doping profile. Thus, the work function of the gate electrode, as well as the thickness of the gate insulator and the doping concentration N in the channel region, A may vary along the channel region. For example, the doping concentration N A is maximum at a depth from the top surface of the semiconductor body of at least 0.5 μm or at least 1.5 μm. A may also be at a distance of at least 0.5 μm or at least 1.5 μm from the source region along the gate insulator. The maximum may be located within a well region. Thus, the maximum is achieved by epitaxial growth rather than ion implantation.

[0032] According to at least one embodiment, the thickness of the gate insulator varies significantly along the channel region, meaning, for example, that the minimum thickness of the gate insulator is at most 70%, or at most 50% of the maximum thickness of the gate insulator, in this respect only the gate insulator along the channel region may be relevant.

[0033] According to at least one embodiment, the minimum doping concentration of the channel region along the gate insulator is at most 50%, or at most 20%, or at most 10% of the maximum doping concentration of the channel region.

[0034] According to at least one embodiment, at least one of the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform work function profile extends continuously and step-free, and thus, each of the at least one profiles may be represented by a differentiable function.

[0035] According to at least one embodiment, at least one of the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform work function profile extends in a step-like manner, and thus at least one respective profile includes one or more steps and may not be represented by a differentiable function.

[0036] A stepwise non-uniform thickness profile, non-uniform channel doping profile, and / or non-uniform work function profile can be combined with a non-stepwise non-uniform thickness profile, non-uniform channel doping profile, and / or non-uniform work function profile.

[0037] According to at least one embodiment, the non-uniform work function profile and at least one of the non-uniform thickness profile and the non-uniform channel doping profile are coextensive with the non-uniform work function profile, e.g., at least one step in the non-uniform work function profile and at least one step in the non-uniform thickness profile and at least one of the non-uniform channel doping profile are at the same location along the channel region.

[0038] According to at least one embodiment, the gate electrode is partially or completely disposed in at least one trench formed in the semiconductor body. The at least one trench, and thus the assigned gate electrode, extends, for example, in a direction away from the top surface of the semiconductor body through the well region into the drift region. As a result, the gate insulator is also partially or completely located in the assigned trench. The power semiconductor device may therefore be a trench-based device.

[0039] Otherwise, the gate electrode and gate insulator are applied to the top surface of the semiconductor body, which may therefore be planar.

[0040] In accordance with at least one embodiment, the gate insulator has a non-uniform gate dielectric constant profile along the channel region such that the dielectric constant of the gate insulator is lowest in a first portion of the channel region away from the source region.

[0041] According to at least one embodiment, there is a non-uniform thickness profile, as well as a non-uniform channel doping profile and / or a non-uniform gate electrode work function profile and / or a non-uniform gate dielectric constant profile, i.e., the non-uniform gate insulator thickness profile can be combined with a non-uniform channel doping profile, a non-uniform gate electrode work function profile, or a non-uniform gate dielectric constant profile, or with two of the non-uniform channel doping profile, the non-uniform gate electrode work function profile, and the non-uniform gate dielectric constant profile, or with all three other non-uniform profiles.

[0042] According to at least one embodiment, the power semiconductor device has a collector-emitter saturation voltage V ce-sat , thus configuring both saturation current and short circuit current to be reduced while on-state losses can remain unaffected. This is true if true due to a non-uniform workfunction profile, optionally supported by at least one of a non-uniform thickness profile and a non-uniform channel doping profile, and compared to a similarly set up reference semiconductor device having a uniform gate electrode workfunction profile along the gate insulator.

[0043] There is further provided a method for manufacturing a power semiconductor device, by which a power semiconductor device is manufactured as shown in relation to at least one of the above-described embodiments, and therefore features of the power semiconductor device are also disclosed for the method and vice versa.

[0044] In at least one embodiment, a method for manufacturing a power semiconductor device includes the following steps, specifically in the order listed: providing a semiconductor substrate; - epitaxially growing at least one semiconductor layer on a semiconductor substrate;

[0045] For example, the semiconductor substrate comprises at least a portion of the drift region. For example, at least one epitaxially grown semiconductor layer comprises a well region and a source region.

[0046] The power semiconductor device and the manufacturing method are described in more detail below by way of exemplary embodiments with reference to the drawings. The same elements in the individual figures are indicated by the same reference numerals. However, the relationship between the elements is not shown to scale, rather the individual elements may be shown exaggerated in size to facilitate understanding. [Brief description of the drawings]

[0047] [Figure 1] 2 is a schematic cross-sectional view of a reference semiconductor device; [Diagram 2] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Diagram 3] FIG. 3 is a top view of the power semiconductor device of FIG. 2. [Figure 4] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Diagram 5] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 6] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 7] FIG. 2 is a schematic diagram of electrical data for a power semiconductor device and a reference semiconductor device described herein. [Figure 8]1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 9] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 10] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 11] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 12] FIG. 2 is a schematic diagram of a non-uniform doping profile and a non-uniform work function profile of a power semiconductor device described herein. [Figure 13] FIG. 2 is a schematic diagram of a non-uniform doping profile and a non-uniform work function profile of a power semiconductor device described herein. [Figure 14] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 15] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 16] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] 1 shows a reference semiconductor device 9 that corresponds to the exemplary embodiment of the power semiconductor device 1 described herein, except for the gate electrode work function profile in a channel region 220 contained in a well region 22. Like the power semiconductor device 1, the reference semiconductor device 9 comprises a semiconductor body 2, e.g. made of Si.

[0049] The semiconductor body 2 also comprises a source region 21 at a top surface 20 of the semiconductor body 2. A trench penetrates both the well region 22 and the source region 21. The source region 21 is of a first conductivity type, such as n-conductivity, and the well region 22, and therefore the channel region 220 contained by the well region 22, is of a second, different conductivity type, such as p-conductivity. Within the trench is a gate electrode 31 separated from the semiconductor body 2 by an electrically insulating gate insulator 4. The trench, and therefore the gate electrode 31, terminates in a drift region 23 of the semiconductor body 2. The drift region 23 is also of the first conductivity type.

[0050] In the reference semiconductor device 9, the gate electrode 31 has a constant work function Φ m That is, there is a uniform work function profile along the length direction x of the channel region 220 away from the source region 21 towards the drift region 23.

[0051] For example, x=0 where the source region 21 and the channel region 220 directly contact adjacent to the gate insulator 4. For example, x=L where the channel region 220 and the drift region 23 directly contact adjacent to the gate insulator 4, where L corresponds to the channel length of the channel region 220. It should be noted that the shape of the channel region 220 is only very roughly drawn.

[0052] For example, x extends perpendicular to the top surface 20 of the semiconductor layer body 2. The length L may therefore correspond to the distance between the source region 21 directly at the gate insulator 4 and the drift region 23. The length L may therefore be defined as the length of the layers of the first conductivity type, i.e. the layers of the second conductivity type between the source region 21 and the drift region 23, which may include enhanced layers of high doping concentration and layers of low doping concentration, not shown. x may be taken as the current direction in the intended use of the reference semiconductor device 9.

[0053] 2 and 3, the gate electrode 31 includes a first material 81 and a second material 82. Along a length direction x, the first material 81 directly follows the second material 82. As a result, the gate electrode 31 has a non-uniform work function profile along the channel region 220.

[0054] Since the semiconductor power device 1 described in Figures 2 and 3 is an n-channel device, i.e. a device with p-doped well regions, the work function of the first material 81 is higher than that of the second material 82, and correspondingly, for a p-channel device with n-doped well regions, the work function of the first material 81 should be lower than that of the second material 82. Thus, in the first section 61, away from the source region 21, there is a minimum in the non-uniform work function profile. The remainder of the channel region 220 is referred to as the second section 64. Within the first section 61 and the second section 64, respectively, the work functions Φ m is constant. Thus, along the channel region 220, the gate electrode 31 may be composed of a second section 64 and a first section 61 having a second material 82 and a first material 81, respectively. In a direction perpendicular to the length direction x, the gate electrode 31 may include only one material, i.e., either the first material 81 or the second material 82.

[0055] For example, the first material 81 has a work function of about 5.22 eV. + For example, the second material 82 is doped polysilicon having a work function of about 4.1 eV. + The first material 81 and the second material 82 are doped polysilicon. Although based on silicon, these first material 81 and second material 82 are sometimes called metals.

[0056] Optionally, there may be at least one plug 25 in the top surface 20 of the semiconductor body 2 to electrically contact the channel region 220. The plug 25 may have a different thickness than the well region 22 such that the plug 25 may extend deeper or shallower into the semiconductor body 2 than the well region 22. Furthermore, the thicknesses of the source region 21 and the plug 25 may be the same or different.

[0057] Both the source region 21 and the at least one plug 25 may be electrically connected, for example, by at least one source electrode 32 located on the top surface 20. Illustratively, the plug 25 has a higher maximum doping concentration than the well region 22 or the channel region 220. The depth of the plug may be lower, deeper, or the same as the depth of the well region 22 and the channel region 220.

[0058] For example, the power semiconductor device 1 is an insulated gate bipolar transistor, IGBT for short. Thus, on the side of the drift region 23 remote from the well region 22, there is also a collector region 26 of the second conductivity type. In the collector region 26, a collector electrode 34 is present. Furthermore, there may be a buffer region of the first conductivity type between the drift region 23 and the collector region 26. The doping concentration of the buffer region may be higher than the doping concentration of the drift region 23.

[0059] For example, the semiconductor body 2 is at least partially produced by epitaxial growth, i.e. the doping concentration of the respective layers of the semiconductor body 2 may be generated during growth and not after growth, for example by ion implantation. This applies, for example, at least to the enhancement layer 27 and to the well region 22, which may thus be doped by epitaxial growth. Optionally, the drift region 23 may be partly or completely part of the growth substrate. The same applies to all other examples.

[0060] When viewed in top view on the top surface 20, the trench housing the gate electrode 31 and the gate insulator 4 may be elongated. The source region 21, the at least one plug 25, and the channel region 220 may be symmetrically disposed on either side of the trench, see FIG.

[0061] For example, instead of the source region 21, the collector region 26 or the drain region 24, and at least one plug 25 has a maximum doping concentration of at least 1×10 18 cm -3 Or at least 5×10 18 cm -3 Or at least 1×10 19 cm -3 and / or at most 5 × 10 20 cm -3 Or at most 2×10 20 cm -3 Or at most 1×10 20 cm -3 Furthermore, the maximum doping concentration of the well region 22, and therefore the channel region 220, is at least 5×10 16 cm -3 Or at least 1×10 17 cm -3 and / or at most 5 × 10 19 cm -3 Or at most 5 x 10 18 cm -3 For example, the maximum doping concentration of the enhancement layer 27 can be at least 10 15 cm -3 and / or at most 10 18 cm -3 It is.

[0062] Depending on the voltage class of the power semiconductor device 1, the maximum doping concentration of the drift region 23 is at least 1×10 11 cm -3 Or at least 1×10 12 cm -3 Or at least 1×10 13 cm -3 and / or at most 1 × 1017 cm -3 Or at most 5 x 10 16 cm -3 Or at most 1×10 16 cm -3 It could be.

[0063] 2 and 3, the source region 21 and the at least one plug 25 are arranged along only one side of the gate electrode 31, so that the channel region 220 is present only along one outer side 42 of the gate insulator 4. However, the source region 21 as well as the at least one plug 25 can also be arranged along two sides of the gate electrode 31, or all around the gate electrode 31 when viewed from a top view, as compared to, for example, FIG.

[0064] If not, the same may be true for Figures 2 and 3 as for Figure 1 . The concept behind the gate electrode 31 having a non-uniform workfunction profile is explained in some detail below.

[0065] For power semiconductor device 1, illustratively for low frequency applications, it may be desirable to have as low an on-state loss as possible in order to minimize total electrical losses. Furthermore, from a device reliability standpoint, it may be advantageous to have a low short circuit current. Thus, a power semiconductor device 1 with minimized on-state losses and improved short circuit capability may be desired.

[0066] However, for example, decreasing the channel length L or increasing the channel width W can reduce the on-state voltage drop V ce-sat Several means of reducing the output characteristic I c Against V ce As shown diagrammatically using the undesirable higher saturation current I sat See Figure 4. High I sat is a high short circuit current I scThis directly relates to the short circuit capability of the power semiconductor device 1 and adversely affects the short circuit capability of the power semiconductor device 1. On the other hand, the I sat In order to reduce the threshold voltage V th As shown in Figure 5, increasing V ce-sat Therefore, Figures 4 and 5 are schematic diagrams of typical output characteristics of an IGBT with a uniform threshold profile along the entire channel region. th and different channel resistances. In Fig. 5, different threshold voltages V th This is the case.

[0067] a) Increasing the channel length L; b) Reducing the anode injection efficiency by reducing the anode implant dose; c) reducing the channel width by reducing the source coverage along the trench; and d) Reducing the channel width by increasing the cell pitch Other techniques for reducing the short circuit current, such as d), also undesirably result in higher on-state losses. Moreover, techniques such as d) may also adversely affect the breakdown capability of the power semiconductor device 1. Reducing the gate bias to reduce the short circuit current may also lead to unstable dynamic behavior and may be undesirable, as it is primarily dictated by the application requirements.

[0068] Thus, in conventional MISFET or IGBT devices, there is a trade-off between minimizing on-state losses and reducing short-circuit current. For applications requiring improved short-circuit capability, V ce-sat Without affecting the short circuit current I sc It may be desirable to be able to reduce

[0069] In the power semiconductor device 1 described herein, the tradeoff between on-state losses and short circuit current is improved by improving the latter without adversely affecting the former. Unlike other approaches, the described design provides a ce-sat The semiconductor laser features a non-uniform threshold voltage profile along the channel region 220 adjacent the gate insulator 4 to reduce the saturation current for the gate insulator 4 .

[0070] The non-uniform V th is realized by implementing a non-uniform work function profile 6 of the gate electrode 31 along the channel region 220. In addition, the described concept is applicable to generally any MOS device such as power MOSFETs or IGBTs or reverse conducting IGBTs and is even compatible with both planar and trench architectures.

[0071] The power semiconductor device 1 described herein introduces improved MISFET, MOSFET or IGBT devices with improved short circuit capability without detrimentally affecting on-state losses. The improved design also relaxes the design constraints of the IGBT, allowing the possibility to independently explore other methods mentioned above to minimize on-state losses that are typically limited by the short circuit capability of the respective device.

[0072] In the following, some theoretical background to the conception of the semiconductor device 1 described herein is presented.

[0073] For standard long channel MOS devices, high V ce It is known that the channel pinch-off at V causes current saturation in the output characteristic, which ultimately determines the short circuit current. pinch-off is the threshold voltage V th Exemplarily, the applied bias V ce is the pinch-off voltage V pinch-off ≒(V g -V th), the channel begins to pinch off near its drain end at x=L, where V g is the applied gate voltage and L is the channel length. ce The voltage drop perpendicular to the channel is V th It is smaller and therefore the channel can no longer persist near the drain end.

[0074] However, for a more detailed understanding of the device, channel pinch-off should be considered as a rather local phenomenon, occurring specifically near the drain end of the channel. More precisely, it is the local threshold voltage V that determines the pinch-off point, and hence the saturation current. th (x). This is because in the first section 61 near the channel end, i.e., the drift region 23, V th By locally increasing (L), V pinch-off This means that it is possible to reduce

[0075] Additionally, it preserves the overall channel resistance, thereby reducing V ce-sat To avoid affecting V th (x) can be reduced.

[0076] This is because the curve pointing to the reference semiconductor device 9 shows a uniform threshold voltage V along the entire channel. th-1 6 including the profile. On the other hand, the curve for the power semiconductor device 1 shows a non-uniform V along the channel. th It consists of a profile, V th is V to lower the pinch-off point. th-2 (L)>V th-1 and in the remainder of the channel, V is increased to keep the overall channel resistance the same. th-2 ' <V th-1In this way, the saturation current, and therefore the short circuit current, can be significantly reduced without affecting the on-state losses, as shown in the schematic output of Figure 7. th Variation holds the key to improving the short circuit capability of MISFET or MOSFET or IGBT devices.

[0077] Channel V th is a function of various other MOS cell design parameters as shown in the following equation:

[0078]

number

[0079] Here, V th is the threshold voltage, V fb is the flat band voltage, V fb =(Φ m -Φ s ), where Φ m and Φ s are the gate electrode work function and the semiconductor work function, respectively. N A is the doping of the channel body, and ε s is the dielectric constant of the semiconductor, and C ox is the gate insulator capacitance, and φ B is the semiconductor surface potential,

[0080]

number

[0081] where k is the Boltzmann constant, T is the temperature, and n i is the intrinsic carrier concentration of the semiconductor.

[0082] Therefore, the relatively high V th The non-uniform V required across the channel thThe profile can be achieved by introducing non-uniformity in one or any combination of the following MOS design parameters:

[0083] 1. Channel doping profile as detailed herein, N A (x), 2. Gate oxide thickness, Tox(x), 3. Gate dielectric constant, ε ox (y), and / or 4.V fb =(Φ m -Φ s ), so the gate metal work function φ m (x).

[0084] In the following, we focus on changing the gate electrode work function profile, however, said work function change can of course be combined with a varying gate insulator thickness, a varying gate dielectric constant, and / or a varying channel doping concentration.

[0085] Φ m Note that more than one combination of (x) can achieve the same goal. Moreover, higher Φ m (x) area and lower Φ m Even the physical length of the (x) region, ie, the length of the first section 61 along the length direction x, can be tailored to overcome manufacturing challenges.

[0086] Therefore, V along the channel region 220 th The profile non-uniformity can be achieved, for example, by introducing gate electrode materials with different work functions, as shown diagrammatically in FIG. m is the flat band voltage V fb =(Φ m -Φ s ) through V th Therefore, Φ m Any change in V th directly results in a corresponding change in

[0087] According to Fig. 8, as in Fig. 2, a step is also present in the non-uniform work function profile, but the first material 81 and the second material 82 do not have a planar interface perpendicular to the length direction x. Instead, the interface may have a spherical or meniscus-like shape. Thus, a transition section 62 is formed.

[0088] Compared to the total channel length L, the length of the transition section 62 along the length direction x is small, for example at most 2% or at most 5% of the total channel length L. The same may apply to all other exemplary embodiments.

[0089] Thus, there is a step in the non-uniform work function profile at the interface between the first section 61 and the second section 64. However, the step does not have to strictly follow a theta function or a unit step function, but can be sinusoidal due to the transition section 62.

[0090] Such a transition section 62 or multiple such transition sections may in all other exemplary embodiments also be present at an interface between different materials of the gate electrode 31. For example, at least one such transition section 62 may result from the manufacturing process of the gate electrode 31.

[0091] 8, at the top surface 20, the well region 22 may extend between the plug 25 and the assigned source region 21. When viewed in cross section, the plug 25 and the assigned source region 21 may have different shapes and / or depths. These design features may be present individually or in combination in all other exemplary embodiments as well.

[0092] If this is not the case, the same may be true for FIG. 8 as for FIG. 2-FIG. 7, and vice versa.

[0093] In the power semiconductor device 1 of Fig. 9, a first material 81 as well as a second material 82 are present in the first section 61, where the first material 81 is located next to the gate insulator 4 and the second material 82 is distant from the gate insulator 4. Thus, perpendicular to the length direction x, both materials 81, 82 are present. Since the second material 82 is confined inside the gate electrode 31, the work function Φ m is determined solely by the first material 81. Thus, when viewed in a cross section perpendicular to the top surface 20, the first material 81 may be U-shaped in the first section 61. In the second section 64, the lower work function Φ m Therefore, perpendicular to the length direction x, in the first section 220, the gate electrode 31 may be considered to be of multi-layer type.

[0094] As is possible in all other exemplary embodiments of the power semiconductor device 1 , the outer side of the gate insulator 4 facing the semiconductor body 2 may be planar at least along the channel region 220 .

[0095] Moreover, in Fig. 9 it is shown that the trench in which the gate electrode 31 and the gate insulator 4 are located does not necessarily have a curved bottom surface facing the drain region 23. Said bottom surface may therefore be planar and parallel to the top surface 20. The same is possible in all other exemplary embodiments.

[0096] If this is not the case, the same may be true for FIG. 9 as for FIG. 2-FIG. 8, and vice versa.

[0097] 10, the gate electrode 31 includes a third material 83 located between the second material 82 and the first material 81 when viewed along the length direction x. For example, if the power semiconductor device 1 is a device having a p-doped well region, the work function Φ m is the work function Φ of the second material 82 m However, the work function Φ of the first material 81 ism and if the power semiconductor device 1 is a device having an n-doped well region, the work function Φ of the third material 83 is m is the work function Φ of the second material 82 m but lower than the work function Φ of the first material 81 m Higher than.

[0098] For example, all materials 81, 82, 83 are based on polysilicon with different dopings. Otherwise, for example, the third material is a metal with a high work function Φ such as Pt. m The metal may have the following structure:

[0099] There may be transition sections not shown between the materials 81, 82, 83 as in Fig. 8. Furthermore, in the middle section 63 and / or in the first section 61, the gate electrode 31 may also be of multi-layer type as in Fig. 9.

[0100] If this is not the case, the same may be true for FIG. 10 as for FIG. 2-FIG. 9, and vice versa.

[0101] Work function difference ΔΦ of 2.5eV to 3.0eV depending on specific requirements m ΔV corresponding to th =V th2 -V th1 This is because n + 4.1eV to p for doped polysilicon + Readily available practical work functions Φ ranging up to about 5.22 eV for doped polysilicon m Therefore, using available materials for the gate electrode 31, it may be difficult to realize ΔV th ≈1 V can be obtained, which should result in some improved short circuit current vs. on-state tradeoff compared to a single work function gate electrode as in Figure 1. Moreover, different metals can be considered as gate electrode materials to obtain higher work function contrast to achieve the required objective.

[0102] For even better results, a non-uniform work function profile can be used to overcome non-uniform V such as a non-uniform doping profile or a non-uniform gate oxide thickness profile. th It can be combined with other proposed techniques to achieve a profile. For example, the required ΔV th can be achieved with the following combinations of gate insulator thickness variation in the first section 61 and second section 82, channel doping, and gate metal work function as shown in the following figures:

[0103] 11 shows that not only the work function profile is of non-uniform design, but also the thickness profile of the gate insulator 4. The gate insulator 4 is therefore thickest in a first section 61, remote from the source region 21. The thickness of the gate insulator 4 may therefore vary in a step manner.

[0104] The non-uniform work function profile may also be stepped, with the materials 81, 82 of the gate electrode 31 varying at the same position along the length direction x as the thickness of the gate insulator 4. For example, the thickness of the gate insulator 4 may vary only at the interface between the first material 81 and the second material 82.

[0105] Optionally, the thickness of the gate insulator 4 in the second section 64 is ≧50 nm and ≦100 nm and / or the thickness of the gate insulator 4 in the first section 61 is ≧100 nm and ≦240 nm.

[0106] For example, the work function of the second material 82 is 4.1 eV and the work function of the first material 82 is 5.22 eV. th To achieve ≈2.5-3V, the gate insulator 4 may have a thickness of 100 nm in the second section 64 and 170 nm in the first section 61 .

[0107] In Fig. 11, the gate electrode 31 is configured similarly to Fig. 2. However, in the power semiconductor device 1 of Fig. 11, the gate electrode 31 may alternatively be designed as shown in any one of Figs. 8 to 10 and 14.

[0108] If this is not the case, the same may be true for FIG. 11 as for FIG. 2-FIG. 10, and vice versa.

[0109] 12 and 13, it is shown that along the length direction x, both a non-uniform work function profile 6 and a non-uniform channel doping profile 7 are applied. Thus, along the length direction x, the doping concentration N A As in the case of the power semiconductor device 1 described above, only the channel region 220 is of interest here, and as a result, the doping concentration N A 12 and 13. Therefore, the non-uniform work function profile 6 and also the non-uniform thickness profile are considered only along the channel region 220, i.e., only for x=0 to x=L.

[0110] According to FIG. 12, both the work function profile 6 and the channel doping profile 7 are designed to be step-like, and the step is x=x S However, for example, the steps in the work function profile 6 may follow a theta function or a unit step function, and the channel doping profile 7 may have a transition section 62. Within the second section 64 and the first section 61, respectively, the doping concentration N A may be a constant.

[0111] For example, the maximum doping concentration present in the channel doping profile 7 is at least 5×10 16 cm -3 and at most 3 × 10 18 cm -3and / or the minimum doping concentration present in the channel doping profile 7 is at most 2×10 17 cm -3 Or at most 1×10 17 cm -3 The maximum doping concentration may be present in the first section 61 and the minimum doping concentration may be present in the second section 64.

[0112] As an example, the work function of the second material 82 is 4.1 eV and the work function of the first material 82 is 5.22 eV. th To achieve ≈2.5 to 3 V, the doping concentration N A is 1×10 17 cm -3 and the doping concentration N A is 2.8 x 10 17 cm -3 It is.

[0113] 13, the channel doping profile 7 is linear. Therefore, no clearly defined interface or dividing line between the first section 61 and the second section 64 is required in the channel doping profile 7. Optionally, the work function profile 6 may have multiple steps such that a linear work function increase is approximated.

[0114] In the power semiconductor device 1 of Figures 12 and 13, there may of course also be a non-uniform thickness profile of the gate insulator 4, as in Figure 11. The thickness profile of the gate insulator 4 can also be linear, as in the channel doping profile 7 of Figure 13. Moreover, different shapes of non-uniform thickness profiles, non-uniform work function profiles and non-uniform channel doping profiles can be combined with each other.

[0115] If this is not the case, the same may be true for Figures 12 and 13 with respect to Figures 2-11, and vice versa.

[0116] In Fig. 14 it is shown that there is a non-uniform thickness profile of the gate insulator 4 as well as a non-uniform work function profile, both profiles being configured in a step-like manner. However, the steps in the profile are at different positions along the length direction x. The same is possible in all other exemplary embodiments. As an option not shown, there may also be a non-uniform channel doping profile in the channel region 220, configured as shown in Fig. 12 or Fig. 13, for example.

[0117] Moreover, the power semiconductor device 1 in Fig. 14 is shown to be a MISFET or MOSFET, rather than an IGBT. As a result, the power semiconductor device 1 comprises a drain region 24 instead of a collector region 26. Thus, on the side of the drift region 23 remote from the well region 22, there is also a drain region 24 which is of the first conductivity type but has, for example, a higher maximum doping concentration than the drift region 23. In the drain region 24, a drain electrode 33 is present.

[0118] Of course, all gate insulator designs for IGBT power semiconductor devices 1 can be applied to MOSFET and MISFET power semiconductor devices 1, and vice versa.

[0119] If this is not the case, the same may be true for FIG. 14 as for FIGS. 2-13, and vice versa.

[0120] According to Fig. 15, the power semiconductor device 1 has a planar design, and not a trench design, as for example the power semiconductor device 1 of Fig. 2 and Fig. 3. Thus, the top surface 20 is planar, and the gate insulator 4 and the gate electrode 31 are applied to the top surface 20. As a result, the length direction x runs parallel to the top surface 20 from the source region 21 to the drift region 23, unlike the other exemplary embodiments which are perpendicular to the top surface 20.

[0121] 15, the well regions 22 protrude laterally, i.e. parallel to the top surface 20, from the source regions 21 and extend below the gate insulator 4. The source regions 21 may also extend below the gate insulator 4, but to a lesser extent.

[0122] All of the above described different designs of non-uniform work function profile and optional non-uniform channel doping profile and / or non-uniform thickness profile can be applied to the planar concept of Fig. 15 for MISFET or MOSFET as well as IGBT. Thus, the same may be applied to Fig. 15 with respect to Figs. 2-13.

[0123] 16 shows that there is a non-uniform gate electrode work function profile 6 of the gate insulator 4 due to the optionally present at least two different materials 71, 72 of which the gate insulator 4 is composed, as well as a non-uniform gate insulator thickness profile and a non-uniform gate dielectric constant profile, i.e. the thickness of the gate insulator 4 varies along the channel region 220.

[0124] For example, the difference in dielectric constant along the channel region 220 due to the at least two different materials 71, 72 is at least 2.0, or at least 3.0, or at least 3.5. Alternatively or additionally, said difference is at most 50, or at most 25. When comparing the respective dielectric constants, textbook values ​​of the respective materials at room temperature, i.e. 300K, and at a frequency of the alternating electric field of at most 1 kHz may be used.

[0125] For example, the thickness of the first material 71 in the first section 61 exceeds the thickness of the second material 72 in the second section 64, and vice versa. For example, the thickness difference between the first material 71 and the second material 72 is at least 20% or at least 40% of the maximum thickness of the gate insulator 4 along the channel region 220. When only a non-uniform gate insulator thickness profile and a uniform gate dielectric constant profile are present, the gate insulator 4 may be made of a single material.

[0126] For example, the thickness of the gate insulator 4 in the second section 64 is 50 nm to 100 nm, and / or the thickness of the gate insulator 4 in the first section 61 is 100 nm to 240 nm. However, other than as shown in FIG. 16 , the thickness of the gate insulator 4 in the first section 61 may alternatively be smaller than in the second section 64, and the maximum thickness may be in the second section 64 instead.

[0127] Thus, there is a step in the non-uniform gate dielectric profile at the interface between the first section 61 and the second section 64, see the inset of FIG.

[0128] In addition to or instead of a non-uniform gate dielectric constant profile and / or a non-uniform gate electrode work function profile 72, there may be a non-uniform channel doping profile 71. That is, the doping concentration N A varies along the channel region 220.

[0129] For example, the maximum doping concentration present in the non-uniform channel doping profile 7 is at least 5×10 16 cm -3 and at most 5 × 10 19 cm -3 and / or the minimum doping concentration present in the non-uniform channel doping profile 71 is at most 2×10 17 cm -3 Or at most 1×1017 cm -3 The maximum doping concentration may be present in the first section 61 and the minimum doping concentration may be present in the second section 64. The doping concentration N A For example, the doping concentration N A However, the doping concentration N A The steps in do not have to follow exactly a theta function or a unit step function, but there can be sinusoidal steps, see the inset in Figure 16. The steps can be at the locations where the material 71, 72 of the gate insulator 4 changes.

[0130] Such at least one of a non-uniform gate insulator thickness profile, a non-uniform gate insulator dielectric constant profile, and a non-uniform channel doping profile 7 may also be present in all other exemplary embodiments analogously.

[0131] If this is not the case, the same may be true for FIG. 16 as for FIG. 2-FIG. 15, and vice versa.

[0132] Components depicted in the figures exemplarily follow one another directly in the specified order, unless otherwise indicated. Components that are not in contact in the figures are exemplarily spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of depicted components relative to one another are accurately reproduced in the drawings.

[0133] The power semiconductor device described herein is not limited by the description based on the exemplary embodiments, but rather includes any novel feature and any combination of features, including any combination of features in the claims, even if this feature or this combination itself is not explicitly specified in the claims or exemplary embodiments.

[0134] This patent application claims priority to European Patent Application No. 21186101.8, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0135] List of References 1. Power semiconductor devices 2. Semiconductor body 20 Top side 21 Source Area 22 Channel Area 23 Drift Region 24 Drain Region 25 Plug 26 Collector Region 27 Reinforcement layer 31 Gate electrode 32 Source electrode 33 Drain electrode 34 Collector electrode 4 Gate insulator 6. Non-uniform work function profile 61 First Section 62 Transition Section 63 Mid Section 64 Second Section 7. Non-uniform channel doping profile 71 First material of gate insulator 72 Second material for gate insulator 81 First Ingredient 82 Second Ingredient 83 The third ingredient 9 Reference Semiconductor Device L is the length of the channel region along the gate insulator x lengthwise along the channel region

Claims

1. - A semiconductor body (2) having a source region (21) of a first conductivity type and a well region (22) of a second conductivity type different from the first conductivity type, wherein the well region (22) includes a channel region (220) starting directly from the source region (21), the first conductivity type is n-conductivity, and the second conductivity type is p-conductivity, the semiconductor body (2); - A gate insulator (4) directly between the semiconductor body (2) and the gate electrode (31); A power semiconductor device (1) comprising: - The gate electrode (31) is partially or completely disposed within a trench formed in the semiconductor body; - The semiconductor body (2) further includes a drift region (23) of the first conductivity type, the drift region (23) is in direct contact with the gate insulator (4), is directly adjacent to the channel region (220), and the trench terminates within the drift region (23); - The threshold voltage (V ｔｈ ) and work function Φ ｍ of the gate electrode (31) are such that they are maximized in the first section (61) of the channel region (220) away from the source region (21), and the gate electrode (31) has a non-uniform work function profile (6) along the channel region (220). A power semiconductor device (1).

2. The semiconductor body (2) further includes a strengthening layer (27) of the first conductivity type directly adjacent to the side of the well region (22) away from the source region (21); Among the following: - Along the channel region (220), the gate insulator (4) has a non-uniform thickness profile along the channel region (220) such that the gate insulator (4) is thickest in the first section (61); - the doping concentration N in the channel region (220) Ａ the channel region (220) has a non-uniform channel doping profile along the gate insulator (4) such that the doping concentration N in the channel region (220) is maximized in the first section (61), or - Along the channel region (220), the gate insulator (4) has a non-uniform gate dielectric constant profile such that the relative dielectric constant of the gate insulator (4) is lowest in the first section (61) of the channel region (220) away from the source region (21); At least one of the above is true; The power semiconductor device (1) according to Claim 1.

3. The work function difference of the gate electrode (31) along the channel region (220) is at least 1.0 eV; The power semiconductor device (1) according to Claim 1 or 2.

4. The gate electrode (31) includes a first material (81) in the first section (61) and a second material (82) in a second section (64) adjacent to the source region (21); When the channel region (220) is p-type doped, the first material (81) has a higher work function Φ than the second material (82). ｍ When the channel region (22) is an n-type doped region, the first material (81) has a lower work function Φ than the second material (82). ｍ The power semiconductor device (1) according to claim 1 or 2, having such characteristics.

5. The first material (81) is p-doped polysilicon and the second material (82) is n-doped polysilicon. The power semiconductor device (1) according to claim 4.

6. Perpendicular to the length direction (x) of the channel region (220), the gate electrode (31) includes either the first material (81) or the second material (82). The power semiconductor device (1) according to claim 4.

7. Perpendicular to the length direction (x) of the channel region (220), within at least the first section (61), the gate electrode (31) includes the first material (81) and the second material (82). The power semiconductor device (1) according to claim 4.

8. The length of the first section (61) is at least 10% and at most 40% of the total length (L) of the channel region (220) along the gate insulator (4). The power semiconductor device (1) according to claim 1 or 2.

9. Along the channel region (220), the minimum thickness of the gate insulator (4) is at most 70% of the maximum thickness of the gate insulator (4). The power semiconductor device (1) according to claim 8.

10. Along the gate insulator (4), the minimum doping concentration of the channel region (220) is at most 50% of the maximum doping concentration of the channel region (220). The power semiconductor device (1) according to claim 1 or 2.

11. At least one of the non-uniform thickness profile and the non-uniform channel doping profile extends continuously without steps. The power semiconductor device (1) according to claim 1 or 2.

12. The non-uniform work function profile (6), and at least one of the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform gate dielectric constant profile has at least one step. The step in the non-uniform work function profile (6), and the step in at least one of the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform gate dielectric constant profile are arranged at the same position along the channel region (220). The power semiconductor device (1) according to claim 2.

13. ​ the non-uniform work function profile (6), and at least one of the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform gate dielectric constant profile has at least one step, the step in the non-uniform work function profile (6), and the step in at least one of the non-uniform thickness profile, the non-uniform channel doping profile, and the non-uniform gate dielectric constant profile are arranged at different positions along the channel region (220), The power semiconductor device (1) according to claim 2.

14. at least two of the non-uniform work function profile (6), the non-uniform thickness profile, the non-uniform channel doping profile, or the non-uniform gate dielectric constant profile are linear, The power semiconductor device (1) according to claim 11.

15. at least one of the non-uniform work function profile (6), and the non-uniform thickness profile, the non-uniform channel doping profile, or the non-uniform gate dielectric constant profile extends in a different shape, The power semiconductor device (1) according to claim 1 or 2.

16. - the source region (21) is in direct contact with the gate insulator (4) and the channel region (220), - the power semiconductor device (1) is a metal-insulator-semiconductor field effect transistor, MISFET, metal-oxide-semiconductor field effect transistor, MOSFET, insulated gate bipolar transistor, IGBT, or reverse conducting insulated gate bipolar transistor, RC-IGBT, The power semiconductor device (1) according to claim 1 or 2.

17. A method for manufacturing the power semiconductor device (1) according to claim 1 or 2, comprising: - providing a semiconductor substrate; - epitaxially growing at least one semiconductor layer on the semiconductor substrate A method.

18. the power semiconductor device (1) according to claim 16 is manufactured, the semiconductor substrate includes at least a part of the drift region (23), the at least one epitaxially grown semiconductor layer includes the well region (22) and the source region (21), The method according to claim 17.

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