Display substrate and its manufacturing method, display device

Abstract

A display substrate and its manufacturing method, and a display device, the display substrate includes a plurality of display units, the display unit includes a display area and a transparent area, the display area includes a first power supply line and a second power supply line in a first direction, a first scanning signal line, a second scanning signal line, a second scanning connection line, and a first scanning connection line in a second direction, the second scanning connection line and the second scanning signal line are connected to form a first ring structure, the display area further includes a third scanning connection line, and the third scanning connection line, the first scanning connection line, and the first scanning signal line are connected to form a second ring structure, orthogonal projections of the first ring structure, the first power supply line, and the second power supply line on a base substrate do not overlap, and orthogonal projections of the second ring structure, the first power supply line, and the second power supply line on the base substrate do not overlap.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to a Chinese patent application filed with the CNIPA on June 30, 2021, bearing application number 202121504315.1, and to a Chinese patent application filed with the CNIPA on August 17, 2021, bearing application number 2021109448352, the contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0003] Organic Light Emitting Diode (OLED) is an active light-emitting display device, which has advantages such as light emission, ultra-thinness, wide viewing angle, high brightness, high contrast, low power consumption, and extremely fast response speed. According to the driving method, OLED can be divided into two types: Passive Matrix (PM) type and Active Matrix (AM) type, where AMOLED is a current driver that uses an independent thin film transistor (TFT) to control each sub-pixel, and each sub-pixel can be driven to emit light continuously and independently.

[0004] With the development of display technology, OLED technology is increasingly applied to transparent display. Transparent display is an important personalized display field in display technology, which refers to displaying images in a transparent state, allowing viewers to not only see the image inside the display device, but also the scene behind the display device, realizing virtual reality (abbreviated as VR), augmented reality (abbreviated as AR) and 3D display functions. In transparent display devices using AMOLED technology, each pixel is usually divided into a display area and a transparent area, and pixel driving circuits and light emitting elements are provided in the display area to realize image display, and light transmission is realized in the transparent area. Summary of the Invention [Means for solving the problem]

[0005] The following is a brief overview of the subject matter described in detail in the text, which is not intended to limit the scope of protection of the claims.

[0006] An embodiment of the present disclosure provides a display substrate, comprising: a base substrate; and a plurality of display units disposed on the base substrate, the display units having a display region and a transparent region, the display region having a plurality of sub-pixels, the display region being provided with a first power line and a second power line in a first direction, the first power line and the second power line extending in a second direction, the display region being provided with a first scanning signal line, a second scanning signal line, a second scanning connection line, and a first scanning connection line in the second direction, the second scanning connection line and the second scanning signal line being connected to each other to form a first ring structure. in the display area, a third scanning connection line is provided between the first scanning signal line and the first scanning connection line, the third scanning connection line, the first scanning connection line, and the first scanning signal line are connected to each other to form a second ring structure, the first direction and the second direction intersect, an orthogonal projection of the first ring structure on the base substrate does not overlap with an orthogonal projection of the first power supply line and the second power supply line on the base substrate, and an orthogonal projection of the second ring structure on the base substrate does not overlap with an orthogonal projection of the first power supply line and the second power supply line on the base substrate.

[0007] In an exemplary embodiment, the orthogonal projection of the first ring structure on the base substrate does not overlap with the orthogonal projection of the second ring structure on the base substrate, and the orthogonal projection of the second ring structure on the base substrate envelops the orthogonal projection of the first ring structure on the base substrate.

[0008] In an exemplary embodiment, in a direction perpendicular to the display substrate, the sub-pixel includes a driving circuit layer provided on the base substrate and a light-emitting structure layer provided on a side of the driving circuit layer away from the base substrate, the driving circuit layer includes a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer, the first conductive layer includes a compensation signal line and a first electrode plate, the semiconductor layer includes an active layer of a plurality of transistors, and the second conductive layer includes the first scanning signal line, the second scanning signal line, the first scanning connecting line, the second scanning connecting line, a second electrode plate, and the active layer of the plurality of transistors. a gate electrode, the third conductive layer comprising the first power supply line, the second power supply line, the third scanning connection line, a data signal line, and source electrodes and drain electrodes of a plurality of transistors, an overlap region exists between the orthogonal projection of the second plate on the base substrate and the orthogonal projection of the first plate on the base substrate, thereby forming a first capacitor, the second scanning connection line and the second scanning signal line are connected to each other to form an integral structure, and the third scanning connection line is electrically connected to the first scanning connection line and the first scanning signal line, respectively, via a through hole.

[0009] In an exemplary embodiment, at least one of the sub-pixels comprises a first transistor, a second transistor, a third transistor, and a first capacitor, the first capacitor having a first plate and a second plate, a gate electrode of the first transistor electrically connected to the first scanning signal line, a first pole of the first transistor electrically connected to a data signal line, a second pole of the first transistor electrically connected to a gate electrode of the second transistor, a first pole of the second transistor electrically connected to the first power supply line, a second pole of the second transistor electrically connected to a first pole of an organic electroluminescent diode, a gate electrode of the third transistor electrically connected to the second scanning signal line, a first pole of the third transistor electrically connected to a compensation signal line, a second pole of the third transistor electrically connected to the second pole of the second transistor, a second pole of the organic electroluminescent diode electrically connected to the second power supply line, the first plate electrically connected to the second pole of the second transistor, and the second plate electrically connected to the gate electrode of the second transistor.

[0010] In an exemplary embodiment, the plurality of subpixels include a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, wherein the first subpixels and the second subpixels are alternately arranged in the first direction to form a first row, the third subpixels and the fourth subpixels are alternately arranged to form a second row, the first subpixels and the third subpixels are alternately arranged in the second direction to form a first column, and the second subpixels and the fourth subpixels are alternately arranged to form a second column, the first scanning connection line and the second scanning connection line are located in the first subpixels and the second subpixels, and the first scanning signal line and the second scanning signal line are located in the third subpixels and the fourth subpixels.

[0011] In an exemplary embodiment, at least one of the sub-pixels comprises a first transistor, a second transistor, and a third transistor, the first transistor comprises a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor comprises a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, and the third transistor comprises a third active layer, a third gate electrode, a third source electrode, and a third drain electrode, and an overlapping area between the second scanning signal line and the third active layer in the third sub-pixel and the fourth sub-pixel is a region where the second scanning connection line and the third active layer in the first subpixel and the second subpixel overlap is defined as a third gate electrode in the first subpixel and the second subpixel, a region where the first scanning signal line and the first active layer in the third subpixel and the fourth subpixel overlap is defined as a first gate electrode in the third subpixel and the fourth subpixel, and a region where the first scanning connection line and the first active layer in the first subpixel and the second subpixel overlap is defined as a first gate electrode in the first subpixel and the second subpixel.

[0012] In an exemplary embodiment, at least one of the display areas further comprises a compensation signal line, the compensation signal line extending in a second direction, the first gate electrode, the second gate electrode, and the third gate electrode in the first subpixel and the second subpixel are mirror-symmetric with respect to a vertical axis, and the first gate electrode, the second gate electrode, and the third gate electrode in the third subpixel and the fourth subpixel are mirror-symmetric with respect to the vertical axis, the vertical axis being the compensation signal line.

[0013] In an exemplary embodiment, the compensation signal line is provided with a compensation connection line protruding in a first direction and a direction opposite to the first direction, the compensation connection line is located at a position where the first subpixel and the third subpixel are adjacent and at a position where the second subpixel and the fourth subpixel are adjacent, and the compensation connection line is electrically connected to a third source electrode of the third transistor via a through hole.

[0014] In an exemplary embodiment, the third active layers in the first to fourth sub-pixels are all located close to the compensation connection line, and there is an overlapping region between the orthogonal projection of the third active layer on the base substrate and the orthogonal projection of the compensation connection line on the base substrate.

[0015] In an exemplary embodiment, the third active layer in the first subpixel and the third active layer in the third subpixel are connected to each other and are an integral structure, and the third active layer in the second subpixel and the third active layer in the fourth subpixel are connected to each other and are an integral structure.

[0016] In an exemplary embodiment, at least one of the subpixels further comprises a first capacitor, the first capacitor comprising a first plate and a second plate arranged opposite each other, the second gate electrode being disposed across the second active layer and connected to the second plate to form an integral structure.

[0017] In an exemplary embodiment, a first electrode plate in the first subpixel has a first opening close to the third subpixel and away from the second subpixel, a first electrode plate in the second subpixel also has the first opening close to the fourth subpixel and away from the first subpixel, a first electrode plate in the third subpixel has a second opening close to the first subpixel and closer to the fourth subpixel, and a first electrode plate in the fourth subpixel also has the second opening close to the second subpixel and closer to the third subpixel, first active layers in the first and second subpixels are located close to the first opening, and a first active layer in the third and fourth subpixels is located close to the second opening.

[0018] In an exemplary embodiment, at least one of the subpixels further comprises a second capacitor, the second capacitor comprising a second plate and a third plate arranged opposite each other, an overlap region exists between the orthogonal projection of the third plate on the base substrate and the orthogonal projection of the second plate on the base substrate, and the third plate is electrically connected to the first plate via a through hole.

[0019] An embodiment of the present disclosure further provides a display device, comprising the above display substrate.

[0020] An embodiment of the present disclosure further provides a method for manufacturing a display substrate, forming a plurality of display units on a base substrate, the display units having a display area and a transparent area, the display area being provided with a first power line and a second power line in a first direction, the first power line and the second power line extending in a second direction, the display area being provided with a first scanning signal line, a second scanning signal line, a second scanning connecting line and a first scanning connecting line in the second direction, the second scanning connecting line and the second scanning signal line being connected to each other to form a first ring structure, the display area being provided with a first scanning signal line, a second scanning signal line, a second scanning connecting line and a first scanning connecting line in the second direction, the second scanning connecting line and the second scanning signal line being connected to each other to form a first ring structure, a third scanning connection line is provided between a first scanning signal line and the first scanning connection line, the third scanning connection line, the first scanning connection line, and the first scanning signal line are connected to each other to form a second ring structure, the first direction and the second direction intersect, an orthogonal projection of the first ring structure on the base substrate does not overlap with an orthogonal projection of the first power supply line and the second power supply line on the base substrate, and an orthogonal projection of the second ring structure on the base substrate does not overlap with an orthogonal projection of the first power supply line and the second power supply line on the base substrate.

[0021] Other aspects may be understood after reading and understanding the accompanying drawings and detailed description.

[0022] The drawings are intended to provide a better understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and are not intended to limit the technical solutions of the present disclosure. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic diagram showing the structure of a display device. [Diagram 2] FIG. 2 is a schematic diagram showing the planar structure of the display substrate. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display substrate. [Figure 4] FIG. 4 is a schematic equivalent circuit diagram of a pixel driving circuit. [Diagram 5] FIG. 5 is a structural schematic diagram of a display panel according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic equivalent circuit diagram of a pixel driving circuit in the four sub-pixels shown in FIG. [Figure 7] FIG. 7 is a schematic diagram after a first conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure. [Figure 8] FIG. 8 is a schematic cross-sectional view of the AA region in FIG. [Figure 9] FIG. 9 is a schematic diagram after a semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic cross-sectional view of the AA region in FIG. [Figure 11] FIG. 11 is a schematic diagram after a second conductive layer pattern has been formed, according to an exemplary embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic cross-sectional view of the AA region in FIG. [Figure 13] FIG. 13 is a schematic diagram after a third insulating layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic cross-sectional view of the AA region in FIG. [Figure 15] FIG. 15 is a schematic diagram after a third conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic cross-sectional view of the AA region in FIG. [Figure 17] FIG. 17 is a schematic diagram after a planar layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 18]FIG. 18 is a schematic cross-sectional view of the AA region in FIG. [Figure 19] FIG. 19 is a schematic diagram after a first transparent conductive layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 20] FIG. 20 is a schematic cross-sectional view of the AA region in FIG. [Figure 21] FIG. 21 is a schematic diagram after an anode pattern is formed, according to an exemplary embodiment of the present disclosure. [Figure 22] FIG. 22 is a schematic cross-sectional view of the AA region in FIG. [Figure 23] FIG. 23 is a schematic diagram after a first pixel defining layer pattern is formed, according to an exemplary embodiment of the present disclosure. [Figure 24] FIG. 24 is a schematic cross-sectional view of the AA region in FIG. [Diagram 25] FIG. 25 is a schematic diagram after an organic light-emitting layer pattern is formed, according to an exemplary embodiment of the present disclosure. [Figure 26] FIG. 26 is a schematic diagram after a cathode pattern is formed, according to an exemplary embodiment of the present disclosure. [Figure 27] FIG. 27 is a schematic diagram of a short circuit fault location and laser repair method of a display substrate according to an exemplary embodiment of the present disclosure. [Figure 28] FIG. 28 is a schematic diagram of another short circuit fault location and laser repair method of a display substrate according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the following will describe in detail the embodiments of the present disclosure with reference to the drawings. The embodiments may be implemented in a number of different forms. As can be easily understood by those skilled in the art, the manner and content may be converted into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments may be arbitrarily combined unless there is a conflict.

[0025] The proportions of the drawings in this disclosure may be taken as reference for the actual process, but are not limited thereto. For example, the aspect ratio of the channel, the thickness and pitch of each film layer, and the width and pitch of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of sub-pixels in each pixel are also not limited to the numbers shown in the drawings, and the drawings in this disclosure are structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0026] In this specification, ordinal numbers such as "first," "second," and "third" are set to avoid confusion of components and are not intended to be limiting in terms of quantity.

[0027] In this specification, for convenience, descriptions indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are used to describe the positional relationship of components with reference to the drawings, but this is merely for the purpose of simplifying the specification, and does not expressly or imply that the indicated devices or elements necessarily have a specific orientation, or are constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure. The positional relationship of components is appropriately changed depending on the direction in which each component is described. Therefore, there is no limitation to the terms described in the specification, and they can be appropriately replaced depending on the situation.

[0028] In this specification, unless otherwise clearly specified or limited, the terms "attached" and "connected" should be understood in a broad sense. For example, it may be fixedly connected, detachably connected, or integrally connected, it may be mechanically connected or electrically connected, it may be directly connected, or indirectly connected via an intermediate part, or it may be in communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific situation.

[0029] In this specification, a transistor refers to an element having at least three terminals, a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. However, in this specification, a channel region refers to a region through which a current mainly flows.

[0030] In this specification, the first pole may be a drain electrode and the second pole may be a source electrode, or the first pole may be a source electrode and the second pole may be a drain electrode. When using transistors with reversed polarity, or when the current direction during circuit operation is changed, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0031] In this specification, "electrical connection" includes cases where components are connected via an element having some electrical function. The "element having some electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the components being connected. Examples of the "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0032] In this specification, "parallel" refers to a state in which the angle between two lines is -10° or more and 10° or less, and therefore includes a state in which the angle is -5° or more and 5° or less. "Perpendicular" refers to a state in which the angle between two lines is 80° or more and 100° or less, and therefore includes a state in which the angle is 85° or more and 95° or less.

[0033] In this specification, the terms "film" and "layer" can be used interchangeably. For example, a "conductive layer" may be replaced with a "conductive film." Similarly, an "insulating film" may be replaced with an "insulating layer."

[0034] The shapes such as triangle, rectangle, trapezoid, pentagon, hexagon, etc. in this specification are not intended to be strict shapes, and may be approximate triangle, rectangle, trapezoid, pentagon, hexagon, etc., and may have small deformations due to tolerances, chamfers, arc edges, deformations, etc.

[0035] In this disclosure, "about" refers to not precisely limiting the limit but rather allowing for numerical values ​​within process and measurement error.

[0036] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array, the timing controllers being respectively connected to the data signal driver and the scan signal driver, the data signal drivers being respectively connected to a plurality of data signal lines (D1 to Dn), and the scan signal drivers being respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting element connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide the data signal driver with grayscale values ​​and control signals suitable for the specifications of the data signal driver, and may provide the scan signal driver with clock signals, scan start signals, etc. suitable for the specifications of the scan signal driver. The data signal driver may generate data voltages provided to the data signal lines D1, D2, D3, ..., and Dn using the grayscale values ​​and control signals received from the timing controller. For example, the data signal driver may sample grayscale values ​​using a clock signal, and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide scan signals having turn-on level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register, and may generate scan signals to sequentially transmit the scan start signal provided in the form of a turn-on level pulse to a next stage circuit under the control of a clock signal, where m may be a natural number.

[0037] Fig. 2 is a schematic diagram of a plane structure of a display substrate. As shown in Fig. 2, the display substrate may include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light, and each of the four sub-pixels may include a circuit unit and a light-emitting element, and the circuit unit may include a scanning signal line, a data signal line, and a pixel driving circuit, and the pixel driving circuits are electrically connected to the scanning signal lines and the data signal lines, respectively, and the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line under the control of the scanning signal line, and output a corresponding current to the light-emitting element. The light-emitting element in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located, and the light-emitting element is configured to emit light of a corresponding brightness according to the current output from the pixel driving circuit of the sub-pixel in which it is located.

[0038] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a green sub-pixel (G) that emits green light, the third sub-pixel P3 may be a white sub-pixel (W) that emits white light, and the fourth sub-pixel P4 may be a blue sub-pixel (B) that emits blue light.

[0039] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond, pentagonal, or hexagonal. In one exemplary embodiment, the four sub-pixels may be arranged in a horizontal parallel manner to form a RWBG pixel array. In other exemplary embodiments, the four sub-pixels may be arranged in a square, diamond, vertical parallel manner, etc., and the present disclosure is not limited in this respect.

[0040] In an exemplary embodiment, a plurality of sub-pixels arranged sequentially in the horizontal direction are referred to as a pixel row, and a plurality of sub-pixels arranged sequentially in the vertical direction are referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns form an array of pixels.

[0041] Fig. 3 is a schematic cross-sectional view of a display substrate, showing the structure of four sub-pixels of the display substrate. As shown in Fig. 3, on a plane perpendicular to the display substrate, each sub-pixel of the display substrate may include a drive circuit layer 102 provided on a base substrate 10, a light-emitting structure layer 103 provided on the side of the drive circuit layer 102 that is away from the base substrate, and a package layer 104 provided on the side of the light-emitting structure layer 103 that is away from the base substrate.

[0042] In an exemplary embodiment, the base substrate 10 may be a flexible base substrate or a rigid base substrate. The driving circuit layer 102 of each subpixel may include a pixel driving circuit, which is composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 of each subpixel may include a light-emitting element composed of a plurality of film layers, which may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode, where the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of a corresponding color when driven by the anode and the cathode. The package layer 104 may include a first package layer, a second package layer, and a third package layer that are stacked together, where the first package layer and the third package layer may adopt inorganic materials, and the second package layer may adopt organic materials, and the second package layer is provided between the first package layer and the third package layer, and can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0043] In an exemplary embodiment, the organic light-emitting layer may include a hole-injection layer (HIL), a hole-transport layer (HTL), an electron-blocking layer (EBL), an emissive layer (EML), a hole-blocking layer (HBL), an electron-transporting layer (ETL), and an electron-injection layer (EIL), which are stacked together. In an exemplary embodiment, the hole-injection layer, the hole-transport layer, the electron-blocking layer, the hole-blocking layer, the electron-transporting layer, and the electron-injection layer of all the subpixels may be a common layer connected to each other, and the light-emitting layers of all the subpixels may be a common layer connected to each other or may be isolated from each other, and the light-emitting layers of adjacent subpixels may have a small amount of overlap. In some possible implementations, the display substrate may include other film layers, and the present disclosure is not limited in this regard.

[0044] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 4 is an equivalent circuit schematic diagram of the pixel driving circuit. As shown in Figure 4, the pixel driving circuit may be a 3T1C structure and include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3), one storage capacitor C, and six signal lines (a data signal line D, a first scanning signal line G1, a second scanning signal line G2, a compensation signal line S, a first power supply line VDD, and a second power supply line VSS).

[0045] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. A first pole of the storage capacitor C is coupled to the control pole of the second transistor T2, and a second pole of the storage capacitor C is coupled to the second pole of the second transistor T2, and the storage capacitor C is used to store the potential of the control pole of the second transistor T2. A control pole of the first transistor T1 is coupled to the first scanning signal line G1, a first pole of the first transistor T1 is coupled to the data signal line D, and a second pole of the first transistor T1 is coupled to the control pole of the second transistor T2, and the first transistor T1 is used to receive a data signal transmitted by the data signal line D under the control of the first scanning signal line G1, and make the control pole of the second transistor T2 receive the data signal. The control pole of the second transistor T2 is coupled to the second pole of the first transistor T1, the first pole of the second transistor T2 is coupled to the first power supply line VDD, the second pole of the second transistor T2 is coupled to the first pole of the light-emitting element, the control pole of the second transistor T2 is used to generate a corresponding current at the second pole under the control of the received data signal. The control pole of the third transistor T3 is coupled to the second scanning signal line G2, the first pole of the third transistor T3 is coupled to the compensation signal line S, the second pole of the third transistor T3 is coupled to the second pole of the second transistor T2, the third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing, thereby compensating the threshold voltage Vth.

[0046] In an exemplary embodiment, the light-emitting element may be an OLED, which includes a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) that are stacked together, the first electrode of the OLED is coupled to the second electrode of the second transistor T2, the second electrode of the OLED is coupled to the second power supply line VSS, and the OLED is used to emit light of corresponding brightness in response to a current at the second electrode of the second transistor T2.

[0047] In an exemplary embodiment, the signal of the first power line VDD is a high-level signal that is continuously provided, and the signal of the second power line VSS is a low-level signal. The first transistor T1 to the third transistor T3 may be P-type transistors or N-type transistors. By using the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the product yield can be increased.

[0048] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may adopt a low-temperature polysilicon thin film transistor, or may adopt an oxide thin film transistor, or may adopt a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (abbreviated as Low Temperature Poly-Silicon, LTPS), and the active layer of the oxide thin film transistor adopts an oxide (oxide). The low-temperature polysilicon thin film transistor has advantages such as high mobility and fast charging, and the oxide thin film transistor has advantages such as low leakage current. In an exemplary embodiment, the low-temperature polysilicon thin film transistor and the oxide thin film transistor may be integrated on one display substrate to form a low-temperature polycrystalline oxide (abbreviated as Low Temperature Polycrystalline Oxide, LTPO) display substrate, which can utilize the advantages of both, realize high resolution (abbreviated as Pixel Per Inch, PPI), low frequency driving, reduce power consumption, and improve display quality. In an exemplary embodiment, the light emitting element may be an organic electroluminescent diode (OLED), which comprises a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked together.

[0049] In an exemplary embodiment, taking the three transistors as an example, all are N-type transistors, the operation process of the exemplary pixel driving circuit of FIG. 4 may include the following first stage A1 and second stage A2.

[0050] In the first stage A1, the signals of the first scanning signal line G1 and the second scanning signal line G2 are high level signals, the data signal line D outputs a data voltage, the compensation signal line S outputs a compensation voltage, the signal of the first power supply line VDD is high level, and the signal of the second power supply line VSS is low level. The signal of the first scanning signal line G1 is a high level signal, which turns on the first transistor T1, and the data voltage output from the data signal line D is written to the first node N1, which pulls up the potential of the first node N1 and charges the storage capacitor C. At this time, the potential of the first node N1 is V1=V data The signal of the second scanning signal line G2 is a high level signal, which turns on the third transistor T3, and the compensation voltage output from the compensation signal line S is written to the second node N2. At this time, the potential of the second node N2 is V2=V s The difference between the potentials of the first node N1 and the second node N2 is the threshold voltage V th Since the first power supply line VDD is greater than the first power supply line VDD, the second transistor T2 is turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the second transistor T2 that is turned on, thereby driving the OLED to emit light.

[0051] In the second stage A2, the signals on the first scanning signal line G1 and the second scanning signal line G2 are low level signals, turning off the first transistor T1 and the third transistor T3, the voltage on the storage capacitor C still keeps the second transistor T2 in the on state, the power supply voltage output from the first power supply line VDD keeps pulling up the potential of the second node N2, and the OLED keeps emitting light. data -V th , the second transistor T2 is turned off and the OLED does not emit light.

[0052] In an exemplary embodiment, in order to drive the OLED to emit normal light, the OLED and the second transistor T2 are both forward biased, and in a first stage, the power supply voltage output from the first power supply line VDD is greater than the data voltage output from the data signal line D, the data voltage output from the data signal line D is greater than the compensation voltage output from the compensation signal line S, and the compensation voltage output from the compensation signal line S is greater than the power supply voltage output from the second power supply line VSS.

[0053] With the development of display technology, OLED technology is increasingly applied to transparent display. Transparent display is an important personalized display field in display technology, which refers to displaying images in a transparent state, allowing viewers to not only see the image inside the display device, but also the scene behind the display device, realizing virtual reality (abbreviated as VR), augmented reality (abbreviated as AR) and 3D display functions. In transparent display devices using AMOLED technology, each pixel is usually divided into a display area and a transparent area, and pixel driving circuits and light emitting elements are provided in the display area to realize image display, and light transmission is realized in the transparent area.

[0054] However, in large transparent display products, the overlapping area between the power line and other signal lines is large, which is likely to affect the product yield, and therefore the product reliability does not meet the process requirements.

[0055] An exemplary embodiment of the present disclosure provides a display substrate, comprising: a base substrate; and a plurality of display units disposed on the base substrate, at least one of the display units comprising a display area and a transparent area, and at least one of the display areas comprising a plurality of sub-pixels.

[0056] At least one display area has a first power supply line and a second power supply line provided in a first direction, the first power supply line and the second power supply line extending in a second direction, at least one display area has a first scanning signal line, a second scanning signal line, a second scanning connection line, and a first scanning connection line provided in the second direction, the second scanning connection line and the second scanning signal line being connected to each other to form a first ring structure, at least one display area has a third scanning connection line provided between the first scanning signal line and the first scanning connection line, the third scanning connection line, the first scanning connection line, and the first scanning signal line being connected to each other to form a second ring structure, and the first direction and the second direction intersect.

[0057] There is no overlapping area between the orthogonal projection of the first ring structure on the base substrate and the orthogonal projection of the first power supply line and the second power supply line on the base substrate, and there is no overlapping area between the orthogonal projection of the second ring structure on the base substrate and the orthogonal projection of the first power supply line and the second power supply line on the base substrate.

[0058] In the display substrate provided in the embodiments of the present disclosure, the first scanning signal line and the second scanning signal line are respectively designed as annular windings with corresponding scanning connecting lines in the display area, and the annular winding positions of the first scanning signal line and the second scanning signal line avoid the first power line and the second power line, thereby avoiding the problem that the overlapping area between the power line and other signal lines is large, which is likely to affect the yield of products, and optimizing the intersections between the signal lines to be minimized while realizing the function of repair, further improving the yield of products, and providing technical support for transparent display products.

[0059] Fig. 5 is a structural schematic diagram of a display panel according to an exemplary embodiment of the present disclosure, which is a schematic diagram of four sub-pixels (one pixel unit), and Fig. 6 is an equivalent circuit schematic diagram of a pixel driving circuit in the four sub-pixels shown in Fig. 5. As shown in Fig. 5 and Fig. 6, in a direction parallel to the display substrate, at least one pixel unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged in sequence, and each sub-pixel includes a pixel driving circuit and a storage capacitor. In the following description, each sub-pixel refers to an area where a pixel driving circuit is provided. In an exemplary embodiment, at least one pixel unit may further include: one first scanning signal line G1, one second scanning signal line G2, one first power supply line VDD, one second power supply line VSS, four data signal lines D (in FIG. 6, the four data signal lines D are the first data signal line D1 to the fourth data signal line D4, respectively, where the first sub-pixel P1 is connected to the first data signal line D1, the second sub-pixel P2 is connected to the second data signal line D2, the third sub-pixel P3 is connected to the third data signal line D3, and the fourth sub-pixel P4 is connected to the fourth data signal line D4), one compensation signal line S, and four pixel driving circuits.

[0060] In an exemplary embodiment, the first scanning signal line G1 and the second scanning signal line G2 may extend in a first direction D1 and be sequentially arranged in a second direction D2, and the first direction D1 and the second direction D2 may cross each other. The first power line VDD, the data signal line D, and the compensation signal line S may extend in the second direction D2 and be correspondingly arranged along the first direction D1.

[0061] In an exemplary embodiment, four data signal lines D and one compensation signal line S are provided between a first power supply line VDD and a second power supply line VSS, two of the four data signal lines D are located between the compensation signal line S and the first power supply line VDD, and the other two of the four data signal lines D are located between the compensation signal line S and the second power supply line VSS. Then, four sub-pixels are formed by providing four data signal lines D and one compensation signal line S between the first power supply line VDD and the second power supply line VSS, and correspondingly, four sub-pixels are formed by providing one first power supply line VDD, one second power supply line VSS, and four data signal lines D between the two compensation signal lines S.

[0062] In an exemplary embodiment, the one first power supply line VDD, the two data signal lines D, the compensation signal line S, the other two data signal lines D, and the one second power supply line VSS may be sequentially arranged in a first direction D1. In the first direction D1, the first sub-pixels P1 and the second sub-pixels P2 are alternately arranged to form a first row, and the third sub-pixels P3 and the fourth sub-pixels P4 are alternately arranged to form a second row, and in the second direction D2, the first sub-pixels P1 and the third sub-pixels P3 are alternately arranged to form a first column, and the second sub-pixels P2 and the fourth sub-pixels P4 are alternately arranged to form a second column.

[0063] In an exemplary embodiment, the pixel driving circuit in each of the four sub-pixels of the at least one pixel unit may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. The first transistor T1 may include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor T2 may include a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, the third transistor T3 may include a third active layer, a third gate electrode, a third source electrode, and a third drain electrode, and the storage capacitor may include a first plate and a second plate.

[0064] In an exemplary embodiment, the first and second plates are transparent conductive layers forming a transparent storage capacitor.

[0065] In an exemplary embodiment, the first scanning signal line G1 is connected to the gate electrode of the first transistor T1 in each subpixel, the second scanning signal line G2 is connected to the gate electrode of the third transistor T3 in each subpixel, the data signal line D is connected to the first pole of the first transistor T1 in each subpixel, the compensation signal line S is connected to the first pole of the third transistor T3 in each subpixel, the first power supply line VDD is connected to the first pole of the second transistor T2 in each subpixel, the second pole of the first transistor T1 in each subpixel is connected to the gate electrode of the second transistor T2, the second pole of the second transistor T2 in each subpixel is connected to the first pole of the third transistor T3 and the anode of the light-emitting element, the first electrode plate in each subpixel is connected to the second pole of the second transistor T2 and the second pole of the third transistor T3, respectively, and the second electrode plate in each subpixel is connected to the second pole of the first transistor T1 and the gate electrode of the second transistor T2, respectively.

[0066] In an exemplary embodiment, at least one pixel unit may have a plurality of connecting lines, including at least two lateral power supply connecting lines extending in a first direction D1 and two compensation connecting lines extending in the first direction D1 and in the opposite direction to the first direction D1, forming a one-for-four structure of the first power supply line and a one-for-four structure of the compensation signal line S.

[0067] In an exemplary embodiment, one horizontal power supply connecting line is provided in the first sub-pixel P1 and the second sub-pixel P2, one end of the horizontal power supply connecting line is connected to the first power supply line VDD via a through hole, and the other end is connected to the second transistor T2 in the first sub-pixel P1 and the second sub-pixel P2 via a through hole. Another horizontal power supply connecting line is provided in the third sub-pixel P3 and the fourth sub-pixel P4, one end of the horizontal power supply connecting line is connected to the first power supply line VDD via a through hole, and the other end is connected to the second transistor T2 in the third sub-pixel P3 and the fourth sub-pixel P4 via a through hole. In this way, one first power supply line VDD can provide a power supply signal to four sub-pixels.

[0068] In an exemplary embodiment, the compensation connection line is provided in the center of one pixel unit, the compensation connection line and the compensation signal line are connected to each other in an integrated structure, and the compensation connection line is connected to the third transistor T3 in each sub-pixel through a through hole, so that one compensation signal line S can provide compensation signals to four sub-pixels.

[0069] In the embodiment of the present disclosure, the one-drag-four structure of the first power line and the one-drag-four structure of the compensation signal line save the number of signal lines, reduce the occupied space, have a simple structure, a reasonable layout, make full use of the layout space, improve the space utilization rate, and are favorable for improving the resolution.

[0070] In an exemplary embodiment, in a direction perpendicular to the display substrate, the driving circuit layer of the subpixel may include a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planar layer, which are stacked on the base substrate. The first conductive layer includes at least a first plate of the storage capacitor, a compensation signal line, and a compensation connection line, the semiconductor layer includes active layers of at least three transistors, the second conductive layer includes at least a first scanning signal line, a second scanning signal line, a lateral power connection line, a second plate of the storage capacitor, and gate electrodes of the three transistors, and the third conductive layer includes at least a first power line VDD, a second power line VSS, a data signal line D, and first and second poles of the three transistors. There is at least an overlapping area between the orthogonal projection of the first plate on the base substrate and the orthogonal projection of the second plate on the base substrate, forming a storage capacitor.

[0071] In an exemplary embodiment, the second conductive layer may include a first scan connecting line and a second scan connecting line, where the first scan connecting line and the second scan connecting line are located in the first sub-pixel P1 and the second sub-pixel P2, the first scan signal line and the second scan signal line are located in the third sub-pixel P3 and the fourth sub-pixel P4, and the second scan connecting line and the second scan signal line are connected to each other to form an integral structure. The third conductive layer may include a third scan connecting line, which is connected to the first scan connecting line and the first scan signal line respectively through the through holes.

[0072] In an exemplary embodiment, the second conductive layer may include a vertical power connection line and an auxiliary power line, where the first power line VDD is electrically connected to the vertical power connection line via a through hole to form a two-layer first power wiring, and the second power line VSS is electrically connected to the auxiliary power line via a through hole to form a two-layer second power wiring.

[0073] In an exemplary embodiment, the third conductive layer may include an auxiliary cathode, and the auxiliary cathode and the second power line VSS are an integral structure connected to each other.

[0074] In an exemplary embodiment, in a direction perpendicular to the display substrate, the subpixel further comprises a light-emitting structure layer provided on a side of the driving circuit layer away from the base substrate, the light-emitting structure layer comprising an anode, and the auxiliary connection electrode is provided in the same layer as the anode.

[0075] Next, the manufacturing process of the display substrate will be described by way of example. The "patterning process" referred to in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, or transparent conductive materials, and organic materials, including processes such as coating, mask exposure, and development. The deposition may adopt any one or more of sputtering, evaporation, and chemical vapor deposition, the coating may adopt any one or more of spray coating, spin coating, and inkjet printing, and the etching may adopt any one or more of dry etching and wet etching, and the disclosure is not limited thereto. A "thin film" refers to a layer of a thin film made of a certain material on a base substrate by deposition, coating, or other process. If the "thin film" does not require a patterning process in the entire manufacturing process, the "thin film" may also be referred to as a "layer". If the "thin film" requires a patterning process in the entire manufacturing process, it is referred to as a "thin film" before the patterning process, and as a "layer" after the patterning process. After the patterning process, the "layer" contains at least one "pattern." In the present disclosure, "A and B are provided in the same layer" refers to A and B being formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthogonal projection of B is within the orthogonal projection of A" or "the orthogonal projection of A includes the orthogonal projection of B" refers to the boundary of the orthogonal projection of B being within the boundary of the orthogonal projection of A, or the boundary of the orthogonal projection of A and the boundary of the orthogonal projection of B overlap.

[0076] 7 to 26 are schematic diagrams of the display substrate manufacturing process of the present disclosure, which are schematic diagrams showing the layout structure of one display unit of a top-emission OLED display substrate, each display unit includes a display area 100 and a transparent area 200, the display area 100 includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4, and the pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor. In an exemplary embodiment, the manufacturing process of the display substrate may include the following operations (1) to (11):

[0077] (1) Form a first conductive layer pattern, which includes depositing a first metal thin film on a base substrate, patterning the first metal thin film by a patterning process, and forming a first conductive layer pattern on the base substrate 10, where the first conductive layer pattern has a first electrode plate 41 and a compensation signal line S, where each sub-pixel forms one first electrode plate 41, and the compensation signal line S is a stripe structure disposed between four sub-pixels, as shown in Figures 7 and 8. Figure 8 is a cross-sectional view of the AA direction in Figure 7.

[0078] In an exemplary embodiment, the first plate 41 is configured as one plate of a first capacitor to form the first capacitor with a subsequently formed second plate, and the first plate 41 is also configured as a shielding layer to provide light shielding to the transistor, reducing the light intensity irradiating the transistor and reducing the drain current, thereby reducing the effect of light irradiation on the transistor characteristics.

[0079] In an exemplary embodiment, the compensation signal line S extends in a second direction D2, and the compensation signal line S is provided with a compensation connection line S-1 protruding in a first direction D1 and in a direction opposite to the first direction D1. The compensation connection line S-1 is connected to a first electrode of a third transistor to be formed subsequently, and is used to provide a compensation signal to the third transistor in each subpixel.

[0080] In an exemplary embodiment, the first electrode plate 41 is an elongated rectangle, and the first electrode plate 41 in the first subpixel P1 and the first electrode plate 41 in the second subpixel P2 are each provided with a first opening 45 at a position close to the center of the pixel unit and away from the compensation signal line S, and the first electrode plate 41 in the third subpixel P3 and the first electrode plate 41 in the fourth subpixel P4 are each provided with a second opening 46 at a position close to the center of the pixel unit and close to the compensation signal line S.

[0081] In an exemplary embodiment, the first conductive layer pattern in the first subpixel P1 and the first conductive layer pattern in the second subpixel P2 are mirror symmetrical about a vertical axis (which may be the compensation signal line S), and the first conductive layer pattern in the third subpixel P3 and the first conductive layer pattern in the fourth subpixel P4 are mirror symmetrical about the vertical axis.

[0082] After this patterning process, the first conductive layer pattern is formed in the display area 100, and the transparent area 200 has no corresponding film layer.

[0083] (2) Forming a semiconductor layer pattern, which includes sequentially depositing a first insulating thin film and a semiconductor layer thin film on the base substrate on which the aforementioned pattern is formed, patterning the semiconductor layer thin film by a patterning process, forming a first insulating layer 61 covering the first conductive layer pattern, and forming a semiconductor layer pattern on the first insulating layer 61, the semiconductor layer having a pattern of a first active layer 11, a second active layer 21, and a third active layer 31 provided in each sub-pixel, as shown in Figures 9 and 10, and Figure 10 is a cross-sectional view taken along the AA direction in Figure 9. The first active layer 11 is the active layer of a first transistor, the second active layer 21 is the active layer of a second transistor, and the third active layer 31 is the active layer of a third transistor.

[0084] In the exemplary embodiment, in the four sub-pixels, there is an overlapping area between the orthogonal projection of the second active layer 21 on the base substrate 10 and the orthogonal projection of the first electrode plate 41 on the base substrate 10, so that the first electrode plate 41 as a shielding layer can shield the channel region of the second transistor, avoiding light rays from affecting the channel, and preventing the channel from generating light-induced leakage current to affect the display effect.

[0085] In an exemplary embodiment, the first active layer 11 in the first subpixel P1 and the second subpixel P2 is located close to the first opening 45, and the first active layer 11 in the third subpixel P3 and the fourth subpixel P4 is located close to the second opening 46.

[0086] In the exemplary embodiment, the third active layers 31 in the four subpixels P1 to P4 are all provided at positions close to the compensation connection line S-1, and there is an overlapping region between the orthogonal projection of the third active layer 31 on the base substrate 10 and the orthogonal projection of the compensation connection line S-1 on the base substrate 10. In the exemplary embodiment, the third active layer 31 in the first subpixel P1 and the third active layer 31 in the third subpixel P3 are connected to each other and have an integral structure, and the third active layer 31 in the second subpixel P2 and the third active layer 31 in the fourth subpixel P4 are connected to each other and have an integral structure.

[0087] In an exemplary embodiment, the semiconductor layer pattern in the first subpixel P1 and the semiconductor layer pattern in the second subpixel P2 are mirror symmetrical about the vertical axis, and the semiconductor layer pattern in the third subpixel P3 and the semiconductor layer pattern in the fourth subpixel P4 are mirror symmetrical about the vertical axis.

[0088] In an exemplary embodiment, the semiconductor layer may employ a metal oxide, for example, an oxide including indium and tin, an oxide including tungsten and indium, an oxide including tungsten, indium, and zinc, an oxide including titanium and indium, an oxide including titanium, indium, and tin, an oxide including indium and zinc, an oxide including silicon, indium, and tin, an oxide including indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, or may be a two-layer, or may be a multilayer.

[0089] After this patterning process, the semiconductor layer pattern is formed in the display area 100 , and the transparent area 200 includes the base substrate 10 and the first insulating layer 61 disposed on the base substrate 10 .

[0090] (3) Forming a second conductive layer pattern, which includes sequentially depositing a second insulating thin film and a second metal thin film on the base substrate on which the aforementioned pattern is formed, and patterning the second insulating thin film and the second metal thin film by a patterning process to form a second insulating layer 62 pattern and a second conductive layer pattern provided on the second insulating layer 62, as shown in Figures 11 and 12, the second conductive layer pattern includes a first scanning signal line G1, a second scanning signal line G2, a first scanning connection line G1-1, a second scanning connection line G2-1, a vertical power supply connection line 51, a horizontal power supply connection line 52, an auxiliary power supply line 53, a second electrode plate 42 formed in each sub-pixel, a first gate electrode 12, a second gate electrode 22, and a third gate electrode 32, which are formed in each sub-pixel, and Figure 12 is a cross-sectional view along the AA direction in Figure 11.

[0091] In the exemplary embodiment, there is an overlap region between the orthogonal projection of the second plate 42 on the base substrate 10 and the orthogonal projection of the first plate 41 on the base substrate 10, and the first plate 41 and the second plate 42 form a first capacitor.

[0092] In the exemplary embodiment, the second electrode plate 42 is an elongated rectangle, and the second electrode plate 42 in the first subpixel P1 and the second subpixel P2 each has a third opening 47 near the center of the pixel unit, and the second electrode plate 42 in the third subpixel P3 and the fourth subpixel P4 each has a fourth opening 48 near the center of the pixel unit.

[0093] In the exemplary embodiment, the first scanning signal line G1 and the second scanning signal line G2 both extend in a first direction D1, the second scanning connecting line G2-1 has an inverted “U” structure, the second scanning connecting line G2-1 and the second scanning signal line G2 are connected to each other to form an integral structure, the first scanning connecting line G1-1 has a “1” structure, the first scanning connecting line G1-1 and the second scanning connecting line G2-1 are located at the first sub-pixel P1 and the second sub-pixel P2, and the first scanning signal line G1 and the second scanning signal line G2 are located at the third sub-pixel P3 and the fourth sub-pixel P4.

[0094] In an exemplary embodiment, there is an overlapping region between the orthogonal projection of the second scanning signal line G2 on the base substrate and the orthogonal projection of the third active layer 31 in the third subpixel P3 and the fourth subpixel P4 on the base substrate, and the overlapping region between the second scanning signal line G2 and the third active layer 31 in the third subpixel P3 and the fourth subpixel P4 is set as the gate electrode 32 of the third transistor T3 in the third subpixel P3 and the fourth subpixel P4. There is an overlapping region between the orthogonal projection of the second scanning connecting line G2-1 on the base substrate and the orthogonal projection of the third active layer 31 in the first subpixel P1 and the second subpixel P2 on the base substrate, and the overlapping region between the second scanning connecting line G2-1 and the third active layer 31 in the first subpixel P1 and the second subpixel P2 is set as the gate electrode 32 of the third transistor T3 in the first subpixel P1 and the second subpixel P2.

[0095] In the exemplary embodiment, the first scanning signal line G1 has a “U” shaped bent portion, there is an overlapping region between the orthogonal projection of the first scanning signal line G1 on the base substrate and the orthogonal projection of the first active layer 11 in the third sub-pixel P3 and the fourth sub-pixel P4 on the base substrate, the overlapping region between the first scanning signal line G1 and the first active layer 11 in the third sub-pixel P3 and the fourth sub-pixel P4 is set to the gate electrode 12 of the first transistor T1 in the third sub-pixel P3 and the fourth sub-pixel P4, there is an overlapping region between the orthogonal projection of the first scanning connecting line G1-1 on the base substrate and the orthogonal projection of the first active layer 11 in the first sub-pixel P1 and the second sub-pixel P2 on the base substrate, and the overlapping region between the first scanning connecting line G1-1 and the first active layer 11 in the first sub-pixel P1 and the second sub-pixel P2 is set to the gate electrode 12 of the first transistor T1 in the first sub-pixel P1 and the second sub-pixel P2.

[0096] In the exemplary embodiment, the second gate electrode 22 spans the second active layer 21 and is interconnected with the second plate 42 to form a unitary structure.

[0097] In an exemplary embodiment, each display unit includes two vertical power supply connecting lines 51, which are formed in the first sub-pixel P1 and the third sub-pixel P3 and have a stripe structure extending in the second direction D2. In the first sub-pixel P1, the vertical power supply connecting line 51 is located on the opposite side of the second electrode plate 42 in the first direction D1. In the third sub-pixel P3, the vertical power supply connecting line 51 is located on the opposite side of the second electrode plate 42 in the first direction D1. The vertical power supply connecting line 51 is configured to be connected to a first power supply line VDD to be formed later to form a double wiring, which ensures the reliability of power supply signal transmission and reduces the resistance of the first power supply line.

[0098] In an exemplary embodiment, each display unit includes two horizontal power supply connecting lines 52, one of which is located at the upper side of the pixel unit (i.e., located at the side of the first sub-pixel P1 and the second sub-pixel P2 away from the third sub-pixel P3 and the fourth sub-pixel P4), and the other is located at the lower side of the pixel unit (i.e., located at the side of the third sub-pixel P3 and the fourth sub-pixel P4 away from the first sub-pixel P1 and the second sub-pixel P2). Each horizontal power supply connecting line 52 may be provided with a through hole, and there is an overlapping area between the orthogonal projection of the through hole on the base substrate and the orthogonal projection of the compensation signal line and the data signal line to be formed later on the base substrate, and the through hole is configured to reduce the parasitic capacitance between the horizontal power supply connecting line 52 and the data signal line and the compensation signal line.

[0099] In an exemplary embodiment, the horizontal power supply connection line 52 located on the upper side of the pixel unit and the vertical power supply connection line 51 located in the first sub-pixel P1 may be connected to each other to form an integrated structure, and the horizontal power supply connection line 52 located on the lower side of the pixel unit and the vertical power supply connection line 51 located in the third sub-pixel P3 may be connected to each other to form an integrated structure.

[0100] In an exemplary embodiment, each display unit includes two auxiliary power lines 53, which are formed in the second sub-pixel P2 and the fourth sub-pixel P4 and have a stripe structure extending in the second direction D2. In the second sub-pixel P2, the auxiliary power line 53 is located on the first direction D1 side of the second electrode plate 42. In the fourth sub-pixel P4, the auxiliary power line 53 is located on the first direction D1 side of the second electrode plate 42. The auxiliary power line 53 is configured to be electrically connected to a second power line to be formed later to form a double wiring, which ensures the reliability of power signal transmission and reduces the resistance of the second power line.

[0101] In an exemplary embodiment, the second insulating layer 62 pattern may be the same as the second conductive layer pattern, i.e., the second insulating layer 62 is located below the second conductive layer (i.e., the side of the second conductive layer closer to the base substrate) and the second insulating layer 62 is not present in areas other than the second conductive layer.

[0102] In an exemplary embodiment, the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 in the first subpixel P1 and the second subpixel P2 are mirror-symmetric with respect to the vertical axis, and the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 in the third subpixel P3 and the fourth subpixel P4 are mirror-symmetric with respect to the vertical axis.

[0103] In an exemplary embodiment, the process further includes a conductorization process, which is to perform a plasma process using the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 as shielding after the second conductive layer pattern is formed, to make the semiconductor layer in the region shielded by the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 (i.e., the region where the semiconductor layer overlaps with the first gate electrode 12, the second gate electrode 22, and the third gate electrode) into a channel region of a transistor, and to process the semiconductor layer in the region not shielded by the second conductive layer into a conductorized layer, thereby forming a conductorized source / drain region.

[0104] After this patterning process, a second conductive layer pattern is formed in the display area 100, and the transparent area 200 includes a base substrate 10, a first insulating layer 61 and a second insulating layer 62 stacked on the base substrate 10, and a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62.

[0105] (4) Forming a third insulating layer pattern. Forming the third insulating layer pattern includes depositing a third insulating thin film on the base substrate on which the aforementioned pattern is formed, patterning the third insulating thin film by a patterning process, and forming a third insulating layer 63 pattern covering the aforementioned structure, and a plurality of through-hole patterns are provided in the third insulating layer 63, and the plurality of through-hole patterns include a first through-hole V1 and a second through-hole V2 located on both sides of the first gate electrode 12, a third through-hole V3 and a fourth through-hole V4 located on both sides of the second gate electrode 22, a fifth through-hole V5 and a sixth through-hole V6 located on both sides of the third gate electrode 32, and a fifth through-hole V7 located at the position of the auxiliary power line 53, as shown in FIG. 13 and FIG. 14. 14 is a cross-sectional view taken along line AA in FIG. 13 . In FIG. 14 , the opening region of the first electrode plate 41 is provided with a plurality of seventh through holes V7 located at the position of the vertical power supply connecting line 51, an eighth through hole V8 located at the position of the compensation connecting line S-1, a ninth through hole V9 located in an overlapping region of the first drain electrode 14 and the second electrode plate 42 to be formed later, a tenth through hole V10 located in the first electrode plate 41 and overlapping with an opening region in the second electrode plate 42, a plurality of eleventh through holes V11 located at the position of the vertical power supply connecting line 51, a thirteenth through hole V13 located at the position of the horizontal power supply connecting line 52, a fourteenth through hole V14 located at the position of the first scanning connecting line G1-1, and a fifteenth through hole V15 located at the position of the first scanning signal line G1.

[0106] The third insulating layer 63 in the first through hole V1 and the second through hole V2 is etched to expose the surfaces of both ends of the first active layer 11. The third insulating layer 63 in the third through hole V3 and the fourth through hole V4 is etched to expose the surfaces of both ends of the second active layer 21. The third insulating layer 63 in the fifth through hole V5 and the sixth through hole V6 is etched to expose the surfaces of both ends of the third active layer 31. The seventh through hole V7 is located at the position of the auxiliary power line 53, and a plurality of seventh through holes V7 are provided at intervals. The third insulating layer 63 in the seventh through hole V7 is etched to expose the surface of the auxiliary power line 53. The eighth through hole V8 is located at the position where the third source electrode 33 to be formed later and the compensation connection line S-1 overlap, and the first insulating layer 61 and the third insulating layer 63 in the eighth through hole V8 are etched to expose the surface of the compensation connection line S-1. The ninth through-hole V9 is formed in the second electrode plate 42, and the third insulating layer 63 in the ninth through-hole V9 is etched to expose the surface of the second electrode plate 42. The tenth through-hole V10 in the first sub-pixel P1 and the second sub-pixel P2 is located at the position of the third opening 47 of the second electrode plate 42, and the tenth through-hole V10 in the third sub-pixel P3 and the fourth sub-pixel P4 is located at the position of the fourth opening 48 of the second electrode plate 42, and the first insulating layer 61 and the third insulating layer 63 in the tenth through-hole V10 are etched to expose the surface of the first electrode plate 41. The eleventh through-hole V11 is located at the position of the vertical power supply connecting line 51, and a plurality of the eleventh through-holes V11 are provided at intervals, and the third insulating layer 63 in the eleventh through-hole V11 is etched to expose the surface of the vertical power supply connecting line 51. The thirteenth through hole V13 is located at a position where the lateral power supply connecting line 52 and the second source electrode 23 to be formed later overlap, and the third insulating layer 63 in the thirteenth through hole V13 is etched to expose the surface of the lateral power supply connecting line 52. The fourteenth through hole V14 is located at a position where the first scanning connecting line G1-1 and the third scanning connecting line 54 to be formed later overlap, and the third insulating layer 63 in the fourteenth through hole V14 is etched to expose the surface of the first scanning connecting line G1-1.The 15th through hole V15 is located at the overlapping area between the first scanning signal line G1 and the third scanning connection line 54 to be formed later, and the third insulating layer 63 in the 15th through hole V15 is etched to expose the surface of the first scanning signal line G1.

[0107] After this patterning process, multiple through-hole patterns are formed in the display area 100, and the transparent area 200 includes a first insulating layer 61 and a second insulating layer 62 stacked on the base substrate 10, a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62, and a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2.

[0108] (5) Forming a third conductive layer pattern, which includes depositing a third metal thin film on the base substrate on which the above-mentioned pattern is formed, patterning the third metal thin film by a patterning process, and forming a third conductive layer pattern on the third insulating layer 63. As shown in Figures 15 and 16, the third conductive layer includes one first power line VDD, one second power line VSS, four data signal lines D, and two third scanning connection lines 54 formed in each display unit, as well as a pattern of a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34, and a third electrode plate 43 formed in each subpixel, and Figure 16 is a cross-sectional view of the AA direction in Figure 15.

[0109] In an exemplary embodiment, the first power supply line VDD, the second power supply line VSS, the compensation signal line S, and the data signal line D are arranged in parallel and all extend in the second direction D2, the second power supply line VSS is arranged in the second subpixel P2 and the fourth subpixel P4, the first power supply line VDD is arranged in the first subpixel P1 and the third subpixel P3, the compensation signal line S is arranged midway between the first power supply line VDD and the second power supply line VSS, two data signal lines D are arranged between the second power supply line VSS and the compensation signal line S, and the other two data signal lines D are arranged between the first power supply line VDD and the compensation signal line S.

[0110] In an exemplary embodiment, the first power supply line VDD is connected to the vertical power supply connecting line 51 and the horizontal power supply connecting line 52 through a plurality of eleventh through holes V11, the horizontal power supply connecting line 52 is connected to the second source electrode 23 of each subpixel through the thirteenth through hole V13, and the second source electrode 23 is connected to one end of the second active layer 21 through the third through hole V3, thereby realizing the connection between the second source electrode 23 and the first power supply line VDD, and the first power supply line VDD and the vertical power supply connecting line 51 form a double wiring, which ensures the reliability of power supply signal transmission and reduces the resistance of the first power supply line VDD.

[0111] In an exemplary embodiment, the second power line VSS is connected to the auxiliary power line 53 through a plurality of seventh through holes V7, and the second power line VSS forms a double wiring with the auxiliary power line 53, so as to ensure the reliability of the power signal transmission and reduce the resistance of the second power line VSS. In some possible implementations, the widths of the first power line VDD and the second power line VSS in the first direction D1 are both greater than the width of the compensation signal line S in the first direction D1, and the widths of the first power line VDD and the second power line VSS in the first direction D1 are both greater than the width of the data signal line D in the first direction D1, so as to further reduce the resistance of the first power line VDD and the second power line VSS.

[0112] In an exemplary embodiment, the compensation connection line S-1 is connected to the third source electrode 33 of each subpixel through the eighth through hole V8. The compensation connection line S-1 is provided at the center of the subpixels on both the upper and lower sides of the display area 100, the compensation signal line S is provided at the center of the subpixels on both the left and right sides of the display area 100, the compensation connection line S-1 and the compensation signal line S are connected to each other in an integrated structure, and the third transistors of the subpixels on both the left and right sides are symmetrically arranged with respect to the compensation signal line S, such a symmetrical design requires that each display unit only adopts one compensation signal line, and can ensure that the RC delays before the compensation signal is written into the transistors are approximately the same, so as to ensure the uniformity of the display.

[0113] In an exemplary embodiment, the third scanning connection line 54 has a straight or bent line structure extending in the second direction D2, the third scanning connection line 54 is connected to the first scanning connection line G1-1 via the fourteenth through hole V14, and the third scanning connection line 54 is connected to the first scanning signal line G1 via the fifteenth through hole V15.

[0114] In an exemplary embodiment, the data signal line D of the first subpixel P1 is provided on a side closer to the first power supply line VDD of the first subpixel P1, the data signal line D of the second subpixel P2 is provided on a side closer to the second power supply line VSS of the second subpixel P2, the data signal line D of the third subpixel P3 is provided on a side closer to the compensation signal line S of the third subpixel P3, and the data signal line D of the fourth subpixel P4 is provided on a side closer to the compensation signal line S of the fourth subpixel P4.

[0115] In the exemplary embodiment, the first source electrode 13 is an integral structure connected to the data signal line D, such that each data signal line D is respectively connected to the first source electrode 13 of the subpixel in which it is located, the first source electrode 13 is connected to one end of the first active layer 11 via the first through hole V1, the first drain electrode 14 is connected to the other end of the first active layer 11 via the second through hole V2, and the first drain electrode 14 is further connected to the second gate electrode 22 and the second electrode plate 42 via the ninth through hole V9, thereby realizing that the first drain electrode 14, the second gate electrode 22 and the second electrode plate 42 have the same potential. The second source electrode 23 is connected to one end of the second active layer 21 via the third through hole V3, and is connected to the lateral power supply connection line 52 via the thirteenth through hole V13, and the lateral power supply connection line 52 is connected to the first power supply line VDD via the eleventh through hole V11, thereby realizing the connection between the second source electrode 23 and the first power supply line VDD, and the second drain electrode 24 is connected to the other end of the second active layer 21 via the fourth through hole V4. The third source electrode 33 is connected to one end of the third active layer 31 via the fifth through hole V5, and is connected to the compensation connection line S-1 via the eighth through hole V8, and the compensation connection line S-1 and the compensation signal line S are connected to each other in an integrated structure, thereby realizing the connection between the third source electrode 33 and the compensation signal line S, and the third drain electrode 34 is connected to the other end of the third active layer 31 via the sixth through hole V6. The second drain electrode 24, the third drain electrode 34, and the third plate 43 are an integral structure connected to each other, and the third plate 43 is connected to the first plate 41 via the tenth through hole V10, so that the second drain electrode 24 is connected to the first plate 41 and the third plate 43, respectively, and the third drain electrode 34 is connected to the first plate 41 and the third plate 43, respectively, and the second drain electrode 24, the third drain electrode 34, the first plate 41, and the third plate 43 have the same potential. There is an overlapping area between the orthogonal projection of the third plate 43 on the base substrate 10 and the orthogonal projection of the second plate 42 on the base substrate 10, and the third plate 43 and the second plate 42 form a second capacitor.

[0116] In an exemplary embodiment, the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34, and the third plate 43 in the first subpixel P1 and the second subpixel P2 are mirror images of each other with respect to the vertical axis, and the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34, and the third plate 43 in the third subpixel P3 and the fourth subpixel P4 are mirror images of each other with respect to the vertical axis.

[0117] After this patterning process, a third conductive layer pattern is formed in the display area 100, and the transparent area 200 includes a first insulating layer 61 and a second insulating layer 62 stacked on the base substrate 10, a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62, and a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2.

[0118] (6) Forming a fourth insulating layer and flat layer pattern, which includes first depositing a fourth insulating thin film on the base substrate on which the above-mentioned patterns are formed, then applying a flat thin film, and etching the fourth insulating thin film by masking, exposing, and developing the flat thin film to form a fourth insulating layer 64 pattern covering the above-mentioned structure, and a flat (PLN) layer 65 pattern provided on the fourth insulating layer 64, as shown in Figures 17 and 18, and a plurality of through-hole patterns are provided in the fourth insulating layer 64 and the flat layer 65, and the plurality of through-hole patterns include at least a 16th through-hole V16 located at the position of the third electrode 43 in each sub-pixel of the display area 100 and a 17th through-hole V17 in the second power line VSS, and Figure 18 is a cross-sectional view in the AA direction in Figure 17.

[0119] In an exemplary embodiment, the 16th through hole V16 is located in the center of the third plate 43, the fourth insulating layer 64 and the flat layer 65 at the 16th through hole V16 are etched to expose the surface of the third plate 43, and the fourth insulating layer 64 and the flat layer 65 at the 17th through hole V17 are etched to expose the surface of the second power line VSS.

[0120] After this patterning process, the transparent area 200 includes a first insulating layer 61 and a second insulating layer 62 stacked on the base substrate 10, a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62, a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2, and a fourth insulating layer 64 and a flat layer 65 provided on the third insulating layer 63.

[0121] (7) Forming a first transparent conductive layer pattern, which includes depositing a first transparent conductive thin film on the base substrate on which the above-mentioned pattern is formed, and patterning the first transparent conductive thin film by a patterning process to form a first transparent conductive layer pattern on the flat layer 65, as shown in Figures 19 and 20, wherein the first transparent conductive layer has a first anode 70 and a first connecting electrode 81, the first anode 70 is formed in each sub-pixel of the display area 100, the first anode 70 in each sub-pixel is connected to the drain electrode of the second transistor T2 through the 16th through-hole V16 in the corresponding sub-pixel, the first connecting electrode 81 is formed at the position of the 17th through-hole V17 on the second power line VSS in the display area 100, and the first connecting electrode 81 is connected to the second power line VSS through the 17th through-hole V17, and Figure 20 is a cross-sectional view along the AA direction in Figure 19. The drain electrode of the second transistor T2, the drain electrode of the third transistor T3, and the third electrode plate 43 in each subpixel are connected to each other in an integrated structure, thereby realizing a connection between the first anode 70 and the drain electrode of the second transistor T2 in each subpixel. In an exemplary embodiment, the four first anodes 70 can form a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit.

[0122] In an exemplary embodiment, the first anode 70 may include two separate sub-anode blocks and a connection structure respectively connected to the two sub-anode blocks, and the two sub-anode blocks are connected to each other by the connection structure. As shown in Fig. 19, the connection structure may include a first connection electrode 701 and a second connection electrode 702, where the first connection electrode 701 is a "U"-shaped structure, both ends of which are respectively connected to one of the two sub-anode blocks, and the second connection electrode 702 has one end connected to the driving transistor and the other end connected to the first connection electrode 701, so that the two sub-anode blocks are connected to each other via the connection structure.

[0123] When a dark spot or a bright spot appears in any one of the subpixels of the display panel, a part of the first connection electrode 701 in the connection structure can be laser cut, so that one of the two sub-anode blocks from one subpixel can be electrically connected to the driving transistor, and the other sub-anode block is floating, so that the subpixel can be driven normally.

[0124] In an exemplary embodiment, the four first anodes 70 are arranged in a square, the upper left first anode 70 is connected to the third electrode plate 43 of the first subpixel P1 through the 16th through-hole V16 of the first subpixel P1, the upper right first anode 70 is connected to the third electrode plate 43 of the second subpixel P2 through the 16th through-hole V16 of the second subpixel P2, the lower left first anode 70 is connected to the third electrode plate 43 of the third subpixel P3 through the 16th through-hole V16 of the third subpixel P3, and the lower right first anode 70 is connected to the third electrode plate 43 of the fourth subpixel P4 through the 16th through-hole V16 of the fourth subpixel P4. In some possible implementation manners, the arrangement manner of the first anodes 70 in the display area 100 can be adjusted according to actual needs, and the present disclosure is not limited thereto.

[0125] After this patterning process, the transparent area 200 includes a first insulating layer 61 and a second insulating layer 62 stacked on the base substrate 10, a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62, a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2, and a fourth insulating layer 64 and a flat layer 65 provided on the third insulating layer 63.

[0126] (8) Forming an anode pattern. In an exemplary embodiment, forming an anode pattern may include sequentially depositing a fourth metal thin film and a second transparent conductive thin film on the base substrate on which the above-mentioned pattern is formed, patterning the fourth metal thin film and the second transparent conductive thin film by a patterning process, and forming a pattern of a second anode 71, a third anode 72, a second connection electrode 82, and a third connection electrode 83, where the second anode 71 is provided on a side of the first anode 70 away from the base substrate and is connected to the first anode 70, the third anode 72 is provided on a side of the second anode 71 away from the base substrate and is connected to the second anode 71, the second connection electrode 82 is provided on a side of the first connection electrode 81 away from the base substrate and is connected to the first connection electrode 81, and the third connection electrode 83 is provided on a side of the second connection electrode 82 away from the base substrate and is connected to the second connection electrode 82. As shown in Figures 21 and 22, the first anode 70, the second anode 71, and the third anode 72, which are stacked, constitute an anode 74, and the first connection electrode 81, the second connection electrode 82, and the third connection electrode 83, which are stacked, constitute an auxiliary connection electrode, and Figure 22 is a cross-sectional view in the AA direction in Figure 21.

[0127] In an exemplary embodiment, in a plane parallel to the display substrate, the shapes of the second anode 71 and the third anode 72 are similar to the shape of the first anode 70. The orthographic projection of the second anode 71 on the base substrate may be located within the range of the orthographic projection of the first anode 70 on the base substrate, and the orthographic projection of the second anode 71 on the base substrate may be located within the range of the orthographic projection of the third anode 72 on the base substrate. In a plane parallel to the display substrate, the shapes of the second connection electrode 82 and the third connection electrode 83 are similar to the shape of the first connection electrode 81. The orthographic projection of the second connection electrode 82 on the base substrate may be located within the range of the orthographic projection of the first connection electrode 81 on the base substrate, and the orthographic projection of the second connection electrode 82 on the base substrate may be located within the range of the orthographic projection of the third connection electrode 83 on the base substrate.

[0128] In an exemplary embodiment, in a plane perpendicular to the display substrate, the first connection electrode 81 located on the side (lower side) adjacent to the base substrate of the second connection electrode 82 has an edge protruding from the contour of the second connection electrode 82, forming a "pedestal" structure. The third connection electrode 83 located on the side (upper side) away from the base substrate of the second connection electrode 82 has an edge protruding from the contour of the second connection electrode 82. The first connection electrode 81 and the third connection electrode 83 form a "roof eaves" structure. Thus, the first connection electrode 81, the second connection electrode 82, and the third connection electrode 83 stacked and installed form an "I" shape.

[0129] In an exemplary embodiment, the first anode 70 located on the side (lower side) adjacent to the base substrate of the second anode 71 has an edge protruding from the contour of the second anode 71, forming a "pedestal" structure. The third anode 72 located on the side (upper side) away from the base substrate of the second anode 71 has an edge protruding from the contour of the second anode 71, forming a "roof eaves" structure. Thus, the first anode 70, the second anode 71, and the third anode 72 stacked and installed form an "I" shape.

[0130] In an exemplary embodiment, in the process of patterning the fourth metal thin film and the second transparent conductive thin film, a first etching solution and a second etching solution may be adopted to perform etching respectively, and drill etching may be adopted to form the "U"-shaped structure of the auxiliary electrode and the anode. In an exemplary embodiment, the first etching solution may be an etching solution (ITO etching solution) for etching the transparent conductive material, and the second etching solution may be an etching solution (Metal etching solution) for etching the metal material. In an exemplary embodiment, after forming a photoresist pattern through masking, exposing, and developing the photoresist, the etching process may include first using an ITO etching solution to etch the second transparent conductive thin film not covered by the photoresist, exposing the fourth metal thin film in the area not covered by the photoresist, and forming the pattern of the third anode 72 and the third connecting electrode 83, and then using a Metal etching solution to etch the exposed fourth metal thin film to form the pattern of the second anode 71 and the second connecting electrode 82. Since the etching rate of the fourth metal thin film by the Metal etching solution is higher than the etching rates of the first transparent conductive thin film and the second transparent conductive thin film, the side surfaces of the second anode 71 and the second connecting electrode 82 are etched to form concave pits. The first anode 70 below the second anode 71 and the third anode 72 above the second anode 71 both protrude one step from the second anode 71, and the first connecting electrode 81 below the second connecting electrode 82 and the third connecting electrode 83 above the second connecting electrode 82 protrude one step from the second connecting electrode 82, forming an "U" shaped structure.

[0131] In an exemplary embodiment, the material of the fourth metal thin film may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, and the second transparent conductive material may adopt indium tin oxide (ITO) or indium zinc oxide (IZO), etc.

[0132] (9) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include coating a pixel definition thin film on the base substrate on which the above-mentioned pattern is formed, and patterning the pixel definition thin film by a patterning process to form a pixel definition (PDL) layer 91 pattern, as shown in Figures 23 and 24, in which a first pixel opening K1 and a second auxiliary electrode opening K2 are provided in the pixel definition layer 91, the pixel definition layer 91 in the first pixel opening K1 is removed to expose a part of the surface of the third anode 72 of the anode, the pixel definition layer 91 in the second auxiliary electrode opening K2 is removed to expose the entire surfaces of the second connection electrode 82 and the third connection electrode 83 in the auxiliary connection electrode, and Figure 24 is a cross-sectional view in the AA direction in Figure 23.

[0133] In an exemplary embodiment, the orthogonal projection of the first pixel opening K1 on the base substrate is located within the range of the orthogonal projection of the third anode 72 on the base substrate, the orthogonal projection of the second auxiliary electrode opening K2 on the base substrate is located within the range of the orthogonal projection of the first connection electrode 81 on the base substrate, and the orthogonal projection of the second connection electrode 82 and the third connection electrode 83 on the base substrate is located within the range of the orthogonal projection of the second auxiliary electrode opening K2 on the base substrate. "All surfaces of the second connection electrode 82 and the third connection electrode 83 are exposed in the second auxiliary electrode opening K2" means that the second auxiliary electrode opening has a second lower opening on a side adjacent to the base substrate and a second upper opening on a side away from the base substrate, and the orthogonal projection of the second connection electrode 82 and the third connection electrode 83 on the base substrate is located within the range of the orthogonal projection of the second lower opening on the base substrate.

[0134] In an exemplary embodiment, the pixel definition layer may adopt polyimide, acrylic, or polyethylene terephthalate, etc. In a plane parallel to the display substrate, the shape of the first pixel opening K1 may be similar to the shape of the anode blocks, and the shape of the second auxiliary electrode opening K2 may be rectangular. In a plane perpendicular to the display substrate, the cross-sectional shapes of the first pixel opening K1 and the second auxiliary electrode opening K2 may be rectangular, trapezoidal, etc.

[0135] (10) Form an organic light-emitting layer pattern. In an exemplary embodiment, forming the organic light-emitting layer pattern includes evaporating an organic light-emitting material on the base substrate on which the above-mentioned pattern is formed to form an organic light-emitting layer 92 and an organic light-emitting block pattern, as shown in Fig. 25, where the organic light-emitting layer 92 is provided in an area other than the third connection electrode 83, the organic light-emitting layer 92 is connected to the third anode 72 in the anode 74 through the first pixel opening K1, the organic light-emitting block is provided on the surface of the third connection electrode 83 away from the base substrate, and the organic light-emitting block and the organic light-emitting layer 92 are provided separately.

[0136] In some other exemplary embodiments, the organic light-emitting layer pattern may be formed by an inkjet printing method, and the embodiments of the present disclosure are not limited thereto.

[0137] In an exemplary embodiment, due to the "U"-shaped structure of the auxiliary electrode, the third connection electrode 83 protrudes from the second connection electrode 82 by a distance of one step, so that the organic light-emitting material is cut at the side edge of the third connection electrode 83, an organic light-emitting block is formed on the second upper surface of the third connection electrode 83, and an organic light-emitting layer 92 is formed in the area other than the third connection electrode 83, thereby realizing the mutual isolation of the organic light-emitting layer 92 and the organic light-emitting block. In an exemplary embodiment, the orthogonal projection of the organic light-emitting block on the base substrate may be approximately equal to the orthogonal projection of the third connection electrode 83 on the base substrate. The "U"-shaped auxiliary electrode blocks the organic light-emitting layer to form an isolated and isolated organic light-emitting block, which effectively avoids the interference of the organic light-emitting block with the emitted light, improves the quality of the emitted light, and is favorable to improving the display quality.

[0138] In an exemplary embodiment, the organic light-emitting layer may include an emitting layer (EML), a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed by employing a fine metal mask (FMM) or an open mask deposition, or may be formed by employing an inkjet process.

[0139] In an exemplary embodiment, the organic light-emitting layer may be manufactured by adopting the following manufacturing method. First, an open mask is used to sequentially deposit a hole injection layer and a hole transport layer, and a common layer of a hole injection layer and a hole transport layer is formed on the display substrate. Then, a fine metal mask is used to deposit an electron blocking layer and a red light-emitting layer in the red subpixel, an electron blocking layer and a green light-emitting layer in the green subpixel, and an electron blocking layer and a blue light-emitting layer in the blue subpixel, and the electron blocking layer and the light-emitting layer of the adjacent subpixels may have a small overlap (for example, the overlap area of ​​each light-emitting layer pattern is less than 10%) or may be isolated. Then, an open mask is used to sequentially deposit a hole blocking layer, an electron transport layer, and an electron injection layer, and a common layer of a hole blocking layer, an electron transport layer, and an electron injection layer is formed on the display substrate.

[0140] In exemplary embodiments, the electron blocking layer may be the microcavity adjusting layer of the light-emitting device, and the thickness of the electron blocking layer may be designed so that the thickness of the organic light-emitting layer between the cathode and the anode meets the design of the length of the microcavity. In some exemplary embodiments, the hole transport layer, the hole blocking layer, or the electron transport layer in the organic light-emitting layer may be employed as the microcavity adjusting layer of the light-emitting device, and the present disclosure is not limited in this respect.

[0141] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped into the host material, and the doping ratio of the light-emitting layer guest material is 1% to 20%. Within this doping ratio range, on the one hand, the light-emitting layer host material can effectively transfer exciton energy to the light-emitting layer guest material to excite the light emission of the light-emitting layer guest material, and on the other hand, the light-emitting layer host material "dilutes" the light-emitting layer guest material, effectively improving the intermolecular collision of the light-emitting layer guest material and the fluorescence quenching caused by the energy collision, thereby improving the light-emitting efficiency and the device life. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, i.e., mass percent. In an exemplary embodiment, the host material and the guest material may be co-deposited by a multi-source deposition process, and the host material and the guest material may be uniformly distributed in the light-emitting layer, and the doping ratio may be adjusted by controlling the deposition rate of the guest material in the deposition process, or the doping ratio may be adjusted by controlling the deposition rate ratio of the host material and the guest material. In an exemplary embodiment, the thickness of the light-emitting layer may be about 10 nm to 50 nm.

[0142] In an exemplary embodiment, the hole injection layer may employ an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, and may employ a strong electron absorbing p-type dopant and a dopant of a hole transport material. In an exemplary embodiment, the thickness of the hole injection layer may be about 5 nm to 20 nm.

[0143] In an exemplary embodiment, the hole transport layer may employ a material having a relatively high hole mobility, for example, an aromatic amine compound, whose substituent may be carbazole, methylfluorene, spirofluorene, dibenzothiophene, or furan, etc. In an exemplary embodiment, the thickness of the hole transport layer may be about 40 nm to 150 nm.

[0144] In an exemplary embodiment, the hole blocking layer and the electron transport layer may employ aromatic heterocyclic compounds, for example, benzimidazole derivatives, imidazopyridine derivatives, benzimidazopyridine derivatives, and other imidazole derivatives, pyrimidine derivatives, triazine derivatives, and other azine derivatives, quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives, and other compounds containing a nitrogen-containing six-membered ring structure (including compounds having a phosphine oxide-based substituent on the heterocycle), etc. In an exemplary embodiment, the hole blocking layer may have a thickness of about 5 nm to 15 nm, and the electron transport layer may have a thickness of about 20 nm to 50 nm.

[0145] In an exemplary embodiment, the electron injection layer may employ materials such as an alkali metal or metals, for example, lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or compounds of these alkali metals or metals, etc. In an exemplary embodiment, the thickness of the electron injection layer may be about 0.5 nm to 2 nm.

[0146] (11) Form a cathode pattern. In an exemplary embodiment, forming a cathode pattern may include evaporating a cathode material on the base substrate on which the above-mentioned pattern is formed, and forming a cathode 94 pattern, and the cathode 94 is connected to the organic light-emitting layer 92, as shown in FIG.

[0147] In an exemplary embodiment, the cathodes 94 may be integral structures that are in communication with each other. In the region other than the auxiliary connecting electrode, the cathode 94 is provided on the organic light-emitting layer 92. In the region where the auxiliary connecting electrode is located, the cathode 94 is provided on the surface where the organic light-emitting block is exposed on one side, and on the surface where the auxiliary connecting electrode is exposed on the other side, forming a structure that envelops the auxiliary connecting electrode and the organic light-emitting block.

[0148] Up to this point, the manufacture of the light emitting structure layer pattern in the driving circuit layer is completed. The light emitting structure layer includes an anode, an auxiliary connecting electrode, a pixel defining layer, an organic light emitting layer, and a cathode. The organic light emitting layer is respectively connected to the anode and the cathode, the cathode is connected to the auxiliary connecting electrode, and the auxiliary connecting electrode is electrically connected to the second power line via the auxiliary cathode.

[0149] In an exemplary embodiment, the manufacturing process of the display substrate may further include forming a package layer pattern, and forming the package layer pattern may include: first depositing a first inorganic thin film by a plasma-enhanced chemical vapor deposition (PECVD) method using an open mask to form a first package layer; then inkjet printing an organic material on the first package layer using an inkjet printing process, curing and forming a film, and then forming a second package layer; and then depositing a second inorganic thin film using an open mask to form a third package layer, wherein the package layer is composed of the first package layer, the second package layer, and the third package layer. In an exemplary embodiment, the first package layer and the third package layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer, and the second package layer may adopt a resin material to form a laminated structure of inorganic material / organic material / inorganic material, and the organic material layer is disposed between two inorganic material layers to ensure that external water vapor cannot enter the light emitting structure layer.

[0150] In an exemplary embodiment, after the manufacturing of the package layer is completed, a color filter layer and a black matrix may be manufactured on another substrate by a patterning process to form a color filter cover plate, a frame sealant may be applied on the surface of the color filter cover plate, and the color filter cover plate and the above-mentioned display substrate may be pressed together to form an OLED display panel as shown in FIG. 5, in which only the black matrix (BM) is shown and the color filter layer is not shown, and the black matrix has a plurality of opening areas exhibiting a matrix arrangement, and the color filter layer is filled in the opening areas.

[0151] In some other exemplary embodiments, the color filter layer and the black matrix may be fabricated on the display substrate, in which case the color filter layer and the black matrix may be fabricated after forming the cathode and before forming the package layer. The provision of the black matrix can effectively prevent optical crosstalk between adjacent sub-pixels, avoid color mixing, and improve the display effect.

[0152] 5 to 26, in each subpixel, a first transistor T1 is formed from a first active layer 11, a first gate electrode 12, a first source electrode 13, and a first drain electrode 14, a second transistor T2 is formed from a second active layer 21, a second gate electrode 22, a second source electrode 23, and a second drain electrode 24, a third transistor T3 is formed from a third active layer 31, a third gate electrode 32, a third source electrode 33, and a third drain electrode 34, a first capacitor is formed from a first electrode plate 41 and a second electrode plate 42, and a second capacitor is formed from a second electrode plate 42 and a third electrode plate 43, the first capacitor and the second capacitor have a parallel structure, and it is possible to store the potential of the second gate electrode 22 of the subpixel in which it is located. The first transistor T1, the second transistor T2, the third transistor T3, the first capacitor, and the second capacitor in the first subpixel P1 and the second subpixel P2 are mirror-symmetric with respect to the compensation signal line S, and the first transistor T1, the second transistor T2, the third transistor T3, the first capacitor, and the second capacitor in the third subpixel P3 and the fourth subpixel P4 are mirror-symmetric with respect to the compensation signal line S.

[0153] In each subpixel, the first gate electrode 12 is connected to the first scanning signal line G1, the first source electrode 13 is connected to the data signal line D, and the first drain electrode 14 is connected to the second gate electrode 22 of the subpixel in which it is located. The second gate electrode 22 is connected to the first drain electrode 14 of the subpixel in which it is located, the second source electrode 23 is connected to the first power supply line VDD via the lateral power supply connection line 52, and the second drain electrode 24 is connected to the anode of the subpixel in which it is located. The third gate electrode 32 is connected to the second scanning signal line G2, the third source electrode 33 is connected to the compensation signal line S, and the third drain electrode 34 is connected to the second drain electrode 24 of the subpixel in which it is located. The first electrode plate 41 is connected to the second drain electrode 24 and the third drain electrode 34 of the subpixel in which it is located, the second electrode plate 42 is connected to the second gate electrode 22 and the first drain electrode 14 of the subpixel in which it is located, and the third electrode plate 43 is connected to the second drain electrode 24 and the third drain electrode 34 of the subpixel in which it is located. The anode 74 is connected to the second drain electrode 24 of the subpixel in which it is located, and the cathode 94 covering all of the subpixels is connected to the second power supply line VSS via the auxiliary connection electrode, so that the organic light-emitting layer 92 between the anode 74 and the cathode 94 emits light of a corresponding brightness in response to the current of the second drain electrode 24 of the subpixel in which it is located.

[0154] In an exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer may adopt any one or more of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer is called a buffer layer and is used to increase the hydrogen oxide resistance of the base substrate, the second insulating layer is called a gate insulating (GI) layer, the third insulating layer is called an interlayer insulating (ILD) layer, and the fourth insulating layer is called a passivation (PVX) layer. The thickness of the second insulating layer is smaller than that of the third insulating layer, and the thickness of the first insulating layer is smaller than the sum of the thicknesses of the second insulating layer and the third insulating layer, thereby ensuring the insulation effect and increasing the capacitance of the storage capacitor. The planar layer may adopt an organic material, the transparent conductive thin film may adopt indium tin oxide (ITO) or indium tin oxide ITO or indium zinc oxide (IZO), and the pixel definition layer may adopt polyimide, acrylic, or polyethylene terephthalate. The cathode may adopt any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

[0155] In some possible implementations, the first insulating layer has a thickness of 3000 Å to 5000 Å, the second insulating layer has a thickness of 1000 Å to 2000 Å, the third insulating layer has a thickness of 4500 Å to 7000 Å, and the fourth insulating layer has a thickness of 3000 Å to 5000 Å. The first conductive layer has a thickness of 80 Å to 1200 Å, the second conductive layer has a thickness of 3000 Å to 5000 Å, and the third conductive layer has a thickness of 3000 Å to 9000 Å.

[0156] In an exemplary embodiment, the semiconductor layer may employ an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer may be a single layer, or may be a two-layer, or may be a multilayer.

[0157] As shown in FIGS. 5 to 26, the display substrate provided in the present disclosure has: The device includes a base substrate 10, a first conductive layer, a first insulating layer 61, a semiconductor layer, a second insulating layer 62, a second conductive layer, a third insulating layer 63, a third conductive layer, a fourth insulating layer 64, a flat layer 65, an anode 74, an auxiliary connecting electrode, a pixel defining layer 91, an organic light-emitting layer 92, an organic light-emitting block, a cathode 94, and a packaging layer. The first conductive layer is provided on the base substrate 10. The first conductive layer includes a first electrode plate 41 and a compensation signal line S. A first insulating layer 61 covers the first conductive layer. The semiconductor layer is provided on a first insulating layer 61. The semiconductor layer comprises a first active layer 11, a second active layer 21 and a third active layer 31. The second conductive layer is provided on the second insulating layer 62. The second conductive layer includes a first scanning signal line G1, a second scanning signal line G2, a second electrode plate 42, a vertical power supply connection line 51, a horizontal power supply connection line 52, an auxiliary power supply line 53, a first gate electrode 12, a second gate electrode 22, and a third gate electrode 32. The second insulating layer 62 has the same pattern as the second conductive layer, and there is an overlapping region between the orthogonal projection of the second electrode plate 42 on the base substrate 10 and the orthogonal projection of the first electrode plate 41 on the base substrate 10, and the second electrode plate 42 and the first electrode plate 41 form a first capacitor. A third insulating layer 63 is provided to cover the second conductive layer, and a plurality of through holes are provided on the third insulating layer 63. The third conductive layer is provided on the third insulating layer 63. The third conductive layer includes a first power supply line VDD, a second power supply line VSS, a data signal line D, a third scanning connection line 54, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34, and a third electrode plate 43. The first power supply line VDD is connected to the vertical power supply connection line 51 and the horizontal power supply connection line 52 via an eleventh through hole V11, the second power supply line VSS is connected to the auxiliary power supply line 53 via a seventh through hole V7, the first source electrode 13 is integral with the data signal line D, the second source electrode 23 is connected to one end of the second active layer 21 via a third through hole V3, the third source electrode 33 is connected to the compensation signal line S via an eighth through hole V8, and the first drain electrode 14 is The second gate electrode 22 and the second plate 42 are connected via the ninth through hole V9, the second drain electrode 24, the third drain electrode 34, and the third plate 43 are connected to each other to form an integral structure, the third plate 43 is connected to the first plate 41 via the tenth through hole V10, there is an overlapping area between the orthogonal projection of the third plate 43 on the base substrate 10 and the orthogonal projection of the second plate 42 on the base substrate 10, and the second plate 42 and the third plate 43 form a second capacitor. A fourth insulating layer 64 and a flat layer 65 cover the third conductive layer, on which a number of through holes are respectively provided. The anode 74 and the auxiliary connection electrode are provided on the flat layer 65. The anode 74 includes a first anode 70, a second anode 71, and a third anode 72 that are stacked, and the auxiliary connection electrode includes a first connection electrode 81, a second connection electrode 82, and a third connection electrode 83 that are stacked, with the first anode 70 connected to the drain electrode of the second transistor via a sixteenth through-hole V16, and the first connection electrode 81 connected to the second power supply line VSS via a seventeenth through-hole V17. The pixel definition layer 91 is provided on the planar layer 65. The pixel definition layer 91 defines a first pixel opening exposing an anode in each sub-pixel, and the pixel definition layer 91 defines a second auxiliary electrode opening exposing an auxiliary connecting electrode in the second power line VSS. The organic light-emitting layer 92 is disposed in the first pixel opening region. The organic light-emitting block is disposed in the second auxiliary electrode opening region. The organic light-emitting layer 92 is connected to the anode, and the organic light-emitting block and the organic light-emitting layer 92 are disposed separately. The cathode 94 of the display region 100 is connected to the organic light-emitting layer 92, and the cathode of the transparent region is connected to the second power line VSS via an auxiliary connection electrode. A packaging layer covers the above structure.

[0158] In the display substrate according to the embodiment of the present disclosure, when a short-circuit fault occurs between the first and / or second scan connecting lines and other signal lines in the driving circuit layer, the first and / or second scan connecting lines on both sides of the short-circuit fault can be cut by laser cutting to repair the short-circuit fault. For example, as shown in Fig. 27, when a short-circuit fault occurs at an overlapping position of a data signal line and the first scan connecting line, the first scan connecting lines on both sides of the short-circuit fault can be cut by laser cutting to repair the short-circuit fault.

[0159] In the display substrate of the embodiment of the present disclosure, as shown in FIG. 28 , when a short-circuit fault occurs between a certain sub-anode block and another signal line in the driving circuit layer, the position where the first connection electrode in the connection structure is located on the sub-anode block side can be cut by a laser, so that another sub-anode block in the sub-pixel corresponding to the sub-anode block can be electrically connected to the driving transistor, and the sub-anode block can be floated, thereby repairing the short-circuit fault.

[0160] The structure and its manufacturing process shown in the present disclosure are merely exemplary descriptions, and in the exemplary embodiment, the corresponding structure can be modified and the patterning process can be increased or decreased according to actual needs. For example, the display area can have three sub-pixels. Also, for example, the pixel driving circuit can be 5T1C or 7T1C. Also, for example, other electrodes or leads can be provided in the film layer structure, and the present disclosure is not limited thereto.

[0161] As can be seen from the structure and manufacturing flow of the display substrate described above, the display substrate according to the present disclosure designs the first scanning signal line and the second scanning signal line to be annularly wound with the corresponding scanning connecting line in the display area, and the annular winding positions of the first scanning signal line and the second scanning signal line avoid the first power line and the second power line, thereby avoiding the problem that the overlapping area between the power line and other signal lines is large and is likely to affect the yield of the product, and can optimize the crossing points between the signal lines to be minimized while realizing the function of repair, further improving the yield of the product, and providing technical support for transparent display products.

[0162] The display substrate according to the present disclosure employs a second plate made of a metal oxide material as a plate of a storage capacitor, so that the second plate forms a storage capacitor with the first plate in the first conductive layer and the third plate in the third conductive layer, respectively, in which the first plate and the third plate have the same potential, and the second plate has a different potential from the first plate and the third plate, so that two parallel storage capacitors are formed between the first plate, the second plate and the third plate, which effectively increases the capacitance of the storage capacitor and is advantageous for realizing high-resolution display.

[0163] The manufacturing process of the present disclosure can be realized by utilizing existing mature manufacturing equipment, requires only small improvements to the existing process, has good compatibility with the existing manufacturing process, is simple to realize and easy to implement, has high production efficiency, low production cost, and high yield rate. The design of the present disclosure enables repair within the sub-pixel, which more than doubles the yield rate of the product.

[0164] In an exemplary embodiment, the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display (QDLED), and the like, and the present disclosure is not limited in this respect.

[0165] An exemplary embodiment of the present disclosure further provides a method for manufacturing a display substrate, the display substrate may include a plurality of sub-pixels, the method comprising: A plurality of display units are formed on a base substrate, and at least one of the display units includes a display region and a transparent region, and at least one of the display regions is provided with a first power supply line and a second power supply line in a first direction, the first power supply line and the second power supply line extend in a second direction, and at least one of the display regions is provided with a first scanning signal line, a second scanning signal line, a second scanning connection line, and a first scanning connection line in the second direction, and the second scanning connection line and the second scanning signal line are connected to each other to form a first ring structure ... first scanning signal line and the second scanning connection line are connected to each other to form a first ring structure, and at least one of the display regions is provided with a first scanning signal line, a second scanning signal line, a second scanning connection line, and a first scanning connection line in the second direction, and the second scanning signal line and the second scanning connection line are connected to each other to form a first ring structure, and at least one of the display regions is provided with a first scanning signal line, a second scanning signal line, a second scanning signal line, and a first scanning connection line in the second direction, and the first scanning signal line and the second scanning connection line are connected to each other to form a first ring structure, and a third scanning connection line is provided between a scanning signal line and the first scanning connection line, the third scanning connection line, the first scanning connection line, and the first scanning signal line are connected to each other to form a second ring structure, the first direction and the second direction intersect, an orthogonal projection of the first ring structure on the base substrate does not have an overlapping region with an orthogonal projection of the first power supply line and the second power supply line on the base substrate, and an orthogonal projection of the second ring structure on the base substrate does not have an overlapping region with an orthogonal projection of the first power supply line and the second power supply line on the base substrate.

[0166] The embodiments disclosed in the present disclosure are as above, but the description is merely an embodiment adopted for understanding the present disclosure, and is not intended to limit the present invention. Those skilled in the art can make modifications and changes in the implementation form and details without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present invention should be in accordance with the scope described in the claims. [Explanation of symbols]

[0167] 10 Base Board 102 Drive circuit layer 103 Light-emitting structure layer 104 Package Layer

Claims

1. A display substrate comprising: a base substrate; and a plurality of display units provided on the base substrate, the display unit comprising a display region and a transparent region, the display region comprising a plurality of sub-pixels; a first power supply line and a second power supply line are provided in the display area in a first direction, the first power supply line and the second power supply line extend in a second direction, a first scanning signal line, a second scanning signal line, a second scanning connection line, and a first scanning connection line are provided in the display area in the second direction, the second scanning connection line and the second scanning signal line are connected to each other to form a first ring structure, a third scanning connection line is provided in the display area between the first scanning signal line and the first scanning connection line, the third scanning connection line, the first scanning connection line, and the first scanning signal line are connected to each other to form a second ring structure, and the first direction and the second direction intersect, a display substrate, wherein an orthogonal projection of the first ring structure on the base substrate does not overlap with an orthogonal projection of the first power line and the second power line on the base substrate, and an orthogonal projection of the second ring structure on the base substrate does not overlap with an orthogonal projection of the first power line and the second power line on the base substrate.

2. The display substrate of claim 1 , wherein an orthogonal projection of the first ring structure on the base substrate does not overlap with an orthogonal projection of the second ring structure on the base substrate, and an orthogonal projection of the second ring structure on the base substrate envelops an orthogonal projection of the first ring structure on the base substrate.

3. In a direction perpendicular to the display substrate, the sub-pixel includes a driving circuit layer provided on the base substrate and a light-emitting structure layer provided on a side of the driving circuit layer away from the base substrate, the driving circuit layer including a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer; the first conductive layer comprises a compensation signal line and a first plate, the semiconductor layer comprises active layers of a plurality of transistors, the second conductive layer comprises the first scanning signal line, the second scanning signal line, the first scanning connection line, the second scanning connection line, a second plate, and gate electrodes of a plurality of transistors, the third conductive layer comprises the first power supply line, the second power supply line, the third scanning connection line, a data signal line, and source and drain electrodes of a plurality of transistors, and an overlap region exists between an orthogonal projection of the second plate on the base substrate and an orthogonal projection of the first plate on the base substrate, thereby forming a first capacitor; the second scanning connection line and the second scanning signal line are connected to each other to form an integral structure; The display substrate according to claim 1 , wherein the third scanning connection line is electrically connected to the first scanning connection line and the first scanning signal line via a through hole.

4. At least one of the subpixels comprises a first transistor, a second transistor, a third transistor, and a first capacitor, the first capacitor having a first plate and a second plate; 2. The display substrate of claim 1, wherein a gate electrode of the first transistor is electrically connected to the first scanning signal line, a first pole of the first transistor is electrically connected to a data signal line, a second pole of the first transistor is electrically connected to a gate electrode of the second transistor, a first pole of the second transistor is electrically connected to the first power supply line, a second pole of the second transistor is electrically connected to a first pole of an organic electroluminescence diode, a gate electrode of the third transistor is electrically connected to the second scanning signal line, a first pole of the third transistor is electrically connected to a compensation signal line, a second pole of the third transistor is electrically connected to the second pole of the second transistor, a second pole of the organic electroluminescence diode is electrically connected to the second power supply line, the first plate is electrically connected to the second pole of the second transistor, and the second plate is electrically connected to the gate electrode of the second transistor.

5. the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixels and the second sub-pixels are alternately arranged to form a first row in the first direction, the third sub-pixels and the fourth sub-pixels are alternately arranged to form a second row, the first sub-pixels and the third sub-pixels are alternately arranged to form a first column in the second direction, and the second sub-pixels and the fourth sub-pixels are alternately arranged to form a second column, 2 . The display substrate of claim 1 , wherein the first and second scan connecting lines are located in the first and second sub-pixels, and the first and second scan signal lines are located in the third and fourth sub-pixels.

6. At least one of the sub-pixels comprises a first transistor, a second transistor and a third transistor, the first transistor comprising a first active layer, a first gate electrode, a first source electrode and a first drain electrode, the second transistor comprising a second active layer, a second gate electrode, a second source electrode and a second drain electrode, and the third transistor comprising a third active layer, a third gate electrode, a third source electrode and a third drain electrode; an overlapping region between the second scanning signal line and the third active layer in the third sub-pixel and the fourth sub-pixel is a third gate electrode in the third sub-pixel and the fourth sub-pixel, and an overlapping region between the second scanning connection line and the third active layer in the first sub-pixel and the second sub-pixel is a third gate electrode in the first sub-pixel and the second sub-pixel, 6. The display substrate of claim 5, wherein an overlapping region between the first scanning signal line and the first active layer in the third subpixel and the fourth subpixel is a first gate electrode in the third subpixel and the fourth subpixel, and an overlapping region between the first scanning connection line and the first active layer in the first subpixel and the second subpixel is a first gate electrode in the first subpixel and the second subpixel.

7. At least one of the display areas further includes a compensation signal line, the compensation signal line extending in a second direction; 7. The display substrate of claim 6, wherein the first gate electrode, the second gate electrode, and the third gate electrode in the first subpixel and the second subpixel are mirror-symmetric with respect to a vertical axis, and the first gate electrode, the second gate electrode, and the third gate electrode in the third subpixel and the fourth subpixel are mirror-symmetric with respect to a vertical axis, the vertical axis being the compensation signal line.

8. The compensation signal line is provided with a compensation connection line protruding in a first direction and in a direction opposite to the first direction; the compensation connection line is located at a position where the first sub-pixel and the third sub-pixel are adjacent to each other and at a position where the second sub-pixel and the fourth sub-pixel are adjacent to each other; The display substrate of claim 7 , wherein the compensation connection line is electrically connected to the third source electrode of the third transistor through a through hole.

9. 9. The display substrate of claim 8, wherein the third active layers in the first to fourth sub-pixels are all located close to the compensation connecting line, and there is an overlapping region between the orthogonal projection of the third active layer on the base substrate and the orthogonal projection of the compensation connecting line on the base substrate.

10. 9. The display substrate of claim 8, wherein the third active layer in the first sub-pixel and the third active layer in the third sub-pixel are connected to each other and have an integral structure, and the third active layer in the second sub-pixel and the third active layer in the fourth sub-pixel are connected to each other and have an integral structure.

11. 7. The display substrate of claim 6, wherein at least one of the sub-pixels further comprises a first capacitor, the first capacitor comprising a first plate and a second plate arranged opposite each other, the second gate electrode being disposed across the second active layer and being connected to the second plate to form an integral structure.

12. a first electrode plate in the first subpixel is provided with a first opening on a side closer to the third subpixel and farther from the second subpixel, and a first electrode plate in the second subpixel is also provided with the first opening on a side closer to the fourth subpixel and farther from the first subpixel; a first electrode plate in the third subpixel has a second opening on a side close to the first subpixel and close to the fourth subpixel, and a first electrode plate in the fourth subpixel has a second opening on a side close to the second subpixel and close to the third subpixel; 12. The display substrate of claim 11, wherein the first active layers in the first and second sub-pixels are disposed near the first opening, and the first active layers in the third and fourth sub-pixels are disposed near the second opening.

13. 12. The display substrate of claim 11, wherein at least one of the subpixels further comprises a second capacitor, the second capacitor comprising a second plate and a third plate arranged opposite each other, an overlapping area exists between the orthogonal projection of the third plate on the base substrate and the orthogonal projection of the second plate on the base substrate, and the third plate is electrically connected to the first plate via a through hole.

14. A display device comprising the display substrate according to any one of claims 1 to 13.

15. A method for manufacturing a display substrate, comprising the steps of: a display unit including a display region and a transparent region, the display region having a first power supply line and a second power supply line provided in a first direction, the first power supply line and the second power supply line extending in a second direction, the display region having a first scanning signal line, a second scanning signal line, a second scanning connection line, and a first scanning connection line provided in the second direction, the second scanning connection line and the second scanning signal line being connected to each other to form a first ring structure, the display region having a third scanning connection line provided between the first scanning signal line and the first scanning connection line, the third scanning connection line, the first scanning connection line, and the first scanning signal line being connected to each other to form a second ring structure, the first direction and the second direction intersect, an orthogonal projection of the first ring structure on the base substrate does not overlap with an orthogonal projection of the first power supply line and the second power supply line on the base substrate, and an orthogonal projection of the second ring structure on the base substrate does not overlap with an orthogonal projection of the first power supply line and the second power supply line on the base substrate.

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