Imaging apparatus and method for controlling the same, program, and storage medium

Abstract

To provide an imaging apparatus that can reduce a signal reading time when one pixel has a plurality of photoelectric conversion elements.SOLUTION: An imaging apparatus comprises: a pixel part in which pixels having photoelectric conversion elements are arranged in matrix; at least three sample hold circuits that are arranged for pixel signals output from one pixel; voltage-current conversion means that outputs the difference between two sample hold circuits of the at least three sample hold circuits as a current signal; AD conversion means that converts an output signal from the voltage-current conversion means into a digital signal; and control means that, in a period in which it causes one sample hold circuit of the at least three sample hold circuits to hold a first pixel signal obtained from the pixel to perform AD conversion, performs control to start an operation to cause another sample hold circuit of the at least three sample hold circuits to hold a second pixel signal obtained from the pixel.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an imaging apparatus and a control method thereof. [Background technology]

[0002] 2. Description of the Related Art Conventionally, a technique is known in which a single pixel of an image sensor is provided with a plurality of photoelectric conversion elements, and focus detection is performed using output signals from the plurality of photoelectric conversion elements.

[0003] Patent Document 1 discloses an imaging device that enables focus detection using an imaging element in which each pixel has one microlens and multiple photoelectric conversion elements. In Patent Document 1, after a reset signal is read out from each pixel, a signal based on the charge of at least one photoelectric conversion element is read out from each pixel, and then signals based on the charges of multiple photoelectric conversion elements are read out from each pixel.

[0004] Patent Document 2 discloses the following configuration of a photoelectric conversion device. That is, two sample-hold circuits are provided in parallel for one output line, one sample-hold circuit holds a reset signal for each pixel, and the other sample-hold circuit holds a photodetection signal. Then, a current based on the difference between the photodetection signal and the reset signal is output to an AD conversion section, and correction processing is performed by correlated double sampling of the photodetection signal and the reset signal. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5755111 [Patent Document 2] JP 2022-119484 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the configuration described in Patent Document 2, when two sample-and-hold circuits connected to a signal line sample and hold a reset signal read out from each pixel, a signal based on the charge of at least one photoelectric conversion element, and signals based on the charges of multiple photoelectric conversion elements, the following processing is carried out.

[0007] First, a reset signal for each pixel is held in one sample-and-hold circuit, and a signal based on the charge of at least one photoelectric conversion element in each pixel is held in another sample-and-hold circuit. After the signal based on the difference is AD-converted, the signal based on the charge of the multiple photoelectric conversion elements in each pixel is held in the sample-and-hold circuit that holds the signal based on the charge of at least one photoelectric conversion element. Then, the signal based on the difference with the reset signal is AD-converted. In this way, since another AD conversion must be performed after one AD conversion is completed, there is a problem that the readout time is long.

[0008] The present invention has been made in consideration of the above-mentioned problems, and its object is to provide an imaging device that can shorten the signal readout time when one pixel has multiple photoelectric conversion elements. [Means for solving the problem]

[0009] The imaging device of the present invention is characterized in that it comprises a pixel section in which pixels having photoelectric conversion elements are arranged in a matrix, at least three sample and hold circuits arranged for a pixel signal output from one pixel, a voltage-to-current conversion means for outputting the difference between the signals of two of the at least three sample and hold circuits as a current signal, an AD conversion means for converting the output signal of the voltage-to-current conversion means into a digital signal, and a control means for controlling the start of an operation to hold a second pixel signal obtained from the pixel in another of the at least three sample and hold circuits during a period in which a first pixel signal obtained from the pixel is held in one of the at least three sample and hold circuits and AD conversion is being performed. Effect of the Invention

[0010] According to the present invention, when one pixel has a plurality of photoelectric conversion elements, it is possible to reduce the signal readout time. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of an imaging apparatus. [Diagram 2] FIG. 1 is a simplified diagram of the configuration of an image sensor. [Diagram 3] FIG. 2 is an equivalent circuit diagram of a unit pixel. [Figure 4] FIG. 2 is a simplified block diagram of a column circuit. [Diagram 5] FIG. 2 is a diagram showing an example of the configuration of a column circuit. [Figure 6] 4 is a timing chart of a read operation. [Figure 7] FIG. 11 is a simplified block diagram of a column circuit according to a second embodiment. [Figure 8] 6 is a timing chart according to the second embodiment. [Figure 9] FIG. 11 is an equivalent circuit diagram of a unit pixel according to a third embodiment. [Figure 10] FIG. 13 is a simplified block diagram of a column circuit according to a third embodiment. [Figure 11] 10 is a timing chart according to the third embodiment. [Figure 12] FIG. 13 is an equivalent circuit diagram of a unit pixel according to a fourth embodiment. [Figure 13] FIG. 13 is a simplified block diagram of a column circuit according to a fourth embodiment. [Figure 14] 13 is a timing chart according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0013] (First embodiment) 1 is a block diagram showing the configuration of an image capturing apparatus according to an embodiment of the present invention, The image capturing apparatus 100 is an image capturing apparatus capable of performing focus detection on an image capturing surface.

[0014] The lens unit 101 collects incident light from a subject and forms an image of the subject on the image sensor 102. The lens unit 101 is composed of, for example, a plurality of lenses, an aperture, and the like, and a lens driving device 103 performs zoom control, focus control, aperture control, and the like.

[0015] The control circuit 112 controls the image processing of the image processing circuit 109 and part of the driving of the image sensor 102. It also controls the reception of instructions from the display unit 113 and the operation unit 116, and the transfer of data to the memory circuit 111 and the recording unit 110. The control circuit 112 also performs focus detection calculations based on image data from the image processing circuit 109, and causes the lens driving device 103 to adjust the focus by the lens unit 101. The control circuit 112 may be built into the image sensor 102 or the image processing circuit 109, for example.

[0016] The image processing circuit 109 performs development processing such as color matrix processing and gamma processing on the image data from the image sensor 102. In these processes, the image processing circuit 109 stores the image data in the memory circuit 111 as necessary. The image processing circuit 109 then outputs the processed image data to the display unit 113 and the recording unit 110. The display unit 113 includes a display device that displays the processed image data and the like. The operation unit 116 generates an operation signal in accordance with the user's operation. The bus 120 is a common path for the image sensor 102, the image processing circuit 109, the display unit 113, the operation unit 116, the recording unit 110, and the memory circuit 111 to exchange data with one another.

[0017] Fig. 2 is a simplified configuration diagram of the image sensor 102. As shown in Fig. 2, the image sensor 102 has a pixel array section 201, a vertical scanning section 202, a column circuit section 210, and a digital memory section 211. It further has a horizontal scanning section 212, a digital signal processing section 215 (also referred to as DFE: Digital Front End), an output section 216, and a control section 203.

[0018] In the pixel array section 201, a plurality of pixels 21 are arranged in a matrix (rows and columns), with the vertical arrangement being called a “column” and the horizontal arrangement being called a “row.” For the sake of convenience, FIG. 2 shows a portion of the plurality of pixels 21 constituting the pixel array section 201.

[0019] A control signal line 22 is arranged in each row of the pixel array unit 201. Each of the control signal lines 22 includes a plurality of control signal lines for supplying a plurality of types of control signals to each of the plurality of pixels 21. The control signal line 22 in each row is connected to the vertical scanning unit 202.

[0020] A column output line 23 is arranged for each column of the pixel array section 202. The number of column output lines 23 for each column of the pixel array is not limited to one, and may be multiple. The column output lines 23 are connected to a column circuit section 210.

[0021] The vertical scanning unit 202 receives a control signal output from the control unit 203, generates a control signal for driving the plurality of pixels 21, and supplies the control signal to the plurality of pixels 21 via a control signal line 22. The vertical scanning unit 202 uses logic circuits such as a shift register and an address decoder. The vertical scanning unit 202 performs control to select the plurality of pixels 21 in the pixel array unit 201 on a row-by-row basis and read out signals, and outputs the signals of the plurality of pixels 21 to the column circuit unit 210 via the column output lines 23.

[0022] The column circuit section 210 includes a plurality of sample-and-hold circuits for holding signals of the output lines, a plurality of voltage-current conversion circuits, and a plurality of AD converters, and performs signal processing including correlated double sampling and AD conversion. A specific configuration of the column circuit section 210 will be described later.

[0023] The digital memory unit 211 is connected to the column circuit unit 210, and has a function of holding digital signals for each column that have been AD converted by the column circuit unit 210. The digital memory unit 211 is connected to the control unit 203, and receives a control signal from the control unit 203 for holding the digital signals output from the column circuit unit 210.

[0024] The horizontal scanning unit 212 is connected to the control unit 203, and generates a control signal for reading out the digital signal held in the digital memory unit 211 based on a control signal from the control unit 203. Then, the horizontal scanning unit 212 causes the digital signal held in the digital memory 211 to be output to the digital signal processing unit 215.

[0025] The digital signal processing unit 215 performs signal processing such as amplification and correction on the digital signal output from the digital memory unit 211 .

[0026] The output unit 216 is an external interface circuit that is controlled by a control signal from the control unit 203 and outputs a signal input from the digital signal processing unit 215 to the outside. The control unit 203 supplies control signals for controlling the vertical scanning unit 202, the column circuit unit 210, the digital memory unit 211, the horizontal scanning unit 212, and the output unit 216. Note that these control signals do not necessarily need to be supplied from the control unit 203, and may be supplied from outside the image sensor 102.

[0027] Fig. 3 is a simplified equivalent circuit of the pixel 21. As shown in Fig. 3, the pixel 21 has a first photoelectric conversion unit 301, a second photoelectric conversion unit 302, a first transfer transistor 303, and a second transfer transistor 304. In addition, the pixel 21 has a reset transistor 32, an amplification transistor 33, a selection transistor 34, and a floating diffusion unit 31.

[0028] The first transfer transistor 303, the second transfer transistor 304, the reset transistor 32, the amplification transistor 33, and the selection transistor 34 are each configured as, for example, an NMOS transistor, but may be other transistors.

[0029] Each of the pixels 21 has a microlens and a color filter (not shown) on an optical path along which incident light is guided to the first photoelectric conversion unit 301 and the second photoelectric conversion unit 302. The first photoelectric conversion unit 301 and the second photoelectric conversion unit 302 are, for example, photodiodes.

[0030] The first transfer transistor 303 and the second transfer transistor 304 are connected to the first photoelectric conversion unit 301 and the second photoelectric conversion unit 302, respectively. Then, the signals of the corresponding photoelectric conversion elements are transferred to the floating diffusion unit 31, which is the input node of the amplification transistor 33.

[0031] The floating diffusion portion 31 includes a capacitance component (floating diffusion capacitance) formed from wiring capacitance and the like, and functions as a charge holding portion.

[0032] The reset transistor 32 is connected to the floating diffusion portion 31, which is the input node of the amplifying transistor 33, and supplies a reset voltage. The drains of the reset transistor 32 and the amplifying transistor 33 are connected to a power supply voltage node.

[0033] The amplifying transistor 33 amplifies the signal transferred to the floating diffusion portion 31, which is its input node, and outputs the amplified signal to the column output line 23. The selecting transistor 34 controls electrical conduction between the amplifying transistor 33 and the column output line 23.

[0034] A current source 35 is electrically connected to the column output line 23. The current source 35 supplies a bias current to the amplifying transistor 33, and the amplifying transistor 33 and the current source 35 form a source follower.

[0035] A control signal line 22 from the vertical scanning unit 202 is connected to each of the first transfer transistor 303, the second transfer transistor 304, the reset transistor 32, the amplification transistor 33, and the selection transistor 34. The control signal line 22 includes four signal lines to which control signals PTXA, PTXB, PRES, and PSEL are supplied. These four signal lines are provided in common to the pixels 21 belonging to the corresponding rows.

[0036] Of the four signal lines in each row, the signal line for the control signal PTXA is connected to the gate of the first transfer transistor 303 in the pixels 21 in the corresponding row. The signal line for the control signal PTXB is connected to the gate of the second transfer transistor 304. The signal line for the control signal PRES is connected to the gate of the reset transistor 32. The signal line for the control signal PSEL is connected to the gate of the selection transistor 34.

[0037] FIG. 4 is a simplified block diagram of the column circuit 41. The column circuit section 210 is composed of a plurality of column circuits 41. The column circuit 41 is connected to at least one of a plurality of column output lines 23 of the pixel array section 201. In FIG. 4, the column output line 23 is connected to a first sample hold circuit 42, a second sample hold circuit 43, and a third sample hold circuit 44. The first sample hold circuit 42, the second sample hold circuit 43, and the third sample hold circuit 44 each hold the potential of the column output line 23 at a predetermined time according to a plurality of control signals (not shown) supplied from the control section 203. Then, the held potential can be supplied to the voltage-current conversion circuit 45. The first sample hold circuit 42 holds an N signal, which will be described later. The second sample hold circuit 43 holds an A signal, which will be described later. The third sample hold circuit 44 holds an A+B signal, which will be described later.

[0038] The voltage-current conversion circuit 45 switches between a current based on the potential difference between the first sample-hold circuit 42 and the second sample-hold circuit 43 and a current signal based on the potential difference between the first sample-hold circuit 42 and the third sample-hold circuit using a control signal (not shown) supplied from the control unit 203, and outputs the switched current to the AD converter 46.

[0039] The AD converter 46 is an AD converter that converts the output current signal of the voltage-current conversion circuit 45 into a digital signal, but may be connected to a voltage-current conversion circuit of another column circuit to perform AD conversion of the signal output therefrom. The AD converter 46 is, for example, a delta-sigma (ΔΣ) type AD conversion circuit, but is not limited to this.

[0040] 5 is a circuit diagram showing an example of the configuration of the column circuit 41. The first sample and hold circuit 42, the second sample and hold circuit 43, and the third sample and hold circuit 44 are connected to the column output line 23 via a switch 501, a switch 502, and a switch 503, respectively. The switches 501, 502, and 503 are controlled by a control signal (not shown) from the control unit 203, and select which sample and hold circuit holds the potential of the column output line 23.

[0041] The first sample and hold circuit 42, the second sample and hold circuit 43, and the third sample and hold circuit 44 each have a capacitance 504, a capacitance 505, and a capacitance 506 for holding a signal. One end of each capacitance is connected to a switch 501, a switch 502, and a switch 503, and the other end is connected to an inverting amplifier 510, an inverting amplifier 511, and an inverting amplifier 512.

[0042] A switch 507, a switch 508, and a switch 509 are connected between the input node and the output node of the inverting amplifier 510, the inverting amplifier 511, and the inverting amplifier 512, respectively. A switch 513, a switch 514, and a switch 515 are provided between the nodes of the switches 501, 502, and 503 on the opposite side of the column output line 23 and the voltage-current conversion circuit 45. The switch 513 is connected to the wiring 51, and the switches 514 and 515 are connected to the wiring 52. A switch 516, a switch 517, and a switch 518 are provided between the output nodes of the inverting amplifier 510, the inverting amplifier 511, and the inverting amplifier 512, and the voltage-current conversion circuit 45. The switch 516 is connected to a PMOS transistor 521, and the switches 517 and 518 are connected to a PMOS transistor 522.

[0043] The voltage-current conversion circuit 45 includes a current source 520, a resistor 523, a PMOS transistor 521, a PMOS transistor 522, a wiring 51, a wiring 52, and a wiring 53. The current source 520 is disposed between the power supply voltage node and the wiring 51, and the resistor 523 is disposed between the wiring 51 and the wiring 52. The PMOS transistor 522 operating as a source follower is disposed between the wiring 53 and the wiring 52, and the PMOS transistor 521 operating as a source follower is disposed between the wiring 51 and the ground. The voltage-current conversion circuit 45 converts the potential difference between the wiring 51 and the wiring 52 into a current signal, and transfers the current signal to the AD converter 46.

[0044] FIG. 6 is a timing chart showing an example of a read operation of a pixel signal from the pixel 21 to the AD converter 46. In FIG.

[0045] 6 shows control signals PSEL, PRES, PTXA, and PTXB output from the vertical scanning unit 202 to the pixels 21 in one row, and an output potential Vout output from the pixels 21 to the column output line 23 of the corresponding column. In a period before time T1, the control signals PSEL, PRES, PTXA, and PTXB are at a low level (hereinafter referred to as an "L level"). Also, it is assumed that charges corresponding to the amount of incident light are accumulated in the first photoelectric conversion unit 301 and the second photoelectric conversion unit 302. Also, it is assumed that the switches 507, 508, and 509 in the column circuit 41 are closed, and the other switches in the column circuit 41 are open.

[0046] At time T1, the vertical scanning unit 202 controls the control signal PSEL to change from L level to High level (hereinafter referred to as "H level"). This turns on the selection transistor 34, and the source of the amplification transistor 33 is connected to the column output line 23 via the selection transistor 34. At this time, the pixel connected to the column output line 23 is not limited to one pixel, and multiple pixels in different columns or rows performing the same operation may be connected at the same time.

[0047] In a predetermined period from the next time T2, the vertical scanning unit 202 controls the control signal PRES from L level to H level. As a result, the reset transistor 32 is turned on, and the floating diffusion unit 31 is reset to a predetermined potential (reset potential) corresponding to the reference potential. This state is the reset state of the pixel 21. As a result, the output potential Vout of the column output line 23 becomes a potential corresponding to the reset potential of the floating diffusion unit 31. This potential is held as a reset signal (also referred to as "N signal") in the capacitances 504, 505, and 506 by the on / off operation of the switches 501, 502, and 503 during the period from the reset transistor 32 being turned off and the potential of the column output line 23 being settled to time T3. The period from time T2 to time T3 includes the settling time of the column output line 23 and the time for writing the N signal to the capacitances 504, 505, and 506, and is referred to as the "N signal sample hold period."

[0048] In a predetermined period from the next time T3, the vertical scanning unit 202 controls the control signal PTXA from L level to H level. As a result, the first transfer transistor 303 is turned on, the charge accumulated in the first photoelectric conversion unit 301 is transferred to the floating diffusion unit 31, and the floating diffusion unit 31 becomes a voltage according to the amount of charge transferred from the photoelectric conversion unit. As a result, the output potential Vout of the column output line 23 becomes a potential according to the amount of charge transferred to the floating diffusion unit 31. This potential is held in the capacitance 505 as a light detection signal for focus detection (also referred to as "A signal") by the switch 502 performing an on / off operation during the period from the first transfer transistor 303 being turned off and the potential of the column output line 23 being settled to time T4. The period from time T3 to time T4 includes the time when the column output line 23 is settled and the time when the A signal is written to the capacitance 505, and is referred to as the "A signal sample hold period."

[0049] During a predetermined period from the next time T4, a control signal (not shown) output from the control unit 203 turns the switches 507 and 508 to the OFF state and the switches 513, 516, 514, and 517 to the ON state. Here, the wire 51 has a potential based on the N signal held in the capacitance 504, and the wire 52 has a potential based on the A signal held in the capacitance 505. A current according to the potential difference between the wires 51 and 52 flows through the resistor 523, and a current signal that has been corrected by correlated double sampling based on the A signal and the N signal can be extracted from the wire 53 connected to the AD converter 46. The current signal on the wire 53 is input to the AD converter 46 and converted into a digital signal, and the converted digital signal is stored in the digital memory unit 211.

[0050] The period from time T4 until this conversion to a digital signal is referred to as the "A signal AD conversion period."

[0051] In a predetermined period from time T5 in the A signal AD conversion period, the vertical scanning unit 202 controls the control signal PTXA to change from L level to H level. Then, in at least a part of the H level period of the control signal PTXA, the vertical scanning unit 202 controls the control signal PTXB to change from L level to H level so that the control signal PTXB becomes H level. This causes the first transfer transistor 303 and the second transfer transistor 304 to be turned on. Then, the charge accumulated in the first photoelectric conversion unit 301 and the charge accumulated in the second photoelectric conversion unit 302 can be transferred to the floating diffusion unit 31 at the same time. That is, the floating diffusion unit 31 becomes a voltage according to the amount of charge transferred from the two photoelectric conversion units. As a result, the output potential Vout of the column output line 23 becomes a potential according to the amount of charge transferred to the floating diffusion unit 31. This potential is held in the capacitor 506 as a light detection signal for image formation (also referred to as "A+B signal") by the switch 503 turning on and off during the period until time T6 after the first transfer transistor 303 and the second transfer transistor 304 are turned off and the potential of the column output line 23 is stabilized. The period from time T5 to time T6 is referred to as the "A+B signal sample and hold period." The A+B signal sample and hold period starts within the A signal AD conversion period, so that the A signal AD conversion and the A+B signal sample and hold operation are performed in parallel. This makes it possible to speed up the pixel signal readout operation. Here, time T5 may be the same as time T4.

[0052] At the next time T6, the switches 514, 517, and 509 are turned off and the switches 515 and 518 are turned on by a control signal (not shown) output from the control unit 203. Here, the wire 51 has a potential based on the N signal held in the capacitance 504, and the wire 52 has a potential based on the A+B signal held in the capacitance 506. A current according to the potential difference between the wires 51 and 52 flows through the resistor 523. As a result, a current signal that has been corrected by correlated double sampling based on the A+B signal and the N signal can be extracted from the wire 53 connected to the AD converter 46. The current signal on the wire 53 is input to the AD converter 46 and converted into a digital signal, and the converted digital signal is stored in the digital memory unit 211. The period from time T6 to the conversion into this digital signal is referred to as the "A+B signal AD conversion period." Since there is only one AD converter 46, the A+B signal AD conversion period must start after the A signal AD conversion period ends.

[0053] At the following time T7, the vertical scanning unit 202 controls the control signal PSEL to change from H level to L level, thereby turning off the selection transistor 34 and disconnecting the source of the amplification transistor 33 from the column output line 23. When the operation at time T7 and the A+B signal AD conversion period are completed, the operation of reading out the signals of the pixels 21 belonging to that one row via the column output line 23 to the AD converter 46 is completed.

[0054] In the first embodiment, three sample-and-hold circuits are provided. As a result, during the period in which AD conversion of the A signal is being performed using the first sample-and-hold circuit and the second sample-and-hold circuit, the A+B signal can be sampled and held using the third sample-and-hold circuit. This makes it possible to shorten the time required to read out signals from pixels.

[0055] Second Embodiment In the first embodiment described above, one voltage-current conversion circuit and one AD converter are connected to three sample-and-hold circuits, but in this configuration, because there is only one AD converter, AD conversion of the A+B signal must be performed after AD conversion of the A signal. Therefore, if the AD conversion period of the A signal is long, the waiting time from the end of sample-and-holding of the A+B signal to the start of AD conversion of the A+B signal becomes long, and the read time becomes long. The second embodiment differs from the first embodiment in that two voltage-current conversion circuits and two AD converters are provided so that AD conversion can be performed in parallel even when the AD conversion period is long.

[0056] A second embodiment of the present invention will be described with reference to FIGS.

[0057] 7 and 8, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted or simplified.

[0058] 7 is a simplified block diagram showing an example of a column circuit in the second embodiment. A voltage-current conversion circuit 71 and an AD converter 72 are added to the pixel configuration of the first embodiment. The voltage-current conversion circuit 71 is connected to a sample-and-hold circuit 42 that holds an N signal, and a sample-and-hold circuit 44 that holds an A+B signal. The voltage-current conversion circuit 71 outputs a current signal based on the difference between the potentials held in the sample-and-hold circuit 42 and the sample-and-hold circuit 44 to the AD converter 72.

[0059] The voltage-current conversion circuit 45 is connected to the sample-and-hold circuit 42 that holds the N signal, and the sample-and-hold circuit 43 that holds the A signal. The voltage-to-current conversion circuit 45 outputs a current signal based on the difference between the potentials held in the sample-and-hold circuit 42 and the sample-and-hold circuit 43 to the AD converter 46.

[0060] The AD converter 46 and the AD converter 72 convert the input analog current signal into a digital signal, and output it to the digital memory unit 211 .

[0061] 8 is a timing chart showing an example of a pixel signal read operation from a pixel to an AD converter in the second embodiment. The operation from before time T1 to time T4 is the same as in the first embodiment, so a description thereof will be omitted.

[0062] At time T4, the N signal and the A signal are respectively held in sample and hold circuits 42 and 43. From time T4, voltage-current conversion circuit 45 starts outputting a current signal based on the potential difference between the A signal and the N signal to AD converter 46, and AD converter 46 starts converting the current signal to a digital signal. The period from time T4 until the A signal is converted into a digital signal is referred to as the "A signal AD conversion period."

[0063] At the following time T5, the first transfer transistor 303 and the second transfer transistor 304 are turned on. After Vout has settled to the potential of the A+B signal, the sample and hold circuit 44 holds the A+B signal. The time when the sample and hold circuit 44 completes the holding operation of the A+B signal is designated as time T6, and the period from time T5 to time T6 is referred to as the "A+B signal sample and hold period."

[0064] At the following time T6, the voltage-current conversion circuit 71 converts the N signal held in the sample-and-hold circuit 42 and the A+B signal held in the sample-and-hold circuit 44 into a current signal based on the difference in potential between them. Also, the AD conversion circuit 72 starts converting the signal into a digital signal. The period from time T6 to when the AD conversion circuit 72 completes converting the signal into a digital signal is referred to as the "A+B signal conversion period."

[0065] At the following time T7, the selection transistor 34 is turned off and the source of the amplification transistor 33 is disconnected from the column output line 23. When the operation at time T7, the A signal AD conversion period, and the A+B signal AD conversion period end, the operation of reading out the signals of the pixels 21 belonging to that one row via the column output line 23 to the AD converter 46 ends.

[0066] In the second embodiment, even if the A signal AD conversion period has not ended at time T6, two voltage-current conversion circuits and two AD converters are provided, so AD conversion of the A+B signal can be started. Therefore, after time T6, AD conversion of the A signal and AD conversion of the A+B signal can be performed in parallel, making it possible to shorten the read operation period compared to the first embodiment.

[0067] (Third embodiment) In the above-described second embodiment, an example was shown in which two voltage-current conversion circuits and two AD conversion circuits are arranged for three sample-and-hold circuits to perform parallel AD conversion. When this configuration is used, even if the number of signals to be read from the pixels increases, the readout time can be reduced by performing AD conversion in parallel using two AD converters, as in the second embodiment.

[0068] It is known that increasing the number of photoelectric conversion elements contained in one pixel enables focus detection to be performed with higher accuracy, and the third embodiment shows an example in which three types of photodetection signals are read out from the pixel section in addition to a reset signal.

[0069] The third embodiment of the present invention will be described with reference to Figures 9, 10, and 11. In Figures 9, 10, and 11, the same components as those in the first and second embodiments are given the same reference numerals, and the description will be omitted or simplified.

[0070] FIG. 9 is an equivalent circuit diagram of a unit pixel in the third embodiment.

[0071] In addition to the pixel configuration in the first embodiment, the pixel includes a third photoelectric conversion unit 901, a fourth photoelectric conversion unit 902, a third transfer transistor 903, a fourth transfer transistor 904, and a signal line that supplies a control signal PTXC, which is a control signal line 22 connected to the vertical scanning unit 202.

[0072] Unlike the first and second embodiments, by increasing the number of photoelectric conversion elements to four, for example, when arranged in a 2x2 matrix, focus detection signals corresponding to the vertical and horizontal directions can be obtained. The third transfer transistor 903 is arranged between the third photoelectric conversion unit 901 and the floating diffusion unit 31, and the fourth transfer transistor 904 is arranged between the fourth photoelectric conversion unit 902 and the floating diffusion unit 31. The gates of the third transfer transistor 903 and the fourth transfer transistor 904 are connected to a signal line PTXC, and transfer the signal of the corresponding photoelectric conversion element to the floating diffusion unit 31 when the control signal is at H level.

[0073] 10 is a simplified block diagram of a column circuit in the third embodiment. A sample and hold circuit 10 holds a signal A, and then holds a signal A+B+C, which will be described later.

[0074] 11 is a timing chart showing an example of a pixel signal readout operation from a pixel to an AD converter in the third embodiment. The operation from before time T1 to time T6 is the same as in the second embodiment, and therefore a description thereof will be omitted.

[0075] At time T6, unlike the second embodiment, the A signal AD conversion period is assumed to have ended. At this time, the sample-and-hold circuit 10 has completed the AD conversion process for the A signal it had been holding, and is therefore able to hold a new signal. To hold a new signal, the control signals PTXA, PTXB, and PTXC become H level at time T6. As a result, the charges accumulated in the first photoelectric conversion unit 301, the second photoelectric conversion unit 302, the third photoelectric conversion unit 901, and the fourth photoelectric conversion unit 902 are transferred to the floating diffusion unit 31. The floating diffusion unit 31 then has a potential corresponding to the transferred charges.

[0076] Even after the control signals PTXA, PTXB, and PTXC go to the L level, the potential of the floating diffusion portion 31 is maintained, and the amplifier transistor 33 causes the potential Vout of the column output line 23 to be stabilized at a potential corresponding to the potential of the floating diffusion portion 31. After Vout is stabilized, the third photodetection signal (also referred to as the "A+B+C signal") is held in the sample and hold circuit 10 by the sample and hold operation of the sample and hold circuit 10. The period from time T6 to the completion of the sample and hold operation of the A+B+C signal is referred to as the "A+B+C signal sample and hold period."

[0077] On the other hand, time T6 is also the time when the A+B signal sample-and-hold period ends, and from time T6, AD conversion of the A+B signal is performed in the voltage-current conversion circuit 71 and the AD converter 72. The period from time T6 to the end of the AD conversion of the A+B signal is referred to as the "A+B signal AD conversion period." Even if the number of signals to be read out from the pixels is increased compared to the first embodiment, such as the third photodetection signal, the readout time can be shortened by processing the signal sample-and-hold and AD conversion in parallel, as from time T6 onwards. The period from the end of the A+B+C signal sample-and-hold period to the end of the AD conversion of the A+B+C signal is referred to as the "A+B+C signal AD conversion period."

[0078] 11, when the A+B+C signal sample-and-hold period ends during the A+B signal AD conversion period, since the column circuit is provided with two voltage-current conversion circuits and two AD converters, AD conversion of the A+B+C signal can be started using the voltage-current conversion circuit 45 and the AD converter 46. In this way, even if the number of signals to be read out from the pixels increases, the readout time can be shortened by performing AD conversion in parallel using two AD converters as in the second embodiment.

[0079] In the third embodiment, even when three signals are read from a pixel, the readout time can be shortened by using the column circuit configuration of the second embodiment. Specifically, after AD conversion of the first pixel signal is completed (A signal AD conversion period) and sample-holding of the second pixel signal is completed (A+B signal sample-hold period), the third pixel signal is held in the sample-hold capacitance (A+B+C signal sample-hold period). Then, the A+B+C signal sample-hold period and the A+B signal AD conversion period, or the A+B signal AD conversion period and the A+B+C signal AD conversion period are performed in parallel, thereby shortening the readout time.

[0080] (Fourth embodiment) The fourth embodiment is an example in which four sample-and-hold circuits, two voltage-to-current conversion circuits, and two AD converters are provided for one pixel, thereby enabling the readout operation of signals from photoelectric conversion elements to be performed in parallel, thereby shortening the readout time.

[0081] The operation of reading out a signal from a photoelectric conversion element in the fourth embodiment of the present invention will be described below with reference to Figures 12 to 14. Descriptions of the same parts as in the first to third embodiments will be omitted or simplified.

[0082] 12 is an equivalent circuit diagram of a unit pixel in the fourth embodiment. The reset transistor 332 and the reset transistor 322 are connected to the floating diffusion section 331 and the floating diffusion section 321, respectively, and reset the floating diffusion section to a power supply voltage by a control signal PRES. The signals of the photoelectric conversion element 301 and the photoelectric conversion element 302 are connected to the transfer transistor 330 and the transfer transistor 320, respectively. These signals are then transferred to the separate floating diffusion section 331 and the floating diffusion section 321, respectively, by a control signal PTXA output from the vertical scanning circuit 202.

[0083] The amplification transistor 333 amplifies and outputs the signal accumulated in the floating diffusion portion 331 to the column output line 23B. The selection transistor 334 is located between the amplification transistor 333 and the column output line 23B, and controls electrical conduction by a control signal PSEL output from the vertical scanning circuit 202. The amplification transistor 323 amplifies and outputs the signal accumulated in the floating diffusion portion 321 to the column output line 23A. The selection transistor 324 is located between the amplification transistor 323 and the column output line 23A, and controls electrical conduction by a control signal PSEL output from the vertical scanning circuit 202.

[0084] A current source 35B is electrically connected to the column output line 23B. The current source 35B supplies a bias current to the amplification transistor 333, and the amplification transistor 333 and the current source 35B form a source follower.

[0085] A current source 35A is electrically connected to the column output line 23A. The current source 35A supplies a bias current to the amplification transistor 323, and the amplification transistor 323 and the current source 35A form a source follower.

[0086] 13 is a simplified block diagram of a column circuit 141 in the fourth embodiment. A plurality of column circuits 141 are arranged in the column circuit section 210, and each is connected to a corresponding output line of the pixel array section.

[0087] The column output line 23B is connected to a sample hold circuit 144 and a sample hold circuit 145. A voltage-current conversion circuit 147 is connected to the outputs of the sample hold circuit 144 and the sample hold circuit 145, and an AD converter 149 is connected to the output of the voltage-current conversion circuit 147.

[0088] A sample hold circuit 142 and a sample hold circuit 143 are connected to the column output line 23A. A voltage-current conversion circuit 146 is connected to the outputs of the sample hold circuit 142 and the sample hold circuit 143, and an AD converter 148 is connected to the output of the voltage-current conversion circuit 146. The outputs of the AD converter 148 and the AD converter 149 are connected to the digital memory unit 211.

[0089] Fig. 14 is a timing chart showing an example of a read operation from when a signal is output from a pixel until it is AD converted in the fourth embodiment. Fig. 14 shows control signals PSEL, PRES, and PTXA output from the vertical scanning unit 202 to one row, and output potentials VoutA and VoutB output to the column output lines 23A and 23B.

[0090] In the period before time T11, the control signals PSEL, PRES, and PTXA are at a low level. Also, it is assumed that the first photoelectric conversion unit 301 and the second photoelectric conversion unit 302 have accumulated electric charges according to the amount of incident light.

[0091] At time T11, the vertical scanning unit 202 controls the control signal PSEL to change from L level to H level. This turns on the selection transistor 334 and the selection transistor 324. Then, the source of the amplification transistor 333 is connected to the column output line 23B via the selection transistor 334, and the source of the amplification transistor 323 is connected to the column output line 23A via the selection transistor 324.

[0092] During a predetermined period from the next time T12, the vertical scanning unit 202 controls the control signal PRES to change from L level to H level, which turns on the reset transistor 332 and the reset transistor 322, and resets the floating diffusion unit 331 and the floating diffusion unit 321 to a predetermined potential (reset potential) corresponding to the reference potential.

[0093] This state is the reset state of the pixel 21. As a result, the output potentials VoutA and VoutB of the column output line 23A and the column output line 23B become potentials corresponding to the reset potential of the floating diffusion section 331 or the floating diffusion section 321. This potential is sampled and held during the period from when the reset transistors 332 and 322 are turned off and the potentials of the column output line 23B and the column output line 23A become statically settled until time T13. As a result, a reset signal (referred to as an "NA signal") based on the reset potential of the floating diffusion section 321 is held in the sample and hold circuit 142 and the sample and hold circuit 143. The period from time T12 to time T13 includes the statically settled time of the column output line 23A and the time for sampling and holding the NA signal, and is referred to as the "NA signal sample and hold period."

[0094] Moreover, the sample and hold circuit 144 and the sample and hold circuit 145 hold a reset signal (referred to as an "NB signal") based on the reset potential of the floating diffusion portion 331. The period from time T12 to time T13 also includes the reset time of the column output line 23B and the time for sampling and holding the NB signal, and is also referred to as the "NB signal sample and hold period."

[0095] In a predetermined period from the next time T13, the vertical scanning unit 202 controls the control signal PTXA from L level to H level. This turns on the transfer transistor 330, and the charge accumulated in the first photoelectric conversion unit 301 is transferred to the floating diffusion unit 331. Then, the floating diffusion unit 331 becomes a voltage according to the amount of charge transferred from the photoelectric conversion unit. This causes the output potential VoutB of the column output line 23B to become a potential according to the amount of charge transferred to the floating diffusion unit 331. This potential is sampled and held by the sample and hold circuit 145 during the period until time T14 after the transfer transistor 330 turns off and the potential of the column output line 23B becomes statically settled. This signal is held in the sample and hold circuit 145 as a first photodetection signal (also referred to as a "B signal"). The period from time T13 to time T14 includes the settling time of the column output line 23B and the time for writing the B signal to the sample-and-hold circuit 145, and is referred to as the "B signal sample-and-hold period."

[0096] On the other hand, by controlling the control signal PTXA from L level to H level, the transfer transistor 320 is also turned on, and the charge accumulated in the second photoelectric conversion unit 302 is transferred to the floating diffusion unit 321. Then, the floating diffusion unit 321 becomes a voltage according to the amount of charge transferred from the photoelectric conversion unit. As a result, the output potential VoutA of the column output line 23A becomes a potential according to the amount of charge transferred to the floating diffusion unit 321. This potential is sampled and held by the sample and hold circuit 143 during the period from when the transfer transistor 320 is turned off and the potential of the column output line 23A becomes statically settled until time T14. This signal is held in the sample and hold circuit 143 as a second photodetection signal (also referred to as "A signal"). The period from time T13 to T14 includes the statically settled time of the column output line 23A and the time for writing the A signal to the sample and hold circuit 145, and is also referred to as the "A signal sample and hold period."

[0097] During a predetermined period from time T14, a control signal (not shown) output from control unit 203 causes the signals held in sample-and-hold circuit 142 and sample-and-hold circuit 143 to be transmitted to voltage-current conversion circuit 146. A current signal based on the difference between the A signal and the NA signal is output from voltage-current conversion circuit 146 to AD converter 148 as a signal corrected by correlated double sampling.

[0098] The current signal input to the AD converter 148 is converted into a digital signal, and the converted digital signal is stored in the digital memory unit 211. The period from time T14 until this conversion into a digital signal is referred to as the "A signal AD conversion period."

[0099] After time T14, the signals held in sample-and-hold circuit 144 and sample-and-hold circuit 145 are also transmitted to voltage-to-current conversion circuit 147. Then, a current signal based on the differential potential between the B signal and the NB signal is output to AD converter 149 as a signal that has been corrected by correlated double sampling.

[0100] The current signal input to AD converter 149 is converted into a digital signal, and the converted digital signal is stored in digital memory unit 211. The period from time T14 until this conversion into a digital signal is also referred to as the "B signal AD conversion period."

[0101] At the following time T15, the vertical scanning unit 202 controls the control signal PSEL to change from H level to L level. This turns off the selection transistor 334 and the selection transistor 324. Then, the source of the amplification transistor 333 is disconnected from the column output line 23B, and the source of the amplification transistor 323 is disconnected from the column output line 23A. When the operation at time T15, the A signal AD conversion period, and the B signal AD conversion period end, the read operation until the signals of the pixels 21 belonging to that one row are AD converted ends.

[0102] In the fourth embodiment, four sample-and-hold circuits, two voltage-current conversion circuits, and two AD converters are provided for one pixel, which allows the period during which the A signal is sampled and held and AD converted, and the period during which the B signal is sampled and held and AD converted, to be performed in parallel, thereby shortening the readout operation period.

[0103] The disclosure of this specification includes the following imaging device, control method, program, and storage medium.

[0104] (Item 1) a pixel section in which pixels having photoelectric conversion elements are arranged in a matrix; At least three sample and hold circuits are arranged for a pixel signal output from one pixel; a voltage-current conversion means for outputting a difference between two of the at least three sample-hold circuits as a current signal; an AD conversion means for converting an output signal of the voltage-current conversion means into a digital signal; a control means for controlling, during a period in which a first pixel signal obtained from the pixel is held in one of the at least three sample and hold circuits and AD conversion is being performed, to start an operation of holding a second pixel signal obtained from the pixel in another of the at least three sample and hold circuits; An imaging device comprising:

[0105] (Item 2) 2. The imaging device according to item 1, wherein the control means causes the reset signal of the pixel to be held in the at least three sample and hold circuits.

[0106] (Item 3) 3. The imaging device according to item 1 or 2, wherein one of the pixels has a plurality of photoelectric conversion elements.

[0107] (Item 4) The imaging device described in item 3, characterized in that the first pixel signal is a signal based on the charge of at least one photoelectric conversion element of one of the pixels, and the second pixel signal is a signal based on the charge of multiple photoelectric conversion elements of one of the pixels.

[0108] (Item 5) The imaging device described in item 3, characterized in that the first pixel signal is a signal based on the charge of at least one photoelectric conversion element of one of the pixels, and the second pixel signal is a signal based on the charge of another photoelectric conversion element of one of the pixels.

[0109] (Item 6) The imaging device described in item 5, wherein the AD conversion means includes a first AD converter and a second AD converter, and the control means controls the second AD converter to perform AD conversion of the first pixel signal while the first AD converter is performing AD conversion of the first pixel signal.

[0110] (Item 7) The imaging device described in any one of items 1 to 4, characterized in that the AD conversion means includes a first AD converter and a second AD converter, and the control means controls the second AD converter to start an operation of converting the second pixel signal into a digital signal during a period in which the first AD converter is converting the first pixel signal into a digital signal.

[0111] (Item 8) 5. The imaging device according to any one of items 1 to 4, wherein the control means controls the sample-and-hold circuit that has held the first pixel signal to start an operation of holding a third pixel signal after AD conversion of the first pixel signal is completed and sampling and holding of the second pixel signal is completed.

[0112] (Item 9) 9. The imaging device according to any one of items 1 to 8, wherein the AD conversion means comprises a delta-sigma type AD converter.

[0113] (Item 10) 10. The imaging device according to any one of items 1 to 9, wherein the pixel signal is a signal based on signals output from a plurality of pixels.

[0114] (Item 11) A method for controlling an imaging device comprising: a pixel section in which pixels having photoelectric conversion elements are arranged in a matrix; at least three sample-and-hold circuits arranged for a pixel signal output from one pixel; a voltage-current conversion means for outputting a difference between two of the at least three sample-and-hold circuits as a current signal; and an AD conversion means for converting an output signal of the voltage-current conversion means into a digital signal, 13. A control method for an imaging device, comprising: a control step of controlling to start an operation of holding a second pixel signal obtained from the pixel in another sample hold circuit of the at least three sample hold circuits during a period in which a first pixel signal obtained from the pixel is held in one sample hold circuit of the at least three sample hold circuits and AD conversion is being performed.

[0115] (Item 12) Item 12. A program for causing a computer to execute the control method according to item 11.

[0116] (Item 13) A computer-readable storage medium storing a program for causing a computer to execute the control method according to item 11.

[0117] (Other embodiments) The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0118] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0119] 100: imaging device, 101: lens unit, 102: imaging element, 109: image processing circuit, 112: control circuit, 21: pixel, 41: column circuit, 42, 43, 44: sample-and-hold circuit, 45: voltage-current conversion circuit, 46: AD converter, 301, 302: photoelectric conversion unit

Claims

1. A pixel section in which a plurality of pixels, each having a plurality of photoelectric conversion elements, are arranged in a matrix, For a pixel signal output from a single pixel, at least three sample-and-hold circuits are arranged, Voltage-to-current conversion means that outputs the difference between two of the at least three sample-and-hold circuits as a current signal, AD conversion means for converting the output signal of the voltage-current conversion means into a digital signal, Control means for controlling the operation to start holding the second pixel signal obtained from the pixel in one of the other of the at least three sample-and-hold circuits during the period in which AD conversion is being performed by holding the first pixel signal obtained from the pixel in one of the at least three sample-and-hold circuits, An imaging device characterized by comprising:

2. The imaging apparatus according to claim 1, characterized in that the control means causes the reset signal of the pixel to be held in the at least three sample-and-hold circuits.

3. The imaging apparatus according to claim 1, characterized in that the first pixel signal is a signal based on the charge of at least one photoelectric conversion element of one of the pixels, and the second pixel signal is a signal based on the charge of a plurality of photoelectric conversion elements of one of the pixels.

4. The imaging apparatus according to claim 1, characterized in that the first pixel signal is a signal based on the charge of at least one photoelectric conversion element of one of the pixels, and the second pixel signal is a signal based on the charge of another photoelectric conversion element of one of the pixels.

5. The imaging apparatus according to claim 4, wherein the AD conversion means includes a first AD converter and a second AD converter, and the control means controls the second AD converter to perform AD conversion of the first pixel signal while the first AD converter is performing AD conversion of the first pixel signal.

6. The imaging apparatus according to claim 1, wherein the AD conversion means includes a first AD converter and a second AD converter, and the control means controls the second AD converter to start converting the second pixel signal to a digital signal during the period in which the first AD converter is converting the first pixel signal to a digital signal.

7. The imaging apparatus according to claim 1, characterized in that the control means controls the sample-and-hold circuit that was holding the first pixel signal to start an operation to hold the third pixel signal after the AD conversion of the first pixel signal has been completed and the sample-and-hold operation of the second pixel signal has been completed.

8. The imaging apparatus according to claim 1, characterized in that the AD conversion means comprises a delta-sigma type AD converter.

9. The imaging apparatus according to claim 1, characterized in that the pixel signal is a signal based on signals output from a plurality of pixels.

10. A method for controlling an imaging device comprising: a pixel section in which a plurality of pixels, each having a plurality of photoelectric conversion elements, are arranged in a matrix; at least three sample-and-hold circuits arranged for a pixel signal output from one pixel; voltage-to-current conversion means for outputting the difference between two of the at least three sample-and-hold circuits as a current signal; and AD conversion means for converting the output signal of the voltage-to-current conversion means into a digital signal, the method being used to control the imaging device. A control method for an imaging apparatus, characterized by having a control step of controlling the system to start an operation to hold a second pixel signal obtained from the pixel in another sample-and-hold circuit among the at least three sample-and-hold circuits during the period in which the first pixel signal obtained from the pixel is held in one of the at least three sample-and-hold circuits for AD conversion.

11. A program for causing a computer to execute the control method described in claim 10.

12. A computer-readable storage medium storing a program for causing a computer to execute the control method described in claim 10.

Images