Semiconductor device

Abstract

To provide a semiconductor device that enables a high-speed operation, and to provide a highly-reliable semiconductor device.SOLUTION: An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed on the semiconductor layer. The formation of the source region and the drain region is performed on the semiconductor layer by the ion doping method or the ion implantation method of one or a plurality of kinds of elements among rare gases and hydrogen, by using a channel protection layer as a mask.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] Semiconductor device having a circuit including a semiconductor element such as a transistor and a manufacturing method thereof For example, power devices mounted on power circuits, memory, thyristors, converters, inverters, etc. semiconductor integrated circuits including image sensors, electro-optical devices such as liquid crystal display panels, The present invention relates to electronic equipment incorporating a light-emitting display device having optical elements as a component.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices, all of which are semiconductor devices. be. [Background technology]

[0003] As typified by liquid crystal display devices, transistors formed on glass substrates are amorphous. It is made of amorphous silicon, polycrystalline silicon, etc. Although the resulting transistor has low field-effect mobility, it can be used on large glass substrates. In addition, although the field effect mobility of a transistor using polycrystalline silicon is high, the glass substrate is However, it has a drawback that it is not suitable for large area applications.

[0004] A transistor using an oxide semiconductor is manufactured in place of a transistor using silicon. Technologies that can be applied to electronic and optical devices are attracting attention. For example, oxide semiconductors In addition, transistors were fabricated using zinc oxide and In-Ga-Zn oxide, and the display device was Techniques for use in elemental switching elements and the like are disclosed in Patent Documents 1 and 2.

[0005] In Patent Document 3, a staggered transistor using an oxide semiconductor is described. A highly conductive nitride layer is provided between the source and drain regions and the source and drain electrodes as a buffer layer. An oxide semiconductor containing an element is provided, and contacts between the oxide semiconductor and a source electrode and a drain electrode are formed. Techniques for reducing contact resistance have been disclosed.

[0006] In addition, Non-Patent Document 1 describes a method for performing argon plasma treatment on an exposed oxide semiconductor. The matching process reduces the resistivity of the oxide semiconductor in that portion to form the source and drain regions. An oxide semiconductor transistor having an in-region is disclosed.

[0007] However, in this method, the oxide semiconductor surface is exposed and then subjected to argon plasma treatment. By this, the oxide semiconductor in the portions to become the source and drain regions is also etched at the same time. The source region and the drain region are thinned by etching (see FIG. 8 of Non-Patent Document 1). As a result, the resistance of the source and drain regions increases, and the over-energy caused by the thinning increases. The probability of defective products due to etching also increases.

[0008] This phenomenon occurs when the atomic radius of the ion species used in the plasma treatment of the oxide semiconductor is large. This becomes evident.

[0009] Of course, if the oxide semiconductor layer is thick enough, this is not a problem. When the length is set to 200 nm or less, the part that becomes the channel must be thin in order to prevent the short channel effect. The thickness of the oxide semiconductor layer is required to be 20 nm or less, preferably 10 nm or less. When such a thin oxide semiconductor layer is used, the above-mentioned plasma treatment is preferable. Not like that. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2010-135774 A [Non-patent literature]

[0011] [Non-Patent Document 1] S. Jeon et al. “180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application”, IEDM Tech. Dig., p.504, 2010. Summary of the Invention [Problem to be solved by the invention]

[0012] An object of the present invention is to provide a semiconductor device capable of operating at high speed.

[0013] To provide a semiconductor device using transistors in which fluctuations in electrical characteristics due to short channel effects are unlikely to occur. One of our goals is to provide

[0014] In addition, the source and drain regions are formed by a self-alignment process, making it easier to miniaturize the semiconductor. An object of the present invention is to provide a semiconductor device.

[0015] In addition, by forming a source region and a drain region having a lower resistance than the channel portion, The contact resistance with the source electrode and the drain electrode can be reduced, and the on-current can be improved. Another object of the present invention is to provide a semiconductor device having such a structure.

[0016] An object of the present invention is to provide a highly reliable semiconductor device. [Means for solving the problem]

[0017] One embodiment of the present invention is a gate electrode, a gate insulating layer, a crystalline oxide semiconductor layer, A channel protection layer is formed on the gate electrode, and an oxide film is formed on the gate insulation layer. a channel protection layer is formed on the oxide semiconductor layer; and The semiconductor device includes a first oxide semiconductor region and a pair of second oxide semiconductor regions. The oxide semiconductor regions are formed to sandwich a first oxide semiconductor region. The gate electrode is overlapped with a gate insulating layer and is in contact with a channel protection layer. The semiconductor device is as follows.

[0018] In another embodiment of the present invention, a gate insulating layer is provided which is formed by stacking a gate insulating layer and a gate electrode. The oxide semiconductor layer has a first oxide semiconductor region and a pair of second oxide semiconductor regions. a pair of second oxide semiconductor regions are formed with a first oxide semiconductor region therebetween. The first oxide semiconductor region overlaps with the gate electrode via a gate insulating layer. This is a semiconductor device having the following characteristics.

[0019] A non-single-crystal semiconductor is used for the oxide semiconductor layer.

[0020] The first oxide semiconductor region is a C Axis Aligned Crystalline Crystal (CAAC-OS) (Talline Oxide Semiconductor). CAAC-OS is a vector in which the c-axis is parallel to the normal vector of the CAAC-OS surface or the normal vector of the surface. The atomic arrangement is aligned in the direction and has a triangular or hexagonal shape when viewed from the direction perpendicular to the ab plane. When viewed from a direction perpendicular to the c-axis, metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. It has crystalline parts.

[0021] The second oxide semiconductor region contains at least one element selected from a rare gas and hydrogen (H). 5×10 19 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 Contains the following concentrations: nothing.

[0022] The oxide semiconductor may contain two or more elements selected from the group consisting of In, Ga, Sn, and Zn. Cut.

[0023] The first oxide semiconductor region serves as a channel formation region of a transistor, and the pair of second oxide semiconductor regions The semiconductor regions become the source and drain regions of the transistor.

[0024] In a bottom gate transistor, the source and drain regions are The protective layer is used as a mask to add a dopant to the oxide semiconductor layer. The panel protection layer is formed to protect the back channel portion of the active layer and is made of silicon oxide. A material selected from silicon nitride, aluminum oxide, aluminum nitride, etc. is used as a single layer or It is preferable to use the same in a laminated state.

[0025] In a top-gate transistor, the source region and the drain region are connected to a gate electrode. The insulating film can be formed by adding a dopant to the oxide semiconductor layer using the insulating film as a mask.

[0026] The addition of dopants to form the source and drain regions of a transistor is done by ion implantation. A doping method or an ion implantation method can be used. The catalyst can be one or more of the following elements: rare gases or hydrogen (H). In addition, oxide can be grown by ion doping or ion implantation. When dopants are added to the semiconductor layer, the dopants are introduced through the insulating layer to the oxide semiconductor layer. By adding dopants to the oxide semiconductor layer, excessive damage to the oxide semiconductor layer caused by doping the dopant can be reduced. In addition, the interface between the oxide semiconductor layer and the insulating layer is kept clean. The characteristics and reliability of the MOSFET are improved. In addition, the doping depth (doped region) of the dopant is easier to control. This allows the dopant to be added to the oxide semiconductor layer with high precision.

[0027] Increasing the concentration of the dopant increases the carrier density in the oxide semiconductor region. However, if the concentration of the dopant is too high, it will hinder the movement of carriers and cause electrical conductivity to decrease. This will reduce sexuality.

[0028] By using an oxide semiconductor to which a dopant is added for the source and drain regions, This has the effect of reducing the bending of the band edge in the channel formation region where no dopants are added. On the other hand, when the source region and the drain region are made of a metal material, the oxide semiconductor The bending of the band edge of the channel region cannot be ignored, and the effective channel length becomes shorter. This tendency is more pronounced when the channel length of a transistor is short. do.

[0029] Highly purified acid with reduced impurities such as water or hydrogen, which act as electron donors. The oxide semiconductor (purified OS) then supplies oxygen to the oxide semiconductor. By reducing oxygen vacancies in the oxide semiconductor, it becomes an i-type (intrinsic semiconductor) or a semiconductor as close to i-type as possible. Therefore, a channel can be formed in the oxide semiconductor. A transistor using an i-type or substantially i-type oxide semiconductor for a semiconductor layer to be Specifically, a highly purified oxide semiconductor has the following characteristics: , Secondary Ion Mass Spectrometry (SIMS) The hydrogen concentration measured by hydrogen trometry was 5×10 18 / cm 3 Less than, preferably 1×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 The following is more preferable: is 1×10 16 / cm 3 In addition, the following is true: Type i or The carrier density of the oxide semiconductor layer that is substantially i-type is 1×10 14 / cm 3 Less than, good Preferably 1×10 12 / cm 3 less than 1×10 11 / cm 3 is less than In addition, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably 1.5 eV or more. The semiconductor layer in which the channel is formed is preferably an i-type or substantially The off-state current of a transistor can be reduced by using an i-type oxide semiconductor. can.

[0030] Here, the SIMS analysis of the hydrogen concentration in the oxide semiconductor will be described. In principle, it is difficult to obtain accurate data near the sample surface or near the interface between layers of different materials. It is known that it is difficult to obtain a hydrogen concentration distribution in the thickness direction of the film. When analyzing fabrics with SIMS, extreme fluctuations in values ​​can occur in areas where the film of interest is present. The average value in the region where the hydrogen concentration is almost constant is adopted as the hydrogen concentration. When the thickness of the film to be measured is small, the hydrogen concentration in the adjacent film affects the measurement. In some cases, it may not be possible to find a region where a constant value is obtained. In this case, The maximum or minimum value of the hydrogen concentration in the film is adopted as the hydrogen concentration in the film. In the region where the film exists, a mountain-shaped peak having a maximum value and a valley-shaped peak having a minimum value are formed. If no peak is present, the value at the inflection point is taken as the hydrogen concentration. Effect of the Invention

[0031] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics and which can be easily miniaturized is used. It is possible to provide a semiconductor device having such a structure.

[0032] Also, the present invention provides a semiconductor device in which fluctuations in electrical characteristics due to short channel effects are unlikely to occur.

[0033] In addition, by adding a dopant to the oxide semiconductor through the insulating layer, This prevents the thinning of the oxide semiconductor and keeps the interface between the oxide semiconductor and the insulating layer clean, improving the characteristics of the semiconductor device. This can improve the reliability and performance. [Brief description of the drawings]

[0034] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Diagram 2] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Diagram 5] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 7] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 9] 1A to 1C are diagrams illustrating band structures of an oxide semiconductor and a metal material. [Figure 10] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 11] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 13] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 14] FIG. 2 is a block diagram showing a specific example of a CPU and a circuit diagram of a portion thereof. [Figure 15] 1A to 1C are diagrams illustrating the crystal structure of an oxide material. [Figure 16] 1A to 1C are diagrams illustrating the crystal structure of an oxide material. [Figure 17] 1A to 1C are diagrams illustrating the crystal structure of an oxide material. [Figure 18] 1A to 1C are diagrams illustrating the crystal structure of an oxide material. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made thereto. The present invention is not limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings. These are commonly used, and their repeated explanations will be omitted.

[0036] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0037] In addition, the terms "first," "second," "third," etc., used in this specification are used interchangeably to avoid confusion of components. The number is not limited to the number of the first one. For example, "first one" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0038] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0039] In addition, the functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it.

[0040] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0041] (Embodiment 1) In this embodiment, a transistor including an oxide semiconductor for a channel and a manufacturing method thereof will be described. This will be described with reference to FIG. 1 to FIG.

[0042] FIG. 1A illustrates a structure of a transistor 100, which is one embodiment of a semiconductor device. FIG. 1(B) is a side view of the laminated structure of the portion indicated by the dashed line A1-A2 in FIG. 1(A). 1(A) is a cross-sectional view showing the structure of the semiconductor device according to the present invention. .

[0043] The transistor 100 shown in FIG. 1 has a base layer 102 formed on a substrate 101. An oxide semiconductor layer 103 is formed on the gate electrode 2. An insulating layer 104 is formed, and a gate electrode 105 is formed on the gate insulating layer 104 . Further, an insulating layer 107 and an insulating layer 108 are formed on the gate electrode 105. , a source electrode 110a and a drain electrode 110b are formed. The drain electrode 110b is provided on the gate insulating layer 104, the insulating layer 107, and the insulating layer 108. The contact hole 109 is electrically connected to the oxide semiconductor layer 103. There are.

[0044] The oxide semiconductor layer 103 is a channel that overlaps with the gate electrode 105 via the gate insulating layer 104. a source region 103a electrically connected to a source electrode 110a; , and has a drain region 103b electrically connected to a drain electrode 110b.

[0045] The gate electrode 105 includes a gate electrode 105a in contact with the gate insulating layer 104 and a gate It has a gate electrode 105b laminated on the electrode 105a.

[0046] In FIG. 1A, the contact hole 109 is formed in the source region 103a and the drain region 103b. In the example shown, a plurality of the source regions 103a and drain regions 103b are provided. Alternatively, one each of the source electrode 110a and the source electrode 110b may be provided on each of the regions 103b. The contact resistance of the source region 103a and the contact resistance of the drain electrode 110b and the drain region 103b In order to reduce the resistance, the contact hole 109 is as large as possible. It is preferable to have a large number of 09s.

[0047] The transistor 140 shown in FIG. 2 has the same configuration as the transistor 100, but has a gate electrode 10 The sidewall 111 of the oxide semiconductor layer 103 is provided on the side surface of the oxide semiconductor layer 103. The low-concentration region 103d and the low-concentration region 103e are located in the region overlapping the low-concentration region 103a. The region 103d is formed between the channel forming region 103c and the source region 103a. The region 103e is formed between the channel forming region 103c and the drain region 103b. FIG. 2A is a top view illustrating a structure of a transistor 140. FIG. 2A is a cross-sectional view illustrating the laminated structure of the portion indicated by the dashed line B1-B2 in FIG.

[0048] By providing the low concentration region 103d and the low concentration region 103e, the deterioration of the transistor characteristics is suppressed. This can reduce the negative shift in threshold voltage due to the short channel effect.

[0049] The transistor 100 and the transistor 140 are types of transistors with a top gate structure. It is an attitude.

[0050] Next, a method for manufacturing the transistor 100 shown in FIG. 1 will be described with reference to FIGS. 3 and 4 correspond to the cross section of the portion indicated by the dashed line A1-A2 in FIG. 1(A). do.

[0051] First, a base layer 102 is formed on a substrate 101 with a thickness of 50 nm to 300 nm, preferably 100 nm. The substrate 101 is a glass substrate, a ceramic substrate, or the like. In addition, a plastic substrate or the like that has sufficient heat resistance to withstand the processing temperature of this manufacturing process is used. In addition, when the substrate does not need to be transparent, a metal substrate such as a stainless steel alloy may be used. The glass substrate may be, for example, a barium phosphide substrate. Non-alkali glass such as borosilicate glass, aluminoborosilicate glass or aluminosilicate glass A glass substrate is preferably used. Alternatively, a quartz substrate or a sapphire substrate can be used. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, silicon It is also possible to apply compound semiconductor substrates such as germanium and SOI substrates. Any of these substrates on which semiconductor elements are provided may be used as the substrate 101 .

[0052] The underlayer 102 may be made of aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum oxynitride. Aluminum nitride, silicon nitride, silicon oxide, silicon nitride oxide or silicon oxynitride The material selected from the above can be formed in a single layer or a laminated layer, and the non-uniformity from the substrate 101 can be eliminated. It has a function of preventing the diffusion of pure elements. The composition of the material contains more nitrogen than oxygen, and the term oxynitride refers to the composition of the material. The composition of the alloy is such that the oxygen content is greater than the nitrogen content. The content of each element is, for example, , Rutherford Backscattering Spectroscopy (RBS) It can be measured using techniques such as Fluorescence Induction Spectrometry (FDI).

[0053] The underlayer 102 can be formed by appropriately using a sputtering method, a CVD method, a coating method, a printing method, or the like. In this embodiment, a laminate of silicon nitride and silicon oxide is used as the underlayer 102. Specifically, silicon nitride is formed on the substrate 101 to a thickness of 50 nm. Silicon oxide is formed on the silicon substrate to a thickness of 150 nm. ) or boron (B) may be doped.

[0054] In addition, by making the underlayer 102 contain halogen elements such as chlorine and fluorine, the substrate 101 The function of preventing the diffusion of impurity elements from the substrate can be further improved. The concentration of halogen elements to be added was obtained by analysis using a SIMS (secondary ion mass spectrometer). At the concentration peak, 1×10 15 / cm 3 More than 1×10 20 / cm 3 Below Good.

[0055] The underlayer 102 may be made of a material that releases oxygen when heated. "Emitted from the atmosphere" refers to the TDS (Thermal Desorption Spectro Thermal desorption spectroscopy (TDA) analysis showed that the amount of oxygen released, calculated as oxygen atoms, was 1. 0×10 18 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 This means that the above is the case.

[0056] Here, the method for measuring the amount of released oxygen converted into oxygen atoms in TDS analysis is as follows: will be explained.

[0057] The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. The amount of gas released is calculated based on the ratio of the integral value of the spectrum of the layer to the reference value of the standard sample. The reference value of the standard sample is the integral of the spectrum of the sample containing a specific atom. is the ratio of the atomic density to the value.

[0058] For example, the results of a TDS analysis of a silicon wafer containing a specific density of hydrogen as a standard sample, From the results of TDS analysis of the insulating layer, the amount of oxygen molecules released from the insulating layer (N O2 ) is calculated using formula 1. Here, all of the spectra detected at mass number 32 obtained by TDS analysis are It is assumed that the mass number of the molecule is 32. There is CH3OH, but there is no known The oxygen atom isotope with mass number 17, which is not considered here. The abundance ratio of oxygen molecules, including the atomic and mass number 18 oxygen atoms, in nature is Not taken into consideration as it is a very small amount.

[0059] N O2 =N H2 / SH2 ×S O2 ×α (Formula 1)

[0060] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the spectrum obtained when the sample was subjected to TDS analysis. H2 / S H2 Let us assume that S O2 is the integral value of the spectrum obtained by TDS analysis of the insulating layer. α is a coefficient that affects the spectral intensity in the TDS analysis. For details of Equation 1, For details, see Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released from the insulating layer is A thermal desorption analyzer EMD-WA1000S / W manufactured by Electron Science Corporation was used to measure the standard sample and 1×10 16 atoms / cm 3 The measurement was performed using a silicon wafer containing hydrogen atoms. .

[0061] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen molecules is included in the calculation, the amount of oxygen atoms released can be calculated by evaluating the amount of oxygen molecules released. It is possible to estimate even if

[0062] In addition, N O2 is the amount of oxygen molecules released. In the insulating layer, when converted to oxygen atoms, The amount of oxygen released is twice as much as the amount of oxygen molecules released.

[0063] In the above structure, the insulating layer from which oxygen is released by heating is silicon oxide (S iO X (X>2)) or silicon oxide (SiOX (X>2) It contains more than twice as many oxygen atoms as silicon atoms per unit volume. The number of silicon atoms and oxygen atoms per volume were measured by Rutherford backscattering spectrometry. value.

[0064] When oxygen is supplied from the underlayer to the oxide semiconductor, the interface state between the underlayer and the oxide semiconductor is As a result, the electric charges that may be generated due to the operation of the transistors can be reduced. Therefore, the deterioration of electrical characteristics can be prevented. Therefore, a transistor with little distortion can be obtained.

[0065] Furthermore, charges may be generated due to oxygen vacancies in oxide semiconductors. Oxygen deficiency in the body produces electrons that act as donors and carriers. The threshold voltage of the transistor shifts in the negative direction. In this specification, the back channel is a channel formed by oxidation. In oxide semiconductors, this refers to the vicinity of the interface of the underlayer. Sufficient oxygen is released from the underlayer to the oxide semiconductor. This leads to a shift in the threshold voltage in the negative direction. It can compensate for oxygen deficiency.

[0066] That is, when oxygen vacancies occur in the oxide semiconductor, the charge at the interface between the underlayer and the oxide semiconductor increases. It is difficult to suppress the capture of oxygen. By providing the oxide semiconductor layer, the interface state between the oxide semiconductor layer and the underlayer and the oxygen vacancies in the oxide semiconductor layer can be reduced. This can reduce the effect of charge trapping at the interface between the oxide semiconductor and the underlayer. Cut.

[0067] The base layer 102 is made of an insulating material containing the same components as the oxide semiconductor to be formed later. In the case where the base layer 102 is a stack of different layers, the layer in contact with the oxide semiconductor may be An insulating material containing the same components as the oxide semiconductor may be used. By using this for the base layer 102, the state of the interface with the oxide semiconductor can be improved. Here, the term "component of the same kind as the oxide semiconductor" means an oxide It means one or more elements selected from the constituent elements of a semiconductor. For example, an oxide semiconductor When the semiconductor is made of In-Ga-Zn oxide semiconductor material, the insulating material containing the same material is The material used for the interface is gallium oxide.

[0068] Next, an oxide semiconductor is formed on the base layer 102. In order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture, the preheating chamber of the deposition equipment is The substrate 101 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 101 and the underlayer 102. It is preferable to desorb and exhaust the gas from the preheating chamber. It is preferable that the preheating step is omitted. The same treatment may be performed on the substrate 101 before the formation of the underlayer 102 .

[0069] The oxide semiconductor must contain at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. In addition, a gas is used as a stabilizer to reduce the variation in the electrical characteristics of the transistors. It is preferable that the alloy contains tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf) as a stabilizer. It is also preferable to have aluminum (Al) as a stabilizer.

[0070] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0071] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0072] The oxide semiconductor layer is preferably an oxide semiconductor containing In, more preferably In, and an oxide semiconductor containing Ga.

[0073] Here, for example, the In-Ga-Zn oxide is an oxide of indium (In), gallium (Ga ), and zinc (Zn) is included in the oxide. The ratio of In, Ga, and Zn does not matter. Moreover, metal elements other than In, Ga, and Zn may be contained.

[0074] The oxide semiconductor layer has the chemical formula InMO3(ZnO) m A thin film expressed as (m>0) Here, M is selected from Sn, Zn, Ga, Al, Mn and Co. The oxide semiconductor is In3SnO5(Zn O) n Materials expressed as (n>0) may also be used.

[0075] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In--Sn--Zn-based oxide having an atomic ratio or an oxide having a composition close to that.

[0076] However, the present invention is not limited to these, and can be applied to any semiconductor characteristics (mobility, threshold, variation, etc.) required. In order to obtain the required semiconductor characteristics, the appropriate composition should be used. Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the above appropriate.

[0077] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0078] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1) is in the vicinity of the oxide composition when a, b, and c are (a-A) 2 +(b-B) 2 +(c-C) 2 ≦r 2 The above condition is satisfied, and r can be set to, for example, 0.05. The same is true for other oxides. .

[0079] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. That's fine too.

[0080] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0081] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility equal to or higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably The thickness of the surface is preferably 0.1 nm or less. It can be evaluated using an Atomic Force Microscope.

[0082] As an example of a crystalline oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor is preferred. The AAC-OS is neither completely single crystalline nor completely amorphous. The oxide semiconductor has a crystalline-amorphous mixed phase structure in which a crystalline portion is included in the crystalline phase. The size of the electrodes is often within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the image of e), the boundary between the amorphous and crystalline parts in the CAAC-OS is not clear. In addition, grain boundaries were not observed in CAAC-OS by TEM. ) was not observed. Therefore, it is considered that the decrease in electron mobility due to grain boundaries is suppressed in CAAC-OS. To be controlled.

[0083] The crystal part in the CAAC-OS has a c-axis that is perpendicular to the normal vector of the CAAC-OS surface. or parallel to the surface normal vector and triangular when viewed from the direction perpendicular to the ab plane. Or it has a hexagonal atomic arrangement, and the metal atoms are layered or metallic when viewed from the direction perpendicular to the c-axis. The a-axis and oxygen atoms are arranged in layers. The direction of the b-axis may be different. In this specification, when it is simply described as vertical, it means 85°. Also, when simply describing it as parallel, it means that the angle is -5° or less. This also includes a range of up to 5°.

[0084] In the CAAC-OS, the distribution of the crystal parts may not be uniform. In the process of forming an OS, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the bottom. By adding impurities to the -OS, the crystalline part in the impurity-added region becomes amorphous. This may also occur.

[0085] The c-axis of the crystalline part in the CAAC-OS is aligned along the normal vector of the CAAC-OS surface. Since the CAAC-OS shape (cross-section of the surface on which it is formed) is Depending on the surface shape or cross-sectional shape of the surface, the directions may differ from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS is formed or The direction is parallel to the normal vector of the surface. The crystal part is formed by or after the film is formed. The film is formed by subjecting the film to a crystallization treatment such as a heat treatment.

[0086] CAAC-OS can be a conductor, a semiconductor, or an insulator depending on its composition. Also, depending on the composition, it may be transparent or opaque to visible light. A part of CAAC-OS may be substituted with nitrogen.

[0087] Transistors using CAAC-OS are able to withstand changes in electrical characteristics caused by exposure to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0088] An example of a crystal structure contained in CAAC-OS will be described in detail with reference to FIGS. 15 to 17. In addition, unless otherwise specified, the upward direction in Fig. 15 to Fig. 17 is the c-axis direction, The plane perpendicular to the ab plane is called the ab plane. Note that when simply referring to the upper and lower halves, the ab plane is used as the boundary. In addition, in Figure 15, the circled O indicates a 4-coordinate O. The double circled O indicates a three-coordinate O.

[0089] In Figure 15(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has one metal atom and one nearby oxygen atom. The structure shown in Fig. 15(A) is an octahedral structure, but it is easy to For simplicity, the structure is shown in a plan view. There are three O atoms in each group that are 4-coordinated. The small group shown in Figure 15(A) has a zero charge.

[0090] In Figure 15(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom are shown. The structure shows a structure having a 4-coordinated O atom and two 4-coordinated O atoms adjacent to Ga. The 3-coordinated O atom is Both exist on the ab plane. There are four of them, one each in the upper and lower halves of Figure 15(B). In addition, since In also has a 5-coordination, the structure shown in Figure 15(B) can be formed. The small group shown in FIG. 15(B) has a charge of 0.

[0091] FIG. 15(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 15(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in the upper half of Fig. 15(C), there are three 4-coordinate Os, and in the lower half, there is one There may be four-coordinated O. The small group shown in Figure 15(C) has a zero charge.

[0092] FIG. 15(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 15(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 15(D) has a charge of +1.

[0093] Figure 15(E) shows a small group containing two Zn atoms. The upper half of Figure 15(E) shows one Zn atom. The small group shown in Figure 15(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0094] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a These are called large groups (also called unit cells).

[0095] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the 6-coordinate In have three adjacent In atoms downward, and the lower half The three O atoms each have three adjacent In atoms in the upward direction. One O in the upper half of a has one adjacent Ga in the downward direction, and one O in the lower half has one adjacent Ga in the upward direction. The one O in the upper half of the 4-coordinated Zn shown in FIG. The three Os in the lower half have one adjacent Zn in the upward direction, and the three Os in the upper half have three adjacent Zn in the upward direction. Thus, the number of tetracoordinated oxygen atoms above a metal atom and the number of neighboring oxygen atoms below the oxygen atom are The number of metal atoms is equal, and similarly, the number of 4-coordinated O atoms below the metal atom and the number of O atoms above the O atoms are The number of adjacent metal atoms is equal. Since O is 4-coordinated, the number of adjacent metal atoms below is equal to the number of adjacent metal atoms above. The sum of the number of adjacent metal atoms in the direction is 4. Therefore, the number of 4-coordinated atoms in the direction above the metal atom is When the sum of the number of O atoms and the number of O atoms below another metal atom is 4, the metal atom is Two small groups can be bonded together. For example, a 6-coordinate metal atom (In or Sn) is bonded through the lower half of the tetracoordinate O, there are three tetracoordinate Os, , bound to either a five-coordinate metal atom (Ga or In) or a four-coordinate metal atom (Zn). It will be combined.

[0096] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0097] Figure 16(A) shows a model diagram of the middle group that constitutes the layered structure of the In-Sn-Zn oxide. FIG. 16B shows a large group consisting of three medium groups. FIG. 16C shows the atomic arrangement when the layer structure of FIG. 16B is observed from the c-axis direction.

[0098] In FIG. 16(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 16(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is indicated by the circle 1. Similarly, in Figure 16 In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0099] In FIG. 16(A), the middle group, which is made up of a layer structure of In-Sn-Zn oxide, is Sn has three tetrahedral O atoms in the upper half and one tetrahedral O atom in the lower half. It bonds to In in the upper and lower halves, and the In has three tetracoordinate O in the upper half. It bonds to Zn, and three tetracoordinate O atoms are bonded to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. The In is bonded to a Zn atom with one tetracoordinated O in the upper half. It bonds to a small group of two via a tetracoordinate O in the lower half of this small group. The structure is such that three tetracoordinate O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple groups combine to form larger groups.

[0100] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67, -0.5. For example, In (6 or 5 coordinates), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. The structure shown in Figure 1 shows a structure that can take a charge of -1. As shown in Figure 5(E), a small group of compounds containing two Zn atoms can be mentioned. For example, Sn-containing compounds If there is one small group with two Zn atoms per small group, the charges are cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0101] Specifically, the large group shown in FIG. 16(B) is repeated to form the In-Sn-Zn The resulting In-S system oxide crystals (In2SnZn3O8) can be obtained. The layer structure of n-Zn oxide is In2SnZn2O7(ZnO) m (m is 0 or a natural number It can be expressed by the formula:

[0102] In addition, there are oxides of four-component metals, such as In-Sn-Ga-Zn oxides and trimetallic oxides. In-Ga-Zn oxide (also written as IGZO), which is an oxide of the elemental metal, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-C e-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm -Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb- Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Z n-type oxides, In-Tm-Zn-type oxides, In-Yb-Zn-type oxides, In-Lu-Zn In-Zn oxides, Sn-Zn oxides, and Al oxides are binary metal oxides. -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I The same applies when n-Ga-based oxides are used.

[0103] For example, in Figure 17(A), a middle group model consisting of a layered structure of In-Ga-Zn oxide is shown. A diagram of the data is shown.

[0104] In FIG. 17(A), the middle group, which is made up of a layer structure of In-Ga-Zn oxide, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to the Zn in the molecule, and the tetracoordinate O atom is connected to the Zn via the three tetracoordinate O atoms in the lower half of the Zn. Each of them bonds to Ga in the upper and lower halves, and one 4-coordinate O in the lower half of the Ga is The structure is such that three tetracoordinate O atoms are bonded to the In atoms in the upper and lower halves via the Several of these medium groups combine to form large groups.

[0105] Figure 17(B) shows a large group consisting of three medium groups. 17(B) shows the atomic arrangement when the layer structure of FIG. 17(B) is observed from the c-axis direction.

[0106] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0107] The middle group, which is made up of a layer structure of In-Ga-Zn oxide, is shown in FIG. The combination of middle groups with different arrangements of In, Ga, and Zn is not limited to the same middle group. Large groups are also possible.

[0108] Specifically, the large group shown in FIG. 17(B) is repeated to form an In-Ga-Zn The layer structure of the resulting In-Ga-Zn oxide is is InGaO3(ZnO) n (n is a natural number.)

[0109] In the case of n=1 (InGaZnO4), for example, the crystal structure shown in FIG. 18(A) can be obtained. In the crystal structure shown in FIG. 18(A), as explained in FIG. 15(B), Ga and Since Ga and In have a 5-coordinate structure, a structure in which Ga is replaced by In is also possible.

[0110] In the case of n=2 (InGaZn2O5), for example, the crystal structure shown in FIG. 18(B) In the crystal structure shown in FIG. 18(B), as explained in FIG. Since Ga and In have five-coordinate groups, a structure in which Ga is replaced by In is also possible.

[0111] In this embodiment, first, a thin film having a thickness of 1 nm to 10 nm is formed on the underlayer 102 by a sputtering method. The first oxide semiconductor is formed at a substrate temperature of The temperature must be between 200℃ and 400℃.

[0112] Here, a sputtering apparatus for forming an oxide semiconductor will be described in detail below.

[0113] The deposition chamber for forming the oxide semiconductor has a leak rate of 1×10 -10 Pa·m 3 / sec or less It is preferable to do so, so that impurities in the film are prevented from being introduced during film formation by sputtering. Contamination can be reduced.

[0114] To reduce the leak rate, it is necessary to reduce not only external leaks but also internal leaks. An external leak is when gas enters the vacuum system from outside due to a tiny hole or poor seal. Internal leaks are leaks from partitions such as valves in the vacuum system or leaks from internal components. Caused by released gas. Leak rate is 1×10 -10Pa·m 3 To achieve a maximum of 1 / second Therefore, measures must be taken to prevent both external and internal leaks.

[0115] To reduce external leakage, it is advisable to seal the opening and closing parts of the deposition chamber with metal gaskets. Tal gaskets are coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets are preferable. Metal gaskets have higher adhesion than O-rings and are suitable for external rings. In addition, the passivation of iron fluoride, aluminum oxide, chromium oxide, etc. By using a metal material coated with fluorine, the gas released from the metal gasket, including hydrogen, is reduced. This suppresses the internal leakage and reduces the internal leakage.

[0116] The materials that make up the inner walls of the deposition chamber are aluminum and chromium, which emit less gas, including hydrogen. , titanium, zirconium, nickel or vanadium. Also, the above materials may be replaced with iron, It may be used by coating an alloy material containing chromium and nickel. The alloy material containing the alloy is rigid, heat resistant, and easy to process. In order to reduce the area, reducing the surface irregularities of the components by polishing, etc., will reduce the amount of gas released. Alternatively, the components of the above-mentioned film forming apparatus can be replaced with iron fluoride, aluminum oxide, chromium oxide, etc. Alternatively, the material may be covered with a passivating material such as SiO 2 .

[0117] Furthermore, a sputtering gas refiner can be installed just before the sputtering gas is introduced into the deposition chamber. In this case, the length of the piping from the refiner to the film-forming chamber is 5 m or less, preferably 1 m or less. By keeping the length of the piping to 5m or less or 1m or less, the effect of gas released from the piping is reduced. The reverberation can be reduced depending on the length.

[0118] The deposition chamber is evacuated by a roughing pump such as a dry pump, a sputter ion pump, and a turbo pump. It is advisable to use a suitable combination of a sub-pump and a high vacuum pump such as a cryopump. In order to remove the residual moisture in the deposition chamber, an adsorption type vacuum pump, for example, a cryopump, is used. It is preferable to use a turbomolecular pump, an ion pump, or a titanium sublimation pump. While pumps are excellent at pumping out large molecules, they have low pumping ability for hydrogen and water. It combines a cryopump with high water pumping capacity and a sputter ion pump with high hydrogen pumping capacity. It is also effective to combine a turbo molecular pump with a cold trap. The deposition chamber evacuated using an adsorption type vacuum pump such as a cryopump may be, for example, For example, hydrogen atoms, water (H2O) and other compounds containing hydrogen atoms (preferably compounds containing carbon atoms) Since impurities such as fluorine and fluorine-containing compounds are exhausted, the impurities contained in the oxide semiconductor layer formed in the deposition chamber are The concentration of substances can be reduced.

[0119] The adsorbates present inside the deposition chamber are adsorbed to the inner wall and do not affect the pressure in the deposition chamber. However, this causes gas emission when the deposition chamber is evacuated. Therefore, the leak rate and the exhaust speed are Although there is no correlation, use a pump with high exhaust capacity to remove as much of the adsorbed matter as possible from the deposition chamber. It is important to evacuate the deposition chamber beforehand. Baking is also possible. Baking increases the desorption rate of adsorbed substances by about 10 times. Baking can be performed at temperatures between 100°C and 450°C. By removing adsorbed substances while adding gas, water and other substances that are difficult to remove by exhausting alone can be removed. The speed can be further increased.

[0120] In the sputtering method, the power supply for generating plasma is an RF power supply, A A C power supply unit, a DC power supply unit, etc. can be used as appropriate.

[0121] To form In-Ga-Zn oxide materials as oxide semiconductors by sputtering, The In-Ga-Zn oxide target is, for example, In2O3:Ga2O3:ZnO=1 A target having a composition ratio of In:1:1 [molar ratio] can be used. A target having a composition ratio of 2O3:Ga2O3:ZnO=1:1:2 [molar ratio], Or a tantalum oxide having a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] The target has a composition ratio of In2O3:Ga2O3:ZnO=2:1:8 [molar ratio]. A target having an atomic ratio of In:Ga:Zn=1:1:1, In-, indicated as 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 A Ga-Zn oxide target having the above-mentioned atomic ratio can be used. By forming an oxide semiconductor using an a-Zn oxide target, polycrystalline or CA AC-OS is more likely to form.

[0122] In addition, when an In-Sn-Zn oxide is formed as an oxide semiconductor by sputtering, Preferably, the atomic ratio of In:Sn:Zn is 1:1:1, 2:1:3, 1:2:2, or or 20:45:35, an In-Sn-Zn oxide target is used. Forming an oxide semiconductor using an In-Sn-Zn oxide target with a specific atomic ratio This makes it easier for polycrystalline or CAAC-OS to form.

[0123] In addition, the relative density of the metal oxide target for forming the oxide semiconductor is 90% or more. 0% or less, preferably 95% to 99.9%. By using the get, the formed oxide semiconductor layer can be a dense film.

[0124] The sputtering gas is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. The sputtering gas is a mixture of hydrogen, water, and oxygen. Alternatively, it is preferable to use a high-purity gas from which impurities such as hydrides have been removed. For example, When using argon as the sputtering gas, the purity is 9N, the dew point is -121℃, and the amount of H2O contained is 0.1ppb or less, H2 content of 0.5ppb or less is preferable. If oxygen is used, the purity 8N, dew point -112℃, H2O content 1ppb or less, H2 content 1ppb or less are preferred .

[0125] The substrate temperature during film formation is 150° C. or higher and 450° C. or lower, preferably 200° C. or higher and 350° C. or lower. The substrate is heated to 150° C. or higher and 450° C. or lower, preferably 200° C. or higher and 350° C. or lower. By forming the film while heating, it is possible to prevent moisture (including hydrogen) from entering the film. This can be done.

[0126] By forming the oxide semiconductor film while heating the substrate, hydrogen, moisture, and The concentration of impurities such as hydrides or hydroxides can be reduced. Damage caused by etching is reduced. The removed sputtering gas is added, and the above target is used to deposit a thickness of 1 nm to 10 nm. The first oxide semiconductor film is preferably formed to a thickness of 2 nm to 5 nm.

[0127] In this embodiment, an In-Ga-Zn-based oxide semiconductor is used as the oxide semiconductor target. Using a target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) The distance between the substrate and the target was 170 mm, the substrate temperature was 250°C, the pressure was 0.4 Pa, and the DC power supply: 0.5 kW; sputtering gas: oxygen only, argon only, or argon only. A first oxide semiconductor film is formed to a thickness of 5 nm using argon and oxygen.

[0128] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and a first heat treatment is performed. The temperature of the first heat treatment is set to 400° C. or more and 750° C. or less. Thus, the first oxide semiconductor is crystallized to become a first crystalline oxide semiconductor.

[0129] Although it depends on the temperature of the first heat treatment, the first heat treatment causes crystallization from the film surface. In the first heat treatment, crystals grow from the surface of the film toward the inside, and crystals with a C-axis orientation are obtained. Due to this process, zinc and oxygen gather on the surface of the film, and the top surface of the film is made up of zinc and oxygen in a hexagonal shape. One or more layers of graphene-type two-dimensional crystals are formed on the outermost surface, and these are aligned in the thickness direction. When the temperature of the heat treatment is increased, the layers grow from the surface to the inside, and then from the inside to the inside. The bottom and crystal growth proceeds.

[0130] By the first heat treatment, oxygen in the base layer 102 is transported to the interface with the first crystalline oxide semiconductor. or in the vicinity thereof (within ±5 nm from the interface) to form a first crystalline oxide semiconductor. Therefore, the underlayer 102 reduces oxygen deficiencies in the body. , or the interface between the first crystalline oxide semiconductor and the underlayer 102. It is preferred that oxygen is present in an amount greater than 0.1.

[0131] Next, a second oxide semiconductor having a thickness of more than 10 nm is formed on the first crystalline oxide semiconductor. The second oxide semiconductor is formed by a sputtering method. The substrate temperature during film formation is set to 200°C or higher and 400°C or lower. By setting the following, it is possible to form an oxide semiconductor film on the surface of the first crystalline oxide semiconductor. The precursors are aligned in the body, giving it what is known as order.

[0132] In this embodiment, an In-Ga-Zn-based oxide semiconductor is used as the oxide semiconductor target. Using a target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) The distance between the substrate and the target was 170 mm, the substrate temperature was 400°C, the pressure was 0.4 Pa, and the DC power supply: 0.5 kW; sputtering gas: oxygen only, argon only, or argon only. A second oxide semiconductor film is formed to a thickness of 25 nm using fluorine and oxygen.

[0133] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and a second heat treatment is performed. The temperature of the second heat treatment is 400° C. or more and 750° C. or less. Thus, a second crystalline oxide semiconductor is formed. The second crystalline oxide semiconductor is formed by performing the process under a nitrogen atmosphere or a mixed atmosphere of nitrogen and oxygen. The second heat treatment increases the density of the first crystalline oxide semiconductor and reduces the number of defects. The conductor acts as a nucleus and crystal growth proceeds in the direction of the film thickness, i.e., from the bottom to the inside, forming a second crystalline oxide semiconductor. At this time, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor are simultaneously formed. The growth of a first crystalline oxide semiconductor and a second crystalline oxide semiconductor is called homo-growth. The crystalline oxide semiconductor of the second embodiment is composed of at least one different element. This is called growth.

[0134] In this manner, in the process of forming an oxide semiconductor, the pressure in the deposition chamber, the leak rate in the deposition chamber, etc. In the above cases, by minimizing the inclusion of impurities, hydrogen, moisture, etc., in the oxide semiconductor can be prevented. The hydrogen contained in the oxide semiconductor reacts with the metal atoms. The bonded oxygen reacts with the water to form water, and the lattice from which the oxygen has been removed (or Defects will be formed in the part.

[0135] Therefore, by drastically reducing impurities in the process of forming the oxide semiconductor, It is possible to reduce defects in semiconductors. For these reasons, it is important to remove impurities as much as possible. By using an oxide semiconductor made of highly purified CAAC-OS for the channel region, Therefore, the amount of change in the threshold voltage of the transistor before and after light irradiation and BT testing is small. Therefore, it is possible to have stable electrical characteristics.

[0136] After the second heat treatment, the temperature was maintained while switching to an oxidizing atmosphere for further heating. Heat treatment is preferably performed. By the heat treatment in an oxidizing atmosphere, oxygen defects in the oxide semiconductor are eliminated. can be reduced.

[0137] Metal oxides that can be used for oxide semiconductors have a band gap of 2 eV or more. The band gap is preferably 2.5 eV or more, and more preferably 3 eV or more. By using a metal oxide with a wide gap, the off-state current of a transistor can be reduced. .

[0138] In addition, the steps from the formation of the underlayer 102 to the second heat treatment can be performed continuously without exposure to the air. The steps from the formation of the base layer 102 to the second heat treatment are preferably carried out in a time-dependent manner. and in an atmosphere containing almost no moisture (inert atmosphere, reduced pressure atmosphere, dry air atmosphere, etc.). For example, the moisture content is controlled to a dew point of -40°C or less, preferably a dew point The atmosphere must be dry nitrogen at -50℃ or below.

[0139] Next, an oxide semiconductor layer consisting of a first crystalline oxide semiconductor and a second crystalline oxide semiconductor is formed. The stack is processed to form an island-shaped oxide semiconductor layer 103 (see FIG. 3A).

[0140] The oxide semiconductor is processed by forming a mask of a desired shape on the oxide semiconductor. This can be done by etching the semiconductor. Alternatively, the insulating layer can be formed by an ink jet method, a printing method, or the like. Any method may be used to form the mask.

[0141] The etching of the oxide semiconductor can be performed by either a dry etching method or a wet etching method. Of course, these may be used in combination.

[0142] The first crystalline oxide semiconductor and the second crystalline oxide semiconductor obtained by the above manufacturing method are The semiconductor has a characteristic that it has a C-axis orientation. The oxide semiconductor and the second crystalline oxide semiconductor have neither a single crystal structure nor an amorphous structure. The structure is a c-axis oriented crystalline oxide semiconductor (CAAC-OS).

[0143] In addition, the present invention is not limited to a two-layer structure in which a second crystalline oxide semiconductor is formed on a first crystalline oxide semiconductor. However, the third crystalline oxide semiconductor is formed after the second crystalline oxide semiconductor is formed. The process of film formation and heat treatment may be repeated to form a laminated structure of three or more layers.

[0144] As in the oxide semiconductor layer 103, a first crystalline oxide semiconductor and a second crystalline oxide semiconductor The use of this stack in transistors provides stable electrical characteristics and high reliability. A transistor can be realized.

[0145] Next, the gate insulating layer 104 is formed over the oxide semiconductor layer 103. , Aluminum nitride, Aluminum oxide, Aluminum nitride oxide, Aluminum oxynitride , silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, tantalum oxide, or lanthanum oxide, can be formed in a single layer or laminated form. .

[0146] The gate insulating layer 104 is made of hafnium silicate (HfSiO x (x>0) Nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0 )), nitrogen-doped hafnium aluminate (HfAl x O y N z (x>0, y>0 , z>0), using high-k materials such as hafnium oxide and yttrium oxide So, without changing the actual thickness of the gate insulating film (e.g., silicon oxide equivalent), By thickening the gate insulating film, the gate leakage can be reduced. HK materials and silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, oxide A laminated structure of aluminum oxide, aluminum oxynitride, and gallium oxide. The thickness of the gate insulating layer 104 is 1 nm or more and 300 nm or less. The thickness is preferably 5 nm or more and 50 nm or less.

[0147] The gate insulating layer 104 is formed by a sputtering method, a CVD method, or the like. The formation of 04 can be achieved by sputtering, plasma CVD, or by using μ-waves (for example, frequency 2. A film formation method such as a high density plasma CVD method using a frequency of 45 GHz can be applied. The gate insulating layer 104 is not limited to a single layer and may be a stack of different layers. The insulating layer 104 is preferably an insulating layer containing oxygen in a portion in contact with the oxide semiconductor layer 103. Particularly preferred is an oxide insulating layer that releases oxygen when heated. For example, a gate insulating layer By using silicon oxide for the oxide semiconductor layer 104, oxygen is diffused into the oxide semiconductor layer 103, and the oxide semiconductor layer 104 is oxidized. This reduces oxygen vacancies in the compound semiconductor layer 103, improving the transistor characteristics. It is possible.

[0148] In the structure described in this embodiment, the structure that generates unevenness over the substrate is the oxide semiconductor layer 103. The gate insulating layer 104 is only required to reduce the leakage current caused by the gate insulating layer 104. Therefore, the gate insulating layer 104 is thinned to about 5 nm. The transistor can be operated even if the gate insulating layer 104 is thinned. By forming a thin film, the short channel effect is reduced and the operating speed of the transistor is increased. Play.

[0149] Note that before the gate insulating layer 104 is formed, the surface of the oxide semiconductor layer 103 is treated with oxygen, ozone, or the like. The surface of the oxide semiconductor layer 103 is oxidized by exposing it to plasma of an oxidizing gas such as nitrous oxide or dinitrogen monoxide. In this embodiment, the gate insulating layer 104 may be formed of an oxide Silicon oxide is formed on the semiconductor layer 103 to a thickness of 100 nm.

[0150] Next, a thin film is formed on the gate insulating layer 104 by using a sputtering method, a vacuum deposition method, or a plating method. forming a conductive layer by etching the conductive layer, forming a mask on the conductive layer, and selectively etching the conductive layer to form a gate The mask formed on the conductive layer is a printing method, an ink jet method, a foil method, or the like. The gate electrode 105 is formed on the gate insulating layer 10. 4 and a gate electrode 105 stacked on the gate electrode 105a. Formed by b.

[0151] The gate electrode 105a is formed of a material such as indium gallium zinc oxide (IGZO) containing nitrogen. (In-Ga-Zn-O), indium tin oxide containing nitrogen (In-Sn-O), Indium gallium oxide (In-Ga-O) containing nitrogen and indium zinc oxide containing nitrogen Indium oxide (In-Zn-O), tin oxide containing nitrogen (Sn-O), and indium oxide containing nitrogen It is preferable to use metal nitrides (In-O) or metal nitrides (InN, ZnN, etc.).

[0152] These materials have a work function of 5 eV or more, preferably 5.5 eV or more, and the gate electrode 105 a is provided between the gate electrode 105b and the gate insulating layer 104, and the gate electrode 105a The oxide semiconductor layer 103 overlaps with the gate insulating layer 104 interposed therebetween, The threshold voltage of the electrical characteristics can be made positive, which allows so-called normally-off switching For example, a gate electrode 105a made of In-Ga-Zn-O containing nitrogen can be used. In the case where the nitrogen concentration is 70%, the nitrogen concentration is higher than that of the oxide semiconductor layer 103. Use In-Ga-Zn-O with an atomic percentage of 100% or more.

[0153] The gate electrode 105b may be formed from a material such as aluminum (Al), chromium (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti), Molybdenum (Mo), Tungsten ( A metal element selected from the group consisting of neodymium (Nd) and scandium (Sc), the above-mentioned metal elements Alloys containing the above metal elements, alloys combining the above metal elements, and nitrides of the above metal elements. It can be formed using manganese (Mn), magnesium (Mg), Metals selected from one or more of zirconium (Zr) and beryllium (Be) Elements may also be used.

[0154] The gate electrode 105b may have a single-layer structure or a laminated structure of two or more layers. A single layer structure using aluminum containing silicon, and a two-layer structure using titanium laminated on aluminum Layered structure, two-layer structure with titanium layered on titanium nitride, and tungsten layered on titanium nitride Two-layer structure with tungsten on tantalum nitride, two-layer structure with tungsten on tantalum nitride, Cu-Mg-Al alloy A two-layer structure with Cu laminated on gold, titanium and aluminum laminated on the titanium, There are also three-layer structures in which titanium is formed on top of the metal.

[0155] The gate electrode 105b is made of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. Alternatively, the conductive material having light-transmitting properties and the metal element may be laminated together.

[0156] In this embodiment, the gate electrode 105a is made of indium gallium zinc oxide containing nitrogen. Also, a material is used for the gate electrode 105b, in which tungsten is laminated on titanium nitride. A two-layer structure is used (see FIG. 3(B)). The hole shape is preferable because it improves the coverage of the layer to be formed later.

[0157] Next, the source region 103a and the drain region 103b are formed by a self-aligned process. Specifically, the gate electrode 105 is used as a mask to perform ion doping or ion implantation. The dopant 106 is added to the oxide semiconductor layer 103 by a plantation method. The dopant 106 added to the semiconductor layer 103 is a rare gas or hydrogen (H), One or more elements may be used.

[0158] Hydrogen acts as an electron donor (donor) in the oxide semiconductor, causing the oxide semiconductor to become n-type. Furthermore, the rare gas element creates defects in the oxide semiconductor, causing the oxide semiconductor to become n-type. Hydrogen is easily diffused, and if hydrogen diffuses into the channel formation region, the transistor characteristics will deteriorate. For this reason, using a rare gas element as the dopant 106 is preferable for the semiconductor device. The reliability of the method is good and preferable.

[0159] In addition, in a region of the oxide semiconductor layer 103 overlapping with the gate electrode 105, the gate electrode 105 This serves as a mask and is not doped with the dopant 106, forming a channel forming region 103c.

[0160] The source region 103a and the drain region 103b to which the dopant 106 is added are n-type The oxide semiconductor has a lower resistivity than the channel formation region 103c. The resistance of the source region 103a and the drain region 103b is reduced, and the transistor 100 In addition, the source region 103a and the drain region 10 3b and the gate electrode 105 hardly overlap each other, so that the parasitic capacitance can be reduced. This allows the transistor 100 to operate at even higher speeds.

[0161] In addition, the gate electrode 105 is used as a mask to form an oxide semiconductor layer that will become a source region and a drain region. The gate insulating layer 104 on the oxide semiconductor layer 103 is removed to expose the oxide semiconductor layer 103. A dopant 106 is added to the oxide semiconductor layer 103 to form a source region 103a and a drain region 103b. The gate insulating layer 104 on the oxide semiconductor layer 103 may be removed by The etching is performed under conditions in which the oxide semiconductor layer 103 is not easily etched.

[0162] The dopant 106 is added to the exposed oxide semiconductor layer 103 by ion doping or The doping of the dopant 106 can be performed by ion implantation. Plasma is generated in a gas atmosphere containing an element to be added, and the oxide semiconductor layer 103 is exposed. This can also be achieved by subjecting the damaged area to a plasma treatment. Addition by plasma treatment may cause the oxide semiconductor to be etched and thinned. For this reason, the dopant 106 is added to the oxide semiconductor layer 103 by ion doping. It is preferable to carry out the method by the deposition method or the ion implantation method.

[0163] Note that the dopant 106 is added to the oxide semiconductor layer 103 by an ion doping method or an indium doping method. In the case of the on-implantation method, the oxide semiconductor layer 103 is not exposed, and the It is preferable to leave the gate insulating layer 104 in place. 04 and added to the oxide semiconductor layer 103, In addition, excessive damage to the oxide semiconductor layer 103 can be reduced. Since the interface between the gate insulating layer 103 and the gate insulating layer 104 is also kept clean, the characteristics and signal quality of the transistor are improved. In addition, the doping depth (doped region) of the dopant 106 becomes easier to control, and the oxidation This allows the dopant 106 to be added to the compound semiconductor layer 103 with high precision.

[0164] In this embodiment, xenon (Xe) is used as the dopant 106. The oxide semiconductor layer 103 is formed by implantation through the gate insulating layer 104. The source region 103a and the drain region 103b are formed by adding xenon. The xenon concentration in region 103b is 5×10 19 atoms / cm 3 That's it, 1×10 22 a toms / cm 3The following is set (see FIG. 3(C)).

[0165] After the dopant 106 is added, the reaction is carried out under a reduced pressure atmosphere and an inert gas atmosphere such as nitrogen or a rare gas. The heat treatment may be performed at a temperature of 300° C. or more and 600° C. or less. Using an electric furnace, which is one of the pieces of equipment, heat treatment is carried out at 450°C for one hour in a nitrogen atmosphere.

[0166] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. The gas used is a rare gas such as argon or nitrogen, which does not react with the workpiece during heat treatment. A suitable inert gas is used.

[0167] For example, the heat treatment may involve moving the substrate into an inert gas heated to a high temperature and heating it for several minutes. After heating, the substrate may be moved and removed from the inert gas heated to a high temperature for GRTA. stomach.

[0168] When the above heat treatment is carried out, it may be carried out at any time after the dopant 106 is added.

[0169] In addition, a dopant 10 is introduced by ion doping or ion implantation. The addition of 6 may be performed while heating the substrate.

[0170] Next, the oxide semiconductor layer 103 and the gate electrode 105 are covered with a metal oxide film by sputtering, CVD, or the like. The insulating layer 107 and the insulating layer 108 are formed by a method or the like. Aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride Silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride. The insulating layer 107 and the insulating layer 108 can be formed using the following materials. These may be used as a single layer or in a laminated form.

[0171] At this time, at least the insulating layer 107 is made of a material that does not easily release oxygen when heated. This reduces the conductivity of the source region 103a and the drain region 103b. Specifically, the CVD method uses silane gas as the main material and nitrogen oxide gas The film may be formed by mixing an appropriate source gas from among nitrogen gas, hydrogen gas, and rare gas. The substrate temperature should be between 300 and 550°C. By using the CVD method, This makes it possible to make the material less likely to release oxygen. In addition, by using silane gas as the main material, Hydrogen remains in the insulating layer, and the hydrogen diffuses to form the source region 103a and the drain region 103b. The electrical conductivity of the insulating layer 103b can be further increased. The hydrogen concentration in the insulating layer 107 is 0.1 atomic percent. It is sufficient to set the content to 25 atomic % or more.

[0172] The thickness of the insulating layer 107 and the insulating layer 108 is 50 nm or more, preferably 200 nm or more and 50 In this embodiment, the insulating layer 107 is a silicon oxide layer having a thickness of 300 nm. Then, aluminum oxide is formed as the insulating layer 108 to a thickness of 100 nm.

[0173] The insulating layer 108 is made of silicon nitride or aluminum oxide to prevent the intrusion of impurities from the outside. In this embodiment, the insulating layer 108 is preferably formed using tungsten. Aluminum oxide having a thickness of 100 nm is formed (see FIG. 3(D)). Either or both of the border layers 108 may be omitted.

[0174] After the insulating layer 108 is formed, if necessary, a heat treatment (temperature range: 150° C. or more and 650° C. or less, preferably Preferably, the heating may be performed at a temperature of 200° C. or higher and 500° C. or lower.

[0175] Next, a mask is formed on the insulating layer 108, and the gate insulating layer 104 and the insulating layer 106 are formed on the insulating layer 108 using the mask. The layer 107 and the insulating layer 108 are selectively etched to form the source region 103a and the drain region 103b. A part of the contact region 103b is exposed, and a contact hole 109 is formed (see FIG. 4(A)). (see).

[0176] Next, a conductive layer is formed on the insulating layer 108, a mask is formed on the conductive layer, and the conductive layer is selected. Then, the source electrode 110a and the drain electrode 110b are formed by selectively etching the The conductive layer for forming the source electrode 110a and the drain electrode 110b is The same material as that for the port electrode 105b can be used.

[0177] In this embodiment, a conductive film for forming the source electrode 110a and the drain electrode 110b is The conductive layer is made of a Cu-Mg-Al alloy and Cu is laminated on the Cu-Mg-Al alloy. By providing a Cu-Mg-Al alloy material as a conductive layer, the adhesion of the conductive layer can be improved. do.

[0178] Note that the channel length of the transistor 100 is determined by dividing the length of the source region 103a and the length of the This corresponds to the length of the channel forming region 103c sandwiched between the drain regions 103b. The channel length of the transistor 100 is approximately equal to the width of the gate electrode 105 .

[0179] The above process allows transistors to be miniaturized and their electrical characteristics to be good even when the channel length is reduced. Therefore, the transistor 100 can be manufactured using an oxide semiconductor, which is excellent in properties and is highly reliable. do.

[0180] The transistor 140 has a low-concentration region 103 d and a low-concentration region 1 The transistor 140 has a side effect of forming the transistor 100. A process for forming the oxide semiconductor layer 103 is added. It can be made in two separate steps.

[0181] The low concentration regions 103d and 103e are formed by using the gate electrode 105 as a mask. It can be formed by a self-alignment process. Specifically, after the gate electrode 105 is formed, Using the gate electrode 105 as a mask, dopant 1 is implanted in the same manner as in the transistor 100. In the first doping step, The dopant 106 added to the oxide semiconductor layer 103 in the step The dopant 106 may be the same element as that used in the first doping step. The concentration of the dopant 106 in the compound semiconductor layer 103 is 5×1018 atoms / cm 3 End , 5×10 19 atoms / cm 3 Add less than 100 ml of water.

[0182] Next, a sidewall 111 is formed on the side surface of the gate electrode 105. 1 can be prepared by known methods.

[0183] Next, the gate electrode 105 and the sidewall 111 are used as a mask to deposit a dopant 106. The oxide semiconductor layer 103 is doped with an acid (also referred to as a second doping step). The dopant 106 added to the compound semiconductor layer 103 is the same as that used in the transistor 100. The same elements as the dopant 106 can be used. In the second doping step, the oxide semiconductor The concentration of the dopant 106 in the conductor layer 103 is 5×10 19 atoms / cm 3 That's it, 1x 10 22 atoms / cm 3 Make it as follows.

[0184] In this manner, the transistor 140 has a source region 103a, a drain region 103b, and a low A high concentration region 103d and a low concentration region 103e can be formed. The low concentration region 103d and the low concentration region 103e are higher than the source region 103a and the drain region 103b. The dopant concentration is low and the resistivity is high.

[0185] By providing the low concentration region 103d and the low concentration region 103e, the deterioration of the transistor characteristics is suppressed. This reduces the negative shift in threshold voltage due to short channel effects and improves A highly reliable transistor can be manufactured.

[0186] Note that the channel length of the transistor 140 is determined by dividing the low concentration region 103d and the low concentration region 103c in FIG. This corresponds to the length of the channel forming region 103c sandwiched between the low concentration regions 103e. The channel length of the transistor 140 is approximately equal to the width of the gate electrode 105 .

[0187] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0188] (Embodiment 2) In this embodiment, a transistor having a different configuration from that disclosed in the first embodiment is used. An example of a register will now be described.

[0189] FIG. 5A is a top view illustrating a structure of a transistor 150. FIG. 5(A) is a cross-sectional view for explaining the laminated structure of the portion indicated by the dashed line C1-C2. In (A), the substrate and insulating layer are omitted.

[0190] The transistor 150 shown in FIG. 5B has the same structure as the transistor 100 described in Embodiment 1. In comparison, the stacking positions of the source electrode 110a and the drain electrode 110b are different. The transistor 150 has a source electrode 110a and a drain electrode 110b on the underlayer 102. An oxide semiconductor layer is formed on the underlayer 102, the source electrode 110a, and the drain electrode 110b. A body layer 103 is formed.

[0191] In the transistor 150, the source electrode 110a and the drain electrode 110b are contacts. The source region 103a and the drain region 103b of the oxide semiconductor layer 103 are Since it is configured to connect to 3b, it is easy to increase the connection area and reduce the contact resistance. .

[0192] The channel length of the transistor 150 is determined by dividing the length of the source region 103a and the length of the This corresponds to the length of the channel forming region 103c sandwiched between the drain regions 103b. The channel length of the transistor 150 is approximately equal to the width of the gate electrode 105 .

[0193] The transistor 160 shown in FIG. 6 has the same configuration as the transistor 150, but has a gate electrode 10. The sidewall 111 of the oxide semiconductor layer 103 is provided on the side surface of the oxide semiconductor layer 103. The low-concentration region 103d and the low-concentration region 103e are located in the region overlapping the low-concentration region 103a. The region 103d is formed between the channel forming region 103c and the source region 103a. The region 103e is formed between the channel forming region 103c and the drain region 103b. FIG. 6A is a top view illustrating a structure of a transistor 160. FIG. 2A is a cross-sectional view illustrating the laminated structure of the portion indicated by the dashed line D1-D2 in FIG.

[0194] By providing the low concentration region 103d or the low concentration region 103e in the oxide semiconductor layer 103, Between the channel forming region 103c and the source region 103a or the drain region 103b This can reduce the electric field generated by the channel. The relaxation of the electric field occurring in the formation region 103c and the drain region 103b leads to deterioration of the transistor characteristics. In addition, the low concentration region 103d or the low concentration region 103e is provided. This makes it possible to suppress the short channel effect that accompanies miniaturization of transistors.

[0195] Note that the channel length of the transistor 160 is determined by dividing the low concentration region 103d and the low concentration region 103c in FIG. This corresponds to the length of the channel forming region 103c sandwiched between the low concentration regions 103e. The channel length of the transistor 160 is approximately equal to the width of the gate electrode 105 .

[0196] The transistor 170 illustrated in FIG. 7A is one type of bottom-gate transistor. do.

[0197] FIG. 7A illustrates a cross-sectional structure of a transistor 170. The transistor 170 has a base A gate electrode 105 is formed on the plate 101, and a gate insulating layer 104 is formed on the gate electrode 105. The gate electrode 105 is formed by stacking the gate electrode 105a on the gate electrode 105b. Between the substrate 101 and the gate electrode 105, the A base layer may be provided.

[0198] In addition, the oxide semiconductor layer 103 is formed over the gate insulating layer 104. A channel protection layer 112, a source electrode 110a, and a drain electrode 110b are formed on the The oxide semiconductor layer 103 has a channel formation region 1 overlapping with the channel protection layer 112. 03c, a source region 103a electrically connected to the source electrode 110a, and a drain electrode It has a drain region 103b electrically connected to 110b.

[0199] The channel protection layer 112 is formed using the same material and method as the gate insulating layer 104. The thickness of the channel protection layer 112 is preferably 10 nm or more and 500 nm or less. The thickness is preferably 100 nm or more and 300 nm or less.

[0200] The source region 103a and the drain region 103b are formed by using the channel protection layer 112 as a mask. 1 and can be formed similarly to transistor 100.

[0201] In addition, an insulating layer is formed on the channel protection layer 112, the source electrode 110a, and the drain electrode 110b. An edge layer 108 is formed. The insulating layer 108 may be a stack of multiple insulating layers.

[0202] The channel length of the transistor 170 is determined by dividing the length of the source region 103a and the length of the This corresponds to the length of the channel forming region 103c sandwiched between the drain regions 103b. The channel length of the transistor 170 is approximately equal to the width of the channel protection layer 112 .

[0203] FIG. 7B illustrates a cross-sectional structure of the transistor 180. The transistor 100 has a structure in which a back gate electrode 115 and an insulating layer 113 are provided. In the transistor 180, a back gate electrode 115 is formed on the underlayer 102. An insulating layer 113 is formed on the gate electrode 115. The semiconductor layer 103 is formed so as to overlap the back gate electrode 115 via the insulating layer 113. is.

[0204] The back gate electrode 115 is formed of an oxide semiconductor. The back gate electrode 115 is disposed so as to sandwich the channel forming region 103c of the layer 103. It is formed of a conductive layer and can function in the same manner as the gate electrode 105. By changing the potential of the gate electrode 115, the threshold voltage of the transistor can be changed. This can be done.

[0205] The back gate electrode 115 may be formed using the same material and method as the gate electrode 105b. In addition, the same structure as the gate electrode 105a can be formed between the back gate electrode 115 and the insulating layer 113. Similar layers may be provided.

[0206] The insulating layer 113 can be formed using a material and a method similar to those of the gate insulating layer 104. Alternatively, the base layer 102 may not be formed, and the insulating layer 113 may function as the base layer 102. Cut.

[0207] The channel length of the transistor 180 is determined by dividing the length of the source region 103a and the length of the This corresponds to the length of the channel forming region 103c sandwiched between the drain regions 103b. The channel length of the transistor 180 is approximately equal to the width of the gate electrode 105 .

[0208] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0209] (Embodiment 3) In this embodiment, a method for forming an oxide semiconductor film including a CAAC-OS will be described. Methods other than those disclosed in the first embodiment will be described below.

[0210] First, an oxide semiconductor film having a thickness of 1 nm to 50 nm is formed over the base layer 102.

[0211] The substrate temperature during film formation is 150°C to 450°C, preferably 200°C to 350°C. The substrate is heated to a temperature of 150° C. to 450° C., preferably 200° C. to 350° C. By depositing the film while heating, it is possible to prevent moisture (including hydrogen) from entering the film. In addition, a CAAC-OS film, which is an oxide semiconductor film having crystallinity, can be formed. .

[0212] Further, after the oxide semiconductor is formed, the substrate 101 is subjected to heat treatment. Hydrogen is released, and part of the oxygen contained in the underlayer 102 is oxidized to the oxide semiconductor and the underlayer 102. It is preferable that the oxide semiconductor layer 102 is diffused in the vicinity of the interface thereof. By performing the above-mentioned treatment, an oxide semiconductor having a CAAC-OS with higher crystallinity can be formed. It is possible.

[0213] The temperature of the heat treatment is set so that hydrogen is released from the oxide semiconductor and the hydrogen contained in the underlayer 102 is removed. A temperature at which a part of the oxygen present in the oxide semiconductor is released and diffused into the oxide semiconductor is preferable. is set to a temperature of 200° C. or higher and lower than the distortion point of the substrate 101, preferably 250° C. or higher and 450° C. or lower. By diffusing oxygen into the oxide semiconductor, oxygen vacancies in the oxide semiconductor can be reduced. This can be done.

[0214] The heat treatment is carried out using an RTA (Rapid Thermal Anneal) device. By using RTA, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. Therefore, an oxide semiconductor having a high ratio of crystalline regions to amorphous regions can be obtained. The time required for forming the

[0215] The heat treatment can be carried out in an inert gas atmosphere, typically helium, neon, or arsenic. It is preferable to carry out the treatment in an atmosphere of a rare gas such as argon, xenon, or krypton, or in a nitrogen atmosphere. The treatment may be performed in an oxygen atmosphere or a reduced pressure atmosphere. The treatment time is 3 minutes to 24 hours. The longer the gap, the higher the ratio of crystalline regions to amorphous regions in the oxide semiconductor formed. However, heat treatment for more than 24 hours is not preferred because it reduces productivity.

[0216] In the above manner, an oxide semiconductor made of CAAC-OS can be formed.

[0217] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0218] (Embodiment 4) In this embodiment, the transistor using the oxide semiconductor described in Embodiments 1 and 2 is The effect of the MOSFET on its electrical characteristics is explained using a band diagram.

[0219] FIG. 8 is a cross-sectional view of a transistor having the same layer structure as the transistor 100 shown in FIG. FIG. 9 shows an energy band diagram (schematic diagram) in the X1-X2 cross section shown in FIG. Furthermore, Figure 9(B) shows the case where the voltage between the source and drain is equipotential (VD=0V). FIG. 8 illustrates a case where a first oxide semiconductor region (referred to as OS1) and a pair of second oxide semiconductor regions are The oxide semiconductor layer is made of an oxide semiconductor region (referred to as OS2), and the source electrode and the drain electrode are A transistor is formed by a pole (assumed to be metal).

[0220] The channel formation region of the transistor in FIG. 8 is formed by OS1. The film is highly purified by removing and desorbing as many impurities as possible, such as moisture (including hydrogen), from the film. Furthermore, by reducing the oxygen vacancies in the film, it is possible to make it intrinsic (i-type) or as close to intrinsic as possible. The structure is made of an oxide semiconductor that is close to the Fermi level ( Ef) can be made the same level as the intrinsic Fermi level (Ei).

[0221] In addition, the source and drain regions of the transistor in FIG. Like the OS1, the OS2 is formed by removing impurities such as moisture (including hydrogen) from the film. By removing and desorbing as many impurities as possible to achieve high purification, and by reducing oxygen vacancies in the film, An oxide semiconductor that is more intrinsic (i-type) or as close to intrinsic as possible is then Adding at least one element selected from hydrogen and rare gases By creating a donor or oxygen vacancy, OS2 is formed. Compared to S1, the carrier density is higher and the Fermi level is closer to the conduction band.

[0222] FIG. 9A shows a state where a first oxide semiconductor region (OS1) is in a vacuum state (Evac). , a second oxide semiconductor region (referred to as OS2), and a source electrode and a drain electrode (met al), where IP is the ionization potential and Ea is Electron affinity, Eg is the energy gap, Wf is the work function. Also, Ec is the conduction band The lower end of the valence band, Ev, the upper end of the valence band, and Ef, the Fermi level. The numbers are 1 for OS1, 2 for OS2, and m for metal. We assume that Wf_m is 4.1 eV (e.g. titanium).

[0223] OS1 is an i-type or substantially i-type oxide semiconductor with extremely low carrier density. Therefore, Ef_1 is approximately in the middle between Ec and Ev. Also, OS2 is the carrier density. It is a high n-type oxide semiconductor, and Ec_2 and Ef_2 are roughly the same. OS1 and OS2 The oxide semiconductor shown in Fig. 1 has an energy gap (Eg) of 3.15 eV and an electron affinity (Ea ) is said to be 4.3 eV.

[0224] As shown in FIG. 9B, the channel forming region OS1 and the source and drain regions When the OS2 regions come into contact, carriers move so that the Fermi levels match, The band edges of OS1 and OS2 are bent. Furthermore, the band edges of OS2 and the source and drain electrodes When two metals contact each other, the carriers move so that the Fermi levels match. This causes the end of the OS2 band to bend.

[0225] In this way, the OS1 which becomes the channel formation region and the met which becomes the source electrode and the drain electrode are The n-type oxide semiconductor OS2 is formed between Al and the oxide semiconductor The contact between the metal and the semiconductor can be made ohmic, and the contact resistance can be reduced. As a result, the on-state current of the transistor can be increased.

[0226] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0227] (Embodiment 5) FIG. 10A is a circuit diagram of a memory element (hereinafter also referred to as a memory cell) constituting a semiconductor device. An example of a memory cell is shown in FIG. A transistor 1160 and a transistor 1162 in which an oxide semiconductor is used for a channel formation region are It is composed of:

[0228] The transistor 1162 in which an oxide semiconductor is used for a channel formation region is It can be made by

[0229] As shown in FIG. 10A, the gate electrode of the transistor 1160 and the The first transistor is electrically connected to one of the source electrode and the drain electrode of the second transistor. What is the wiring (1st Line: also called the source line) and the source electrode of the transistor 1160? , electrically connected to the second wiring (also called the bit line) and the transistor The drain electrode of the capacitor 1160 is electrically connected to the third wiring (3rd Line: also called the first signal line) and the source electrode or drain electrode of the transistor 1162 The other electrode is electrically connected to a fourth wiring (also called a second signal line). The gate electrode of the transistor 1162 is electrically connected to the first gate electrode of the transistor 1162 .

[0230] A transistor using a material other than an oxide semiconductor, for example, single crystal silicon, in the channel formation region. Since the transistor 1160 can operate at a sufficiently high speed, It is possible to read out the stored contents at high speed. The transistor 1162 used in the formation region has a smaller off-state current than the transistor 1160. Therefore, by turning off the transistor 1162, Therefore, the potential of the gate electrode of the transistor 1160 can be held for a very long time. It is Noh.

[0231] By utilizing the feature that the potential of the gate electrode can be maintained, information can be written, It is possible to store and read the information.

[0232] First, writing and holding of information will be described. The transistor 1162 is turned on as a potential at which the transistor 1162 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 1160 ( After that, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned off. By turning off the transistor 1162, the gate of the transistor 1160 is turned on. The potential of the port electrode is maintained (retained).

[0233] Since the off-state current of the transistor 1162 is smaller than that of the transistor 1160, The potential of the gate electrode of the transistor 1160 is maintained for a long time. If the potential of the gate electrode of 1160 is a potential that turns on the transistor 1160, The transistor 1160 is maintained in an on state for a long period of time. If the potential of the gate electrode of the transistor 1160 is a potential that turns off the transistor 1160, For example, transistor 1160 is held off for a long period of time.

[0234] Next, the reading of information will be described. As described above, when the transistor 1160 is in the on state, When the transistor is in the on or off state, a predetermined potential (low potential) is applied to the first wiring. When the transistor 1160 is turned on or off, the potential of the second wiring changes depending on whether the transistor 1160 is turned on or off. For example, when the transistor 1160 is on, the first wiring The potential of the second wiring is lowered relative to the potential of the transistor 1160. In the off state, the potential of the second wiring does not change.

[0235] In this manner, in a state in which the information is held, the potential of the second wiring is compared with a predetermined potential. This allows the information to be read out.

[0236] Next, rewriting of information will be described. Rewriting of information is the same as writing and storing the above information. That is, the potential of the fourth wiring is changed when the transistor 1162 is turned on. This causes the transistor 1162 to be turned on. A potential (a potential related to new information) is applied to the gate electrode of transistor 1160. After that, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned off. By turning off the starter 1162, the new information is held.

[0237] In this way, the memory cell according to the disclosed invention can directly rewrite information. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and makes it possible to suppress a decrease in operation speed caused by the erase operation. That is, high speed operation of the semiconductor device having memory cells is realized.

[0238] FIG. 10B shows an example of a circuit diagram of a memory cell which is an extension of FIG. 10A.

[0239] The memory cell 1100 shown in FIG. 10B includes a first wiring SL (source line) and a second wiring BL (bit line), a third line S1 (first signal line), and a fourth line S2 (second signal line) a fifth wiring WL (word line), a transistor 1164 (first transistor), A transistor 1161 (a second transistor) and a transistor 1163 (a third transistor) The transistor 1164 and the transistor 1163 are A material other than an oxide semiconductor is used for a channel formation region. A semiconductor is used for the channel formation region.

[0240] Here, the gate electrode of the transistor 1164 and the source electrode of the transistor 1161 The first wiring SL is electrically connected to one of the drain electrodes. The source electrode of the transistor 1164 is electrically connected to the drain electrode of the transistor 1164. The electrode and the source electrode of the transistor 1163 are electrically connected to each other. The second wiring BL and the drain electrode of the transistor 1163 are electrically connected to each other. The wiring S1 and the other of the source electrode and the drain electrode of the transistor 1161 are electrically The fourth wiring S2 and the gate electrode of the transistor 1161 are electrically connected to each other. The fifth wiring WL and the gate electrode of the transistor 1163 are electrically connected to each other. do.

[0241] Next, the operation of the circuit will be specifically described.

[0242] When writing data to the memory cell 1100, the first wiring SL is set to 0 V, and the fifth wiring WL is set to The first wiring BL is set to 0 V, the second wiring BL is set to 0 V, and the fourth wiring S2 is set to 2 V. When data "0" is written, the third line S1 is set to 0V. At this time, the transistor 1163 is in an off state and the transistor 1161 is in an on state. Note that, when writing is completed, before the potential of the third wiring S1 changes, The wiring S2 is set to 0 V, so that the transistor 1161 is turned off.

[0243] As a result, after writing data "1", the node connected to the gate electrode of the transistor 1164 After writing data "0", the potential of the node A is about 2V. 0 V. Charges corresponding to the potential of the third wiring S1 are stored in the node A, but The off-state current of the transistor 1161 is a transistor that uses single crystal silicon for the channel formation region. is small compared to the potential of the gate electrode of transistor 1164, and the potential is maintained for a long time. do.

[0244] Next, when reading the memory cell, the first line SL is set to 0 V and the fifth line WL is set to 2 V. V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and it is connected to the second wiring BL. At this time, the transistor 1163 is in an on state, and the transistor Start 1161 is turned off.

[0245] If the data is "0", that is, if node A is at approximately 0V, the transistor 1164 is in an off state. Therefore, the resistance between the second wiring BL and the first wiring SL is high. When the voltage at node A is "1", that is, when the voltage at node A is about 2 V, the transistor 1164 is in an on state. Therefore, the resistance between the second wiring BL and the first wiring SL is low. The data "0" or "1" can be read out based on the difference in the resistance state of the recell. The second wiring BL was set to 0V when the input was made, but it may be in a floating state or charged to a potential of 0V or higher. The third wiring S1 was set to 0V during readout, but it can be set to a floating state. or may be charged to a potential of 0 V or higher.

[0246] Note that data "1" and data "0" are defined for convenience, and may be reversed. The above-mentioned operating voltage is an example. When the data is "1", the transistor 1164 is turned on. In this way, the transistor 1161 is turned on during writing and turned off during other times. Also, if the transistor 1163 is selected to be in the on state during reading, In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0247] In this embodiment, for ease of understanding, a memory cell having a minimum storage unit (1 bit) will be described. However, the configuration of the memory cells is not limited to this. For example, the memory cells described above can be connected together to form a more advanced semiconductor device. By using these, it is possible to configure a NAND type or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 10(A) or 10(B) and can be changed as appropriate.

[0248] FIG. 11 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a memory capacity of m×n bits. The circuit diagram is shown.

[0249] The semiconductor device shown in FIG. 11 includes m fifth wirings and fourth wirings, n second wirings and A third wiring and a plurality of memory cells 1100(1, 1) to 1100(m, n) are arranged vertically (in rows and columns). A memory cell array 11 arranged in a matrix of n rows and n columns (m and n are natural numbers). 10, the second wiring and the third wiring driving circuit 1111, the fourth wiring and the fifth wiring driving circuit It is composed of peripheral circuits such as a circuit 1113 and a read circuit 1112. A refresh circuit or the like may be provided as a side circuit.

[0250] Consider memory cell 1100(i, j) as a representative of each memory cell. Rule 1100(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is the second The wiring BL(j), the third wiring S1(j), the fifth wiring WL(i) and the fourth wiring S2(i ) and the first wiring. A first wiring potential Vs is applied to the first wiring. In addition, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S 1(n) is a second wiring and a third wiring driver circuit 1111 and a read circuit 1112, The wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are the fourth wirings and They are each connected to a fifth wiring driver circuit 1113 .

[0251] The operation of the semiconductor device shown in FIG. 11 will be described. In this configuration, writing and reading are performed row by row. Make a payment.

[0252] When writing to the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, The potential Vs of the first wiring WL(i) is set to 0 V, the potential of the fifth wiring WL(i) is set to 0 V, and the potentials of the second wirings BL(1) to BL( The fourth wiring S2(i) is set to 0 V, and the fourth wiring S2(i) is set to 2 V. At this time, the transistor 1161 is turned on. The third wiring S1(1) to S1(n) are in a 2V The column to which data "0" is written is set to 0V. Before the potential of the lines S1(1) to S1(n) changes, the fourth line S2(i) is set to 0 V, The transistor 1161 is turned off. The unselected fifth wiring WL is set to 0 V. The fourth wiring S2 is set to 0V.

[0253] As a result, the gate voltage of the transistor 1164 of the memory cell in which data "1" is written The potential of the node connected to the pole (hereinafter, node A) is about 2V, and data “0” is written. The potential of node A of the selected memory cell is about 0V. The position remains unchanged.

[0254] When reading data from the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, The first wiring potential Vs is 0V, the fifth wiring WL(i) is 2V, and the fourth wiring S2(i) is 0V. The third wirings S1(1) to S1(n) are set to 0 V, and the second wirings BL(1) to BL(n) are set to The connected read circuit is put into an operating state. In the read circuit, for example, the resistance of the memory cell is Depending on the difference in resistance state, data "0" and "1" can be read out. The wiring WL is set to 0V, and the unselected fourth wiring S2 is set to 0V. BL is set to 0V, but it may be floating or charged to a potential above 0V. The third wiring S1 was set to 0V during reading, but it may be set in a floating state or charged to a potential of 0V or higher. It doesn't matter if it's electrified.

[0255] Note that data "1" and data "0" are defined for convenience, and may be reversed. The above-mentioned operating voltage is an example. When the data is "1", the transistor 1164 is turned on. In this way, the transistor 1161 is turned on during writing and turned off during other times. Also, if the transistor 1163 is selected to be in the on state during reading, In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0256] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0257] (Embodiment 6) In this embodiment, an example of a circuit diagram of a memory cell having a capacitor is shown. The memory cell 1170 shown in FIG. 1 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, and a A wiring S2, a fifth wiring WL, a transistor 1171 (a first transistor), and a transistor The transistor 1172 (second transistor) and a capacitor element 1173 . The transistor 1171 includes a material other than an oxide semiconductor in a channel formation region. The transistor 1172 has a channel formation region formed using an oxide semiconductor.

[0258] Here, the gate electrode of the transistor 1171 and the source electrode of the transistor 1172 One of the drain electrodes is electrically connected to one of the electrodes of the capacitor 1173. The first wiring SL and the source electrode of the transistor 1171 are electrically connected to each other. The second wiring BL and the drain electrode of the transistor 1171 are electrically connected to each other. The third wiring S1 and the other of the source electrode and the drain electrode of the transistor 1172 are connected to each other. The fourth wiring S2 and the gate electrode of the transistor 1172 are electrically connected to each other. The fifth wiring WL and the other electrode of the capacitor 1173 are electrically connected to each other. There are.

[0259] Next, the operation of the circuit will be specifically described.

[0260] When writing data to the memory cell 1170, the first wiring SL is set to 0 V, and the fifth wiring WL is set to The first wiring BL is set to 0 V, the second wiring BL is set to 0 V, and the fourth wiring S2 is set to 2 V. When data "0" is written, the third line S1 is set to 0V. At this time, the transistor 1172 is turned on. In this case, before the potential of the third wiring S1 changes, the fourth wiring S2 is set to 0 V, and the transistor The controller 1172 is turned off.

[0261] As a result, after writing data "1", The potential of the node (hereinafter referred to as node A) is about 2V. After writing data “0”, the potential of node A becomes approximately 0V.

[0262] When reading the memory cell 1170, the first wiring SL is set to 0 V, and the fifth wiring WL is set to 2V, the fourth wiring S2 is 0V, the third wiring S1 is 0V, and it is connected to the second wiring BL. The read circuit is put into an operating state. At this time, the transistor 1172 is turned off. .

[0263] The state of the transistor 1171 when the fifth wiring WL is set to 2 V will be described. The potential of the node A that determines the state of the transistor 1171 is determined by the capacitance between the fifth wiring WL and the node A. C1, the capacitance C between the gate electrode of the transistor 1171 and the source and drain electrodes Depends on 2.

[0264] Although the third wiring S1 was set to 0V during reading, it may be set to a floating state or a potential of 0V or more. Data "1" and data "0" are just definitions for convenience, and the opposite is true. That's fine.

[0265] The potential of the third wiring S1 during writing is such that the transistor 1172 is turned off after writing. Also, when the potential of the fifth wiring is 0 V, the transistor 1171 is in an off state. The potential of the fifth line during readout is set to the data "0" or "1". When data is "0", the transistor 1171 is turned off, and when data is "1", the transistor The transistor 1171 should be selected so that it is turned on. The threshold voltage is also an example. Any threshold value is acceptable.

[0266] Also, a selection transistor having a first gate electrode and a second gate electrode; FIG. 12B shows an example of a NOR type semiconductor memory device using a memory cell having He explains.

[0267] The semiconductor device according to one embodiment of the present invention shown in FIG. 12B has I rows (I is a natural number of 2 or more). A memory cell array having a plurality of memory cells arranged in a matrix in columns (J is a natural number). It is equipped with (i).

[0268] The memory cell array shown in FIG. 12B has i rows (i is a natural number of 3 or more) and j columns (j is a natural number of 3 or more). A plurality of memory cells 1180 arranged in a matrix (a natural number of 1180 x 1180 x 1180 ) and i word lines W L (word lines WL_1 to WL_i), and i capacitance lines CL (capacitance lines CL_1 to a capacitance line CL_i) and i gate lines BGL (gate lines BGL_1 to BGL _i), j bit lines BL (bit lines BL_1 to BL_j), and a source line SL and.

[0269] Further, each of the plurality of memory cells 1180 (memory cell 1180(M,N) (where , M is a natural number between 1 and i, and N is a natural number between 1 and j) is a transistor 1181(M,N), a capacitance element 1183(M,N), and a transistor 1182(M,N ) and.

[0270] In the semiconductor memory device, the capacitance element includes a first capacitance electrode, a second capacitance electrode, and The capacitance element is composed of a dielectric layer overlapping the first capacitance electrode and the second capacitance electrode. Charge is accumulated between the first capacitive electrode and the second capacitive electrode in response to a voltage applied between the first capacitive electrode and the second capacitive electrode.

[0271] The transistor 1181 (M, N) is an N-channel transistor, and has a source electrode, The semiconductor device has a drain electrode, a first gate electrode, and a second gate electrode. In the semiconductor memory device, the transistor 1181 is not necessarily an N-channel transistor. You don't have to.

[0272] One of the source electrode and the drain electrode of the transistor 1181(M,N) is connected to the bit line BL _N, and the first gate electrode of the transistor 1181(M,N) is connected to the word line WL _M, and the second gate electrode of the transistor 1181(M,N) is connected to the gate line BG The source and drain electrodes of the transistor 1181(M,N) are connected to By configuring one of the terminals to be connected to the bit line BL_N, the de- The data can be read out.

[0273] The transistor 1181(M,N) is a selected transistor in the memory cell 1180(M,N). It functions as a register.

[0274] The transistor 1181 (M, N) is a transistor in which an oxide semiconductor is used for a channel formation region. A transistor can be used.

[0275] The transistor 1182 (M, N) is a P-channel transistor. In the semiconductor memory device of the present embodiment, the transistor 1182 is not necessarily a P-channel transistor. It doesn't have to be sta.

[0276] One of the source electrode and the drain electrode of the transistor 1182(M,N) is connected to the source line SL The other of the source electrode and the drain electrode of the transistor 1182(M,N) is connected to The gate electrode of the transistor 1182(M,N) is connected to the bit line BL_N. The other of the source electrode and drain electrode of the transistor 1181(M,N) is connected to the other of the source electrode and drain electrode of the transistor 1181(M,N).

[0277] The transistor 1182(M,N) is an output transistor in the memory cell 1180(M,N). The transistor 1182 (M, N) has a function as a single-ended transistor. A transistor using crystalline silicon for a channel formation region can be used.

[0278] The first capacitance electrode of the capacitance element 1183(M,N) is connected to the capacitance line CL_M. The second capacitance electrode of 1183(M,N) is the source electrode of the transistor 1181(M,N). The other of the drain electrodes is connected to the drain electrode of the capacitor 1183 (M,N). It has the function as follows.

[0279] The voltages of the word lines WL_1 to WL_i are, for example, driven by a decoder. It is controlled by an automatic circuit.

[0280] The voltages of the bit lines BL_1 to BL_j are, for example, It is controlled by an automatic circuit.

[0281] The voltages of the capacitance lines CL_1 to CL_i are respectively controlled by a driving circuit using a decoder, for example. It is controlled by the path.

[0282] The voltages of the gate lines BGL_1 to BGL_i are respectively set by, for example, a gate line driving circuit. It is controlled using a path.

[0283] The gate line driving circuit includes, for example, a diode and a first capacitance electrode, It is configured with a circuit having a capacitive element electrically connected to the gate line BGL.

[0284] By adjusting the voltage of the second gate electrode of the transistor 1181, the transistor 1 The threshold voltage of the transistor 181 can be adjusted. The threshold voltage of the transistor 1181 is adjusted to reduce the source voltage of the transistor 1181 in the off state. Therefore, the current flowing between the source electrode and the drain electrode can be minimized. The data retention period in the circuit can be extended. The voltage required for readout can be made lower than that of conventional semiconductor devices, reducing power consumption. It is possible.

[0285] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0286] (Embodiment 7) In this embodiment, an example of a semiconductor device including the transistor described in the above embodiment will be described. This will be explained with reference to FIG.

[0287] FIG. 13(A) shows a so-called DRAM (Dynamic Random Access Memory). An example of a semiconductor device having a structure corresponding to a memory cell shown in FIG. The memory array 1120 has a configuration in which a plurality of memory cells 1130 are arranged in a matrix. The memory cell array 1120 includes m first wirings and n second wirings. In this embodiment, the first wiring is called a bit line BL, and the second wiring is called a The line is called the word line WL.

[0288] The memory cell 1130 includes a transistor 1131 and a capacitor 1132. The gate electrode of the transistor 1131 is connected to the first wiring (word line WL). In addition, one of the source electrode and the drain electrode of the transistor 1131 is connected to the second line (bit line BL), and the source electrode or drain electrode of the transistor 1131 The other of the electrodes is connected to one of the electrodes of the capacitance element. The transistor 1131 is connected to a capacitance line CL and is given a constant potential. The transistor shown in the embodiment is applied.

[0289] The transistor in which an oxide semiconductor is used for a channel formation region, which is described in the above embodiment, The off-state current is smaller than that of a transistor using single crystal silicon for the channel formation region. For this reason, the so-called DRAM shown in FIG. When the transistor is applied to a semiconductor device, a substantially non-volatile memory can be obtained. It is possible.

[0290] Figure 13(B) shows a so-called SRAM (Static Random Access Memory). An example of a semiconductor device having a structure corresponding to the memory cell shown in FIG. The array 1140 is configured such that a plurality of memory cells 1150 are arranged in a matrix. In addition, the memory cell array 1140 includes a first wiring (word line WL), a second The pixel has a plurality of wirings (bit lines BL) and a plurality of third wirings (inverted bit lines / BL).

[0291] The memory cell 1150 includes a first transistor 1151, a second transistor 1152, and a third transistor 1153. A third transistor 1153, a fourth transistor 1154, and a fifth transistor 1155 The first transistor 1151 and the second transistor 1152 are connected to the first and second transistors 1153 and 1154. The transistor 1152 functions as a selection transistor. One of the first transistor 1153 and the fourth transistor 1154 is an n-channel transistor (herein Here, the fourth transistor 1154) and the other is a p-channel transistor (here The third transistor 1153 is the third transistor 1154. The fifth transistor 1154 constitutes a CMOS circuit. A CMOS circuit is formed by a sixth transistor 1155 and a sixth transistor 1156.

[0292] A first transistor 1151, a second transistor 1152, and a fourth transistor 115 The fourth and sixth transistors 1156 are n-channel transistors, and are the same as in the previous embodiment. The third transistor 1153 and the transistor shown in the embodiment can be used. The fifth transistor 1155 is a p-channel transistor including a semiconductor other than an oxide semiconductor. A material such as single crystal silicon is used for the channel formation region.

[0293] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0294] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0295] (Embodiment 8) A CPU using at least a part of a transistor in which an oxide semiconductor is used for a channel formation region (Central Processing Unit) can be configured.

[0296] FIG. 14A is a block diagram showing a specific configuration of a CPU. The PU is a logic unit (ALU) on a board 1190. nit) 1191, ALU controller 1192, instruction decoder 1193 , an interrupt controller 1194, a timing controller 1195, and a register 11 96, register controller 1197, bus interface (Bus I / F) 119 8, rewritable ROM 1199, and ROM interface (ROM I / F) 1 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 14(A) is merely a simplified example of the configuration, and in actual CPUs have a wide variety of configurations depending on their applications.

[0297] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0298] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0299] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock generator generates the clock signal CLK2. Supply to the road.

[0300] In the CPU shown in FIG. 14A, a register 1196 is provided with a memory element. The memory element of the master 1196 may be the memory element described in the fifth embodiment. Cut.

[0301] In the CPU shown in FIG. 14A, the register controller 1197 controls the ALU 1191. The holding operation in the register 1196 is selected according to the instruction from the register. In the memory element of the 1196, data is held by a phase inversion element or a capacitance Select whether to hold data by the element. Data retention by the phase inversion element is selected. If the capacitance is set to 0, the power supply voltage is supplied to the storage element in the register 1196. When data retention in the element is selected, data is rewritten to the capacitive element. This allows the supply of power supply voltage to the storage element in the register 1196 to be stopped.

[0302] Regarding the power supply cutoff, as shown in FIG. 14(B) or FIG. 14(C), A switching element is installed between the nodes to which the power supply potential VDD or VSS is applied. The circuits in Fig. 14(B) and Fig. 14(C) are explained below. conduct.

[0303] In FIG. 14B and FIG. 14C, a switch that controls the supply of a power supply potential to a memory element is shown. A memory circuit including a transistor in which an oxide semiconductor is used for a channel formation region, An example is shown below.

[0304] The memory device shown in FIG. 14B includes a switching element 1141 and a memory element 1142. Specifically, each of the memory elements 1142 includes The memory element described in the fifth embodiment can be used. The memory element 1142 is supplied with a high-level power supply potential VD Further, each memory element 1142 in the memory element group 1143 is supplied with a signal D. The potential of the signal IN and the potential of the low-level power supply potential VSS are applied.

[0305] In FIG. 14B, a switching element 1141 is formed by using an oxide semiconductor as a channel formation region. The transistor has a gate electrode connected to the signal Switching is controlled by signal SigA.

[0306] In FIG. 14B, the switching element 1141 has only one transistor. However, there is no particular limitation and a plurality of transistors may be included. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, a combination of series and parallel connections may be used.

[0307] In FIG. 14B, the switching element 1141 changes the The supply of a high-level power supply potential VDD to each memory element 1142 is controlled. Even if the supply of the low-level power supply potential VSS is controlled by the switching element 1141, good.

[0308] In addition, in FIG. 14C, a switch is provided in each memory element 1142 included in the memory element group 1143. A low-level power supply potential VSS is supplied through the switching element 1141. An example is shown in FIG. 1. Each memory element included in the memory element group 1143 is switched by the switching element 1141. The supply of a low-level power supply potential VSS to 1142 can be controlled.

[0309] A switch is provided between the memory element group and a node to which the power supply potential VDD or VSS is applied. When a switching element is provided to temporarily stop the CPU operation and the supply of power voltage is stopped, It is possible to retain data even in a low power state, and power consumption can be reduced. Specifically, for example, a user of a personal computer may input commands to an input device such as a keyboard. Even when you stop inputting information, the CPU can be stopped, reducing power consumption. The power consumption can be reduced.

[0310] Here, we have taken the CPU as an example, but the same can also be said for DSP (Digital Signal Processor). processor), custom LSI, FPGA (Field Programmable Gauge It can also be applied to LSIs such as MOSFET's (MOSFET gate arrays).

[0311] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0312] 100 transistors 101 Substrate 102 Base layer 103 Oxide semiconductor layer 104 Gate insulation layer 105 Gate electrode 106 Dopant 107 Insulating layer 108 Insulating layer 109 Contact Hole 111 Sidewall 112 Channel Protection Layer 113 Insulating Layer 115 Back gate electrode 140 Transistor 150 Transistors 160 Transistors 170 Transistors 180 Transistors 190 Transistors 1100 memory cells 1110 Memory Cell Array 1111 Wiring drive circuit 1112 Circuit 1113 Wiring drive circuit 1120 Memory Cell Array 1130 Memory Cells 1131 Transistor 1132 Capacitive element 1140 Memory Cell Array 1141 Switching element 1142 Memory element 1143 Memory Element Group 1150 memory cells 1151 Transistor 1152 Transistor 1153 Transistor 1154 Transistor 1155 Transistor 1156 Transistor 1160 Transistor 1161 Transistor 1162 Transistor 1163 Transistor 1164 Transistor 1170 Memory Cells 1171 Transistor 1172 Transistor 1173 Capacitive element 1180 memory cells 1181 Transistor 1182 Transistor 1183 Capacitive element 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 103a Source Area 103b Drain region 103c Channel formation region 103d Low concentration area 103e Low concentration area 105a Gate electrode 105b Gate electrode 110a source electrode 110b Drain electrode

Claims

[Claim 1] a gate electrode, a gate insulating layer, a crystalline oxide semiconductor layer, and a channel protection layer; the gate insulating layer is formed on the gate electrode; the oxide semiconductor layer is formed on the gate insulating layer, the channel protection layer is formed on the oxide semiconductor layer, the oxide semiconductor layer includes a first oxide semiconductor region and a pair of second oxide semiconductor regions; the pair of second oxide semiconductor regions are formed to sandwich the first oxide semiconductor region, the first oxide semiconductor region overlaps with the gate electrode via the gate insulating layer and is in contact with the channel protection layer; The second oxide semiconductor region contains at least one of a rare gas and hydrogen at a concentration of 5×10 19 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less.

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