Signal processing method, signal processing device, photoelectric conversion device, equipment

Abstract

To reduce noise.SOLUTION: A signal processing method, for performing analog to digital (AD) conversion to convert an analog signal to a digital signal with different number of bits by using a ramp signal having slope, performs first AD conversion for converting signal to digital signal with first bit number using at least either a first ramp signal having first slope or a second ramp signal having second slope having grater slope than the first slope, and second AD conversion for converting signal to a digital signal with second bit number less than the first bit number by using at least either a third ramp signal having third slope or fourth ramp signal having fourth slope grater slope than the third slope, the ratio of the second slop against the first slope is less than the ratio of the fourth slope against the third slope.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a signal processing method, a signal processing device, and an apparatus. [Background technology]

[0002] Patent Document 1 discloses an AD (Analog-Digital) converter that converts pixel signals output from pixels into digital signals. The AD converter disclosed in Patent Document 1 is said to achieve a high dynamic range and high-speed driving by using ramp signals with different slopes (amount of voltage change per unit time). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-126241 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in an AD converter such as that shown in Patent Document 1, noise may occur due to the influence of quantization error.

[0005] An object of the present invention is to provide a signal processing method capable of reducing noise in AD conversion using ramp signals having different slopes. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a signal processing method for performing analog-to-digital (AD) conversion using a ramp signal having a slope to convert an analog signal into a digital signal with a different number of bits, the signal processing method comprising: a first AD conversion for converting an analog signal into a digital signal with a first number of bits using at least one of a first ramp signal with a first slope and a second ramp signal with a second slope larger than the first slope; and a second AD conversion for converting an analog signal into a digital signal with a second number of bits smaller than the first number of bits using at least one of a third ramp signal with a third slope and a fourth ramp signal with a fourth slope larger than the third slope, wherein a ratio of the second slope to the first slope is smaller than a ratio of the fourth slope to the third slope. Effect of the Invention

[0007] According to the present invention, it is possible to reduce noise in AD conversion using ramp signals having different slopes. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Diagram 2] FIG. 1 is a circuit diagram illustrating a pixel according to a first embodiment; [Diagram 3] FIG. 1 is a drive timing chart illustrating a signal processing method according to a first embodiment. [Figure 4] FIG. 11 is a block diagram illustrating a photoelectric conversion device according to a second embodiment. [Diagram 5] FIG. 11 is a drive timing chart for explaining a signal processing method according to the second embodiment. [Figure 6] FIG. 11 is a block diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 7] FIG. 11 is a drive timing chart illustrating a signal processing method according to the third embodiment. [Figure 8] FIG. 13 is a block diagram illustrating a photoelectric conversion device according to a fourth embodiment. [Figure 9] FIG. 13 is a drive timing chart for explaining a signal processing method according to the fourth embodiment. [Figure 10] FIG. 13 is a plan view illustrating a pixel array unit according to the fifth embodiment. [Figure 11] FIG. 13 is a drive timing chart illustrating a signal processing method according to the fifth embodiment. [Figure 12] FIG. 13 is a drive timing chart illustrating a signal processing method according to the fifth embodiment. [Figure 13] FIG. 13 is a diagram for explaining a correction process of a signal processing method according to the fifth embodiment. [Figure 14] FIG. 13 is a schematic diagram illustrating a device according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these features are necessarily essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same or similar configurations are given the same reference numbers, and duplicated descriptions are omitted. Furthermore, in each embodiment described below, a sensor for imaging will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to a sensor for imaging, and can be applied to other examples of photoelectric conversion devices. For example, there are an imaging device, a distance measuring device (a device for distance measurement using focus detection or TOF (Time Of Flight), a photometric device (a device for measuring the amount of incident light, etc.), and the like.

[0010] In the following description, it is assumed that the charge accumulated by the photoelectric conversion unit in the pixel is an electron. Also, it is assumed that all the transistors provided in the pixel are N-channel type MOS transistors (hereinafter abbreviated as NMOS transistors). However, the charge accumulated by the photoelectric conversion unit may be holes, in which case the transistor of the pixel may be a P-channel type MOS transistor (hereinafter abbreviated as PMOS transistor). In other words, the conductivity type of the transistors etc. can be appropriately changed according to the polarity of the charge treated as a signal.

[0011] First Embodiment A signal processing method according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG.

[0012] 1 is a block diagram of an example of an apparatus for implementing the signal processing method according to the present embodiment. The apparatus for implementing the signal processing method is, for example, a photoelectric conversion apparatus such as a CMOS image sensor, and the present specification will be described using a photoelectric conversion apparatus.

[0013] 1, the photoelectric conversion device 1 includes a pixel array section 10, signal lines 12, a row selection circuit 15, a column signal processing circuit 20, a reference signal output circuit 30, a counter circuit 40, and a column selection circuit 50. The photoelectric conversion device 1 also includes a DSP (Digital Signal Processor) 60, an output circuit 70, and a timing generation circuit (control unit) 80. In this specification, the signal processing circuit includes at least the column signal processing circuit 20 and the timing generation circuit (control unit) 80.

[0014] In the pixel array unit 10, a plurality of pixels 11 are arranged in a matrix across a plurality of rows and a plurality of columns. The pixels 11 generate pixel signals by photoelectric conversion. In addition, signal lines 12 and column signal processing circuits 20 are arranged so as to correspond to each column of the pixels 11. The column signal processing circuit 20 includes an AD (Analog Digital) conversion circuit 22 and a memory circuit 24. The AD conversion circuit 22 includes a comparator 221 and a selection circuit 222. A pixel signal output from the pixel 11 is input to one input terminal of the comparator 221 included in the corresponding column signal processing circuit 20 via the corresponding signal line 12. In addition, the reference signal output circuit 30 outputs a ramp signal VRAMP, which is a signal whose voltage changes with the passage of time. The output ramp signal VRAMP is input to the other input terminal of the comparator 221 via the selection circuit 222. The AD conversion circuit 22 performs AD (analog digital) conversion on the pixel signal, which is an analog signal, using the ramp signal VRAMP, and outputs a digital signal.

[0015] The reference signal output circuit 30 may generate the ramp signal VRAMP, or a circuit different from the reference signal output circuit 30 may generate the ramp signal VRAMP. In this embodiment, a ramp signal VRAMP having a constant slope (amount of voltage change per unit time) is used, but a ramp signal VRAMP whose slope changes midway may also be used. The ramp signal VRAMP whose slope changes midway may change in a step-like manner, for example. The reference signal output circuit 30 can output a plurality of ramp signals VRAMP having different slopes, and the selection circuit 222 selects one of the plurality of ramp signals VRAMP.

[0016] The counter circuit 40 outputs a count signal CNT used for AD conversion performed in the column signal processing circuit 20. The count signal CNT is a signal that counts the clock pulse signal CLK supplied from a clock pulse supply circuit (not shown) from the time when the ramp signal VRAMP of the reference signal output circuit 30 starts to change depending on time. Note that the counter circuit 40 shown in FIG. 1 is provided in common to each column signal processing circuit 20, but may be provided corresponding to each column signal processing circuit 20.

[0017] The memory circuit 24 includes a flag memory 241, an S memory 242, and an N memory 243. The comparator 221 outputs a comparison result signal indicating a result of comparing the pixel signal input via the signal line 12 with the ramp signal VRAMP to the memory circuit 24. Specifically, the comparator 221 outputs a low level when the voltage of the ramp signal VRAMP is higher than the voltage of the pixel signal (when the signal amplitude of the ramp signal VRAMP is smaller than that of the pixel signal). The comparator 221 outputs a high level when the voltage of the ramp signal VRAMP is lower than the voltage of the pixel signal (when the signal amplitude of the ramp signal VRAMP is larger than that of the pixel signal). This signal amplitude means a difference voltage with respect to a reference voltage that serves as a reference. Here, this reference voltage can be considered as the voltage of a reset level signal (described later) output by the pixel 11. From another perspective, it can be considered as a power supply voltage supplied to an amplification transistor 430 (described later) of the pixel 11. Note that the relationship between the high level and the low level at this time is just an example, and the relationship may be reversed. The memory circuit 24 holds the count signal CNT output from the counter circuit 40 based on a change in the signal level of the comparison result signal output from the comparator 221. As a result, the memory circuit 24 holds the count signal CNT having a signal value corresponding to the value of the pixel signal as a digital signal corresponding to the pixel signal, and the pixel signal output from the pixel 11 is AD converted.

[0018] The N memory 243 holds a digital signal obtained by AD converting a reset level signal (hereinafter, N signal) of the floating diffusion section 420 described later. Note that this digital signal also includes a component of characteristic variation for each column signal processing circuit 20. The S memory 242 holds a digital signal obtained by AD converting a signal (hereinafter, S signal) obtained by superimposing a signal (photoelectric conversion signal) of the photoelectric conversion section 400 described later on the N signal of the FD section 420. The flag memory 241 holds the result (hereinafter, J signal) of comparing the threshold voltage and the pixel signal output by the reference signal output circuit 30 with each other by the comparator 221. The J signal is also input to the selection circuit 222. In this embodiment, the reference signal output circuit 30 outputs a signal whose voltage changes with time when outputting the threshold voltage, but the threshold voltage may be output as a constant signal whose voltage does not change with time. Note that a circuit provided separately from the reference signal output circuit 30 may generate or output the above-mentioned constant signal whose voltage does not change.

[0019] The column selection circuit 50 selects the memory circuit 24. The signals held in the selected memory circuit 24 are sequentially transferred to the DSP 60 by the horizontal scanning signal output from the column selection circuit 50. The row selection circuit 15 performs an operation of sequentially selecting a predetermined row. The DSP 60 performs a correction process on the obtained signal. For example, the digitalized N signal is subtracted from the digitalized S signal in the DSP 60, and a signal with reduced noise components is output. The output circuit 70 outputs the signal output from the DSP 60 to the outside of the photoelectric conversion device 1. The output circuit 70 may have a buffer function. The timing generation circuit 80 supplies drive signals to the row selection circuit 15, the column signal processing circuit 20, the reference signal output circuit 30, the counter circuit 40, and the column selection circuit 50.

[0020] FIG. 2 is an example of a circuit diagram of a pixel 11 included in a photoelectric conversion device 1 that performs a signal processing method according to this embodiment.

[0021] As shown in FIG. 2, the pixel 11 includes a photoelectric conversion unit 400, a transfer transistor 410, and a floating diffusion unit 420. Hereinafter, in this specification, the floating diffusion unit 420 may be referred to as an FD unit 420 (FD is an abbreviation for floating diffusion). Furthermore, the pixel 11 has a reset transistor 455 for resetting the FD unit 420, an amplification transistor 430 for amplifying a signal, and a selection transistor 440. Furthermore, the photoelectric conversion unit 400 is electrically connected to a ground voltage node 450. Furthermore, the reset transistor 455 and the amplification transistor 430 are electrically connected to a power supply voltage node 460, and a power supply voltage is supplied thereto. Note that the selection transistor 440 may not be disposed. Note that each of the transfer transistor 410, the reset transistor 455, the amplification transistor 430, and the selection transistor 440 may be an N-type MOS transistor or a P-type MOS transistor.

[0022] The photoelectric conversion unit 400 is, for example, a photodiode. The photoelectric conversion unit 400 is not limited to a photodiode, and may be, for example, a photoelectric conversion film. The photoelectric conversion unit 400 receives light incident on the pixel 11 and generates charges according to the incident light. The reset transistor 455 is driven by a control signal RES. When the reset transistor 455 is turned on, the FD unit 420 is reset to a voltage based on the power supply voltage. When the reset transistor 455 is turned off, the reset of the FD unit 420 is released. The transfer transistor 410 is driven by a control signal TX. When the transfer transistor 410 is turned on, the charge generated in the photoelectric conversion unit 400 is transferred to the FD unit 420. The FD unit 420 temporarily holds the charge input from the photoelectric conversion unit 400 and functions as a charge-voltage conversion unit that converts the held charge into a voltage signal. The amplification transistor 430 amplifies the pixel signal converted by the FD unit 420. The selection transistor 440 is driven by a control signal SEL to connect the amplification transistor 430 to the signal line 12 and output the pixel signal amplified by the amplification transistor 430 to the signal line 12. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0023] 2 is an example, and the pixel 11 may further include a transistor. For example, a transistor for changing the capacitance value of the FD section 420 or a transistor for discharging charge from the photoelectric conversion section 400 may further be provided. Alternatively, the pixel 11 may be configured not to include the selection transistor 440, and the selected / unselected state of the pixel 11 may be changed by the voltage input from the reset transistor 455 to the FD section 420.

[0024] FIG. 3 is an example of a drive timing chart of the photoelectric conversion device 1 which performs the signal processing method according to this embodiment.

[0025] In FIG. 3, the horizontal axis indicates time and the vertical axis indicates voltage, and the timing of each drive pulse, pixel signal, and reference signal are shown. Each control signal shown in FIG. 3 corresponds to each control signal shown in FIG. 2. The period from time t408 to time t410, in which the slope of the ramp signal VRAMP used for AD conversion is set, is defined as the first step. The period from time t411 to time t413, in which the AD conversion of the S signal is performed, is defined as the second step, and the period from time t402 to time t404, in which the AD conversion of the N signal is performed, is defined as the third step. The operation of transferring the charge from the photoelectric conversion unit 400 of the pixel 11 is performed at multiple timings, and for example, the first step and the second step are each performed between two consecutive timings among the multiple timings. In addition to the first step and the second step, the third step may be performed between two consecutive timings among the above multiple timings. The operation of transferring the charge from the photoelectric conversion unit of the pixel 11 is performed at multiple timings, including, for example, a case where it is performed once each in multiple frames. Moreover, the operation of transferring charges from the photoelectric conversion unit of the pixel 11 being performed at multiple timings includes, for example, the case where the operation is performed multiple times within one frame.

[0026] At time t400, the row selection circuit 15 sets the control signal SEL to a high level to select a row of the pixel 11 from which the pixel signal PIXOUT is to be output. The row selection circuit 15 also sets the control signal RES to a high level to reset the voltage of the FD unit 420. At time t401, the row selection circuit 15 sets the control signal RES to a low level. The pixel signal PIXOUT output when the control signal RES is set to a low level is an N signal. The N signal is a signal that mainly contains noise components that the pixel 11 has.

[0027] During the period from time t402 to time t404, the reference signal output circuit 30 increases the voltage of the ramp signal VRAMP_L from the initial value depending on time. The reference signal output circuit 30 can output multiple ramp signals VRAMP with different slopes in parallel and input them to the column signal processing circuit 20. The multiple ramp signals VRAMP with different slopes are, for example, a ramp signal VRAMP_L with a small slope, a ramp signal VRAMP_H with a large slope, and a ramp signal VRAMP_J with an even larger slope. In FIG. 3, for example, the ramp signal VRAMP_L is input to the comparator 221 via the selection circuit 222. By using the ramp signal VRAMP_L as a reference signal, the amount of voltage change per unit time is smaller than when the ramp signal VRAMP_H is used, so that AD conversion with high resolution can be performed. Therefore, during the period from time t402 to time t404, the pixel signal PIXOUT, which is an analog signal, is converted into a digital signal based on the result of comparing the pixel signal PIXOUT with the ramp signal VRAMP_L. The above driving is performed by sending control signals from the timing generating circuit 80 to the reference signal output circuit 30 and the selection circuit 222.

[0028] At time t402, the voltage change of the ramp signal VRAMP_L starts, and the counter circuit 40 starts counting the clock pulse signal and supplies the count signal CNT to the N memory 243 of each column. At time t403, the voltage of the ramp signal VRAMP_L exceeds the pixel signal PIXOUT, and the signal value of the comparator output COMPOUT output by the comparator 221 changes. The value of the count signal CNT at this time (count value) is held by the N memory 243. The value of the count signal CNT held by the N memory 243 at this time is the digital value obtained by AD converting the N signal. At time t404, the time-dependent voltage change of the ramp signal VRAMP_L stops, and is reset to the state of time t400. The counter circuit 40 stops counting the clock pulse signal, and returns the count signal CNT to its initial value.

[0029] At time t405, the control signal TX is set to a high level, and at time t406, the control signal TX is set to a low level. As a result, charges generated by light incident on the photoelectric conversion unit 400 are transferred to the FD unit 420. The amplification transistor 430 outputs a voltage signal based on the charges transferred to the FD unit 420. This voltage signal is output to the signal line 12 via the selection transistor 440, and the pixel signal is input to one input terminal of the comparator 221. This signal is an S signal, which is one of the pixel signals PIXOUT. The S signal is an analog signal having a voltage according to the amount of light received by the photoelectric conversion unit 400 in one frame period.

[0030] In the period from time t408 to time t409, the reference signal output circuit 30 increases the voltage of the ramp signal VRAMP_J from the initial value depending on time. At time t409, the voltage change of the ramp signal VRAMP_J is stopped. The voltage of the ramp signal VRAMP_J at time t409 becomes the threshold voltage VREF. This threshold voltage VREF is used as a threshold for determining whether the ramp signal VRAMP_L or VRAMP_H is to be selected as the ramp signal for AD converting the pixel signal PIXOUT. The value of the threshold voltage VREF is smaller than the final reaching voltage value (maximum value) of the ramp signal VRAMP_L.

[0031] In the period from time t409 to time t410, the comparator 221 compares the threshold voltage VREF with the pixel signal PIXOUT. When the voltage of the pixel signal PIXOUT is higher than the threshold voltage VREF (when the signal amplitude of the pixel signal PIXOUT is smaller than the threshold voltage VREF), the comparator output COMPOUT (J signal) changes from low level to high level (=1). The comparator output COMPOUT based on the result of comparing the threshold voltage VREF with the pixel signal PIXOUT is input to the selection circuit 222. Then, the selection circuit 222 selects the ramp signal VRAMP_L and inputs it to the comparator 221. When the voltage of the pixel signal PIXOUT is higher than the threshold voltage VREF, the ramp signal VRAMP_L with a smaller slope is used for AD conversion. That is, the ramp signal VRAMP_L is used in the second step based on the comparison result of the first step.

[0032] When the voltage of the pixel signal PIXOUT is lower than the threshold voltage VREF (when the signal amplitude of the pixel signal PIXOUT is greater than the threshold voltage VREF), the comparator output COMPOUT (J signal) remains at low level (=0). The comparator output COMPOUT based on the result of comparing the threshold voltage VREF with the pixel signal PIXOUT is input to the selection circuit 222. Then, the selection circuit 222 selects the ramp signal VRAMP_H and inputs it to the comparator 221. When the voltage of the pixel signal PIXOUT is lower than the threshold voltage VREF (when the signal amplitude is large), the ramp signal VRAMP_H, which has a larger slope than the ramp signal VRAMP_L, is used for AD conversion. That is, based on the comparison result of the first step, the ramp signal VRAMP_H is used in the second step.

[0033] The above driving method allows AD conversion with an appropriate resolution according to the signal output level of the pixel signal PIXOUT. In other words, it is possible to achieve a high dynamic range and high-speed driving. Note that Figure 3 shows a case where the voltage of the pixel signal PIXOUT is lower than the threshold voltage VREF and the ramp signal VRAMP_H is used in the second step.

[0034] In the period from time t409 to time t410, the value of the comparator output COMPOUT (J signal) is input to the selection circuit 222. The J signal is also held in the flag memory 241. At time t410, the determination of which of the ramp signals VRAMP_H and VRAMP_L is to be used during the AD conversion period of the S signal is completed, and the voltage of the ramp signal VRAMP_J is reset.

[0035] During the period from time t411 to time t413, the reference signal output circuit 30 increases the voltage of the ramp signal VRAMP_L or the ramp signal VRAMP_H from the initial value depending on time. Then, the pixel signal PIXOUT is compared with the ramp signal VRAMP_L or the ramp signal VRAMP_H. Furthermore, based on the comparison result, the pixel signal PIXOUT is converted into a digital signal. Which of the ramp signals VRAMP_L and VRAMP_H is input to the comparator 221 by each column signal processing circuit 20 is determined according to the value (J signal) of the comparator output COMPOUT during the period from time t409 to time t410. In the case of FIG. 3, if the voltage of the pixel signal PIXOUT during the period from time t409 to time t410 is lower than the threshold voltage VREF, the ramp signal VRAMP_H with a steeper slope is selected.

[0036] At time t411, the voltage change of the ramp signal VRAMP_L or the ramp signal VRAMP_H starts, and the counter circuit 40 starts counting the clock pulse signals and supplies the count signal CNT to the S memory 242 of each column.

[0037] At time t412, the voltage of the ramp signal VRAMP_L or the ramp signal VRAMP_H exceeds the pixel signal PIXOUT, and the signal value of the comparator output COMPOUT changes. The value of the count signal CNT (count value) at this time is held by the S memory 242. The value of the count signal CNT held by the S memory 242 at this time is a digital value obtained by AD converting the S signal.

[0038] At time t413, the time-dependent voltage change of the ramp signal VRAMP_L or the ramp signal VRAMP_H is stopped and reset to the state at time t400. The counter circuit 40 stops counting the clock pulse signal and returns the count signal CNT to the initial value.

[0039] After time t414, the column signal processing circuits 20 are sequentially operated by the horizontal scanning signal output from the column selection circuit 50, and the signals held in the flag memory 241, the S memory 242, and the N memory 243 are sent to the DSP 60. Then, after arithmetic processing is performed, the signals are output to the outside of the photoelectric conversion device 1.

[0040] The DSP 60 calculates a differential signal level (optical component) by subtracting the digitized N signal from the digitized S signal.

[0041] Here, as the second step, a first AD conversion for converting into a digital signal with a first bit number and a second AD conversion for converting into a digital signal with a second bit number smaller than the first bit number are considered to be performed in different frames. The ramp signal VRAMP_L used in the first AD conversion is a first ramp signal with a first slope, and the ramp signal VRAMP_H is a second ramp signal with a second slope. The ramp signal VRAMP_L used in the second AD conversion is a third ramp signal with a third slope, and the ramp signal VRAMP_H is a fourth ramp signal with a fourth slope. Note that the ratio of the number of gradations of the first AD conversion to the number of gradations of the second AD conversion is approximately equal to the ratio of the fourth slope to the second slope. Also, the final voltage value (maximum value) of the second ramp signal and the final voltage value (maximum value) of the fourth ramp signal may be approximately equal. Note that the relationship of "approximately equal" here will be explained. Although they are equal in design, a slight difference may occur due to manufacturing errors. The term "substantially equal" includes slight differences caused by manufacturing errors.

[0042] For example, when the ratio of the second slope to the first slope is equal to or greater than the ratio of the fourth slope to the third slope, the second AD conversion may generate more noise than the first AD conversion due to the influence of quantization error. However, in this embodiment, by making the ratio of the second slope to the first slope smaller than the ratio of the fourth slope to the third slope, the influence of quantization error in the second AD conversion is reduced, and noise can be reduced.

[0043] Also, a device (e.g., a camera) equipped with a photoelectric conversion device may have a plurality of modes. The plurality of modes may be, for example, a still image acquisition mode and a video acquisition mode, or a high-resolution mode and a low-resolution mode for a captured image. The signal processing circuit may also have a plurality of modes with different AD conversion operations. The mode of the signal processing circuit may be changed according to the mode executed by the device. That is, the signal processing circuit may have a first mode in which the second AD conversion is not performed during a period in which a plurality of first AD conversions are performed, and a second mode in which the first AD conversion is not performed during a period in which a plurality of second AD conversions are performed. For example, when the obtained photoelectric conversion signal is used as an imaging signal, the optimal resolution of AD conversion differs for each imaging purpose, so that AD conversion with a different number of bits (number of gradations) is performed. For example, in the still image acquisition mode, high-resolution AD conversion is performed to obtain a digital signal used for a still image, and in the video acquisition mode, low-resolution AD conversion is performed to obtain a digital signal used for a video. Therefore, the above-mentioned first mode may be performed as the still image acquisition mode, and the above-mentioned second mode may be performed as the video acquisition mode. It should be noted that a live view acquisition mode may be provided, and in the live view acquisition mode, further low-resolution AD conversion may be performed to acquire a digital signal to be used for the live view.

[0044] Here, the threshold voltage VREF used when the first step is performed corresponding to the first AD conversion in order to determine the ramp signal VRAMP used in the first AD conversion (second step) is defined as a first threshold voltage VREF1. Also, the threshold voltage VREF used when the first step is performed corresponding to the second AD conversion in order to determine the ramp signal VRAMP used in the second AD conversion (second step) is defined as a second threshold voltage VREF2. The voltage (signal amplitude) of the second threshold voltage VREF2 may be smaller than the voltage (signal amplitude) of the first threshold voltage VREF1.

[0045] Note that, before the first AD conversion and the second AD conversion, AD conversion of N signals (third step) performed during the period from time t402 to time t404 in Fig. 3 may be performed as a third AD conversion. The third AD conversion can use a ramp signal with a different slope. For example, the third AD conversion corresponding to the first AD conversion uses the first ramp signal or the second ramp signal, and the third AD conversion corresponding to the second AD conversion uses the third ramp signal or the fourth ramp signal.

[0046] The ratio of the number of gray scales of the first AD conversion to the number of gray scales of the second AD conversion may be smaller than the ratio of the fourth gradient to the third gradient.

[0047] In order to make the AD conversion gains uniform between the first AD conversion with the first bit number and the second AD conversion with the second bit number, the AD conversion result of the second AD conversion may be bit-extended to the first bit number by the DSP 60. However, this is not limited to the example, and the DSP 60 may not perform bit extension, and the output circuit 70 may output a digital signal with the second bit number unchanged to the outside of the photoelectric conversion device 1.

[0048] As described above, this embodiment can use ramp signals with different slopes, and performs AD conversion to convert to digital signals with different numbers of bits. In this operation, the ratio of the slope of the ramp signal in AD conversion with a small number of bits is made larger than the ratio of the slope of the ramp signal in AD conversion with a large number of bits. By performing such a signal processing method, the effect of quantization error is reduced in AD conversion with a small number of bits, making it possible to reduce noise.

[0049] Second Embodiment A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figures 4 and 5. Note that components similar to those in the first embodiment are given the same reference numerals, and descriptions of these components may be omitted or simplified.

[0050] This embodiment differs from the first embodiment in that AD conversion is performed using ramp signals VRAMP with different slopes for one N signal. Fig. 4 is an example of a block diagram of a photoelectric conversion device that implements the signal processing method according to this embodiment.

[0051] 4, in addition to the configuration in Fig. 1, the memory circuit 24 includes an N memory 244. Like the N memory 243, the N memory 244 holds a digital signal obtained by AD converting the N signal.

[0052] FIG. 5 is an example of a drive timing chart of the photoelectric conversion device 1 that performs the signal processing method according to this embodiment.

[0053] In FIG. 5, the horizontal axis indicates time and the vertical axis indicates voltage, and the timing of each drive pulse, pixel signal, and reference signal are shown. Each control signal shown in FIG. 5 corresponds to each control signal shown in FIG. 2. The period from time t408 to time t410, in which the slope of the ramp signal VRAMP used for AD conversion is set, is defined as the first step. The period from time t411 to time t413, in which AD conversion of the S signal is performed, is defined as the second step, and the period from time t500 to time t404, in which AD conversion of the N signal is performed, is defined as the third step. The signal processing method other than the third step is the same as that of the first embodiment. Below, the signal processing method of the third step, which is different from that of the first embodiment, will be described with reference to FIG. 5.

[0054] The signal processing method in the period from time t400 to time t500 is similar to the signal processing method in the period from time t400 to time t402 described with reference to FIG.

[0055] In the period from time t500 to time t502, the voltage of the ramp signal VRAMP_H is time-dependently decreased from the initial value by the reference signal output circuit 30. In the period from time t500 to time t502, the pixel signal PIXOUT and the ramp signal VRAMP_H are compared. Then, based on the result of the comparison, the pixel signal PIXOUT, which is an analog signal, is converted into a digital signal.

[0056] At time t500, the voltage change of the ramp signal VRAMP_H starts, and the counter circuit 40 starts counting the clock pulse signal and supplies the count signal CNT to the N memory 244 of each column. At time t501, the voltage of the ramp signal VRAMP_H falls below the pixel signal PIXOUT, and the signal value of the comparator output COMPOUT output by the comparator 221 changes. The value of the count signal CNT at this time (count value) is held by the N memory 244. The value of the count signal CNT held by the N memory 244 at this time is the digital value obtained by AD converting the N signal. At time t502, the time-dependent voltage change of the ramp signal VRAMP_H stops, and is reset to the state of time t400. The counter circuit 40 stops counting the clock pulse signal, and returns the count signal CNT to its initial value.

[0057] In the period from time t402 to time t404, the voltage of the ramp signal VRAMP_L is time-dependently decreased from the initial value by the reference signal output circuit 30. In the period from time t402 to time t404, the pixel signal PIXOUT and the ramp signal VRAMP_L are compared. Then, based on the result of the comparison, the pixel signal PIXOUT, which is an analog signal, is converted into a digital signal.

[0058] At time t402, the voltage change of the ramp signal VRAMP_L starts, and the counter circuit 40 starts counting the clock pulse signal and supplies the count signal CNT to the N memory 243 of each column. At time t403, the voltage of the ramp signal VRAMP_L falls below the pixel signal PIXOUT, and the signal value of the comparator output COMPOUT output by the comparator 221 changes. The value of the count signal CNT at this time (count value) is held by the N memory 243. The value of the count signal CNT held by the N memory 243 at this time is the digital value obtained by AD converting the N signal. At time t404, the time-dependent voltage change of the ramp signal VRAMP_L stops, and is reset to the state of time t400. The counter circuit 40 stops counting the clock pulse signal, and returns the count signal CNT to its initial value.

[0059] Therefore, in the third step in the period from time t500 to time t404, AD conversion using ramp signals VRAMP with different slopes is continuously performed on one N signal. Continuously performing AD conversion means that after AD conversion using one of the multiple ramp signals is completed, AD conversion using the other of the multiple ramp signals is started. In Fig. 5, AD conversion using the ramp signal VRAMP_L is started after AD conversion using the ramp signal VRAMP_H is completed.

[0060] The signal processing method during the period from time t404 to time t414 is the same as the signal processing method during the period from time t404 to time t414 described in Fig. 3. Note that Fig. 5 shows a case where the voltage of the pixel signal PIXOUT is lower than the threshold voltage VREF and the ramp signal VRAMP_H is used in the second step. After time t414, the horizontal scanning signal output from the column selection circuit 50 sequentially operates the column signal processing circuit 20, and the signals held in the flag memory 241, S memory 242, N memory 243, and N memory 244 are sent to the DSP 60. Then, after arithmetic processing, the signals are output to the outside of the photoelectric conversion device 1.

[0061] DSP 60 calculates a differential signal level (light component) by subtracting the digitized N signal from the digitized S signal. Here, the S signal held in S memory 242 may be subjected to differential processing with either the N signal held in N memory 243 or N memory 244. A digital signal with fewer noise components can be obtained by calculating the difference between the S signal and the N signal using the AD conversion result of the N signal using a ramp signal with the same slope as the ramp signal selected during AD conversion of the S signal.

[0062] 5, the ramp signal VRAMP_H is used from time t500 to time t502, and the ramp signal VRAMP_L is used from time t402 to time t404, but either of the ramp signals with different slopes may be used first. In other words, the ramp signal VRAMP_L may be used from time t500 to time t502, and the ramp signal VRAMP_H may be used from time t402 to time t404.

[0063] In this embodiment, as in the first embodiment, the first AD conversion for converting into a digital signal with a first bit number and the second AD conversion for converting into a digital signal with a second bit number smaller than the first bit number can be performed in different frames as the second step. Also, before the first AD conversion and the second AD conversion, AD conversion of the N signal (third step) performed in the period from time t500 to time t404 in Fig. 5 may be performed as the third AD conversion. In this embodiment, too, the ratio of the second slope to the first slope is made smaller than the ratio of the fourth slope to the third slope, thereby reducing the effect of quantization error in the second AD conversion and reducing noise.

[0064] As described above, this embodiment can use ramp signals with different slopes, and performs AD conversion to convert to digital signals with different numbers of bits. In this operation, the ratio of the slope of the ramp signal in AD conversion with a small number of bits is made larger than the ratio of the slope of the ramp signal in AD conversion with a large number of bits. By performing such a signal processing method, the effect of quantization error is reduced in AD conversion with a small number of bits, making it possible to reduce noise.

[0065] Furthermore, in this embodiment, in the AD conversion of the N signal, multiple AD conversions are performed on one N signal using ramp signals with different slopes. As a result, the AD conversion result of the N signal using a ramp signal with the same slope as the ramp signal used in the AD conversion of the S signal can be used when calculating the difference between the S signal and the N signal. By performing signal processing in this manner, it is possible to obtain a digital signal in which the characteristic variation for each column signal processing circuit 20 is reduced with high accuracy.

[0066] Third embodiment A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figures 6 and 7. Note that the same components as those in the first and second embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0067] This embodiment differs from the first and second embodiments in that a ramp signal VRAMP having a different slope is used to perform AD conversion on one pixel signal PIXOUT (S signal and N signal). Fig. 6 is an example of a block diagram of a photoelectric conversion device that implements a signal processing method according to this embodiment.

[0068] 6, unlike the configuration in Fig. 4, the memory circuit 24 does not include the flag memory 241 but includes an S memory 245. Like the S memory 242, the S memory 245 holds a digital signal obtained by AD converting the S signal.

[0069] FIG. 7 is an example of a drive timing chart of the photoelectric conversion device 1 that performs the signal processing method according to this embodiment.

[0070] In Fig. 7, the horizontal axis indicates time and the vertical axis indicates voltage, and the timing of each drive pulse, pixel signal, and reference signal are shown. The control signals shown in Fig. 7 correspond to the control signals shown in Fig. 2. The period from time t600 to time t413 when AD conversion of the S signal is performed is defined as a second step, and the period from time t500 to time t404 when AD conversion of the N signal is performed is defined as a third step. Below, a signal processing method of the second step that differs from the second embodiment will be described with reference to Fig. 7.

[0071] The signal processing method in the period from time t400 to time t407 is similar to the signal processing method in the period from time t400 to time t407 described with reference to FIG.

[0072] In the period from time t600 to time t602, the voltage of the ramp signal VRAMP_H is decreased from the initial value depending on time by the reference signal output circuit 30. Then, the pixel signal PIXOUT is compared with the ramp signal VRAMP_H. Furthermore, based on the comparison result, the pixel signal PIXOUT is converted into a digital signal.

[0073] At time t600, the voltage change of the ramp signal VRAMP_H starts, and the counter circuit 40 starts counting the clock pulse signals and supplies the count signal CNT to the S memory 245 of each column.

[0074] At time t601, the voltage of the ramp signal VRAMP_H falls below the pixel signal PIXOUT, and the signal value of the comparator output COMPOUT changes. The value of the count signal CNT (count value) at this time is held by the S memory 245. The value of the count signal CNT held by the S memory 245 at this time is the digital value obtained by AD converting the S signal.

[0075] At time t602, the time-dependent voltage change of the ramp signal VRAMP_H stops and is reset to the state at time t400. The counter circuit 40 stops counting the clock pulse signal and returns the count signal CNT to its initial value.

[0076] In the period from time t411 to time t413, the voltage of the ramp signal VRAMP_L is decreased from the initial value depending on time by the reference signal output circuit 30. Then, the pixel signal PIXOUT is compared with the ramp signal VRAMP_L. Furthermore, based on the comparison result, the pixel signal PIXOUT is converted into a digital signal.

[0077] At time t411, the voltage change of the ramp signal VRAMP_L starts, and the counter circuit 40 starts counting the clock pulse signals and supplies the count signal CNT to the S memory 242 of each column.

[0078] At time t412, the voltage of the ramp signal VRAMP_L falls below the pixel signal PIXOUT, and the signal value of the comparator output COMPOUT changes. The value of the count signal CNT (count value) at this time is held by the S memory 242. The value of the count signal CNT held by the S memory 242 at this time is a digital value obtained by AD converting the S signal.

[0079] At time t413, the time-dependent voltage change of the ramp signal VRAMP_L is stopped and reset to the state at time t400. The counter circuit 40 stops counting the clock pulse signal and returns the count signal CNT to its initial value.

[0080] Therefore, in the second step in the period from time t600 to time t413, AD conversion using ramp signals VRAMP with different slopes is continuously performed on one S signal. Continuously performing AD conversion means that after AD conversion using one of the multiple ramp signals is completed, AD conversion using the other of the multiple ramp signals is started. In Fig. 7, AD conversion using the ramp signal VRAMP_L is started after AD conversion using the ramp signal VRAMP_H is completed.

[0081] After time t414, the column signal processing circuits 20 are sequentially operated by the horizontal scanning signal output from the column selection circuit 50, and the signals held in the S memory 242, the S memory 245, the N memory 243, and the N memory 244 are sent to the DSP 60. Then, after arithmetic processing is performed, the signals are output to the outside of the photoelectric conversion device 1.

[0082] DSP 60 calculates a differential signal level (light component) by subtracting the digitized N signal from the digitized S signal. Here, the S signals held in S memory 242 and S memory 245 may be subjected to differential processing with either the N signal held in N memory 243 and N memory 244. A digital signal with fewer noise components can be obtained by calculating the difference between the S signal and the N signal using the AD conversion result of the N signal using a ramp signal with the same slope as the ramp signal selected during AD conversion of the S signal.

[0083] 7, the ramp signal VRAMP_H is used from time t600 to time t602, and the ramp signal VRAMP_L is used from time t411 to time t413, but either of the ramp signals with different slopes may be used first. In other words, the ramp signal VRAMP_L may be used from time t600 to time t602, and the ramp signal VRAMP_H may be used from time t411 to time t413.

[0084] In this embodiment, as in the first and second embodiments, the first AD conversion for converting into a digital signal with a first bit number and the second AD conversion for converting into a digital signal with a second bit number smaller than the first bit number can be performed in different frames as the second step. Furthermore, before the first AD conversion and the second AD conversion, AD conversion of the N signal (third step) performed in the period from time t500 to time t404 in Fig. 7 may be performed as the third AD conversion. In this embodiment, too, the ratio of the second slope to the first slope is made smaller than the ratio of the fourth slope to the third slope, thereby reducing the effect of quantization error in the second AD conversion and reducing noise.

[0085] As described above, this embodiment can use ramp signals with different slopes, and performs AD conversion to convert to digital signals with different numbers of bits. In this operation, the ratio of the slope of the ramp signal in AD conversion with a small number of bits is made larger than the ratio of the slope of the ramp signal in AD conversion with a large number of bits. By performing such a signal processing method, the effect of quantization error is reduced in AD conversion with a small number of bits, making it possible to reduce noise.

[0086] Furthermore, in this embodiment, in the AD conversion of the N signal, multiple AD conversions are performed on one N signal using ramp signals with different slopes. As a result, the AD conversion result of the N signal using a ramp signal with the same slope as the ramp signal used in the AD conversion of the S signal can be used when calculating the difference between the S signal and the N signal. By performing signal processing in this manner, it is possible to obtain a digital signal in which the characteristic variation for each column signal processing circuit 20 is reduced with high accuracy.

[0087] Furthermore, in this embodiment, since the pixel signal is not compared with the threshold voltage, a flag memory is not required, and the circuit area can be reduced.

[0088] Fourth embodiment A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Figures 8 and 9. Note that components similar to those in the first, second and third embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0089] This embodiment differs from the first, second and third embodiments in that AD conversion is performed in parallel using ramp signals VRAMP with different slopes for one pixel signal PIXOUT (S signal and N signal). Fig. 8 is an example of a block diagram of a photoelectric conversion device that implements the signal processing method according to this embodiment.

[0090] As shown in FIG. 8, each column signal processing circuit 20 has a plurality of systems per column corresponding to the ramp signals VRAMP_L and VRAMP_H. The column signal processing circuit 20 includes an AD conversion circuit 22 and a memory circuit 24. The AD conversion circuit 22 includes a comparator 221 and a comparator 261. A pixel signal output from a pixel 11 is input to one input terminal of the comparator 221 and the comparator 261 included in the corresponding column signal processing circuit 20 via a corresponding signal line 12. In addition, the reference signal output circuit 30 inputs the ramp signal VRAMP_H to the other input terminal of the comparator 221 via a wiring 311. In addition, the reference signal output circuit 30 inputs the ramp signal VRAMP_L to the other input terminal of the comparator 261 via a wiring 312. Thus, the photoelectric conversion device 1 has at least one signal line 12 provided corresponding to one column of pixels 11, and the AD conversion circuit 22 includes a plurality of comparators connected to one signal line 12.

[0091] The memory circuit 24 includes an S memory 242, an S memory 252, an N memory 243, and an N memory 253. The comparator 221 outputs a comparison result signal indicating a result of comparing the pixel signal input via the signal line 12 with the ramp signal VRAMP_H to the S memory 242 and the N memory 243. The S memory 242 and the N memory 243 hold the count signal CNT output from the counter circuit 40 based on a change in the signal level of the comparison result signal output from the comparator 221. The comparator 261 outputs a comparison result signal indicating a result of comparing the pixel signal input via the signal line 12 with the ramp signal VRAMP_L to the S memory 252 and the N memory 253. The S memory 252 and the N memory 253 hold the count signal CNT output from the counter circuit 40 based on a change in the signal level of the comparison result signal output from the comparator 261. As a result, the count signal CNT having a signal value corresponding to the value of the pixel signal is held in the memory circuit 24 as a digital signal corresponding to the pixel signal, and the pixel signal output from the pixel 11 is AD converted.

[0092] FIG. 9 is an example of a drive timing chart of the photoelectric conversion device 1 that performs the signal processing method according to this embodiment.

[0093] In FIG. 9, the horizontal axis indicates time and the vertical axis indicates voltage, and the timing of each drive pulse, pixel signal, and reference signal are shown. Each control signal shown in FIG. 9 corresponds to each control signal shown in FIG. 2. FIG. 9 also shows the driving of signal processing in a plurality of systems (comparator 221 and comparator 261) of each column signal processing circuit 20. Note that the system in which comparator 221, S memory 242, and N memory 243 are electrically connected is the first system, and the system in which comparator 261, S memory 252, and N memory 253 are electrically connected is the second system. Note that the period from time t411 to time t413 in which AD conversion of the S signal is performed is the second step, and the period from time t402 to time t404 in which AD conversion of the N signal is performed is the third step. Below, a signal processing method in the first system in the second step and the third step, which is different from the third embodiment, will be described with reference to FIG. 9.

[0094] The signal processing method in the period from time t400 to time t401 is similar to the signal processing method in the period from time t400 to time t401 described with reference to FIG.

[0095] In the period from time t402 to time t404, the voltage of the ramp signal VRAMP_H is time-dependently decreased from the initial value by the reference signal output circuit 30. In the period from time t402 to time t404, the pixel signal PIXOUT and the ramp signal VRAMP_H are compared. Then, based on the result of the comparison, the pixel signal PIXOUT, which is an analog signal, is converted into a digital signal.

[0096] At time t402, the voltage change of the ramp signal VRAMP_H starts, and the counter circuit 40 starts counting the clock pulse signal and supplies the count signal CNT to the N memory 243 of each column. At time t403, the voltage of the ramp signal VRAMP_H falls below the pixel signal PIXOUT, and the signal value of the comparator output COMPOUT output by the comparator 221 changes. The value of the count signal CNT at this time (count value) is held by the N memory 243. The value of the count signal CNT held by the N memory 243 at this time is the digital value obtained by AD converting the N signal. At time t404, the time-dependent voltage change of the ramp signal VRAMP_H stops, and is reset to the state of time t400. The counter circuit 40 stops counting the clock pulse signal, and returns the count signal CNT to its initial value.

[0097] In the second system, the comparator 261 and the N memory 253 are used to perform the above driving by the ramp signal VRAMP_L.

[0098] Therefore, in the third step in the period from time t402 to time t404, AD conversion using ramp signals VRAMP with different slopes is performed in parallel for one N signal. Performing AD conversion in parallel means that at least a part of an AD conversion period using one of the multiple ramp signals overlaps with at least a part of an AD conversion period using the other of the multiple ramp signals. In Fig. 9, at least a part of an AD conversion period using the ramp signal VRAMP_H overlaps with at least a part of an AD conversion period using the ramp signal VRAMP_L.

[0099] At time t405, the control signal TX is set to a high level, and at time t406, the control signal TX is set to a low level. As a result, charges generated by light incident on the photoelectric conversion unit 400 are transferred to the FD unit 420. The amplification transistor 430 outputs a voltage signal based on the charges transferred to the FD unit 420. This voltage signal is output to the signal line 12 via the selection transistor 440, and the pixel signal is input to one input terminal of the comparator 221. This signal is an S signal, which is one of the pixel signals PIXOUT. The S signal is an analog signal having a voltage according to the amount of light received by the photoelectric conversion unit 400 in one frame period.

[0100] In the period from time t411 to time t413, the voltage of the ramp signal VRAMP_H is decreased from the initial value depending on time by the reference signal output circuit 30. Then, the pixel signal PIXOUT is compared with the ramp signal VRAMP_H. Furthermore, based on the comparison result, the pixel signal PIXOUT is converted into a digital signal.

[0101] At time t411, the voltage change of the ramp signal VRAMP_H starts, and the counter circuit 40 starts counting the clock pulse signals and supplies the count signal CNT to the S memory 242 of each column.

[0102] At time t412, the voltage of the ramp signal VRAMP_H falls below the pixel signal PIXOUT, and the signal value of the comparator output COMPOUT changes. The value of the count signal CNT (count value) at this time is held by the S memory 242. The value of the count signal CNT held by the S memory 242 at this time is a digital value obtained by AD converting the S signal.

[0103] At time t413, the time-dependent voltage change of the ramp signal VRAMP_H stops and is reset to the state at time t400. The counter circuit 40 stops counting the clock pulse signal and returns the count signal CNT to its initial value.

[0104] In the second system, the comparator 261 and the S memory 252 are used to perform the above driving by the ramp signal VRAMP_L.

[0105] Therefore, in the second step in the period from time t411 to time t413, AD conversion using ramp signals VRAMP with different slopes is performed in parallel for one S signal. Performing AD conversion in parallel means that at least a part of an AD conversion period using one of the multiple ramp signals overlaps with at least a part of an AD conversion period using the other of the multiple ramp signals. In FIG. 9, at least a part of an AD conversion period using the ramp signal VRAMP_H overlaps with at least a part of an AD conversion period using the ramp signal VRAMP_L.

[0106] After time t414, the column signal processing circuits 20 are sequentially operated by the horizontal scanning signal output from the column selection circuit 50, and the signals held in the S memory 242, the S memory 252, the N memory 243, and the N memory 253 are sent to the DSP 60. Then, after arithmetic processing is performed, the signals are output to the outside of the photoelectric conversion device 1.

[0107] DSP 60 calculates a differential signal level (light component) by subtracting the digitized N signal from the digitized S signal. Here, the S signals held in S memory 242 and S memory 252 may be subjected to differential processing with either the N signal held in N memory 243 and N memory 253. A digital signal with fewer noise components can be obtained by calculating the difference between the S signal and the N signal using the AD conversion result of the N signal using a ramp signal with the same slope as the ramp signal selected during AD conversion of the S signal.

[0108] In this embodiment, similarly to the first, second and third embodiments, as the second step, the first AD conversion for converting into a digital signal with a first bit number and the second AD conversion for converting into a digital signal with a second bit number smaller than the first bit number can be performed in different frames. Furthermore, before the first AD conversion and the second AD conversion, AD conversion of the N signal (third step) performed in the period from time t402 to time t404 in Fig. 9 may be performed as the third AD conversion. In this embodiment, too, by making the ratio of the second slope to the first slope smaller than the ratio of the fourth slope to the third slope, the effect of quantization error in the second AD conversion is reduced, and noise can be reduced.

[0109] As described above, this embodiment can use ramp signals with different slopes, and performs AD conversion to convert to digital signals with different numbers of bits. In this operation, the ratio of the slope of the ramp signal in AD conversion with a small number of bits is made larger than the ratio of the slope of the ramp signal in AD conversion with a large number of bits. By performing such a signal processing method, the effect of quantization error is reduced in AD conversion with a small number of bits, making it possible to reduce noise.

[0110] Furthermore, in this embodiment, in the AD conversion of the N signal, multiple AD conversions are performed on one N signal using ramp signals with different slopes. As a result, the AD conversion result of the N signal using a ramp signal with the same slope as the ramp signal used in the AD conversion of the S signal can be used when calculating the difference between the S signal and the N signal. By performing signal processing in this manner, it is possible to obtain a digital signal in which the characteristic variation for each column signal processing circuit 20 is reduced with high accuracy.

[0111] Furthermore, in this embodiment, since the pixel signal is not compared with the threshold voltage, a flag memory is not required, and the circuit area can be reduced.

[0112] Furthermore, in this embodiment, AD conversion is performed in parallel using ramp signals with different slopes, making it possible to perform AD conversion at higher speeds than when AD conversion is performed continuously.

[0113] Fifth embodiment A signal processing method according to the fifth embodiment of the present invention will be described with reference to Figures 10 to 13. Note that components similar to those in the first, second, third and fourth embodiments are given the same reference numerals, and descriptions of these components may be omitted or simplified.

[0114] This embodiment is a signal processing method related to correction processing of AD conversion, and can be applied to any of the first, second, third, and fourth embodiments. This embodiment is a method for acquiring a correction value for correcting the linearity of a ramp signal VRAMP (reference signal). An example of calculating the slope ratio (α1 and α2), which is the correction value of the ramp signal VRAMP, and the offset amount (β1 and β2) to be added will be described.

[0115] FIG. 10 is an example of a plan view of a pixel array section 10 included in a photoelectric conversion device 1 for implementing a signal processing method according to this embodiment.

[0116] As shown in FIG. 10, the optical black region is disposed on the outer periphery of the effective pixel region. Also, the dummy pixel region (correction value calculation region) is disposed on the outer periphery of the optical black region. Note that this arrangement is an example, and the arrangement can be changed as appropriate. For example, a dummy pixel region may be provided between the optical black region and the effective pixel region. Also, a plurality of dummy pixel regions may be distributed and disposed at the outermost periphery of the pixel region and between the optical black region and the effective pixel region. The optical black region is an area in which a plurality of optical black pixels, each having a light-shielded photoelectric conversion unit, are disposed. Typically, the structure of the optical black pixel is the same as that of the effective pixel, except that the photoelectric conversion unit is light-shielded. On the other hand, the dummy pixel region is an area in which a plurality of dummy pixels, each of which does not have a photoelectric conversion unit and each of which has the amplification transistor 430 and the selection transistor 440 shown in FIG. 2, are disposed. Note that this dummy pixel may further include a reset transistor 455 and a transfer transistor 410. The photoelectric conversion signal output from the effective pixel region is used as, for example, an imaging signal in the subsequent processing. On the other hand, the signal output from the dummy pixel region is used to correct the linearity of the ramp signal VRAMP (reference signal). The signal output from the dummy pixel region includes not only the signal output from the dummy pixel but also the signal output from the signal line 12 corresponding to the dummy pixel region. The signal output from the signal line 12 corresponding to the dummy pixel region is, for example, a signal output from a circuit (such as a voltage source) that applies a predetermined voltage to the signal line 12. In this embodiment, a correction value including the slope ratio α and the offset amount β is calculated using the signal output from the dummy pixel region. In addition, the dummy pixel is connected to one input terminal of the comparator 221 via the signal line 12. During the period in which the signal from the dummy pixel is read out, for example, a voltage source (not shown) outputs a fixed voltage, thereby controlling the voltage input to the comparator 221 via the signal line 12 to be the fixed voltage. In this embodiment, V1 and V2 larger than V1 are used as the fixed voltages.In this embodiment, the first AD conversion for converting to a digital signal of a first bit number uses a combination of a ramp signal VRAMP_L1 (first ramp signal) and a ramp signal VRAMP_H1 (second ramp signal). In this embodiment, the second AD conversion for converting to a digital signal of a second bit number uses a combination of a ramp signal VRAMP_L2 (third ramp signal) and a ramp signal VRAMP_H2 (fourth ramp signal). The operations of acquiring the correction values ​​used in the first AD conversion and the second AD conversion may be performed in the same frame, or may be performed in different frames. Here, a case in which the operations of acquiring the correction values ​​used in the first AD conversion and the second AD conversion are performed in the same frame will be described. By performing the operations of acquiring the correction values ​​in the same frame, rather than in different frames, the number of times the correction values ​​are acquired can be reduced when switching modes between frames, and the signal processing speed can be improved.

[0117] 11 and 12 are examples of drive timing charts of the photoelectric conversion device 1 that implements the signal processing method according to this embodiment.

[0118] In Fig. 11 and Fig. 12, the horizontal axis indicates time and the vertical axis indicates voltage, and the timing of each drive pulse, the dummy pixel region output signal, and the reference signal are shown. Fig. 11 and Fig. 12 show a signal processing method when AD converting a fixed voltage as a signal output from the dummy pixel region (a signal output from the signal line 12). Note that V1 is used as the fixed voltage in Fig. 11, and V2 is used as the fixed voltage in Fig. 12. Note that in Fig. 11(a), (b) and Fig. 12(a), (b) showing the drive of the first AD conversion, a combination of the ramp signal VRAMP_L1 and the ramp signal VRAMP_H1 is used as the ramp signal VRAMP. Note that in Fig. 11(c), (d) and Fig. 12(c), (d) showing the drive of the second AD conversion, a combination of the ramp signal VRAMP_L2 and the ramp signal VRAMP_H2 is used. Note that the period in which the slope of the ramp signal VRAMP used in the AD conversion is set is the first step. Note that the period in which the AD conversion is performed is the second step.

[0119] 11(a), in the first step, the threshold voltage VREF is set to, for example, a minimum value so that the fixed voltage V1 always exceeds the threshold voltage VREF. Then, in the second step, the fixed voltage V1 is always AD-converted using the ramp signal VRAMP_L1. In this case, the digital value resulting from the AD conversion of the fixed voltage V1 is designated as D1.

[0120] 11(b), in the first step, the threshold voltage VREF is set to, for example, a maximum value so that the fixed voltage V1 is always lower than the threshold voltage VREF. Then, in the second step, the ramp signal VRAMP_H1 is always used to perform AD conversion of the fixed voltage V1. In this case, the digital value resulting from the AD conversion of the fixed voltage V1 is designated as D3.

[0121] 11(c), in the first step, the threshold voltage VREF is set to, for example, a minimum value so that the fixed voltage V1 always exceeds the threshold voltage VREF. Then, in the second step, the fixed voltage V1 is always AD-converted using the ramp signal VRAMP_L2. In this case, the digital value resulting from the AD conversion of the fixed voltage V1 is designated as D2.

[0122] 11(d), in the first step, the threshold voltage VREF is set to, for example, a maximum value so that the fixed voltage V1 is always lower than the threshold voltage VREF. Then, in the second step, the ramp signal VRAMP_H2 is always used to perform AD conversion of the fixed voltage V1. In this case, the digital value resulting from AD conversion of the fixed voltage V1 is designated as D4.

[0123] 12(a), in the first step, the threshold voltage VREF is set to, for example, a minimum value so that the fixed voltage V2 always exceeds the threshold voltage VREF. Then, in the second step, the ramp signal VRAMP_L1 is always used to perform AD conversion of the fixed voltage V2. In this case, the digital value resulting from AD conversion of the fixed voltage V2 is designated as D5.

[0124] 12(b), in the first step, the threshold voltage VREF is set to, for example, a maximum value so that the fixed voltage V2 is always lower than the threshold voltage VREF. Then, in the second step, the ramp signal VRAMP_H1 is always used to perform AD conversion of the fixed voltage V2. In this case, the digital value resulting from the AD conversion of the fixed voltage V2 is designated as D7.

[0125] 12(c), in the first step, the threshold voltage VREF is set to, for example, a minimum value so that the fixed voltage V2 always exceeds the threshold voltage VREF. Then, in the second step, the ramp signal VRAMP_L2 is always used to perform AD conversion of the fixed voltage V2. In this case, the digital value resulting from AD conversion of the fixed voltage V2 is designated as D6.

[0126] 12(d), in the first step, the threshold voltage VREF is set to, for example, a maximum value so that the fixed voltage V2 is always lower than the threshold voltage VREF. Then, in the second step, the ramp signal VRAMP_H2 is always used to perform AD conversion of the fixed voltage V2. In this case, the digital value resulting from AD conversion of the fixed voltage V2 is designated as D8.

[0127] Fig. 13 is a diagram illustrating the correction process of the photoelectric conversion device 1 according to this embodiment. In Fig. 13, the horizontal axis indicates the input value input to one input terminal of the comparator via the signal line 12, and the vertical axis indicates the digital value after AD conversion.

[0128] 13(a) represents the digital values ​​input to the DSP 60. A signal whose signal amplitude is smaller (voltage is larger) than the threshold voltage VREF is AD converted by the ramp signal VRAMP_L, and a signal whose signal amplitude is larger (voltage is smaller) than the threshold voltage VREF is AD converted by the ramp signal VRAMP_H. Therefore, a step occurs in the digital value after AD conversion for the input value (voltage value of the pixel signal) before and after the threshold voltage VREF used for AD conversion of the S signal of the effective pixel.

[0129] Therefore, in this embodiment, for example, the DSP 60 multiplies an S signal having a signal amplitude larger than the threshold voltage VREF used for AD conversion of the S signal of the effective pixel by the ratio α of the slopes of the ramp signal VRAMP_L and the ramp signal VRAMP_H. Furthermore, by adding a predetermined offset amount β so that a step does not occur at the threshold voltage VREF, a step or the like is corrected so that the input value (the voltage value of the pixel signal) and the digital value after AD conversion are in a straight line. That is, in this embodiment, a step correction at the time of synthesis is performed with high accuracy by performing gain correction and offset correction on the signal AD converted by the ramp signal VRAMP_L or the ramp signal VRAMP_H. If an S signal is output without correction as in this embodiment, a step may occur in the S signal level at a certain luminance, resulting in an unnatural image, but according to this embodiment, such a problem can be suppressed. This correction value changes depending on the temperature of the photoelectric conversion element, the drive timing or drive setting (power supply setting, etc.) of the photoelectric conversion element, so in this embodiment, the correction value is acquired, for example, periodically.

[0130] Figure 13(b) shows the AD conversion result obtained in the AD conversion shown in Figures 11 and 12. The slope ratios α1 and α2 and the offset amounts β1 and β2 can be calculated from the coordinates of the eight points (D1, D2, D3, D4, D5, D6, D7, and D8) shown in Figure 13(b). For example, the slope ratio α can be calculated using the following formula. α1=(D5-D1) / (D7-D3) α2=(D6-D2) / (D8-D4)

[0131] After determining the slope ratio α, an offset amount β1 can be determined so that the two straight lines corresponding to the reference signals L1 and H1 respectively have the same possible values ​​at the threshold voltage VREF. Also, an offset amount β2 can be determined so that the two straight lines corresponding to the reference signals L2 and H2 respectively have the same possible values ​​at the threshold voltage VREF. Note that, as an example, the threshold voltage VREF used for AD conversion of the S signal of the effective pixel is described as being greater than the fixed voltages V1 and V2, but the threshold voltage VREF used for AD conversion of the S signal of the effective pixel can be set freely.

[0132] The above calculations may be performed inside the photoelectric conversion device 1, or may be performed by an image processing LSI external to the photoelectric conversion device 1. The above calculations may also be performed, for example, before the photoelectric conversion device 1 is incorporated into a photoelectric conversion system, and correction data may be stored in a memory provided in the photoelectric conversion system. By performing the calculations prior to the photoelectric conversion operation, correction data including the effects of environmental conditions such as temperature can be obtained and corrections can be made, so that a good photoelectric conversion signal suited to the environmental conditions can be obtained.

[0133] Sixth embodiment The sixth embodiment is applicable to any of the first to fifth embodiments. FIG. 14(a) is a schematic diagram for explaining a device 9191 including a semiconductor device 930 of this embodiment. The photoelectric conversion device (imaging device) of each of the above-mentioned embodiments can be used for the semiconductor device 930. The device 9191 including the semiconductor device 930 will be explained in detail. The semiconductor device 930 can include a semiconductor device 910. The semiconductor device 910 has a pixel area 901 in which pixel circuits 900 including a photoelectric conversion unit are arranged in a matrix. The semiconductor device 910 can have a peripheral area 902 around the pixel area 901. Circuits other than the pixel circuits 900 can be arranged in the peripheral area 902. The semiconductor device 930 can include a package 920 that accommodates the semiconductor device 910 in addition to the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a cover such as glass that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base and terminals provided on the semiconductor device 910 .

[0134] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0135] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0136] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0137] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0138] The device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft (drone, aircraft, etc.). The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0139] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, reducing size, and reducing weight.

[0140] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment or measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0141] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS.

[0142] FIG. 14(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 has a photoelectric conversion device 1. The photoelectric conversion device 1 is a photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 1, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also has a distance acquisition unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0143] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., and vibrating the seat belt or steering wheel.

[0144] In this embodiment, the surroundings of the vehicle, for example the front or rear, are imaged by the photoelectric conversion system 8. Fig. 14(c) shows the photoelectric conversion system 8 when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 1. With this configuration, the accuracy of distance measurement can be further improved.

[0145] Although the above describes an example of control to prevent collision with other vehicles, the system can also be applied to automatic driving control to follow other vehicles and automatic driving control to prevent deviation from lanes. Furthermore, the photoelectric conversion system 8 can be applied not only to vehicles such as automobiles, but also to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the system can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0146] The above-described embodiments can be modified as appropriate without departing from the technical concept. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the concepts described in this specification. In other words, if this specification contains a statement that "A is greater than B," for example, this specification can be said to disclose that "A is not greater than B" even if the statement that "A is not greater than B" is omitted. This is because when it is stated that "A is greater than B," it is assumed that the case in which "A is not greater than B" is taken into consideration.

[0147] The disclosure of this embodiment includes the following configuration.

[0148] (Method 1) A signal processing method performing analog-digital (AD) conversion to convert an analog signal into a digital signal with a different number of bits using a ramp signal having a slope, the signal processing method comprising: a first AD conversion to convert an analog signal into a digital signal with a first number of bits using at least one of a first ramp signal with a first slope and a second ramp signal with a second slope larger than the first slope; and a second AD conversion to convert an analog signal into a digital signal with a second number of bits smaller than the first number of bits using at least one of a third ramp signal with a third slope and a fourth ramp signal with a fourth slope larger than the third slope, wherein a ratio of the second slope to the first slope is smaller than a ratio of the fourth slope to the third slope.

[0149] (Method 2) The signal processing method according to method 1, characterized in that the first AD conversion is performed using the first ramp signal or the second ramp signal, and the second AD conversion is performed using the third ramp signal or the fourth ramp signal.

[0150] (Method 3) the signal processing method according to method 1 or 2, characterized in that, based on a result of comparing the analog signal with a first threshold voltage, one of the first ramp signal and the second ramp signal is selected as a ramp signal to be used in the first AD conversion, and based on a result of comparing the analog signal with a second threshold voltage having a value different from the first threshold voltage, one of the third ramp signal and the fourth ramp signal is selected as a ramp signal to be used in the second AD conversion.

[0151] (Method 4) 4. A signal processing method according to any one of methods 1 to 3, characterized in that the signal amplitude of the second threshold voltage is smaller than the signal amplitude of the first threshold voltage.

[0152] (Method 5) 5. The signal processing method according to any one of Methods 1 to 4, characterized in that a ratio of the number of gray levels of the first AD conversion to the number of gray levels of the second AD conversion is approximately equal to a ratio of the fourth slope to the second slope.

[0153] (Method 6) The signal processing method according to any one of Methods 1 to 5, characterized in that a third AD conversion is performed before the first AD conversion and the second AD conversion, the first AD conversion and the second AD conversion are performed using, as the analog signal, a photoelectric conversion signal based on charges output by a pixel including a photoelectric conversion unit that generates charges by photoelectric conversion, and the third AD conversion is performed using, as the analog signal, a reset level signal output by the pixel.

[0154] (Method 7) 7. The signal processing method according to any one of Methods 1 to 6, characterized in that the third AD conversion is performed using a ramp signal selected from a plurality of ramp signals having different slopes.

[0155] (Method 8) The signal processing method according to any one of Methods 1 to 7, characterized in that either an operation of using the first ramp signal and the second ramp signal as ramp signals to be used in the third AD conversion, or an operation of using the third ramp signal and the fourth ramp signal as ramp signals to be used in the third AD conversion, is performed.

[0156] (Method 9) 9. The signal processing method according to any one of Methods 1 to 8, characterized in that the third AD conversion is performed so as to start AD conversion using one of the plurality of ramp signals after AD conversion using one of the plurality of ramp signals is completed.

[0157] (Method 10) 10. The signal processing method according to any one of Methods 1 to 9, characterized in that the third AD conversion is performed so that at least a part of an AD conversion period using one of the plurality of ramp signals overlaps with at least a part of an AD conversion period using the other of the plurality of ramp signals.

[0158] (Method 11) 11. The signal processing method according to any one of Methods 1 to 10, characterized in that the first AD conversion is performed such that an AD conversion using the second ramp signal starts after an AD conversion using the first ramp signal is completed, and the second AD conversion is performed such that an AD conversion using the fourth ramp signal starts after an AD conversion using the third ramp signal is completed.

[0159] (Method 12) 12. The signal processing method according to any one of Methods 1 to 11, characterized in that the first AD conversion is performed such that at least a portion of an AD conversion period using the first ramp signal overlaps with at least a portion of an AD conversion period using the second ramp signal, and the second AD conversion is performed such that at least a portion of an AD conversion period using the third ramp signal overlaps with at least a portion of an AD conversion period using the fourth ramp signal.

[0160] (Method 13) 13. The signal processing method according to any one of Methods 1 to 12, comprising a first mode in which the second AD conversion is not performed during a period in which a plurality of the first AD conversions are performed, and a second mode in which the first AD conversion is not performed during a period in which a plurality of the second AD conversions are performed.

[0161] (Method 14) 14. A signal processing method according to any one of methods 1 to 13, characterized in that the first mode acquires the digital signal used for a still image, and the second mode acquires the digital signal used for a moving image.

[0162] (Method 15) 15. The signal processing method according to any one of Methods 1 to 14, wherein an operation of acquiring the correction values ​​used in the first AD conversion and the second AD conversion is performed in the same frame.

[0163] (Method 16) 16. A signal processing method according to any one of methods 1 to 15, characterized in that a ratio of the number of gray levels of the first AD conversion to the number of gray levels of the second AD conversion is smaller than a ratio of the fourth slope to the third slope.

[0164] (Method 17) 17. The signal processing method according to any one of Methods 1 to 16, wherein the slope is a voltage change amount of the ramp signal per unit time.

[0165] (Configuration 1) 1. A signal processing circuit including: an AD conversion circuit that performs analog-to-digital (AD) conversion to convert an analog signal into a digital signal with a different number of bits using a ramp signal having a slope; and a control unit that controls the AD conversion circuit, wherein the control unit controls the AD conversion circuit to perform a first AD conversion to convert the analog signal into a digital signal with a first number of bits and a second AD conversion to convert the analog signal into a digital signal with a second number of bits smaller than the first number of bits; the control unit controls the AD conversion circuit to use, in the first AD conversion, at least one of a first ramp signal with a first slope and a second ramp signal with a second slope larger than the first slope; and the control unit controls the AD conversion circuit to use, in the second AD conversion, at least one of a third ramp signal with a third slope and a fourth ramp signal with a fourth slope larger than the third slope; and a ratio of the second slope to the first slope is smaller than a ratio of the fourth slope to the third slope.

[0166] (Configuration 2) The signal processing circuit according to configuration 1, further comprising: a signal line provided for one column of pixels among a plurality of pixels arranged in a matrix; and the AD conversion circuit including a plurality of comparators connected to the one signal line.

[0167] (Configuration 3) A photoelectric conversion device having the signal processing circuit according to configuration 1 and a pixel including a photoelectric conversion unit that generates electric charges by photoelectric conversion, wherein the pixel outputs a photoelectric conversion signal based on the electric charges, and the AD conversion circuit converts the photoelectric conversion signal as the analog signal into the digital signal by either the first AD conversion or the second AD conversion.

[0168] (Configuration 4) An apparatus including a photoelectric conversion device having the signal processing circuit described in configuration 1 and a pixel including a photoelectric conversion unit that generates an electric charge by photoelectric conversion receiving light and outputs a photoelectric conversion signal based on the electric charge light as the analog signal to the signal processing circuit, characterized in that the apparatus further includes at least one of an optical device that guides light to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes a signal output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on the information obtained by the photoelectric conversion device.

Claims

1. A signal processing method that performs analog-to-digital (AD) conversion, which converts an analog signal into a digital signal with a different number of bits using a ramp signal having a slope, A first AD conversion that performs at least one of the following operations: converting to a digital signal of a first number of bits using a first ramp signal with a first slope, and converting to a digital signal of a first number of bits using a second ramp signal with a second slope greater than the first slope, and A second AD conversion is performed, which involves at least one of the following: converting to a digital signal of two bits smaller than the first bit number using a third ramp signal with a third slope, and converting to a digital signal of two bits using a fourth ramp signal with a fourth slope greater than the third slope. The ratio of the second slope to the first slope is smaller than the ratio of the fourth slope to the third slope. A signal processing method characterized by the following:

2. The signal processing method according to claim 1, characterized in that the first AD conversion is performed using the first lamp signal or the second lamp signal, and the second AD conversion is performed using the third lamp signal or the fourth lamp signal.

3. The signal processing method according to claim 2, characterized in that, based on the result of comparing the analog signal with a first threshold voltage, one of the first ramp signal and the second ramp signal is selected as the ramp signal to be used for the first AD conversion, and based on the result of comparing the analog signal with a second threshold voltage having a different value from the first threshold voltage, one of the third ramp signal and the fourth ramp signal is selected as the ramp signal to be used for the second AD conversion.

4. The signal processing method according to claim 3, characterized in that the signal amplitude of the second threshold voltage is smaller than the signal amplitude of the first threshold voltage.

5. The signal processing method according to claim 1, characterized in that the ratio of the number of gradations of the first AD conversion to the number of gradations of the second AD conversion is approximately equal to the ratio of the fourth slope to the second slope.

6. The signal processing method according to claim 1, characterized in that a third AD conversion is performed before the first AD conversion and the second AD conversion, the first AD conversion and the second AD conversion are performed using the photoelectric conversion signal based on the charge output by a pixel including a photoelectric conversion unit that generates an electric charge by photoelectric conversion as the analog signal, and the third AD conversion is performed using the reset level signal output by the pixel as the analog signal.

7. The signal processing method according to claim 6, characterized in that the third AD conversion is performed using a ramp signal selected from among a plurality of ramp signals having different inclinations.

8. The signal processing method according to claim 7, characterized in that it performs either the operation of using the first lamp signal and the second lamp signal as lamp signals used for the third AD conversion, or the operation of using the third lamp signal and the fourth lamp signal as lamp signals used for the third AD conversion.

9. The signal processing method according to claim 7, characterized in that the third AD conversion is performed such that an AD conversion using one of the plurality of lamp signals is started after an AD conversion using one of the plurality of lamp signals is completed.

10. The signal processing method according to claim 7, characterized in that the third AD conversion is performed such that at least a portion of the AD conversion period using one of the plurality of lamp signals overlaps with at least a portion of the AD conversion period using the other of the plurality of lamp signals.

11. The signal processing method according to claim 1, characterized in that the first AD conversion is performed such that the AD conversion using the second lamp signal starts after the AD conversion using the first lamp signal is completed, and the second AD conversion is performed such that the AD conversion using the fourth lamp signal starts after the AD conversion using the third lamp signal is completed.

12. The signal processing method according to claim 1, characterized in that the first AD conversion is performed such that at least a portion of the AD conversion period using the first lamp signal overlaps with at least a portion of the AD conversion period using the second lamp signal, and the second AD conversion is performed such that at least a portion of the AD conversion period using the third lamp signal overlaps with at least a portion of the AD conversion period using the fourth lamp signal.

13. The signal processing method according to claim 1, characterized by having a first mode in which the second AD conversion is not performed during a period in which a plurality of the first AD conversions are performed, and a second mode in which the first AD conversion is not performed during a period in which a plurality of the second AD conversions are performed.

14. The signal processing method according to claim 13, characterized in that the first mode acquires the digital signal used for still images, and the second mode acquires the digital signal used for moving images.

15. The signal processing method according to claim 1, characterized in that the acquisition operations of the respective correction values ​​used in the first AD conversion and the second AD conversion are performed in the same frame.

16. The signal processing method according to claim 1, characterized in that the ratio of the number of gradations of the first AD conversion to the number of gradations of the second AD conversion is smaller than the ratio of the fourth slope to the third slope.

17. The signal processing method according to claim 1, characterized in that the slope is the amount of voltage change per unit time of the lamp signal.

18. A signal processing circuit comprising: an AD conversion circuit that performs analog-to-digital (AD) conversion using a ramp signal having a slope to convert an analog signal into a digital signal with a different number of bits; and a control unit that controls the AD conversion circuit, The control unit controls the AD conversion circuit to perform a first AD conversion that converts the analog signal into a digital signal of a first number of bits, and a second AD conversion that converts the analog signal into a digital signal of a second number of bits smaller than the first number of bits. The control unit controls the AD conversion circuit to perform at least one of the following: a first AD conversion that converts a first ramp signal with a first slope into a digital signal of the first number of bits, and a second AD conversion that converts a second ramp signal with a second slope greater than the first slope into a digital signal of the first number of bits. The control unit controls the AD conversion circuit to perform at least one of the following: a second AD conversion that converts a third ramp signal with a third slope into a two-bit digital signal, and a second AD conversion that converts a fourth ramp signal with a fourth slope greater than the third slope into a two-bit digital signal. The ratio of the second slope to the first slope is smaller than the ratio of the fourth slope to the third slope. A signal processing circuit characterized by the following features.

19. Among the multiple pixels arranged in a matrix, one signal line is provided corresponding to the pixels in one row. The signal processing circuit according to claim 18, characterized in that the AD conversion circuit includes a plurality of comparators connected to the single signal line.

20. The signal processing circuit according to claim 18, A photoelectric conversion device having a pixel including a photoelectric conversion unit that generates electric charge by photoelectric conversion, The pixel outputs a photoelectric conversion signal based on the charge, The AD conversion circuit is a photoelectric conversion device characterized by converting the photoelectric conversion signal as an analog signal into a digital signal by either the first AD conversion or the second AD conversion.

21. A device comprising a photoelectric conversion device having a signal processing circuit as described in claim 18, and a pixel that includes a photoelectric conversion unit that generates an electric charge by photoelectric conversion and outputs a photoelectric conversion signal based on the electric charge as an analog signal to the signal processing circuit, An optical device that guides light to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A display device that displays information obtained by the aforementioned photoelectric converter. A storage device for storing information obtained by the photoelectric converter, and The apparatus is characterized by further comprising at least one of the following: a mechanical device that operates based on information obtained from the photoelectric converter.

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