Semiconductor device, system, and method for manufacturing semiconductor device

Abstract

To realize a normally-off operation in an FET having a diamond layer including a hydrogen-terminated region.SOLUTION: In an embodiment, assuming that a channel formation region 105 is composed of a first region P1 and a second region P2, when a gate voltage of "0 V" is applied to a gate electrode 111, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a system, and a manufacturing technique for a semiconductor device, and relates to a technique that is effective when applied to a semiconductor device including, for example, a field effect transistor using diamond as a semiconductor material. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2018-6572 (Patent Document 1) describes a technology relating to a diamond semiconductor device including a field effect transistor whose operating characteristics are normally off.

[0003] Japanese Patent Application Laid-Open No. 2017-50485 (Patent Document 2) describes a technique related to manufacturing method conditions for obtaining a normally-off hydrogen-terminated diamond FET.

[0004] Japanese Patent Application Laid-Open No. 2022-104826 (Patent Document 3) describes a technology related to a field effect transistor that has high radiation resistance while also ensuring circuit characteristics.

[0005] JP 2020-161587 A (Patent Document 4) describes a technology related to a semiconductor device including a field effect transistor capable of normally-off operation with high carrier mobility, excellent switching characteristics, and low gate leakage current. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2018-6572 A [Patent Document 2] JP 2017-50485 A [Patent Document 3] JP 2022-104826 A [Patent Document 4] JP 2020-161587 A Summary of the Invention [Problem to be solved by the invention]

[0007] For example, field effect transistors (hereafter sometimes referred to as FETs) that use wide band gap semiconductor materials, which have a larger band gap than silicon, have superior characteristics compared to FETs that use silicon, and for this reason, FETs that use wide band gap semiconductor materials are expected to be the next generation of FETs.

[0008] In this regard, diamond is a wide bandgap semiconductor material with a bandgap of 5.5 eV, and has excellent properties such as high dielectric breakdown voltage, high thermal conductivity, and high mobility. For this reason, diamond is expected to be the next-generation wide bandgap semiconductor material following silicon carbide (SiC) and gallium nitride (GaN).

[0009] However, there are hurdles to overcome in order to improve the performance of diamond-based FETs, and efforts are needed to put them to practical use. For example, it is difficult to achieve normally-off operation in diamond-based FETs, and efforts are needed to achieve normally-off operation in FETs that can be used for practical purposes.

[0010] In addition, "normally off" means that the FET is in an off state when a gate voltage of 0V is applied to the gate electrode. In particular, an FET configured such that no channel is formed in the channel formation region immediately below the gate electrode when a gate voltage of 0V is applied to the gate electrode is called a "normally off type FET". On the other hand, an FET configured such that a channel is formed in the channel formation region immediately below the gate electrode even when a gate voltage of 0V is applied to the gate electrode is called a "normally on type FET". In addition, in this specification, the application of a gate voltage of 0V to the gate electrode may be referred to as "no gate voltage is applied to the gate electrode". In this case, "normally off" can also be expressed as an FET being in an off state when no gate voltage is applied to the gate electrode. [Means for solving the problem]

[0011] The semiconductor device in one embodiment is a semiconductor device including a field effect transistor, the field effect transistor having a diamond layer including a hydrogen termination region, a channel formation region formed in the diamond layer, an insulating film formed on an upper surface of the diamond layer, and a gate electrode formed on the insulating film.

[0012] The channel formation region includes a first region overlapping with the gate electrode in a plan view and a second region not overlapping with the gate electrode in a plan view, and when the field-effect transistor is in an off state, the hole concentration of the first region is lower than the hole concentration of the second region.

[0013] The semiconductor device in one embodiment is a semiconductor device including a field effect transistor, the field effect transistor having a diamond layer including a hydrogen termination region, a channel formation region formed in the diamond layer, an insulating film formed on an upper surface of the diamond layer, and a gate electrode formed on the insulating film.

[0014] Here, the insulating film includes a first insulating region that overlaps with the gate electrode in a plan view and a second insulating region that does not overlap with the gate electrode in a plan view. The second insulating region has a larger negative charge amount than the first insulating region. Or, the first insulating region has a larger positive charge amount than the second insulating region.

[0015] The semiconductor device in one embodiment is a semiconductor device including a field effect transistor, the field effect transistor having a diamond layer including a hydrogen termination region, a channel formation region formed in the diamond layer, an insulating film formed on an upper surface of the diamond layer, and a gate electrode formed on the insulating film.

[0016] Here, in the off state of the field effect transistor, the hole concentration in the channel formation region is 10 12 / cm 2The following is the result.

[0017] In one embodiment, a method for manufacturing a semiconductor device including a field effect transistor includes the steps of: (a) forming a diamond layer including a hydrogen-terminated region; and (b) reducing the hole concentration in the hydrogen-terminated region. Effect of the Invention

[0018] According to one embodiment, a normally-off operation can be achieved in a FET having a diamond layer including a hydrogen-terminated region. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a diagram illustrating a surface-conduction type FET according to an embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment. [Diagram 3] 3 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 2; [Figure 4] 4 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 3. [Diagram 5] 5 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 4. [Figure 6] 6 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 5. [Figure 7] 7 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 6. [Figure 8] 8 is a diagram showing a manufacturing process of the semiconductor device subsequent to FIG. 7. [Figure 9] 13 is a graph showing the drain current-gate voltage characteristics of a surface-conduction type FET manufactured without carrying out a hole concentration adjustment step. [Figure 10] 13 is a graph showing the drain current-gate voltage characteristics of a surface-conduction type FET manufactured by carrying out a hole concentration adjustment step. [Figure 11] FIG. 1 is a diagram illustrating a surface-conduction type FET having an “overlapping structure” in Modification 1.

BEST MODE FOR CARRYING OUT THE INVENTION

[0020] In all the drawings for explaining the embodiments, the same members are basically denoted by the same reference numerals, and repeated explanations thereof are omitted. Note that, in order to make the drawings easy to understand, hatching may be added even to a plan view.

[0021] <Usefulness of Diamond as a Semiconductor Material> For example, in fields such as future mobile communication, satellite communication, or ultra-small radar, an FET capable of high-power and high-frequency transmission is required. In this regard, semiconductor materials typified by silicon (Si) and gallium arsenide (GaAs) reach a limit in output density at frequencies of several GHz or higher. For this reason, use of wide-bandgap semiconductor materials typified by silicon carbide (SiC), gallium nitride (GaN), and diamond in FETs has been studied. In particular, diamond has the highest thermal conductivity among substances (four times that of SiC and 16 times that of GaN) and the highest breakdown electric field strength among semiconductor materials (three times that of SiC and 10 times that of GaN). Furthermore, the hole mobility and hole saturation velocity in diamond are equivalent to the electron mobility and electron saturation velocity in silicon.

[0022] Therefore, since diamond has excellent heat dissipation characteristics due to its high thermal conductivity, heat generation of the semiconductor device can be suppressed and high-temperature operation of the semiconductor device can also be expected. In addition, since the semiconductor device is less likely to be destroyed even when a high voltage is applied due to the high breakdown electric field strength of diamond, it is suitable for semiconductor devices for high-power applications. Furthermore, the high carrier mobility of diamond suggests that diamond has high potential as a semiconductor device for high frequencies.

[0023] From the above, it can be seen that diamond as a semiconductor material is regarded as promising in realizing next-generation semiconductor devices including FETs capable of high-power and high-frequency operation.

[0024] <Difficulty in Fabricating n-Type Diamond> As mentioned above, diamond is a wide band gap semiconductor material, and it is believed that n-type diamond can be produced by introducing n-type impurities called donors into diamond. Specifically, it is believed that n-type diamond can be realized by supplying electrons from the donor level of the donor to the conduction band of diamond.

[0025] Here, nitrogen can be mentioned as a donor, but in diamond, the donor level of nitrogen does not exist near the conduction band, but exists at a "deep level" away from the conduction band. Specifically, the donor level of nitrogen exists at an energy position 1.7 eV lower than the conduction band of diamond. This means that in diamond, the activation energy for exciting electrons from the donor level of nitrogen to the conduction band of diamond is large.

[0026] For this reason, even if nitrogen, which acts as a donor, is introduced into diamond, it is difficult to increase the number of electrons supplied to the conduction band, and as a result, it is difficult to make a diamond into which nitrogen has been introduced function as an n-type diamond.

[0027] On the other hand, it is believed that p-type diamond can be created by introducing p-type impurities called acceptors into diamond. Specifically, it is believed that p-type diamond can be realized by exciting electrons from the valence band of diamond to the acceptor level of the acceptor, thereby generating holes in the valence band of diamond.

[0028] Here, the acceptor can be boron, and the acceptor level of this boron exists near the valence band of diamond. Specifically, the acceptor boron forms an acceptor level at an energy position 0.37 eV higher than the valence band of diamond. In other words, in diamond, the acceptor level of boron does not constitute a "deep level" like the donor level of nitrogen. For this reason, the activation energy for exciting electrons from the valence band of diamond to the acceptor level of boron is not so large. As a result, it is easier to produce p-type diamond in diamond than to produce n-type diamond.

[0029] Therefore, FETs manufactured using diamond are not n-channel FETs, which generally require n-type diamond, but p-channel FETs, which use p-type diamond, which is easier to manufacture than n-type diamond. In other words, FETs manufactured using diamond are realized as FETs with holes as carriers, not FETs with electrons as carriers. In particular, FETs manufactured using diamond include p-channel FETs called "surface conduction FETs." This "surface conduction FET" will be explained below.

[0030] <Surface conduction FET> When diamond is hydrogen-terminated, there is a phenomenon in which holes (two-dimensional hole gas) are induced on the surface of the hydrogen-terminated diamond. A FET that utilizes this phenomenon is called a "surface-conduction FET." In other words, a "surface-conduction FET" is an FET that uses the two-dimensional hole gas induced on the hydrogen-terminated diamond surface as the FET channel, and controls the conduction / non-conduction of the channel by changing the gate voltage applied to the gate electrode to perform switching operations. This "surface-conduction FET" has the advantage of being able to withstand high voltages and operate at high temperatures. This is because hydrogen-terminating diamond forms "CH" bonds, which are stronger than the "CC" bonds of diamond.

[0031] The mechanism by which holes are induced on the surface of hydrogen-terminated diamond has not been fully elucidated, but two theories are considered to be the most likely.

[0032] First, one theory is the "transfer doping model." This theory posits that due to differences in chemical potential caused by adsorbates or changes in the pH of the surface, electrons in the valence band of diamond move to a level determined by the chemical potential of the surface, generating holes near the surface where these electrons are lost.

[0033] On the other hand, the other theory is the "negative ion model." This theory is as follows. In other words, in the "CH" bonds created by hydrogen-terminating diamond, hydrogen becomes positively charged and carbon becomes negatively charged due to the difference in electronegativity. As a result, negative ions in the air are adsorbed to the positively charged hydrogen, and these adsorbed negative ions attract holes to the surface of the diamond.

[0034] Although the mechanism has not been fully elucidated, a phenomenon occurs in which holes are induced on the hydrogen-terminated surface of diamond. This phenomenon has been exploited to create a superior FET called a "surface-conduction FET," which is capable of high-temperature operation with high voltage resistance.

[0035] However, in the "surface conduction FET", even if no gate voltage is applied to the gate electrode, two-dimensional hole gas is induced in the hydrogen-terminated region of the diamond layer. This means that in the "surface conduction FET", even if no gate voltage is applied to the gate electrode, a channel made of two-dimensional hole gas is formed in the hydrogen-terminated region. In other words, in the "surface conduction FET", even if a gate voltage of 0 V is applied to the gate electrode, a channel made of two-dimensional hole gas is formed in the hydrogen-terminated region. Therefore, unless some ingenuity is applied, the "surface conduction FET" inevitably tends to become a "normally-on FET". In other words, the mainstream of "surface conduction FET" is the "normally-on FET".

[0036] <The usefulness of "normally-off FET"> In this regard, when comparing a "normally-on type FET" with a "normally-off type FET," the "normally-off type FET" is more desirable from the standpoint of safety and power consumption. This is because the "normally-off type FET" (1) does not conduct electricity during a system failure, for example, when the gate voltage is not supplied to the gate electrode, and therefore it is possible to suppress runaway of the FET due to conduction. In other words, the "normally-off type FET" has the advantage of being excellent in fail-safe and having high safety. The "normally-off type FET" also has the advantage of (2) being able to reduce dark current during high-temperature operation and suppress malfunctions caused by noise. Furthermore, (3) it has the advantage of being able to reduce power consumption because it does not conduct electricity when no gate voltage is supplied to the gate electrode (i.e., when 0 V is applied to the gate electrode). As described above, due to the advantages (1) to (3), it can be seen that the "normally-off type FET" is superior to the "normally-on type FET" from the standpoint of system safety and power consumption reduction.

[0037] For example, the "normally-off FET" is the most important power device. Specifically, power devices are widely used in transportation equipment that uses large amounts of electricity, such as automobiles, railway vehicles, and airplanes. For this reason, safety is of the utmost importance, and the "normally-off FET," which outputs "0" when broken, is the minimum requirement for a power device.

[0038] Furthermore, from the perspective of reducing standby power consumption, "normally-off FETs," which have almost no leakage current when off, are also effective.

[0039] Therefore, in order to use a "surface-conduction FET" in a system, it is important to realize a "normally-off FET" in the "surface-conduction FET." In other words, a "normally-off FET" is essential to build a system that is both safe and high-performance, and some ingenuity is required to realize a "normally-off FET" in a "surface-conduction FET," where "normally-on FETs" are the mainstream.

[0040] Therefore, the present inventors have devised a method for transforming a "surface conduction type FET" into a "normally-off type FET" by utilizing the following findings.

[0041] <Knowledge used by the inventor> The findings utilized by the present inventors will be described below.

[0042] For example, it is known that when a constant voltage is applied to the surface of a hydrogen-terminated diamond layer, the current value decreases, while when the layer is exposed to the air, the current value almost returns to the original value. This can be understood as follows: when the layer is evacuated, the two-dimensional hole gas induced in the hydrogen-terminated diamond layer disappears, while when the layer is exposed to the air, the two-dimensional hole gas is generated. Therefore, the above-mentioned phenomenon suggests that molecules contained in the air are necessary to induce two-dimensional hole gas in the hydrogen-terminated diamond layer. That is, it is considered that conductivity is not expressed only by hydrogen-terminating the diamond layer, and that conductivity is expressed only when surface adsorbates made of negative ions are attached to the hydrogen-terminated diamond layer. Based on this knowledge, the present inventor has devised a way to make the "surface conduction type FET" a "normally-off type FET". The technical idea of ​​this embodiment in which this devise is implemented will be explained below.

[0043] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is to realize a "surface conduction FET" as a "normally-off FET" by utilizing the fact that the conductivity of the hydrogen-terminated diamond layer can be controlled by controlling the amount of surface adsorbates attached to the surface of the hydrogen-terminated diamond layer based on the above-mentioned findings. In detail, the basic idea is to eliminate the conductivity of the channel formation region formed in the hydrogen-terminated diamond layer by desorbing surface adsorbates. In other words, the basic idea is to reduce the hole concentration in the channel formation region formed in the hydrogen-terminated diamond layer by desorbing surface adsorbates.

[0044] According to this basic concept, in the off state where no gate voltage is applied to the gate electrode, the hole concentration in the channel formation region can be reduced to a level where the FET is not conductive. On the other hand, when a gate voltage of negative potential is applied to the gate electrode, a two-dimensional hole gas is induced in the channel formation region located directly below the gate electrode, as if attracted by the negative potential. As a result, in the on state where a gate voltage of negative potential is applied to the gate electrode, the hole concentration in the channel formation region can be increased to a level where the FET is conductive. In this way, according to the basic concept, a "surface conduction FET" can be realized as a "normally off FET".

[0045] The following describes an embodiment that embodies the above-mentioned basic concept. Note that the embodiment is merely an example that embodies the basic concept, and it goes without saying that the technical concept of the present embodiment is not limited to the embodiment described below.

[0046] <Embodiment> <<Structure of Surface Conduction FET>> FIG. 1 is a diagram illustrating a surface-conduction type FET 100 according to an embodiment.

[0047] 1, a surface-conduction FET 100 has a diamond substrate 101 into which nitrogen has been introduced, and an undoped layer 102 is provided on the diamond substrate 101. For example, the top surface of the undoped layer 102 is a (001) plane.

[0048] Here, a diamond substrate 101 having nitrogen introduced therein is used, but this is not limited thereto, and for example, the substrate may be configured to manufacture a surface-conduction FET 100 on a free-standing film made of a non-doped layer 102.

[0049] The non-doped layer 102 has a (001) surface. <110> The off-angle may be set to a few degrees (for example, 3 degrees) in the direction.

[0050] Here, the non-doped layer 102 in this specification is a diamond layer in which the nitrogen impurity concentration is 100 nm, which is the lower limit of detection by a measuring device using SIMS (Secondary Ion Mass Spectrometry). 16 / cm 3 Diamond layer having a thickness of less than 100 nm.

[0051] A hydrogen termination region 103 and an oxygen termination region 104 are formed on the surface of the non-doped layer 102. As a result, a channel formation region 105 having a two-dimensional hole gas is formed in the hydrogen termination region 103 of the non-doped layer 102.

[0052] 1, the channel formation region 105 has a first region P1 overlapping with the gate electrode 111 and a second region P2 not overlapping with the gate electrode 111. More specifically, the channel formation region 105 includes the first region P1 overlapping with the gate electrode 111 in a planar view and the second region P2 not overlapping with the gate electrode 111 in a planar view. In other words, the first region P1 is a region located directly below the gate electrode 111, and the second region P2 is a region disposed so as to sandwich the first region P1 therebetween.

[0053] At this time, in a state where a gate voltage of 0 V is applied to the gate electrode of the surface-conduction type FET 100, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2. Specifically, in a state where a gate voltage of 0 V is applied to the gate electrode of the surface-conduction type FET 100, the hole concentration in the first region P1 is 10 12 / cm 2 Less than or equal to 10 11 / cm 2 On the other hand, the hole concentration in the second region P2 is 10 13 / cm 2 It is more than enough.

[0054] Next, a contact layer 106 and a contact layer 107 are provided on the non-doped layer 102. Each of the contact layers 106 and 107 is a p-type doped layer having a high concentration of boron, which is a p-type impurity (acceptor). + Specifically, a high concentration of boron is introduced into each of the contact layers 106 and 107 so as to be in ohmic contact with the non-doped layer 102. Specifically, the concentration of boron is, for example, 5×10 19 / cm 3 That's it, 1 x 10 22 / cm 3 The thickness of each of the contact layer 106 and the contact layer 107 is, for example, about 20 nm or more and 300 nm or less.

[0055] It should be noted that the contact layers 106 and 107 do not necessarily have to be provided. For example, a source electrode and a drain electrode made of gold electrodes or the like may be formed directly on the hydrogen-terminated non-doped layer 102 to provide ohmic contact.

[0056] A source electrode 108 is provided on the contact layer 106. Meanwhile, a drain electrode 109 is provided on the contact layer 107. Next, an insulating film 110 is provided on the non-doped layer 102 between the contact layer 106 and the contact layer 107, and a gate electrode 111 is provided on the insulating film 110.

[0057] 1, the insulating film 110 has a first insulating region R1 overlapping with the gate electrode 111 and a second region R2 not overlapping with the gate electrode 111. More specifically, the insulating film 110 includes the first insulating region R1 overlapping with the gate electrode 111 in a planar view and a second insulating region R2 not overlapping with the gate electrode 111 in a planar view. In other words, the first insulating region R1 is a region in contact with the gate electrode 111, and the second insulating region R2 is a region not in contact with the gate electrode 111. At this time, the insulating film 110 is negatively charged, and the amount of negative charge of the second insulating region R2 is greater than the amount of negative charge of the first insulating region R1.

[0058] Here, the electrode materials of the source electrode 108, the drain electrode 109, and the gate electrode 111 are, for example, gold (Au), ruthenium (Ru), aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), chromium (Cr), lead (Pb), zinc (Zn), platinum (Pt), or a combination thereof (such as Ti / Mo / Au). The thicknesses of the source electrode 108, the drain electrode 109, and the gate electrode 111 are, for example, about 10 nm or more and 500 nm or less.

[0059] On the other hand, the insulating film 110 is configured to include, for example, any one of an aluminum oxide film (Al2O3), a silicon oxide film (SiO2), a calcium fluoride film (CaF2), a hafnium oxide film (HfO2), an aluminum nitride film (AlN), a boron nitride film (BN), a silicon nitride film (Si3N4), a silicon oxynitride film (SiON), a tantalum oxide film (Ta2O5), a titanium oxide film (TiO2), a tungsten oxide film (WO3), a lanthanum fluoride film (LaF3), or a magnesium fluoride film (MgF2). The thickness of the gate insulating film 110 is, for example, about 5 nm or more and 1000 nm or less. When manufacturing a fine surface conduction type FET 100, it is desirable to set the thickness of the gate insulating film 110 to a thickness of 100 nm or less.

[0060] 1, the gate electrode 111 does not overlap with the contact layer 106, and the gate electrode 111 does not overlap with the contact layer 107. Moreover, in a plan view, the gate electrode 111 does not overlap with the contact layer 106, and the gate electrode 111 does not overlap with the contact layer 107.

[0061] In this manner, the surface conduction type FET 100 is constructed.

[0062] <<Operation of surface conduction FET>> Next, the operation of the surface conduction type FET 100 will be described.

[0063] The surface conduction FET 100 is a p-channel FET, and has a channel formation region 105 having a two-dimensional hole gas formed in the vicinity of the surface of the non-doped layer 102. The channel formation region 105 has a first region P1 located directly under the gate electrode 111 and a second region P2 located outside both ends of the gate electrode 111.

[0064] In the surface conduction type FET according to the embodiment, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2. For example, when 0 V is applied to the gate electrode 111, the hole concentration in the first region P1 is 10 12 / cm 2 while the hole concentration in the second region P2 is 10 13 / cm 2 This is because, as shown in Fig. 1, the amount of negative charge in the second insulating region R2 of the insulating film 110 is greater than the amount of negative charge in the first insulating region R1 of the insulating film 110, and as a result, the second region P2 in contact with the second insulating region R2 attracts more holes than the first region P2 in contact with the first insulating region R1.

[0065] As a result, when 0 V is applied to the gate electrode 111, the second region P2 is conductive, while the first region P1 is not conductive. In other words, a channel due to two-dimensional hole gas is formed in the second region P2, while a channel sufficient to provide conductivity is not formed in the first region P1. In other words, a channel is not formed throughout the entire channel formation region 105 including the first region P1 and the second region P2.

[0066] Therefore, when 0 V is applied to the gate electrode 111, the surface-conduction FET 100 is turned off. That is, when 0 V is applied to the gate electrode 111, even if a potential difference is applied between the source electrode 108 and the drain electrode 109, no channel is formed in the first region P1 of the channel formation region 105, and therefore no hole current flows between the source electrode 108 and the drain electrode 109. Therefore, the surface-conduction FET 100 in this embodiment is a "normally-off FET."

[0067] In contrast, when a negative potential equal to or greater than the threshold voltage is applied to the gate electrode 111, holes are attracted to the gate electrode 111 at the negative potential, and as a result, the hole concentration in the first region P1 located directly below the gate electrode 111 increases. As a result, a channel due to the two-dimensional electron gas is formed not only in the second region P2 but also in the first region P1. That is, a channel is formed throughout the entire channel formation region 105 including the first region P1 and the second region P2.

[0068] As a result, in a state where a potential equal to or higher than the threshold voltage is applied to the gate electrode 111, for example, a positive potential is applied to the source electrode 108, while a reference potential of 0 V is applied to the drain electrode 109. As a result, a hole current flows through the path of the source electrode 108 → the contact layer 106 → the second region P2 of the channel formation region 105 → the first region P1 of the channel formation region 105 → the second region P2 of the channel formation region 105 → the contact layer 107 → the drain electrode 109.

[0069] By controlling the gate voltage applied to the gate electrode 111 in this manner, the switching operation (ON / OFF operation) of the surface conduction type FET 100 can be realized.

[0070] In particular, in the embodiment, the surface-conduction type FET 100 can be operated as a "normally-off type FET."

[0071] <<Method of manufacturing surface conduction FET>> Next, a method for manufacturing a semiconductor device including a surface conduction type FET will be described.

[0072] First, as shown in FIG. 2, for example, a non-doped layer 102 is formed on a diamond substrate 101 containing nitrogen. The non-doped layer 102 is a diamond layer, and can be formed, for example, by using the MPCVD method. The film formation conditions include CH4 / H2=0.5% and no impurities are added. The thickness of the non-doped layer 102 is, for example, about several μm.

[0073] Here, it is desirable to grow the layer by CVD so that the top surface of the non-doped layer is the (001) plane. This is because, from the viewpoint of improving flatness, etc., the (001) plane is excellent for growing a high-quality film by CVD, and as a result, there is an advantage in that a semiconductor device including a high-performance surface conduction type FET can be easily manufactured. Furthermore, from the viewpoint of forming a high-quality film by CVD, it is desirable to provide an off-angle of several degrees. Specifically, in the embodied embodiment, the (001) plane is <110> The direction is given an off angle of 3 degrees.

[0074] By providing an off-angle, the number of steps can be increased, which makes it easier for growth seeds flowing on the surface to reach the edge of the steps, promoting step-flow growth and suppressing the occurrence of abnormal growth.

[0075] 3, the contact layer 106 and the contact layer 107 are selectively grown on the non-doped layer 102. + The contact layer 106 and the contact layer 107 can be formed by using, for example, the HFCVD method. At this time, boron is introduced as a p-type impurity. The impurity concentration of boron is, for example, 10 21 / cm 3 The thickness of each of the contact layers 106 and 107 is, for example, about 0.2 μm. In this process, the hydrogen-terminated region 103A is formed. Alternatively, a hydrogen-termination process may be performed using hydrogen plasma generated in a separate CVD apparatus.

[0076] Next, as shown in Fig. 4, photolithography and hydrogen plasma treatment are used to selectively form hydrogen termination region 103 (conductive region), and photolithography and oxygen plasma treatment are used to selectively form oxygen termination region 104 (insulating region). Note that if hydrogen termination region 103A is formed in the step shown in Fig. 3, the step of forming hydrogen termination region 103 shown in Fig. 4 may be omitted.

[0077] Thereafter, when the diamond substrate 101 is exposed to the atmosphere, surface adsorbates 120 consisting of negative ions are adsorbed to the hydrogen-terminated region 103. As a result, holes constituting a two-dimensional hole gas are induced throughout the channel formation region 105, as shown in FIG.

[0078] 5, a step of reducing the hole concentration of holes (two-dimensional hole gas) induced in the hydrogen-terminated region 103 is carried out. Specifically, this step is carried out by a step of desorbing surface adsorbates attached to the hydrogen-terminated region 103. This is because, since holes are induced when surface adsorbates are adsorbed on the hydrogen-terminated region 103, it is believed that the hole concentration in the hydrogen-terminated region 103 can be reduced by desorbing the surface adsorbates. In particular, the hole concentration is reduced in the channel formation region, which is the hydrogen-terminated region 103.

[0079] The step of desorbing surface adsorbates attached to the hydrogen-terminated region 103 can be achieved, for example, by carrying out hydrogen plasma treatment in a vacuum. This makes the channel formation region non-conductive. The hydrogen plasma treatment conditions are 50 mTorr (1 Torr = 1.33 × 10 2 For example, the following conditions can be given: ICP: 500 W, bias: 50 W, time: 10 min. However, since the conditions can vary significantly depending on the device structure and the equipment used, it is necessary to determine the conditions for each measurement environment.

[0080] The hydrogen plasma treatment in a vacuum that is performed to desorb the surface adsorbates is performed not only on the hydrogen-terminated region 103 but also on the oxygen-terminated region 104. In this regard, it has been confirmed that the insulating properties of the oxygen-terminated region 104 do not deteriorate when the above-mentioned hydrogen plasma treatment in a vacuum is performed on the oxygen-terminated region 104 (the oxygen-terminated region 104 is maintained). In other words, it has been confirmed that the hydrogen plasma treatment in a vacuum can desorb the surface adsorbates attached to the hydrogen-terminated region 103 while sufficiently reducing the side effect of degrading the insulating properties of the oxygen-terminated region 104.

[0081] 6, an insulating film 110 is formed to cover the hydrogen-terminated region 103 and the oxygen-terminated region 104. The insulating film 110 is made of, for example, an aluminum oxide film, and can be formed by using an ALD method with a film formation temperature 1 of about 300° C.

[0082] Thereafter, the insulating film 110 is patterned by using photolithography and etching techniques. The insulating film 110 is patterned by forming an opening in the insulating film 110, removing the hydrogen-terminated region 103 exposed from the opening, and exposing a part of the upper surface of each of the contact layer 106 and the contact layer 107.

[0083] 7, a metal film is formed on the patterned insulating film 110. The metal film is formed of, for example, a ruthenium film, and can be formed by using a sputtering method. At this time, the thickness of the metal film is, for example, about 100 nm.

[0084] Then, the metal film is patterned using photolithography and etching techniques, thereby forming the source electrode 108, the drain electrode 109, and the gate electrode 111, each made of the metal film.

[0085] 8, a negative charging process is performed on the region (second insulating region R2) of the insulating film 110 exposed from the gate electrode 111. Specifically, an oxygen plasma process is performed on the insulating film 110. Here, the input power and the process time can be adjusted depending on the device used and the extent of the charging process to be performed.

[0086] Such oxygen plasma treatment supplies excess oxygen to the aluminum oxide film constituting the insulating film 110 or changes the film quality, so that the second insulating region R2 of the insulating film 110 exposed to the oxygen plasma becomes negatively charged. On the other hand, the first insulating region R1 of the insulating film 110 overlapping with the gate electrode 110 is not exposed to the oxygen plasma and is therefore not charged. As a result, the amount of negative charge in the second insulating region R2 becomes greater than the amount of negative charge in the first insulating region R1.

[0087] 8, the second region P2 of the channel formation region 105 that does not overlap with the gate electrode 111 in plan view is in contact with the second insulating region R2 that has a large amount of negative charge, and holes are attracted to this negative charge, resulting in a large hole concentration. On the other hand, the first region P1 of the channel formation region 105 that overlaps with the gate electrode 111 in plan view is in contact with the first insulating region R1 that has almost no negative charge, and therefore maintains a small hole concentration. In this way, the channel formation region 105 is composed of the first region P1 with a small hole concentration and the second region P2 with a large hole concentration in the off state of the field effect transistor. As a result of the above, the semiconductor device in the embodied embodiment can be manufactured.

[0088] According to the embodiment, the surface-conduction FET can be made into a "normally-off FET" simply by adding (1) a step of desorbing surface adsorbates (hydrogen plasma treatment in a vacuum) and (2) a step of performing a negative charging treatment (oxygen plasma treatment). That is, the method for manufacturing a semiconductor device according to the embodiment can make a surface-conduction FET into a "normally-off FET" through a simple manufacturing process. Furthermore, being able to manufacture the FET through a simple manufacturing process also leads to improved manufacturing yields, so the method for manufacturing a semiconductor device according to the embodiment is extremely useful from the viewpoint of practical application with mass production in mind.

[0089] <<Features of the Realization>> For example, as shown in Fig. 1, a surface-conduction FET 100 in an embodiment has a "non-overlapping structure." The "non-overlapping structure" is an FET structure in which the entire channel-forming region 105 does not overlap with the gate electrode 111, but the channel-forming region 105 has a region that does not overlap with the gate electrode 111 in a plan view, as shown in Fig. 1. That is, in the "non-overlapping structure," the channel-forming region 105 has a first region P1 that overlaps with the gate electrode 111 and a second region P2 that does not overlap with the gate electrode 111. The "non-overlapping structure" configured in this manner has the following advantages.

[0090] 1, in the "non-overlapping structure," the distance between the gate electrode 111 and the source electrode 108 is large. This means that the gate-source capacitance, which is the parasitic capacitance between the gate electrode 111 and the source electrode 108, can be reduced.

[0091] Similarly, in the "non-overlapping structure", the distance between the gate electrode 111 and the drain electrode 109 is large. This means that the gate-drain capacitance, which is the parasitic capacitance between the gate electrode 111 and the drain electrode 109, can be reduced.

[0092] Therefore, the "non-overlap structure" can reduce the gate-source capacitance and gate-drain capacitance, thereby suppressing signal delay and a decrease in switching speed caused by parasitic capacitance. In other words, the "non-overlap structure" can improve the frequency characteristics of the surface-conduction FET 100. This can improve the amplification factor in an amplifier circuit, for example. In this way, the surface-conduction FET 100 having the "non-overlap structure" has the advantage of improving performance.

[0093] Furthermore, increasing the distance between the gate electrode 111 and the source electrode 108 means that the gate-source breakdown voltage can be improved. Similarly, increasing the distance between the gate electrode 111 and the drain electrode 109 means that the gate-drain breakdown voltage can be improved. As a result, the surface-conduction FET 100 having the "non-overlapping structure" has a high dielectric strength, and therefore has the advantage of being able to be driven at a high voltage. For this reason, the surface-conduction FET 100 having the "non-overlapping structure" is very useful when applied to transistors for power electronics, which require high-voltage operation.

[0094] For the above reasons, the surface-conduction FET 100 having a "non-overlapping structure" has excellent performance. Furthermore, if this surface-conduction FET 100 is a "normally-off FET", it is desirable to be able to achieve even further improvements in performance.

[0095] In the embodiment, therefore, a "normally-off type FET" is realized by implementing a technique for embodying the basic concept of the surface-conduction type FET 100 having a "non-overlapping structure."

[0096] The following describes the characteristics adopted in the embodiment.

[0097] A characteristic feature of the embodiment is that, for example, as shown in FIG. 1, assuming that the channel formation region 105 is composed of a first region P1 and a second region P2, when a gate voltage of "0V" is applied to the gate electrode 111, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2 (representation A). In detail, when a gate voltage of "0V" is applied to the gate electrode 111, the hole concentration in the first region P1 is low enough to not have conductivity, while the hole concentration in the second region P2 is high enough to have conductivity. For example, when a gate voltage of "0V" is applied to the gate electrode 111, the hole concentration in the first region P1 is 10 12 / cm 2 Less than or equal to 10 11 / cm 2 The hole concentration in the second region P2 is 10 13 / cm 2 The concentration is above that.

[0098] According to the characteristic point, therefore, when a gate voltage of "0V" is applied to the gate electrode 111, no channel is formed in the first region P1 located directly below the gate electrode 111. Therefore, the surface conduction FET 100 is in an off state when a gate voltage of "0V" is applied to the gate electrode 111. That is, when a gate voltage of "0V" is applied to the gate electrode 111, the hole concentration in the second region P2 is high enough to have conductivity, so that a channel is formed in the second region P2, but no channel is formed in the first region P1 as described above. Therefore, when a gate voltage of "0V" is applied to the gate electrode 111, no channel is formed over the entire channel formation region 105, so that the surface conduction FET 100 is in an off state.

[0099] In contrast, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, holes are attracted to the negative potential. This increases the hole concentration in the first region P1 located directly below the gate electrode 111. In other words, a two-dimensional hole gas is induced in the first region P1. As a result, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, a channel is formed in the first region P1.

[0100] Then, since the hole concentration in the second region P2 is high enough to have conductivity even when a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 111, a channel is formed in the second region P2. Therefore, when a gate voltage (negative potential) equal to or higher than the threshold voltage is applied to the gate electrode 111, a channel is formed throughout the channel formation region 105, so that the device is in the on state.

[0101] In this way, according to the characteristic feature of the embodiment, the surface-conduction FET 100 having the “non-overlapping structure” can be made into a “normally-off FET.” Therefore, according to the characteristic feature, the performance of the surface-conduction FET 100 can be improved.

[0102] The features of the above-described embodiment are realized, for example, in a method for manufacturing a semiconductor device including: (1) a step of desorbing surface adsorbates (hydrogen plasma treatment in a vacuum); and (2) a step of negatively charging the insulating film 110 (oxygen plasma treatment).

[0103] For this reason, the characteristic feature of the embodiment described above can be expressed as follows: For example, as shown in Fig. 1, the characteristic feature of the embodiment is that, on the premise that the insulating film 110 includes a first insulating region R1 overlapping with the gate electrode 111 and a second insulating region R2 not overlapping with the gate electrode 111, the negative charge amount of the second insulating region R2 is larger than the negative charge amount of the first insulating region R1 (expression B).

[0104] This expression is possible because the first region P1 is disposed directly below the first insulating region R1, while the second region P2 is disposed directly below the second insulating region R2. In other words, in the second region P2 located below the second insulating region R2, which has a larger negative charge than the first insulating region R1, the number of holes attracted to the negative charge increases. As a result, the hole concentration in the second region P2 increases more than the hole concentration in the first region P1, and as a result, when the configuration of expression B is adopted, the configuration of expression A is inevitably realized. In this way, the characteristic points in the embodied mode can be expressed as expression A or expression B.

[0105] In the embodiment, the surface adsorbates attached to the hydrogen-terminated region 103 are desorbed. This improves the mobility of holes (carriers) in the channel. This is because the surface adsorbates attached to the upper surface of the channel formation region 105 are removed, reducing Coulomb scattering of holes (carriers) caused by the surface adsorbates. As a result, the embodiment improves the frequency characteristics by improving the mobility of holes.

[0106] <<Verification of effectiveness>> Next, a description will be given of the results of verification that a surface-conduction FET can be realized as a "normally-off FET" according to the embodiment.

[0107] In an embodiment, for example, a surface conduction FET is manufactured by a semiconductor device manufacturing method including: (1) a step of desorbing surface adsorbates (hydrogen plasma treatment in a vacuum); and (2) a step of negatively charging the insulating film 110 (oxygen plasma treatment).

[0108] Here, the steps (1) and (2) are collectively referred to as a hole concentration adjusting step.

[0109] First, the drain current-gate voltage characteristics of a surface-conduction FET manufactured without performing the hole concentration adjustment process will be described. Fig. 9 is a graph showing the drain current-gate voltage characteristics of a surface-conduction FET manufactured without performing the hole concentration adjustment process.

[0110] In Fig. 9, the horizontal axis indicates the gate voltage (V), while the vertical axis indicates the drain current (A). As shown in Fig. 9, when the gate voltage is "0 V", a drain current flows that is seven orders of magnitude larger than the off level. This shows that a surface-conduction FET manufactured without implementing the hole concentration adjustment process is manufactured as a "normally-on type FET".

[0111] Next, the drain current-gate voltage characteristic of the surface conduction FET manufactured by carrying out the hole concentration adjustment process will be described. FIG. 10 is a graph showing the drain current-gate voltage characteristic of the surface conduction FET manufactured by carrying out the hole concentration adjustment process. In FIG. 10, the horizontal axis shows the gate voltage (V), while the vertical axis shows the drain current (A). As shown in FIG. 10, when the gate voltage is "0V", it can be seen that the drain current has a current value smaller than the lower limit of measurement. This shows that the surface conduction FET manufactured by carrying out the hole concentration adjustment process is manufactured as a "normally-off type FET". In particular, the result shown in FIG. 10 has been confirmed for a plurality of surface conduction FETs, and a "normally-off type FET" is realized with good reproducibility by carrying out the hole concentration adjustment process in the embodied embodiment.

[0112] Furthermore, when the hole concentration directly below the gate electrode was measured at a gate voltage of 0 V using Hall effect measurements and drain current-gate voltage characteristics, the hole concentration was found to be 10 11 / cm 2 It was experimentally confirmed that the on / off ratio (ratio of on current to off current) was less than 10. 12 / cm 2 It was also confirmed that the surface-conduction FET described below may also be used practically as a "normally-off FET."

[0113] The above demonstrates that, according to the embodiment, a surface-conduction FET can be manufactured and used as a "normally-off FET."

[0114] <Variation 1> In the embodiment, an example has been described in which a "normally-off FET" is realized by applying the basic concept to a surface-conduction FET having a "non-overlapping structure". In this regard, in the present modified example 1, an example has been described in which a "normally-off FET" is realized by applying the basic concept to a surface-conduction FET having an "overlapping structure". In other words, the basic concept can be widely applied not only to surface-conduction FETs having a "non-overlapping structure", but also to surface-conduction FETs having an "overlapping structure".

[0115] Fig. 11 is a cross-sectional view showing a schematic diagram of a surface-conduction FET 200 having an "overlapping structure" according to Modification 1. In Fig. 11, the "overlapping structure" refers to a FET structure in which the entire channel formation region 105 overlaps with the gate electrode 111 in a plan view.

[0116] In the surface conduction FET 200 having such an "overlap structure", when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the channel formation region 105 is low enough to not have conductivity. 12 / cm 2 Below, preferably 10 11 / cm 2 The concentration is as follows. As a result, when a gate voltage of "0 V" is applied to the gate electrode 111, no channel is formed in the channel formation region 105. For this reason, the surface conduction type FET 200 having the "overlap structure" is in the off state.

[0117] On the other hand, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, holes are attracted to the negative potential. As a result, the hole concentration increases to a level at which the channel formation region 105, which overlaps with the gate electrode 111 in a planar manner, is conductive. In other words, a two-dimensional hole gas is induced throughout the channel formation region 105. As a result, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, a channel is formed throughout the channel formation region 105.

[0118] Therefore, when a gate voltage (negative potential) equal to or greater than the threshold voltage is applied to the gate electrode 111, a channel is formed throughout the channel formation region 105, and the surface conduction FET 200 having an "overlap structure" is turned on.

[0119] In this way, according to the first modification, the surface-conduction type FET 200 having the "overlap structure" can be operated as a "normally-off type FET."

[0120] Here, the surface-conduction FET 200 having the "overlap structure" in the present modified example 1 can be manufactured by simply adding a step of desorbing surface adsorbates (hydrogen plasma treatment in a vacuum). That is, the surface-conduction FET 200 having the "overlap structure" in the present modified example 1 does not require a step of negatively charging the insulating film 110 (oxygen plasma treatment). This is because, in the surface-conduction FET 200 having the "overlap structure", the entire channel-forming region 105 overlaps with the gate electrode 111, and therefore, when the surface-conduction FET 200 is turned on, the channel modulation effect from the gate electrode 111 can be applied to the entire channel-forming region 105. That is, in the surface-conduction FET 200 having the "overlap structure" in the present modified example 1, unlike the surface-conduction FET 100 having the "non-overlap structure" in the embodied embodiment, there is no second region P2 (a region that does not overlap with the gate electrode 111 in plan view) in which the channel modulation effect is not effective, and therefore it is not necessary to make the hole concentration of the second region P2 high enough to have conductivity.

[0121] Therefore, according to the first modification, the surface-conduction type FET 200 can be made into a "normally-off type FET" through an even simpler manufacturing process than that of the embodied mode.

[0122] <Variation 2> <<Expansion of the basic idea>> The basic idea is to reduce the hole concentration in the channel formation region formed in the hydrogen-terminated diamond layer to a level where the hole concentration in the channel formation region is not conductive by desorbing the surface adsorbents.In this regard, the basic idea described above is not limited to the means of desorbing the surface adsorbents, but can be expanded to the idea of ​​reducing the hole concentration in the channel formation region to a level where the hole concentration is not conductive by any means.

[0123] An example that embodies the expanded basic concept will be described below. Specifically, in this modification 2, a means for reducing the hole concentration in the channel formation region to a level at which the channel formation region is not conductive is adopted that is different from the means for desorbing surface adsorbates.

[0124] In this second modification, the surface adsorbates attached to the hydrogen-terminated region are not desorbed. As a result, in the surface-conduction FET in this second modification, the hole concentration in the channel-forming region is high enough to have conductivity. In other words, a channel is formed in the channel-forming region when a gate voltage of "0 V" is applied to the gate electrode. Therefore, in this case, since it becomes a "normally-on FET," it is necessary to reduce the hole concentration in the channel-forming region to a level that does not have conductivity by some means.

[0125] In this regard, focusing on the "non-overlapping structure", in this modification 2, for example, in FIG. 1, the first insulating region R1 of the insulating film 110 located on the first region P1 of the channel formation region 105 is positively charged. As a result, a repulsive force is applied from the positively charged first insulating region R1 to the holes induced in the first region P1. As a result, the holes are moved away from the first region P1 by the repulsive force, so that the hole concentration in the first region P1 is reduced to a level at which the region does not have conductivity. That is, in this modification 2, instead of a means of desorbing surface adsorbates, a means of positively charging the first insulating region R1 of the insulating film 110 is adopted as a means for reducing the hole concentration in the channel formation region 105 to a level at which the region does not have conductivity.

[0126] As a result, according to the present modification 2, when a gate voltage of "0 V" is applied to the gate electrode 111, the hole concentration in the channel formation region 105 is reduced to a concentration that does not have conductivity. In other words, according to the present modification 2, when a gate voltage of "0 V" is applied to the gate electrode 111, no channel is formed in the first region P1 of the channel formation region 105. As a result, according to the present modification 2, the surface conduction type FET 100 can be a "normally off type FET". Note that since the second insulating region R2 of the insulating film 110 is not positively charged, no repulsive force acts in the second region P2 of the channel formation region 105. As a result, the hole concentration in the second region P2 is maintained to a degree that has conductivity.

[0127] In this manner, in this second modification, the expanded basic idea of ​​reducing the hole concentration in the channel formation region 105 to a level that does not have conductivity by some means is embodied by positively charging the first insulating region R1 of the insulating film 110.

[0128] As a result, also in this second modification, for example, as shown in FIG. 1, assuming that the channel formation region 105 is composed of a first region P1 and a second region P2, when a gate voltage of "0V" is applied to the gate electrode 111, the hole concentration in the first region P1 is smaller than the hole concentration in the second region P2 (representation A). In detail, when a gate voltage of "0V" is applied to the gate electrode 111, the hole concentration in the first region P1 is low enough to not have conductivity, while the hole concentration in the second region P2 is high enough to have conductivity. For example, when a gate voltage of "0V" is applied to the gate electrode 111, the hole concentration in the first region P1 is 10 12 / cm 2 Less than or equal to 10 11 / cm 2 The hole concentration in the second region P2 is 10 13 / cm 2 The concentration is greater than or equal to 100 ppm.

[0129] The configuration of the above-described second modification can be realized by a method for manufacturing a semiconductor device that includes a step of positively charging the first insulating region R1 of the insulating film 110.

[0130] For this reason, the configuration of the present modified example 2 can be expressed as follows: For example, as shown in Fig. 1, the configuration of the present modified example 2 can be expressed as follows (expression C): on the premise that the insulating film 110 includes a first insulating region R1 that overlaps with the gate electrode 111 and a second insulating region R2 that does not overlap with the gate electrode 111, the amount of positive charge in the first insulating region R1 is greater than the amount of positive charge in the second insulating region R2.

[0131] This expression is possible because the first region P1 is disposed directly below the first insulating region R1, while the second region P2 is disposed directly below the second insulating region R2. In other words, in the first region P1 located below the first insulating region R1, which has a larger positive charge amount than the second insulating region R2, the number of holes decreases due to repulsive forces from the positive charges. Therefore, the hole concentration in the first region P1 is lower than the hole concentration in the second region P2, and as a result, when the configuration of expression C is adopted, the configuration of expression A is necessarily realized. In this way, the configuration in this modification 2 can be expressed as expression A or expression C.

[0132] The surface-conduction FET 100 having the "non-overlapping structure" in the present modified example 2 can be manufactured simply by adding a step of positively charging the first insulating region R1 of the insulating film 110. Thus, according to the present modified example 2, the surface-conduction FET having the "non-overlapping structure" can be made into a "normally-off FET" by a simple manufacturing process.

[0133] The technical idea of ​​the present modified example 2 can be applied not only to a surface-conduction type FET having a "non-overlapping structure" but also to a surface-conduction type FET having an "overlapping structure".

[0134] For example, in a surface-conduction FET 200 having an “overlap structure” shown in FIG. 11, the insulating film 110 is positively charged, thereby realizing an expanded basic idea of ​​reducing the hole concentration in the channel formation region 105 to a level at which the region is not conductive.

[0135] <Application Examples> Next, an application example of the surface conduction type FET according to this embodiment will be described.

[0136] The surface-conduction FET according to the present embodiment has high potential as a semiconductor device and is expected to be applied to various systems. An example of a system to which the surface-conduction FET according to the present embodiment can be applied will be described below.

[0137] <<Application to power conversion systems>> The most important issues in realizing a sustainable society are the depletion of energy resources and the excessive emission of greenhouse gases such as carbon dioxide. For this reason, power conversion systems that are both energy efficient and emit little carbon dioxide are becoming increasingly important. Most power conversion systems are composed of power modules in which power electronics transistors, which are switching elements, and diodes, which are rectifying elements, are connected in parallel.

[0138] For example, a power conversion system applied to a railway vehicle will be described.

[0139] Electric power is supplied to the railway vehicle from the overhead line via a pantograph. The high-voltage AC voltage supplied to the railway vehicle from the overhead line via the pantograph is stepped down, for example, to an AC voltage by an insulated main transformer. This stepped-down AC voltage is forward converted to a DC voltage by a converter. The DC voltage converted by the converter is then converted by an inverter via a capacitor into three-phase AC voltages with phases shifted by 120 degrees from each other. The three-phase AC voltages converted by the inverter are then supplied to a three-phase motor. As a result, the three-phase motor is driven to rotate the wheels, thereby allowing the railway vehicle to run.

[0140] Thus, the power conversion system of a railway vehicle includes an inverter. For example, the inverter is composed of six power electronics transistors and six freewheel diodes. As described above, power devices such as power electronics transistors and freewheel diodes are used as main components having switching and rectification functions.

[0141] In this regard, the surface conduction FET of the present embodiment can be used as a power electronics transistor. This is because diamond has a larger band gap than silicon, and hence has a higher dielectric breakdown field strength than silicon. In other words, a power electronics transistor using diamond has a higher dielectric breakdown field strength than silicon, and therefore it is easier to ensure a breakdown voltage than a power electronics transistor using silicon as a substrate material. Furthermore, a surface conduction FET using diamond has a large carrier density, and therefore it is possible to reduce the on-resistance. In other words, a surface conduction FET using diamond as a substrate material can achieve both the breakdown voltage and the on-resistance, which are in a trade-off relationship.

[0142] Here, for example, a "normally-off FET" is the most important in a power device. Specifically, power devices are widely used in power conversion systems that utilize large amounts of power, such as in automobiles, railroad cars, and airplanes, and safety is of utmost importance in power conversion systems. For this reason, a "normally-off FET" that outputs "0" when broken is necessary in a power conversion system. In this regard, the surface-conduction FET in this embodiment realizes a "normally-off FET." Therefore, it is useful to use the surface-conduction FET in this embodiment as a power electronics transistor, which is a component of a power conversion system.

[0143] <<Application to communication systems>> In recent years, with the advancement of broadband information and communications, there is a demand for higher frequencies and higher output for high-frequency transistors that support communication systems. On the other hand, from the perspective of energy conservation, there is also a demand for energy efficiency in high-frequency transistors. In this regard, diamond can be cited as a semiconductor material that meets the above-mentioned requirements.

[0144] For example, the operating frequencies and output power of broadcasting earth stations, communication satellites, and radar exceed the performance of current semiconductors, so vacuum tubes called traveling wave tubes are still in use, and there is a demand for improved reliability, higher efficiency, and smaller size through the use of semiconductors.

[0145] Therefore, if a high-frequency transistor using diamond as a semiconductor material is put to practical use, it will be possible to dramatically improve the high-frequency characteristics and high-output characteristics in communication systems including broadcasting terrestrial stations, communication satellites, radars, etc. Therefore, using the surface conduction FET of this embodiment as a high-frequency transistor, which is a component of the above-mentioned communication system, is very useful from the viewpoint of improving the high-frequency characteristics and high-output characteristics of the communication system.

[0146] <<Application to harsh environment systems>> Silicon has low resistance to gamma rays and neutrons. In contrast, diamond is a single element crystal of carbon and is a semiconductor with the same crystal structure as silicon. In diamond, the carbon elements that make up the crystal have strong bonds. For this reason, diamond has the characteristics of having a large band gap, high carrier mobility, and low intrinsic carrier density even at high temperatures, which allows semiconductor devices using diamond to operate at high speeds, with low loss, and at high temperatures.

[0147] Furthermore, the semiconductor device using diamond has a characteristic that the resistance to X-rays is 10MGy or more, and the resistance to neutrons is four or more orders of magnitude higher than that of silicon. That is, diamond has a characteristic that electron-hole pairs are generated very little under high temperature or radiation. Therefore, the surface-conduction type FET in this embodiment using diamond with excellent radiation resistance and high temperature resistance is suitable for use as a harsh environment transistor, which is a component of a harsh environment system placed in a harsh environment where radiation exists or a harsh environment system placed in a high temperature environment. In other words, by using the surface-conduction type FET in this embodiment in a harsh environment system, the performance of the harsh environment system can be improved.

[0148] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0149] 100 Surface conduction FET 200 Surface Conduction FET 101 Diamond Substrate 102 Non-doped layer 103 Hydrogen-terminated region 103A Hydrogen-terminated region 104 Oxygen termination region 105 Channel formation region 106 Contact Layer 107 Contact Layer 108 Source Electrode 109 Drain electrode 110 Insulating film 111 Gate electrode 120 Surface adsorbate P1 1st area P2 2nd area R1 First insulation region R2 Second insulation area

Claims

1. A semiconductor device including a field-effect transistor, The aforementioned field-effect transistor is A diamond layer containing a hydrogen-terminated region, The channel-forming region formed in the diamond layer, An insulating film formed on the upper surface of the diamond layer, A gate electrode formed on the insulating film, It has, The channel formation region is In a plan view, the first region overlaps with the gate electrode, A second region that does not overlap with the gate electrode in a plan view, Includes, The first region is hydrogen-terminated, The aforementioned second region is hydrogen-terminated, In the off state of the field-effect transistor, The hole concentration in the first region is smaller than the hole concentration in the second region.

2. A semiconductor device including a field-effect transistor, The aforementioned field-effect transistor is A diamond layer containing a hydrogen-terminated region, The channel-forming region formed in the diamond layer, An insulating film formed on the upper surface of the diamond layer, A gate electrode formed on the insulating film, It has, The channel formation region is In a plan view, the first region overlaps with the gate electrode, A second region that does not overlap with the gate electrode in a plan view, Includes, The first region is hydrogen-terminated, The aforementioned second region is hydrogen-terminated, The insulating film is In a plan view, the first insulating region overlaps with the gate electrode, A second insulating region that does not overlap with the gate electrode in a plan view, Includes, The amount of negative charge in the second insulating region is greater than the amount of negative charge in the first insulating region.

3. A semiconductor device including a field-effect transistor, The aforementioned field-effect transistor is A diamond layer containing a hydrogen-terminated region, The channel-forming region formed in the diamond layer, An insulating film formed on the upper surface of the diamond layer, A gate electrode formed on the insulating film, It has, The channel formation region is In a plan view, the first region overlaps with the gate electrode, A second region that does not overlap with the gate electrode in a plan view, Includes, The first region is hydrogen-terminated, The aforementioned second region is hydrogen-terminated, The insulating film is In a plan view, the first insulating region overlaps with the gate electrode, A second insulating region that does not overlap with the gate electrode in a plan view, Includes, The amount of positive charge in the first insulating region is greater than the amount of positive charge in the second insulating region.

4. A semiconductor device including a field-effect transistor, The aforementioned field-effect transistor is A diamond layer containing a hydrogen-terminated region, The channel-forming region formed in the diamond layer, An insulating film formed on the upper surface of the diamond layer, A gate electrode formed on the insulating film, It has, The channel formation region is hydrogen-terminated, In the off state of the field-effect transistor, The hole concentration in the channel-forming region is 10 １２ / cm ２ The following applies:

5. In the semiconductor device described in claim 1, The insulating film is In a plan view, the first insulating region overlaps with the gate electrode, A second insulating region that does not overlap with the gate electrode in a plan view, Includes, The amount of negative charge in the second insulating region is greater than the amount of negative charge in the first insulating region.

6. In the semiconductor device described in claim 1, The off state of the field-effect transistor refers to a state in which the gate voltage applied to the gate electrode is 0V.

7. In the semiconductor device described in claim 1, The upper surface of the diamond layer is the (001) plane.

8. In the semiconductor device described in claim 1, The diamond layer has an off-angle of 3 degrees in the <110> direction with respect to the (001) plane.

9. In the semiconductor device described in claim 1, In the off state of the field-effect transistor, The hole concentration in the first region is 10 １２ / cm ２ The following applies:

10. In the semiconductor device described in claim 1, In the off state of the field-effect transistor, The hole concentration in the first region is 10 １１ / cm ２ The following applies:

11. In the semiconductor device described in claim 1, The insulating film includes any of the following: an aluminum oxide film, a silicon oxide film, a calcium fluoride film, a hafnium oxide film, an aluminum nitride film, a boron nitride film, a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, a titanium oxide film, a tungsten oxide film, a lanthanum fluoride film, or a magnesium fluoride film.

12. In the semiconductor device described in claim 2, In the off state of the field-effect transistor, The hole concentration in the first region is smaller than the hole concentration in the second region.

13. In the semiconductor device described in claim 2, The off state of the field-effect transistor refers to a state in which the gate voltage applied to the gate electrode is 0V.

14. In the semiconductor device described in claim 2, The upper surface of the diamond layer is the (001) plane.

15. In the semiconductor device described in claim 2, The diamond layer has an off-angle of 3 degrees in the <110> direction with respect to the (001) plane.

16. In the semiconductor device described in claim 2, In the off state of the field-effect transistor, The hole concentration in the first region is 10 １２ / cm ２ The following applies:

17. In the semiconductor device described in claim 2, In the off state of the field-effect transistor, The hole concentration in the first region is 10 １１ / cm ２ or less.

18. In the semiconductor device described in claim 2, The insulating film includes any of the following: an aluminum oxide film, a silicon oxide film, a calcium fluoride film, a hafnium oxide film, an aluminum nitride film, a boron nitride film, a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, a titanium oxide film, a tungsten oxide film, a lanthanum fluoride film, or a magnesium fluoride film.

19. In the semiconductor device according to claim 4, In the off state of the field-effect transistor, The hole concentration in the channel-forming region is 10 １１ / cm ２ The following applies:

20. In the semiconductor device according to claim 4, In a plan view, the channel-forming region overlaps with the gate electrode.

21. A system comprising a semiconductor device according to any one of claims 1 to 20.

22. A semiconductor device including a field-effect transistor, The aforementioned field-effect transistor is A diamond layer containing a hydrogen-terminated region, The channel-forming region formed in the diamond layer, An insulating film formed on the upper surface of the diamond layer, A gate electrode formed on the insulating film, It has, The channel formation region is In a plan view, the first region overlaps with the gate electrode, A second region that does not overlap with the gate electrode in a plan view, Includes, The first region is hydrogen-terminated, The aforementioned second region is hydrogen-terminated, The insulating film is In a plan view, the first insulating region overlaps with the gate electrode, A second insulating region that does not overlap with the gate electrode in a plan view, Includes, The amount of oxygen in the second insulating region is greater than the amount of oxygen in the first insulating region.

23. A method for manufacturing a semiconductor device including a field-effect transistor, (a) A step of forming a diamond layer including a hydrogen termination region, (b) A step of reducing the hole concentration in the hydrogen-terminated region, Equipped with, The (b) step includes a step of desorbing surface adsorbents attached to the hydrogen termination region.

24. In the method for manufacturing a semiconductor device according to claim 23, The (b) step includes a step of performing hydrogen plasma treatment in a vacuum.

25. A method for manufacturing a semiconductor device including a field-effect transistor, (a) A step of forming a diamond layer including a hydrogen termination region, (b) A step of reducing the hole concentration in the hydrogen-terminated region, (c) A step of forming an insulating film on the diamond layer, (d) A step of forming a gate electrode on the insulating film, (e) A step of applying a charging treatment to the region of the insulating film exposed from the gate electrode, It has.

26. In the method for manufacturing a semiconductor device according to claim 25, The aforementioned step (e) includes a step of performing oxygen plasma treatment.

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