Semiconductor equipment

Abstract

To provide a storage device in which high integration can be realized, and a semiconductor device that provides the storage device.SOLUTION: A storage device includes a first wiring, a second wiring, and a memory cell. The memory cell includes a first insulation layer, a second insulation layer, a semiconductor, a first conductive layer, a second conductive layer, and a function layer. The memory cell is positioned on the first wiring and positioned below the second wiring. The semiconductor layer, the second insulation layer, the first conductive layer, the function layer, and the second conductive layer are provided in this order in a concentric circular manner around the first insulation layer. Further, in a cros-sectional view, the function layer is provided in contact with an upper surface, a side surface, and a bottom surface of the second conductive layer. The semiconductor layer is in contact with the first wiring and the second wiring. In addition, the function layer includes a ferroelectric material.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] 1. Field of the Invention One aspect of the present invention relates to a memory device. 1. Field of the Invention One aspect of the present invention relates to a semiconductor device including a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] Non-volatile storage devices are embedded in a variety of portable devices, including smartphones, tablet devices, wristwatch-type devices, and wearable devices for AR (Augmented Reality) or VR (Virtual Reality). Hard disk drives have been the main type of non-volatile storage devices up until now, but flash memory is often used in the portable devices mentioned above because it is shock-resistant, can be made small, is lightweight, and does not require physical operation.

[0004] Meanwhile, transistors having an oxide semiconductor or metal oxide in a channel formation region of the transistor (also referred to as oxide semiconductor transistors or OS (oxide semiconductor) transistors) are known. OS transistors have a characteristic that their drain current (also referred to as off-current) is very small when the transistor is in an off state. Patent Document 1 discloses a NAND memory device to which an OS transistor is applied. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2022 / 0068967 Summary of the Invention [Problem to be solved by the invention]

[0006] For non-volatile memory devices used as storage, the larger the memory capacity, the more preferable it is, and high integration is desirable. For memory elements used in non-volatile memory devices, it is desirable to have high rewrite resistance, low voltage operation, and the like.

[0007] An object of one embodiment of the present invention is to provide a memory device that can be highly integrated and a semiconductor device including the memory device.An object of one embodiment of the present invention is to provide a memory element having high rewrite resistance and a semiconductor device including the memory element.An object of one embodiment of the present invention is to provide a memory element that can be driven at a low voltage and a semiconductor device including the memory element.

[0008] An object of one embodiment of the present invention is to provide a highly reliable memory device or semiconductor device.An object of one embodiment of the present invention is to provide a memory device or semiconductor device having a novel structure.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device having a first wiring, a second wiring, and a memory cell. The memory cell has a first insulating layer, a second insulating layer, a semiconductor layer, a first conductive layer, a second conductive layer, and a functional layer. The memory cell is located on the first wiring and below the second wiring. The semiconductor layer, the second insulating layer, the first conductive layer, the functional layer, and the second conductive layer are concentrically arranged in this order around the first insulating layer. In addition, in a cross-sectional view, the functional layer is provided in contact with the top surface, side surface, and bottom surface of the second conductive layer. The semiconductor layer is in contact with the first wiring and the second wiring. Furthermore, the functional layer includes a ferroelectric.

[0011] Another embodiment of the present invention is a semiconductor device having a first wiring, a second wiring, and a memory cell. The memory cell has a first insulating layer, a second insulating layer, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a functional layer. The memory cell is located on the first wiring and below the second wiring. The first insulating layer, the semiconductor layer, the second insulating layer, the first conductive layer, the functional layer, and the second conductive layer are concentrically arranged in this order around the third conductive layer. In addition, in a cross-sectional view, the functional layer is provided in contact with the top surface, side surface, and bottom surface of the second conductive layer. The semiconductor layer is in contact with the first wiring and the second wiring. Furthermore, the functional layer includes a ferroelectric.

[0012] In any of the above, the semiconductor layer preferably includes an oxide film containing indium.

[0013] In any of the above, the functional layer preferably contains an oxide containing hafnium and zirconium, and in this case, the functional layer preferably further contains one or more elements selected from the group consisting of scandium, yttrium, and lanthanum.

[0014] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming a stack of a first interlayer insulating layer, a second interlayer insulating layer, and a first dummy layer in this order; forming a cylindrical opening in the stack; forming a second dummy layer to fill the opening; etching another part of the stack to expose a side surface of the first interlayer insulating layer, a side surface of the second interlayer insulating layer, and a side surface of the first dummy layer; removing the first dummy layer to form a recess surrounded by the second dummy layer, an upper surface of the first interlayer insulating layer, and a lower surface of the second interlayer insulating layer; forming a functional layer along the recess; subsequently forming a second conductive layer to fill the recess; removing the second dummy layer to form an opening again to expose a part of the functional layer; forming a first conductive layer in contact with the exposed surface of the functional layer; performing a heat treatment; and forming a first insulating layer in contact with the first conductive layer and a semiconductor layer in contact with the first insulating layer in the opening.

[0015] In the above, the functional layer is preferably an oxide film containing hafnium and zirconium formed by atomic layer deposition. In this case, the functional layer is preferably an oxide film containing at least one selected from scandium, yttrium, and lanthanum in addition to hafnium and zirconium formed by atomic layer deposition.

[0016] In any of the above, the heat treatment is preferably carried out at a temperature of 300° C. or more and 750° C. or less using an RTA apparatus.

[0017] In the above, the semiconductor layer is preferably an oxide film containing indium formed by atomic layer deposition. Effect of the Invention

[0018] According to one embodiment of the present invention, a memory device capable of being highly integrated or a semiconductor device including the memory device can be provided. According to one embodiment of the present invention, a memory element having high rewrite resistance or a semiconductor device including the memory element can be provided. According to one embodiment of the present invention, a memory element capable of being driven at a low voltage and a semiconductor device including the memory element can be provided.

[0019] According to one embodiment of the present invention, a highly reliable memory device or semiconductor device can be provided. Alternatively, a memory device or semiconductor device having a novel configuration can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0021] [Figure 1] 1A and 1E are configuration examples of a storage device. [Diagram 2] 2A and 2B show examples of the configuration of a storage device. [Diagram 3] 3A and 3B show configuration examples of a storage device. [Figure 4] FIG. 4 is a diagram showing the characteristics of a ferroelectric material. [Diagram 5] 5A and 5B show configuration examples of a storage device. [Figure 6] 6A and 6B show examples of the configuration of a storage device. [Figure 7] 7A and 7B show examples of the configuration of a storage device. [Figure 8] 8(A) and 8(B) show configuration examples of a storage device. [Figure 9] 9A and 9B are diagrams illustrating a method for manufacturing a memory device. [Figure 10] 10A and 10B are diagrams illustrating a method for manufacturing a memory device. [Figure 11] 11A and 11B are diagrams illustrating a method for manufacturing a memory device. [Figure 12]12A and 12B are diagrams illustrating a method for manufacturing a memory device. [Figure 13] FIG. 13 shows an example of the configuration of a storage device. [Figure 14] FIG. 14 shows an example of the configuration of a storage device. [Figure 15] 15A to 15C show configuration examples of the arithmetic processing device. [Figure 16] 16A to 16D show configuration examples of the arithmetic processing device. [Figure 17] FIG. 17 shows an example of the configuration of a semiconductor device. [Figure 18] FIG. 18 shows a configuration example of a semiconductor device. [Figure 19] FIG. 19 shows an example of the configuration of a semiconductor device. [Figure 20] FIG. 20 shows an example of the configuration of a semiconductor device. [Figure 21] FIG. 21 shows an example of the configuration of a semiconductor device. [Figure 22] FIG. 22 shows a configuration example of a semiconductor device. [Diagram 23] FIG. 23 shows a configuration example of a semiconductor device. [Figure 24] 24(A) and 24(B) are diagrams showing various storage devices by hierarchical level. [Diagram 25] 25A to 25J show configuration examples of electronic devices. [Figure 26] 26A to 26H show configuration examples of electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0024] In addition, in each figure described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0025] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components and do not limit the numbers.

[0026] (Embodiment 1) In this embodiment, a semiconductor device and a memory device according to one embodiment of the present invention will be described.

[0027] The semiconductor device according to one embodiment of the present invention has a nonvolatile memory element that functions as a storage. For example, it is preferable to use a large-capacity memory device having a so-called three-dimensional structure in which memory elements are arranged not only in the in-plane direction but also stacked in the thickness direction. As a more specific example, a 3D NAND type memory device having a memory string extending in the normal direction to the formation surface can be used.

[0028] Furthermore, a memory element using a ferroelectric material can be used as a non-volatile memory element. This makes it possible to realize a memory device that is more reliable and consumes less power than a so-called charge trap type memory element. Note that a memory element using an antiferroelectric material may be used in place of a ferroelectric material.

[0029] In addition, the nonvolatile memory element preferably uses an oxide containing hafnium and zirconium as the ferroelectric layer provided between a pair of electrodes. In particular, it is preferable to use an oxide obtained by adding one or more elements selected from yttrium, lanthanum, and scandium to these oxides. Furthermore, in the manufacturing process of the memory element, it is preferable to manufacture the memory element by performing a heat treatment at 300° C. to 750° C. in a state where the ferroelectric layer is in contact with one or more electrodes, preferably in a state where the ferroelectric layer is in contact with a pair of electrodes. This allows the memory element to operate (write and read) at a low voltage and has an extremely high rewrite resistance.

[0030] Another embodiment of the present invention is a semiconductor device in which the memory device is stacked over a substrate on which one or more driver circuits or control circuits are provided. With such a configuration, the wiring length between the memory device and the various circuits can be shortened by an order of magnitude compared to when these are arranged side by side or when these are configured as different chips and mounted on a printed board or the like, and therefore the amount of data per unit time in data exchange between them can be increased.

[0031] Furthermore, one embodiment of the present invention may have a structure in which two types of memory devices, the above-mentioned memory device (also referred to as a first memory device) and a different memory device (also referred to as a second memory device), are stacked. This allows the wiring length between the first memory device and the second memory device to be significantly shortened, thereby increasing the amount of data per unit time in data exchange between them.

[0032] The second storage device is preferably a storage device with a higher access speed than the first storage device. The second storage device may be a volatile storage device that loses information when the power supply is stopped. As a more specific example, a dynamic random access memory (DRAM) can be used. For example, when data stored in the first storage device used as storage is temporarily read into the second storage device, which is a higher-level memory device, and then sent to a processor, the operating speed can be made extremely fast.

[0033] As the second memory device, it is more preferable to use a memory device using a transistor (OS transistor) in which an oxide semiconductor is used for a channel formation region as a memory cell. Since OS transistors have a significantly small leakage current in an off state, a memory device using such a transistor can retain data for a longer period of time than a DRAM, and can reduce power consumption. Furthermore, an oxide semiconductor can be formed as a thin film, so that an OS transistor can be manufactured regardless of the surface on which it is formed. For example, there is an advantage that a circuit formed of an OS transistor can be stacked directly on a semiconductor circuit formed of single crystal silicon.

[0034] A more specific example will be described below with reference to the drawings.

[0035] [Storage device configuration example] FIG. 1A is a schematic perspective view of a storage device 21. FIG.

[0036] The memory device 21 is provided on an insulating layer 50 and has a plurality of memory strings 60. The memory string 60 has a plurality of cell transistors stacked in a direction perpendicular to the upper surface of the insulating layer 50. The memory device 21 further has a plurality of conductive layers 51, a plurality of conductive layers 52, a conductive layer 53, a plurality of conductive layers 54, and a plurality of conductive layers 55 functioning as various wirings, and a plurality of plugs 56.

[0037] In Fig. 1(A), the orthogonal X, Y, and Z directions are indicated by arrows. The memory strings 60 are arranged at equal intervals in the X and Y directions. Fig. 1(A) shows, as an example, one block having 5 x 5 memory strings 60. The memory device 21 has a plurality of such blocks. In practice, it is preferable that one block has a larger number of memory strings 60.

[0038] One memory string 60 is provided so as to connect between the conductive layers 53 and 54. For example, the conductive layer 53 functions as a source line, and the conductive layer 54 functions as a bit line. A plurality of conductive layers 51 are stacked and provided between the conductive layers 53 and 54. The conductive layer 51 functions as a control gate line. A conductive layer 52 functioning as a selection line is provided between the uppermost conductive layer 51 and the conductive layer 54. Each of the plurality of conductive layers 51 is connected to one of the plurality of conductive layers 55 via a plug 56.

[0039] The conductive layers 54 and 52 extend in intersecting directions to form a 5 × 5 matrix. The conductive layers 51 and 53 are connected to all memory strings 60 (here, 5 × 5) in the block.

[0040] 1A shows an example of a configuration having five conductive layers 51, but the number of layers is not limited to this. The greater the number of stacked layers, the greater the number of cell transistors constituting one memory string 60, and the greater the data capacity of the memory device 21. The greater the number of cell transistors constituting one memory string 60, the more preferable it is, and the number can be, for example, 64 or more, 128 or more, 160 or more, 192 or more, 224 or more, or 256 or more.

[0041] 1B shows one memory string 60 and its surrounding configuration. A memory cell 65 functioning as a cell transistor is provided at a portion of the memory string 60 that intersects with the conductive layer 51. The conductive layer 51 located at the bottom among the multiple conductive layers 51 may function as a selection line.

[0042] Fig. 1(C) is a circuit diagram of the configuration shown in Fig. 1(B). The conductive layer 53 corresponds to the wiring CL, the conductive layer 54 corresponds to the wiring BL, the lowermost conductive layer 51 corresponds to the wiring SSL, the other conductive layers 51 correspond to the wiring WL (wirings WL1 to WLm (m is an integer of 2 or more)), and the conductive layer 52 corresponds to the wiring BSL.

[0043] 1C, a transistor STr, a plurality of transistors CTr, and a transistor BTr are provided between the wiring BL and the wiring CL. The transistors STr and BTr each function as a selection transistor, and the transistor CTr functions as a cell transistor. The transistor CTr functions as a memory element.

[0044] The transistor CTr may be a memory element using a ferroelectric, such as a configuration in which a ferroelectric capacitor is connected to the gate, a configuration in which a ferroelectric is applied to the gate insulating layer, etc. In addition, for example, a charge trap type flash memory or a floating gate type flash memory may also be used.

[0045] 1(D) and (E) show an example in which one memory string 60 is configured by a pair of memory strings. In this case, the conductive layer 53 functions as a pipe gate line, and the conductive layer 57 functions as a source line. The transistor PTr provided at the bottom of the U-shaped memory string functions as a selection transistor (also called a pipe transistor) for connecting the pair of memory strings.

[0046] [Memory string configuration example] A specific configuration example of a memory string that can be used in a storage device of one embodiment of the present invention will be described below.

[0047] The memory string 100 of one embodiment of the present invention can be used in a 3D NAND type memory device. Note that in the drawings illustrated below, the X direction, the Y direction, and the Z direction, which are orthogonal to each other, are indicated by arrows.

[0048] FIG. 2(A) is a cross-sectional view of the memory string 100 as viewed from the Y direction. FIG. 2(A) shows one memory string 100 extending in the Z direction and a central axis 120 passing through the center of the memory string 100. FIG. 2(B) is an equivalent circuit of the memory string 100. The memory string 100 has a configuration in which a plurality of transistors Tr are connected in series. For ease of explanation, the selection transistors exemplified above are omitted. FIG. 3(A) and (B) are cross-sectional views of the portions A1-A2 and B1-B2 shown by the dashed lines in FIG. 2(A) as viewed from the Z direction.

[0049] The transistor Tr constituting the memory string 100 has a configuration in which a ferroelectric capacitor is connected to the gate of the transistor. Such a configuration functions as a ferroelectric transistor (FeFET: Ferroelectric Field Effect Transistor). Other configurations of ferroelectric transistors include a configuration in which a ferroelectric is used as an insulator that functions as a gate insulator. The threshold voltage of a ferroelectric transistor can be changed by applying a voltage of a certain level or higher to the gate. By using such a transistor Tr, a NAND type ferroelectric memory can be realized.

[0050] The memory string 100 has a conductive layer 101, m layers (m is an integer of 2 or more) of insulating layers 102, and n layers (n is an integer of 2 or more) of conductive layers 103, which are arranged above a substrate (not shown). The insulating layers 102 and the conductive layers 103 are alternately stacked above the substrate. In FIG. 2(A) and the like, the first insulating layer 102 is indicated as insulating layer 102_1, and the m-th insulating layer 102 is indicated as insulating layer 102_m. Similarly, the first conductive layer 103 is indicated as conductive layer 103_1, and the n-th conductive layer 103 is indicated as conductive layer 103_n. Note that in the present embodiment and the like, when an arbitrary insulating layer 102 is indicated, it is simply indicated as "insulating layer 102". Similarly, when an arbitrary conductive layer 103 is indicated, it is simply indicated as "conductive layer 103".

[0051] The memory string 100 also includes a conductive layer 104, an insulating layer 105, a structure 110, and an insulating layer 121. The structure 110 extends along the Z direction. The structure 110 is provided between the conductive layer 101 and the conductive layer 104 so as to penetrate the insulating layers 102_1 to 102_m.

[0052] The conductive layer 101 corresponds to the wiring SL, the conductive layer 104 corresponds to the wiring BL, and the conductive layer 103 corresponds to the wiring CG.

[0053] The structure 110 includes a columnar structure including a semiconductor layer 112 and an insulating layer 111. More specifically, the semiconductor layer 112 and the insulating layer 111 are provided concentrically on the outside of the cylindrical insulating layer 107 along the central axis 120 (with the insulating layer 107 at the center).

[0054] The cross-sectional shape of the structure 110 in a cross section perpendicular to the Z direction is not limited to a circle, and may be a triangle, a rectangle, or a polygon with pentagons or more sides. The outline of the structure 110 in a cross section perpendicular to the Z direction may be composed of curves only, or may be a combination of straight lines and curves.

[0055] The insulating layer 121 is provided to cover side surfaces of the insulating layers 102_1 to 102_m and the conductive layers 103_1 to 103_n. The conductive layer 104 is provided over the insulating layer 102_m. The conductive layer 101 and the conductive layer 104 are electrically connected to the semiconductor layer 112. The insulating layer 105 is provided over the insulating layer 102_m, the insulating layer 121, and the conductive layer 104.

[0056] An intersection of the structure 110 and the conductive layer 103 functions as a transistor Tr. The transistor Tr functions as a memory cell (also referred to as a "memory element"). In FIG. 2A, an enlarged view of a region surrounded by a two-dot chain line is shown at the bottom.

[0057] The conductive layer 103, the functional layer 118, the insulating layer 114, and the conductive layer 113 are provided in an area surrounded by a pair of insulating layers 102, 111, and 121. The conductive layer 103 is provided in contact with the insulating layer 121. The conductive layer 113 is provided along the side surface of the insulating layer 111 on the conductive layer 103 side. The insulating layer 114 has a portion in contact with the upper surface of the lower insulating layer 102 and a portion in contact with the lower surface of the upper insulating layer 102. The functional layer 118 has at least a portion located between the conductive layer 103 and the conductive layer 113. The functional layer 118 also has a portion located between the conductive layer 103 and the insulating layer 114. The functional layer 118 is provided in contact with the upper surface, the bottom surface, and the side surface opposite to the insulating layer 121 of the conductive layer 102.

[0058] A ferroelectric material can be used for the functional layer 118. As a result, a ferroelectric capacitor is formed by the conductive layer 103, the conductive layer 113, and the functional layer 118 located therebetween.

[0059] In addition, an insulating layer 111 is provided between the conductive layer 113 and the semiconductor layer 112. At this time, part of the semiconductor layer 112 functions as a channel formation region of the transistor, part of the insulating layer 111 functions as a gate insulating layer, and the conductive layer 113 functions as a gate electrode.

[0060] In this manner, the transistor Tr has a configuration in which a ferroelectric capacitor is connected to the gate of the transistor.

[0061] The memory string 100 has n intersections between the structures 110 and the conductive layers 103. Therefore, the memory string 100 has n transistors Tr, that is, n memory cells.

[0062] In many cases, polycrystalline silicon is used for the body portion of the memory string of the 3D NAND. Note that in the memory string 100 according to one embodiment of the present invention, the semiconductor layer 112 corresponds to the body portion. For the semiconductor layer 112, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. For example, silicon, germanium, or the like can be used as the semiconductor material. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide (SiC), gallium arsenide, an oxide semiconductor, or a nitride semiconductor may be used.

[0063] The semiconductor layer 112 may be a semiconductor having improved crystallinity using a catalytic element. The catalytic element may be an element selected from metal elements such as nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (Au), and germanium (Ge).

[0064] For example, the crystallinity may be improved by forming amorphous silicon as the semiconductor layer 112, adding nickel as a catalytic element, and performing heat treatment. Alternatively, the crystallinity may be improved by providing a layer containing nickel in contact with the upper part, the lower part, or both of the amorphous silicon, and performing heat treatment. The catalytic element bonds with silicon to form silicide. In addition, the catalytic element is likely to bond with a portion with many defects such as an amorphous state. Therefore, the catalytic element contained in the silicide reacts with the amorphous silicon to form a new silicide. In this way, crystallization progresses while the silicide moves. In addition, the re-diffusion of the catalytic element can be suppressed by making the catalytic element reach a semiconductor containing an impurity element such as a Group 15 element or a Group 13 element.

[0065] Furthermore, when nickel is added as a catalytic element to the semiconductor layer 112, a concentration gradient of the nickel element may occur in the semiconductor layer 112. For example, the nickel concentration may be lower in a region that functions as a channel of a transistor than in other regions (e.g., a source region and a drain region). In other words, the nickel concentration may be higher in the source region and the drain region than in the region that functions as a channel.

[0066] In addition, when crystallization is performed using a catalytic element, it is preferable to provide a gettering layer in contact with the semiconductor layer 112 to absorb the catalytic element by thermal diffusion. By performing heat treatment in a state where the gettering layer is in contact with the semiconductor layer 112, the catalytic element is diffused into the gettering layer, and the concentration of the catalytic element in the semiconductor layer 112 is reduced, which is preferable. For example, a silicon film or a conductive film containing a Group 15 element such as phosphorus, arsenic, nitrogen, antimony, or bismuth as an impurity can be used. The concentration of the impurity is 1×10 19 atoms / cm 3 More than 1×10 21 atoms / cm 3 It is preferable that the following conditions be satisfied: For example, when the conductive layer 101 and the conductive layer 104 are doped with the above-mentioned impurities, they can be used as gettering layers.

[0067] Furthermore, when amorphous silicon containing phosphorus is used as the gettering layer, after forming the amorphous silicon film, phosphorus may be introduced into the amorphous silicon film by a plasma doping method, an ion implantation method, or the like, or when forming the amorphous silicon film by plasma CVD, a gas containing phosphorus (e.g., PH3 gas) may be used in addition to the film forming gas to form the amorphous silicon film.

[0068] The semiconductor layer 112 functions as a semiconductor layer in which a channel of the transistor Tr is formed. The semiconductor layer used in the transistor may be a stack of semiconductors. When the semiconductor layers are stacked, semiconductor materials having different crystal states may be used for each layer, or different semiconductor materials may be used for each layer.

[0069] In particular, the transistor Tr is preferably a transistor using a metal oxide (oxide semiconductor) that functions as a semiconductor for the semiconductor layer 112 in which a channel is formed. The oxide semiconductor has a band gap of 2 eV or more and therefore has an extremely small off-state current. This allows the power consumption of the memory string 100 to be reduced. As a result, the power consumption of a semiconductor device including the memory string 100 can be reduced.

[0070] In addition, while polycrystalline silicon transistors have threshold voltage variations due to grain boundaries, OS transistors are less affected by grain boundaries and have small threshold voltage variations. Therefore, by using OS transistors for the transistors Tr, the memory string 100 can suppress malfunctions due to threshold voltage variations.

[0071] Moreover, the OS transistor operates stably even in a high-temperature environment, and the characteristics fluctuate little. For example, the off-current hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. Moreover, the on-current is unlikely to decrease even in a high-temperature environment. Therefore, the memory string 100 including the OS memory operates stably even in a high-temperature environment, and high reliability can be obtained. Furthermore, the OS transistor has a high withstand voltage between the source and the drain. By using the OS transistor as the transistor constituting the memory string 100, the memory string 100 can be realized which operates stably even in a high-temperature environment and has good reliability. Therefore, the reliability of the semiconductor device including the memory string 100 can be improved.

[0072] A material exhibiting ferroelectricity is used for the functional layer 118. Examples of the material exhibiting ferroelectricity include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. It is also preferable to use a material obtained by adding a Group 3 (IIIa) element to these oxides. For example, it is preferable to include one or more of elements belonging to scandium, yttrium, and lanthanoids. In particular, yttrium, lanthanum, and scandium are preferable because they are relatively easy to handle and have high affinity with semiconductor manufacturing processes. By adding such elements, not only can ferroelectricity be stably expressed, but also deterioration of characteristics during repeated rewriting can be suppressed, and reliability can be improved. For example, it is preferable to add these elements at a ratio of 0.5 at% or more and 10 at% or less. Other additive elements include silicon, aluminum, gadolinium, and scandium. It is also possible to use not only a material exhibiting ferroelectricity but also a material exhibiting antiferroelectricity for the functional layer 118.

[0073] Oxides containing either or both of hafnium and zirconium easily exhibit ferroelectricity even in extremely thin films prepared using thin-film deposition methods such as sputtering and atomic layer deposition (ALD). This makes them highly compatible with semiconductor manufacturing processes and allows for reduced production costs.

[0074] Furthermore, the functional layer 118 may be made of piezoelectric ceramics having a perovskite structure, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium tantalate bismuthate (SBT), or bismuth ferrite (BFO).

[0075] Alternatively, the functional layer 118 may be made of an organic ferroelectric material such as polyvinylidene fluoride (PVDF) or a copolymer of vinylidene fluoride (VDF) and trifluoroethylene (TrFE).

[0076] In addition, as the material exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the functional layer 118 can have a laminated structure made of multiple materials selected from the materials listed above.

[0077] Among them, hafnium oxide, a material having hafnium oxide and zirconium oxide (HZO), and a material further including yttrium in HZO (HZYO) are preferable as materials exhibiting ferroelectricity because they exhibit ferroelectricity even when processed into a thin film of a few nm. By using a film containing hafnium oxide, HZO, or HZYO, the film thickness of the functional layer 118 can be set to 3 nm to 100 nm, preferably 3 nm to 50 nm, more preferably 3 nm to 20 nm, and even more preferably 4 nm to 10 nm.

[0078] In addition, hafnium zirconium oxide (HfZrO XWhen using a thin film deposition method (X is a real number greater than 0), it is preferable to form the film using an ALD method, particularly a thermal ALD method. It is also preferable to use an ALD method (including a thermal ALD method) that uses plasma to enhance reactivity (PEALD method: Plasma Enhanced ALD).

[0079] In addition, when using the thermal ALD method, it is preferable to use a material that does not contain hydrocarbons (also called Hydro Carbon, HC) as a precursor. Either or both of hydrogen and carbon contained in the film may inhibit crystallization. For this reason, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the film. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. In addition, when hafnium zirconium oxide is used, a chlorine-based precursor such as HfCl4 or ZrCl4 can be used as the precursor.

[0080] When an oxide such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide is used as the functional layer 118, the remanent polarization may be increased by adding an appropriate amount of carbon. In this case, for example, it is preferable to add these elements at a ratio of 0.5 at % or more and 10 at % or less.

[0081] Furthermore, when hafnium zirconium oxide is used for the functional layer 118, it is preferable to deposit films of hafnium and zirconium alternately in a 1:1 composition using a thermal ALD method or an ALD method using plasma.

[0082] The oxidizing agent used in the thermal ALD method or the ALD method using plasma may be H2O or O3. However, the oxidizing agent is not limited to this and may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0083] It is preferable that the hydrogen concentration in the film used for the functional layer 118 is low. This makes it possible to prevent hydrogen from diffusing from the functional layer 118 to the semiconductor layer 112, and to prevent the carrier concentration in the semiconductor layer 112 from increasing. Specifically, the hydrogen concentration in the film is 5×10 20 atoms / cm 3 Less than or equal to 1×10 is preferred 20 atoms / cm 3 The following is more preferred:

[0084] The crystal structure of the film used in the functional layer 118 is not particularly limited as long as it is a crystal structure that does not have centrosymmetrical and has polarity. For example, it may be a crystal system other than a cubic system. The film used in the functional layer 118 may be a single crystal structure, a polycrystalline structure, or a composite structure having an amorphous structure and a crystalline structure.

[0085] It is preferable to use a conductive material having a function of absorbing oxygen for one or both of the conductive layers 103 and 113 sandwiching the functional layer 118. This makes it possible to absorb oxygen from the functional layer 118 and increase the oxygen vacancy concentration in the functional layer 118. This makes it possible to increase the remnant polarization of the functional layer 118. It is preferable to use a metal or an alloy as the conductive material having a function of absorbing oxygen. In particular, it is preferable to use tungsten, molybdenum, titanium, tantalum, or the like. In particular, tungsten is preferable because it is easy to increase the remnant polarization of the functional layer 118 from the viewpoint of stress.

[0086] It is also preferable to use a conductive material that does not easily diffuse oxygen for one or both of the conductive layers 103 and 113 that sandwich the functional layer 118. This improves the withstand voltage of the functional layer 118, and improves the rewrite resistance of the ferroelectric capacitor. In particular, it is preferable to use a metal nitride such as titanium nitride or tantalum nitride.

[0087] The conductive layer 103 and the conductive layer 113 may have a stacked structure. In this case, it is preferable to use a low-resistance conductive material on the side not in contact with the functional layer 118. For example, a metal or alloy containing one or more selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like can be used. In particular, it is preferable to use a high-melting-point material such as tungsten, molybdenum, tantalum, ruthenium, or hafnium, because the temperature of the subsequent heat treatment can be increased. Note that, in addition to the above low-resistance conductive material, an oxide material such as indium tin oxide, indium tin oxide to which silicon is added, indium zinc oxide, or indium gallium zinc oxide may be used.

[0088] A layer exhibiting ferroelectricity used in the functional layer 118 is also called a "ferroelectric layer." One of the differences between a ferroelectric and a paraelectric is that the voltage-polarization characteristics have hysteresis. FIG. 4 is a graph showing an example of the voltage-polarization characteristics. In FIG. 4, the horizontal axis indicates the voltage applied to the ferroelectric layer, and the vertical axis indicates the polarization of the ferroelectric layer. The electric field strength can be calculated by dividing the voltage by the thickness of the ferroelectric layer.

[0089] The hysteresis characteristics of the ferroelectric layer can be represented by a curve 71 and a curve 72. The two voltages at the two intersections of the curve 71 and the curve 72 are called saturation polarization voltages (VSP, -VSP), respectively.

[0090] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 71. On the other hand, when a voltage equal to or more than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 72. Note that VSP may be called the "positive saturation polarization voltage" or the "first saturation polarization voltage," and -VSP may be called the "negative saturation polarization voltage" or the "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0091] Here, the voltage at which the polarization of the ferroelectric layer changes according to the curve 71 and becomes zero is called the coercive voltage Vc, and the voltage at which the polarization of the ferroelectric layer changes according to the curve 72 and becomes zero is called the coercive voltage -Vc. The values ​​of Vc and -Vc are between -VSP and VSP. The absolute values ​​of the two coercive voltages may be the same or different.

[0092] When a voltage exceeding the coercive voltage is applied to the ferroelectric layer, the polarization of the ferroelectric layer is easily reversed. In an FeFET, if you do not want to reverse the polarization of the ferroelectric layer, you can set the voltage applied between the gate and source (also called the "gate voltage" or "Vg") to be between -Vc and Vc. In order to control the on and off states of the FeFET without reversing the polarization of the ferroelectric layer, it is preferable to have a large absolute value for the coercive voltage.

[0093] The two polarizations when no voltage is applied to the ferroelectric layer (when the voltage is 0 V) ​​are called remnant polarization (Pr, -Pr). The larger the absolute value of the difference between Pr and -Pr (2Pr), the greater the fluctuation range of the threshold voltage in the FeFET due to polarization reversal, which is preferable.

[0094] Note that a charge storage layer may be used instead of a ferroelectric layer as the functional layer 118. For example, by using a stacked structure of a block layer, a charge storage layer, and a tunnel layer as the functional layer 118, it is possible to realize a transistor that functions as a memory cell that stores data by holding charges in the charge storage layer.

[0095] Such memory cells may be called by various names depending on the stacked structure from the control gate to the semiconductor. For example, if the control gate, block layer, charge storage layer, tunnel layer, and semiconductor layer are made of metal, oxide, nitride, oxide, and semiconductor, it is called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell.

[0096] Alternatively, the memory cell may be a SONOS (Silicon Oxide Nitride Oxide Semiconductor) type using n-type silicon or p-type silicon for the control gate, a TANOS (Tantalum nitride Aluminium oxide Nitride Oxide Semiconductor) type using tantalum nitride for the control gate and aluminum oxide for the block layer, or a THNOS (Tantalum nitride Hafnium oxide Nitride Oxide Semiconductor) type using tantalum nitride for the control gate and hafnium oxide for the block layer.

[0097] For example, a gate insulating layer of a transistor can have a stacked structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film from the semiconductor layer side, in which the silicon nitride film functions as a charge storage layer.

[0098] This concludes the explanation of the memory string.

[0099] Although one memory string has been described above, the memory capacity can be increased by periodically arranging multiple memory strings with a common control gate as shown in Fig. 1(A) etc. For example, memory strings can be arranged in a lattice pattern as shown in Fig. 5(A) or a houndstooth pattern as shown in Fig. 5(B). Figs. 5(A) and (B) are cross-sectional views corresponding to Fig. 3(A).

[0100] [Variations] In the following, an example of the configuration of a memory string that is partially different from the above will be described. Note that in the following, parts that overlap with the above will be referred to and will not be described.

[0101] [Variation 1] 6A and 6B show a memory string 100A having a back gate. The memory string 100A differs from the memory string 100 described above mainly in that the memory string 100A has a conductive layer 106 and an insulating layer 108.

[0102] The memory string 100A has a structural body 100A that has a conductive layer 106 located on the central axis, and an insulating layer 108, a semiconductor layer 112, and an insulating layer 111 are provided concentrically in this order around the conductive layer 106.

[0103] The conductive layer 106 functions as a back gate of the transistor Tr. The insulating layer 108 functions as a back gate insulating layer of the transistor Tr.

[0104] In FIG. 6B, the back gates of the transistors Tr (transistors Tr_1 to Tr_n) are electrically connected to the wiring SL through the wiring BGL. Note that the conductive layer 106 can function as the wiring BGL. That is, the potential of the wiring SL is applied to the back gates of the transistors Tr. This makes the threshold voltage of each transistor Tr more stable than when the transistors Tr do not have a back gate, thereby enabling more reliable write and erase operations.

[0105] [Modification 2] 7A and 7B show a memory string 100B in which the functional layer 118 also serves as a gate insulating layer of a transistor. The memory string 100B differs from the memory string 100 in that it does not have the insulating layer 111, the conductive layer 113, the insulating layer 114, etc.

[0106] The structure 110B of the collar string 100B includes an insulating layer 197, a semiconductor layer 112, and a functional layer 118. The conductive layer 103 is provided in a region surrounded by a pair of insulating layers 102, an insulating layer 121, and the functional layer 118. The semiconductor layer 112 has a portion provided opposite the conductive layer 103 with the functional layer 118 sandwiched therebetween.

[0107] The functional layer 118 also functions as a gate insulating layer for the transistor Tr. That is, the transistor Tr in the memory string 100B is a ferroelectric transistor that uses a dielectric for the gate insulating layer.

[0108] With this configuration, the manufacturing process can be simplified compared to the memory string 100.

[0109] [Modification 3] 8A and 8B show a memory string 100C in which a back gate is further provided in addition to the configuration of the memory string 100B.

[0110] The structure 110C of the memory string 100C has a conductive layer 106 that functions as a back gate and an insulating layer 108 that functions as a back gate insulating layer. For the description of these, refer to the above-mentioned first modification.

[0111] The above is a description of the modified example.

[0112] [Example of manufacturing method] As an example of a method for manufacturing a semiconductor device of one embodiment of the present invention, an example of a method for manufacturing the memory string 100A exemplified in the above-described Modification 1 will be described below.

[0113] 9(A), a laminate is formed by laminating an insulating layer 102 and a dummy layer 109. The i-th (i is an integer of 1 or more) insulating layer 102_i is disposed above a substrate (not shown), and the dummy layer 109_i is laminated above it.

[0114] The insulating layer 102 functions as an interlayer insulating layer. An inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride can be used as the insulating layer 102. The insulating layer 102 may have a stacked structure of a plurality of insulating layers, for example, a stacked structure of hafnium oxide and silicon oxynitride or a stacked structure of silicon oxide and silicon nitride.

[0115] The dummy layer 109 is a layer that will be removed later. The dummy layer 109 can be made of any material, regardless of its conductivity, so long as it can increase the etching rate selectivity with respect to the insulating layer 102. For example, any of an insulating film, a conductive film, and a semiconductor film can be used. In addition, it is preferable that the dummy layer 109 be made of a material that allows the portion sandwiched between the pair of insulating layers 102 to be reliably removed.

[0116] Next, a resist mask is formed on the laminate, and an opening is formed in the insulating layer 102 and the dummy layer 109 by etching using the resist mask as a mask. It is preferable to use an anisotropic dry etching process as the etching process, and to process the sidewall of the opening so as to be as vertical as possible. At this time, it is preferable that the shape of the opening is cylindrical.

[0117] The resist mask can be formed by, for example, lithography, printing, inkjet, or the like. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced in some cases. In addition, the etching process may be a dry etching method, a wet etching method, or both. Processing by the dry etching method is suitable for fine processing.

[0118] In the formation of a resist mask by lithography, a resist is first formed, and then the resist is exposed through a photomask. Next, the exposed or unexposed region is removed using a developer to form a resist mask.

[0119] By carrying out an etching process through the resist mask, a conductive layer, a semiconductor layer, an insulating layer, or the like can be processed into a desired shape. For example, KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like can be used for exposure. A liquid immersion technique may also be used. Moreover, it is preferable to use a beam such as an electron beam or an ion beam instead of the above-mentioned light, since a photomask is not required. The resist mask can be removed by a wet etching process, a dry etching process, or both.

[0120] Alternatively, a hard mask made of an inorganic material may be used instead of a resist mask. In the case of using a hard mask, a film serving as a hard mask material is formed on a layer to be processed, a resist mask is formed thereon, and the film is etched to form a hard mask having a desired shape.

[0121] As the dry etching device, for example, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes or an inductively coupled plasma (ICP) etching device can be used.

[0122] Next, the opening formed above is filled with a dummy layer 115. The dummy layer 115 can be formed by forming the dummy layer 115 so as to fill the entire opening using a film forming method with high step coverage, and then performing a planarization process such as chemical mechanical polishing (CMP) until the insulating layer 102 located on the uppermost surface is exposed.

[0123] The dummy layer 115 is a layer that will be removed later, similar to the dummy layer 109. The dummy layer 115 may be made of any material that can increase the etching rate selectivity with respect to the dummy layer 109 and the insulating layer 102.

[0124] Next, a part of the laminate is removed by etching to process the laminate into a strip shape in a plan view. The shape at this stage becomes the contour shape of the conductive layer 103 that will become the control gate. At this stage, the side surfaces of the insulating layer 102 and the side surfaces of the dummy layer 109 are exposed.

[0125] Next, the dummy layer 109 is removed by etching (FIG. 10(A)). The etching of the dummy layer 109 can be performed by an isotropic dry etching process or a wet etching process. At this time, it is important to perform the etching under conditions in which the etching rate of the dummy layer 109 is sufficiently higher than that of the dummy layer 115 and the insulating layer 102. As a result, the upper surface, lower surface and side surface of the insulating layer 102 are exposed. Furthermore, the dummy layer 109 is removed, and a recess 116 is formed that is surrounded by the upper surface of the insulating layer 102, the lower surface of the insulating layer 102 located thereon, and the side surface of the dummy layer 115.

[0126] Next, an insulating film 114f that will later become the insulating layer 114, a functional film 118f that will later become the functional layer 118, and a conductive film 103f that will later become the conductive layer 103 are formed in this order (FIG. 10(B)).

[0127] The insulating film 114f and the functional film 118f are preferably formed using a film formation method with high coverage so that they are formed along the recess 116 located between the pair of insulating layers 102. Furthermore, the conductive film 103f is preferably formed so as to fill the recess. For example, the insulating film 114f and the functional film 118f can be formed by the ALD method, and the conductive film 103f can be formed by the thermal CVD method.

[0128] A part of the insulating film 114f functions as a dummy layer for creating a recess for later forming the conductive layer 113. The insulating film 114f can be made of an insulating material that can increase the etching rate selectivity with respect to the functional layer 118 and the insulating layer 102.

[0129] When forming a hafnium zirconium oxide film as the functional film 118f by the ALD method, a precursor containing hafnium, a precursor containing zirconium, and an oxidizing agent can be used. As the precursor containing hafnium, tetrakis(ethylmethylamido)hafnium (TEMAHf), HfCl4, etc. can be used. As the precursor containing zirconium, tetrakis(ethylmethylamido)zirconium (TEMAZr), ZrCl4, etc. can be used. As the oxidizing agent, any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2 can be used.

[0130] In addition, it is preferable to use an oxide containing a Group 3 element such as scandium, yttrium, or lanthanum in addition to hafnium zirconium oxide for the functional film 118f. By adding such an element to hafnium zirconium oxide, it is expected that the rewrite endurance of the ferroelectric capacitor can be improved.

[0131] As a precursor containing a Group 3 element such as scandium, yttrium, or lanthanum, an inorganic compound or an organic compound containing the target element can be used. The precursor may be liquid or solid at room temperature and pressure. For example, as a precursor containing yttrium, yttrium compounds such as tris(methylcyclopentadienyl)yttrium(III) (Y(MeCp)3), tris(isopropylcyclopentadienyl)yttrium(III) (Y(iPrCp)3), and tris[N,N-bis(trimethylsilyl)amido]yttrium(III) (Y(tmsa)3) can be mentioned. On the other hand, precursors containing lanthanum include lanthanum compounds such as tris(cyclopentadienyl)lanthanum(III) (La(Cp)3), tris(methylcyclopentadienyl)lanthanum(III) (La(MeCp)3), and tris(isopropylcyclopentadienyl)lanthanum(III) (La(iPrCp)3).

[0132] It is preferable that the conductive film 103f be formed without any gap so as to fill the gap between the pair of insulating layers 102, because this can prevent a space from being formed between the conductive layer 103 and the insulating layer 102 later.

[0133] Next, the conductive film 103f, the functional film 118f, and the insulating film 114f are anisotropically etched to remove the portions provided along the side surfaces of the insulating layer 102. This makes it possible to form the conductive layer 103, the functional layer 118, and the insulating layer 114 provided between the pair of insulating layers 102. Note that in this process, it is sufficient to separate at least the multiple conductive layers 103 stacked in the Z direction, and it is not necessary to etch the functional film 118f and the insulating layer 114. In that case, the insulating layer 114, or the functional layer 118 and the insulating layer 114 may be continuous in the Z direction without being separated.

[0134] Subsequently, the insulating layer 121 is formed so as to cover the side surfaces of the conductive layer 103 and the insulating layer 102. The insulating layer 121 may be provided so as to fill the outer portion of the laminate. When at least one of the functional film 118f and the insulating film 114f is not separated by etching, the functional layer 118 or the insulating layer 114 is located between the insulating layer 121 and the insulating layer 102.

[0135] The insulating layer 121 can be formed using a material similar to that of the insulating layer 102 .

[0136] Next, the dummy layer 115 is removed by etching (FIG. 11(A)). At this time, it is important that the dummy layer 115 is etched under conditions that provide a sufficiently high etching rate with respect to the insulating layer 102.

[0137] Next, a part of the insulating layer 114 is removed by etching to expose the functional layer 118. At this time, if the entire insulating layer 114 is etched, it is not preferable because the conductive layer 113 to be formed later cannot be separated between the memory cells. Therefore, it is important that the etching process of the insulating layer 114 is performed so that at least the part of the insulating layer 114 that is in contact with the insulating layer 121 remains. Therefore, it is preferable to use isotropic dry etching for etching the insulating layer 114 because the etching rate can be easily controlled compared to the case of using a wet etching method.

[0138] Etching the insulating layer 114 forms a so-called recess in which the surface of the functional layer 118 is recessed below the surface of the insulating layer 102. Note that only a portion of the insulating layer 114 along the central axis 120 is etched here. Note that a portion of the insulating layer 114 sandwiched between the functional layer 118 and the insulating layer 102 may also be etched.

[0139] Next, a conductive film 113f, which will later become the conductive layer 113, is formed to cover the exposed surface of the functional layer 118 and the side surface of the insulating layer 102 (FIG. 11(B)). The conductive film 113f is preferably formed by a film forming method with high coverage such as an ALD method or a thermal CVD method. At this time, the conductive film 113f is formed so that a part of it covers the recessed portion described above.

[0140] Next, the portion of the conductive film 113f in contact with the insulating layer 102 is removed by etching to form the conductive layer 113 in contact with the functional layer 118. In this step, it is important to separate the multiple conductive layers 113 stacked in the Z direction.

[0141] Here, it is preferable to perform a heat treatment after the formation of the functional layer 118 and before the subsequent formation of the semiconductor layer 112. The heat treatment crystallizes the functional layer 118, causing the functional layer 118 to exhibit ferroelectricity. A higher temperature for the heat treatment is preferable because it promotes crystallization and increases remnant polarization.

[0142] The heat treatment for crystallizing the functional layer 118 is preferably performed in a state in which the functional layer 118 is in contact with the conductive layer 103 (or the conductive film 103f) or in a state in which the functional layer 118 is in contact with both the conductive layer 103 and the conductive layer 113 (or the conductive film 113f). This makes it easier for the functional layer 118 to have a crystal structure that exhibits ferroelectricity, compared to a case in which the heat treatment is performed in a state in which the functional layer 118 is not in contact with a conductive layer or a conductive film. In particular, performing the heat treatment in a state in which the functional layer 118 is sandwiched between a pair of conductive layers is preferable because it exhibits large remanent polarization.

[0143] For example, a rapid thermal annealing (RTA) device, a resistance heating furnace, or a microwave heating device can be used for the heat treatment. In particular, the use of an RTA device is preferable because it is possible to apply a high temperature in a short time, thereby enhancing the ferroelectricity of the functional layer 118, shortening the process time, and reducing thermal damage to layers other than the functional layer 118. The heat treatment is preferably performed in an inert gas or reducing gas atmosphere, since oxidation of the electrodes can be suppressed. Examples of the inert gas that can be used include noble gases such as helium, argon, and neon, and nitrogen gas. Examples of the reducing gas that can be used include hydrogen gas, carbon monoxide gas, and hydrocarbon gas.

[0144] In particular, when an oxide such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide is used for the functional layer 118, the crystal structure exhibiting ferroelectricity is not a stable structure (stable phase) but is classified as a metastable phase that is expressed at relatively high temperatures. Therefore, by heating at high temperatures using the RTA method and then rapidly cooling, the metastable phase in the film is maintained, and a functional layer 118 containing a large amount of crystal structures exhibiting ferroelectricity can be formed.

[0145] As the RTA device, an LRTA (Lamp Rapid Thermal Anneal) device, a GRTA (Gas Rapid Thermal Anneal) device, etc. can be used. The LRTA device is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0146] When the RTA method is used for the heat treatment, the treatment temperature can be 300° C. to 750° C., preferably 400° C. to 700° C., and more preferably 500° C. to 650° C. The treatment time can be 1 second to 10 minutes, preferably 3 seconds to 5 minutes, and more preferably 5 seconds to 1 minute. When the heat treatment is performed using a device other than an RTA device such as a resistance heating furnace, the treatment time excluding the temperature rise period and the temperature fall period can be 1 minute to 5 hours, and preferably 1 minute to 2 hours.

[0147] Next, an insulating layer 111 is formed in contact with the surface of the insulating layer 102 and the surface of the conductive layer 113 in the opening, and then a semiconductor layer 112 is formed (FIG. 12(A)).

[0148] The insulating layer 111 is preferably formed by, for example, a CVD method or an ALD method. In particular, it is preferable to use the ALD method to laminate a plurality of different insulating films.

[0149] For example, the insulating layer 111 is preferably an insulating film having a barrier property against oxygen. Furthermore, the insulating layer 111 is preferably an insulating film having a function of trapping or fixing hydrogen. By providing such an insulating film, oxidation of the conductive layer 113 in contact with the insulating layer 111 can be suppressed. Furthermore, hydrogen contained in the semiconductor layer 112 and its vicinity can be trapped or fixed to the insulating layer 111. As a result, the hydrogen concentration in the semiconductor layer 112 can be reduced, and the reliability of the transistor can be improved.

[0150] For example, a laminated film of an aluminum oxide film and a hafnium oxide film can be used for the insulating layer 111. Since aluminum oxide and hafnium oxide are high dielectric constant (high-k) materials, using these for the gate insulating layer makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. In other words, it becomes possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0151] A silicon oxide film, a silicon oxynitride film, or the like having high withstand voltage is preferably used for the insulating layer 111. This can reduce leakage current of the transistor.

[0152] An insulating film having a barrier property against hydrogen may be provided on the side of the insulating layer 111 in contact with the semiconductor layer 112. This can suppress diffusion of impurities such as hydrogen contained in the conductive layer 113 to the semiconductor layer 112. Examples of insulating films having a barrier property against hydrogen include a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. In particular, a silicon nitride film is preferable because of its high barrier property against hydrogen. Furthermore, such an insulating film has a barrier property against oxygen in addition to hydrogen, and can block oxygen diffusing from the semiconductor layer 112 to the conductive layer 113, thereby preventing the conductive layer 113 from being oxidized.

[0153] When the insulating layer 111 is a stacked film of a plurality of insulating films, the thickness of each film is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and further preferably 0.5 nm to 10 nm. For example, a stacked film of aluminum oxide having a thickness of 1 nm, a silicon oxide film having a thickness of 2 nm, and a hafnium oxide film having a thickness of 2 nm can be used from the semiconductor layer 112 side. Alternatively, in addition to this, a stacked film in which a silicon nitride film having a thickness of 1 nm is stacked on the conductive layer 113 side may be used. However, the thickness is not limited to the above, and for example, a configuration in which the thickness of any one or more of the films is 15 nm or more may be used.

[0154] The semiconductor layer 112 is preferably formed by ALD. In particular, it is preferable to use a thermal ALD method or a PEALD method. However, the method is not limited thereto, and a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, a molecular beam epitaxy (MBE) method, or the like may be used.

[0155] The crystallinity of the semiconductor material used for the semiconductor layer 112 is not particularly limited, and any of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0156] The semiconductor layer 112 preferably has a crystalline metal oxide layer. Examples of the structure of the crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystal (Poly-crystal) structure, and a nanocrystal (nc) structure. By using a crystalline metal oxide layer for the semiconductor layer 112, the density of defect states in the semiconductor layer 112 can be reduced, and a highly reliable semiconductor device can be realized. Note that the CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of IGZO microcrystals) have a c-axis alignment and are connected without being oriented in the ab plane. In addition, when a cross section of an OS film having a CAAC structure is observed using a high-resolution TEM image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal portion. Therefore, the OS film having a CAAC structure can be said to have a structure having a layered crystal portion.

[0157] The polycrystalline structure has crystal grain boundaries. When a heat treatment is performed after forming an oxide semiconductor layer having a polycrystalline structure, a minute gap (also referred to as a nanocrack or a microcrack) or a minute space (also referred to as a nanospace or a microspace) may be formed between crystal parts. When a minute gap or a minute space is formed in the oxide semiconductor layer, the electric resistance of the oxide semiconductor layer increases. This is because the electric resistance of the minute gap or minute space is very high, for example, infinite. When an oxide semiconductor layer having a minute gap or minute space is used for a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. Since no clear crystal grain boundary (grain boundary) is confirmed in the ab plane in the CAAC structure, a semiconductor device having higher reliability than that of a polycrystalline structure can be realized.

[0158] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 112, the more the density of defect states in the semiconductor layer 112 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0159] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer that can be formed. Also, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during the formation (hereinafter, also referred to as oxygen flow rate ratio), the higher the crystallinity of the metal oxide layer that can be formed.

[0160] The semiconductor layer 112 can have a stacked structure of two or more metal oxide layers with different crystallinity. In this case, the two or more metal oxide layers may have different compositions or may have the same or approximately the same composition. For example, when the semiconductor layer 112 has a two-layer structure, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, so that the crystallinity of the second metal oxide layer can be increased in some cases. Furthermore, by performing heat treatment (also referred to as crystallization treatment) after the second metal oxide layer is formed, the crystallinity of the first layer can be increased.

[0161] For example, a first metal oxide layer is formed by ALD, and a second metal oxide layer is formed by sputtering to have a higher crystallinity than the first layer. Then, a heat treatment is performed to improve the crystallinity of the first and second metal oxide layers. At this time, the crystals in the second layer grow continuously vertically toward the first layer, and the boundary between the first and second layers may not be recognized by cross-sectional observation.

[0162] Alternatively, a three-layer structure may be formed by forming a third metal oxide layer on the second metal oxide layer using the ALD method. After the formation of the third metal oxide layer, a heat treatment can be performed to improve the crystallinity of the first to third metal oxide layers. In this case, the crystals contained in the second layer grow continuously in the vertical direction toward the first and third layers, and then grow laterally as well, so that the boundary between the first and second layers and the boundary between the second and third layers may not be recognized by cross-sectional observation.

[0163] In this way, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, crystal growth occurs continuously between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the entire film thickness. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, crystal growth occurs continuously between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the entire film thickness direction. This makes it possible to realize a highly reliable transistor.

[0164] For example, if a first metal oxide layer is formed using the ALD method, a second metal oxide layer is formed using a film with a CAAC structure by sputtering, and a third metal oxide layer is formed using the ALD method to form a three-layer structure, the second CAAC structure can be used as a nucleus or seed to enhance the crystallinity of the upper and lower metal oxide layers. A metal oxide layer with enhanced crystallinity in this way can be called Axial Growth CAAC (AG CAAC).

[0165] The heat treatment is preferably carried out at a temperature of 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. The treatment time is preferably, for example, 1 minute to 1 hour, or 10 minutes to 30 minutes, at a temperature of 350° C. to 550° C.

[0166] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace, an RTA device such as an LRTA device, or a GRTA device may be used.

[0167] Next, an insulating layer 108 and a conductive layer 106 are sequentially filled into the opening, and the portion of the conductive layer 106 located at the top of the stack is processed into a desired shape, thereby fabricating a memory string (Figure 12(B)).

[0168] For the insulating layer 108, the description of the insulating layer 111 can be referred to. The conductive layer 106 can be formed by a method similar to that for the conductive layer 103 or the conductive layer 113.

[0169] The above is a description of the example of the manufacturing method.

[0170] [Storage device configuration example] Next, a configuration example of a storage device in which the above-mentioned memory string can be used will be described.

[0171] 13 is a block diagram showing a configuration example of the circuit OSC and the memory cell unit MCL. The memory cell unit MCL is a circuit including the above-mentioned memory cells and memory strings.

[0172] The memory cell unit MCL has a memory cell array MCA. The memory cell array MCA has a plurality of strings SRG. The strings SRG are electrically connected to the wiring BL. The strings SRG have a plurality of transistors CTr electrically connected in series, and a selection transistor BTr and a transistor STr. Note that one transistor CTr functions as a cell transistor and is included in a memory cell MC of the string SRG.

[0173] The cell transistor is a transistor that operates with normally-on characteristics and has a control gate and a functional layer. The functional layer can be a ferroelectric layer or a charge storage layer. The configuration in which a ferroelectric layer is used as the functional layer can be the above-mentioned configuration in which a ferroelectric capacitor is connected to the gate or the configuration in which a ferroelectric is used for the gate insulating layer.

[0174] On the other hand, when a charge storage layer is used as the functional layer, it is provided in a region overlapping the channel formation region via a tunnel insulating film. A control gate is provided in a region overlapping the charge storage layer via a blocking film. A tunnel current is generated by applying a write potential to the control gate and a predetermined potential to either the first terminal or the second terminal of the cell transistor, and electrons are injected from the channel formation region of the cell transistor to the charge storage layer. As a result, the threshold voltage of the cell transistor in which electrons are injected into the charge storage layer becomes high. A floating gate may be used instead of the charge storage layer.

[0175] The channel formation regions of the transistors BTr, CTr, and STr preferably include, for example, one of silicon, germanium, gallium arsenide, silicon carbide (SiC), metal oxide, and the like, or a plurality of materials selected from the above.

[0176] In particular, it is preferable to use an oxide of one or more metals selected from indium, element M (element M is, for example, one or more elements selected from aluminum, gallium, yttrium, and tin), and zinc in the channel formation region. The metal oxide can be used as a wide-gap semiconductor, and can impart a characteristic of extremely small off-state current to the transistors BTr, CTr, and STr in which the metal oxide is included in the channel formation region. In other words, the leakage current in the transistors BTr, CTr, and STr in the off state can be reduced, which may reduce the power consumption of the storage device.

[0177] In addition, in FIG. 13, an example is shown in which the transistors BTr and STr are formed in the memory cell unit MCL, but the transistors BTr and STr may be formed in the circuit OSC.

[0178] The memory cell array MCA has a plurality of memory cells MC in the string SRG. The plurality of memory cells MC are arranged in a matrix. The memory cell array MCA has m memory cells MC in each column and n memory cells MC in each row, totaling m×n memory cells MC (m and n are integers of 2 or more). A memory cell MC located in the i-th row and j-th column (i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less) is represented as MC[i,j].

[0179] The wirings WL are a plurality of word lines, each of which is electrically connected to a memory cell MC for each row, the wirings BL are a plurality of bit lines, each of which is electrically connected to a memory cell MC for each column, and the wirings CL are power supply lines.

[0180] Next, a connection configuration of the string SRG will be described. A transistor BTr, a plurality of transistors CTr, and a transistor STr are connected in series, and the transistor BTr is electrically connected to a wiring BL, and the transistor STr is electrically connected to a wiring BL.

[0181] The wiring BSL and the wiring SSL function as wirings for selecting a string when performing operations such as writing, reading, erasing, etc. The wiring BSL is electrically connected to the gate of the transistor BTr, and the wiring SSL is electrically connected to the gate of the transistor STr.

[0182] Although one string SRG is electrically connected to one wiring BL in this embodiment, one embodiment of the present invention is not limited to this. For example, as shown in Fig. 14, the memory cell portion MCL may have a configuration in which a plurality of strings SRG are electrically connected to one wiring BL. Note that the block diagram in Fig. 14 illustrates only the memory cell portion MCL and a part of the circuit OSC.

[0183] The circuit OSC includes a control circuit CTR, a circuit PRPH, and an output circuit OUTP. The control circuit CTR receives, for example, control signals CS (such as a clock signal, a chip enable signal, a write enable signal, and an address signal) and a data signal WDATA from outside the memory device.

[0184] The control circuit CTR has a function of accessing the circuit PRPH to write data to the memory cell unit MCL and a function of reading data from the memory cell unit MCL. For example, when a write command and a data signal WDATA are input by a control signal CS from outside the memory device, the control circuit CTR writes the data signal WDATA to the memory cell unit MCL. In addition, in response to a read command by the control signal CS, the control circuit CTR reads data from the memory cell unit MCL and outputs it as a data signal RDATA. Note that the write command and read command include an address signal.

[0185] Furthermore, the control circuit CTR may have a function of performing error detection and correction (also called ECC: Error Check and Correct) when data is read from the memory cell unit MCL.

[0186] The circuit PRPH includes, for example, a circuit WLD, a circuit BLD, and a circuit CVC. The circuit WLD functions as a word line driver circuit and is electrically connected to the wiring WL. The circuit BLD functions as a bit line driver circuit and is electrically connected to the wiring BL. The circuit CVC functions as a power supply that generates a constant potential and outputs the constant potential and is electrically connected to the wiring CL. The circuit CVC may not be included in the circuit PRPH and may be provided outside the memory device. In this case, the memory device is configured such that a constant potential is applied to the memory cell unit MCL from outside.

[0187] The above is a description of an example of the configuration of the storage device.

[0188] [Example of the configuration of the computing device] An example of the configuration of a processor to which the above-mentioned storage device can be applied will be described below.

[0189] 15A shows a block diagram of a processing device 1100. In FIG 15A, an example of the configuration of a CPU is shown as an example of the configuration that can be used for the processing device 1100.

[0190] The arithmetic processing device 1100 shown in FIG. 15(A) has an ALU 1191 (ALU: arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189 on a substrate 1190. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may be provided on separate chips.

[0191] The cache 1199 is connected to a main memory provided on a separate chip via a cache interface 1189. The cache interface 1189 has a function of supplying a portion of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding that data.

[0192] The arithmetic processing device 1100 shown in Fig. 15(A) is merely one example showing a simplified configuration, and the actual arithmetic processing device 1100 has a wide variety of configurations depending on its application. For example, the arithmetic processing device 1100 shown in Fig. 15 or a configuration including an arithmetic circuit may be one core, and a configuration including multiple such cores and each core may operate in parallel, that is, a configuration like a GPU. In addition, the number of bits that the arithmetic processing device 1100 can handle in the internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0193] An instruction input to the processor 1100 via the bus interface 1198 is input to an instruction decoder 1193 , decoded, and then input to an ALU controller 1192 , an interrupt controller 1194 , a register controller 1197 , and a timing controller 1195 .

[0194] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority or mask state while the arithmetic processing device 1100 is executing a program. The register controller 1197 generates an address for the register 1196, and reads or writes data from the register 1196 depending on the state of the arithmetic processing device 1100.

[0195] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0196] In the processor 1100 shown in FIG. 15A, a register 1196 and a cache 1199 are provided with a storage device.

[0197] In the arithmetic processing device 1100 shown in FIG. 15A, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is to be held by a flip-flop or by a capacitive element in the memory cell of the register 1196. When holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When holding data in a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cell in the register 1196 can be stopped.

[0198] The arithmetic processing device 1100 is not limited to a CPU, but may be a GPU, a DSP (Digital Signal Processor), an FPGA (Field-Programmable Gate Array), or the like.

[0199] The semiconductor device 1000 having the memory device exemplified above and the arithmetic processing device 1100 can be provided overlapping each other. Fig. 15(B) and (C) show perspective views of the semiconductor device 1150A. The semiconductor device 1150A has the semiconductor device 1000 functioning as a memory device on the arithmetic processing device 1100. The arithmetic processing device 1100 and the semiconductor device 1000 have overlapping regions. In order to make the configuration of the semiconductor device 1150A easier to understand, Fig. 15(C) shows the arithmetic processing device 1100 and the semiconductor device 1000 separated from each other.

[0200] By stacking the semiconductor device 1000 and the arithmetic processing device 1100, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance allows for reduced power consumption.

[0201] Moreover, a plurality of semiconductor devices 1000 may be provided overlapping the arithmetic processing device 1100. FIGS. 16(A) and (B) show perspective views of a semiconductor device 1150B. The semiconductor device 1150B has a semiconductor device 1000a and a semiconductor device 1000b on the arithmetic processing device 1100. The arithmetic processing device 1100, the semiconductor device 1000a, and the semiconductor device 1000b have overlapping regions. In order to make the configuration of the semiconductor device 1150B easier to understand, the arithmetic processing device 1100, the semiconductor device 1000a, and the semiconductor device 1000b are shown separately in FIG. 16(B).

[0202] The semiconductor device 1000a and the semiconductor device 1000b function as storage devices. For example, a NOR type storage device may be used for one of the semiconductor device 1000a or the semiconductor device 1000b, and a NAND type storage device may be used for the other. Both the semiconductor device 1000a and the semiconductor device 1000b may be NAND type storage devices. Examples of NOR type storage devices include DRAM and SRAM. Since a NOR type storage device can operate faster than a NAND type storage device, for example, a part of the semiconductor device 1000a can be used as a main memory and / or a cache 1199. The semiconductor device 1000a and the semiconductor device 1000b may be stacked in the reverse order.

[0203] 16C and 16D are perspective views of a semiconductor device 1150C. The semiconductor device 1150C has a configuration in which a processor 1100 is sandwiched between a semiconductor device 1000a and a semiconductor device 1000b.

[0204] The configuration of the semiconductor device 1150C can increase the communication speed between the semiconductor device 1000a and the arithmetic processing device 1100 and the communication speed between the semiconductor device 1000b and the arithmetic processing device 1100. In addition, the power consumption can be reduced more than that of the semiconductor device 1150B.

[0205] Next, a cross-sectional configuration example of the semiconductor device will be described.

[0206] 17 shows an example in which a layer 11 including a transistor 300 and a layer 12 including a plurality of memory strings are stacked. A circuit using a single crystal silicon substrate as a substrate can be applied as the layer 11, and a memory device having a three-dimensional NAND type memory can be applied as the layer 12. For example, the layer 11 is the arithmetic processing device 1100 exemplified above, and the layer 12 is the semiconductor device 1000 that functions as a memory device.

[0207] Each memory string provided in the layer 12 includes a transistor 141, a plurality of transistors 142, and a transistor 143. Note that a detailed description of the configuration of the layer 12 that can be referred to the memory string 100 illustrated in FIG. 2A and the like will be omitted, and only differences will be described.

[0208] <Layer 11> The transistor 300 in the layer 11 is provided over a substrate 311 and includes a conductive layer 316, an insulating layer 315, a semiconductor region 313 formed of part of the substrate 311, and a low-resistance region 314a functioning as a source region or a drain region, and a low-resistance region 314b. FIG. 17 shows a cross section of the transistor 300 in the channel length direction.

[0209] The transistor 300 is preferably a so-called fin-type transistor in which the top surface and the side surface in the channel width direction of the semiconductor region 313 are covered with the conductive layer 316 via the insulating layer 315 in a cross section in the channel width direction. This increases the effective channel width, improving the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, improving the off-characteristics of the transistor 300.

[0210] The transistor 300 may be either a p-channel type or an n-channel type.

[0211] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaN (gallium nitride), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0212] Low resistance region 314a and low resistance region 314b contain, in addition to the semiconductor material applied to semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0213] The conductive layer 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0214] Since the work function is determined by the material of the conductor, the threshold voltage (Vth) of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as the conductor in a laminated layer, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0215] Note that the transistor 300 illustrated in FIG. 17 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0216] An insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order to cover the transistor 300.

[0217] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used for the insulating layers 320, 322, 324, and 326.

[0218] The insulating layer 322 may function as a planarizing film that planarizes steps caused by the transistor 300 provided thereunder. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like in order to improve the planarity.

[0219] The insulating layer 324 is preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or the transistor 300 to a region where the transistor 141 and the like are provided.

[0220] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 141, the characteristics of the semiconductor element may deteriorate. Therefore, a film that suppresses the diffusion of hydrogen is preferably used between the transistor 141 or the like and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film from which the amount of hydrogen desorbed is small.

[0221] The amount of desorption of hydrogen can be analyzed, for example, by using a thermal desorption spectroscopy (TDS) analysis method. For example, the amount of desorption of hydrogen from the insulating layer 324 is calculated as 10×10 per area of ​​the insulating layer 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in a TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0222] It is preferable that insulating layer 326 has a lower dielectric constant than insulating layer 324. For example, the relative dielectric constant of insulating layer 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of insulating layer 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of insulating layer 324. By using a material with a low relative dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance generated between wirings.

[0223] Conductive layers 328 and 330 are embedded in insulating layers 320, 322, 324, and 326. Conductive layers 328 and 330 function as plugs or wiring. A plurality of structures of conductors functioning as plugs or wiring may be collectively given the same reference numeral. In this specification, the wiring and the plug connected to the wiring may be integral. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0224] As the material of each plug and wiring (conductive layer 328, conductive layer 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0225] 17, a wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, it is preferable to provide an insulator having a barrier property against hydrogen, similar to the insulating layer 324, over the insulating layer 326 and the conductive layer 330, and to form a conductor having a barrier property against hydrogen in the insulator. By forming a conductor having a barrier property against hydrogen in an opening of the insulator having a barrier property against hydrogen, the transistor 300 and the transistor 141, etc. can be separated by the barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 141, etc. can be suppressed.

[0226] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Furthermore, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity as a wiring. In this case, a structure in which a tantalum nitride layer having a barrier property against hydrogen is in contact with an insulator having a barrier property against hydrogen is preferable. Note that in FIG. 17, an insulating layer 350 having a barrier property against hydrogen is provided over the insulating layer 326 and the conductive layer 330.

[0227] <Layer 12> The layer 12 includes a conductive layer 125, a plurality of conductive layers 103, a conductive layer 126, a conductive layer 127, an insulating layer 111, a semiconductor layer 112, a conductive layer 113, a functional layer 118, a conductive layer 101, a conductive layer 104, and the like.

[0228] The transistor 142 and the transistor 143 function as selection transistors. The conductive layer 126 functions as a gate of the transistor 142, and the conductive layer 127 functions as a gate of the transistor 143. The transistor 142 and the transistor 143 do not include the conductive layer 113, the insulating layer 114, the functional layer 118, or the like, and the conductive layer 126 or the conductive layer 127 is in contact with the insulating layer 111.

[0229] The transistors 142 and 143 can be manufactured, for example, in the above-described manufacturing method example, by forming a conductive film to be the conductive layer 126 or the conductive layer 127 using a conductive material that is not removed by etching the dummy layer 109 instead of the dummy layer 109.

[0230] An insulating layer 105 is provided on the conductive layer 104, and an insulating layer 384 is provided on the insulating layer 105. A conductive layer 386 reaching the conductive layer 104 is provided on the insulating layer 105 and the insulating layer 384. The conductive layer 386 functions as a plug.

[0231] The conductive layer 125 may be made of a material containing one or more metal elements selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like. A semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may also be used. A conductive material containing a metal element such as titanium or tantalum and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. For example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon has been added, or the like may also be used. For example, indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen or water mixed in from a surrounding insulator or the like may be captured in some cases.

[0232] There is no particular limitation on the method for forming the conductive layer 125. For example, the conductive layer 125 can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), a MBE (Molecular Beam Epitaxy) method, an ALD (Atomic Layer Deposition) method, a PLD (Pulsed Laser Deposition) method, etc.

[0233] It is preferable to use a material with a low dielectric constant for the insulating layer 102. This can reduce the capacitance between the conductive layer 126 and the conductive layer 103, between the conductive layers 103, or between the conductive layer 103 and the conductive layer 127, thereby improving the driving speed of the semiconductor device.

[0234] For example, a material containing silicon oxide or silicon oxynitride can be used as the insulating layer 102. Also, for example, an insulator containing a material selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. can be used in a single layer or a multilayer. The insulating layer 102 can be formed by a film formation method such as a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, etc.

[0235] The conductive layer 126 and the conductive layer 127 can be formed using a material similar to that of the conductive layer 125. The conductive layer 101 and the conductive layer 104 can be formed using a material similar to that of the conductive layer 125.

[0236] In addition, when silicon is used for the semiconductor layer 112, it is preferable that the conductive layer 101 and the conductive layer 104 are silicon in which impurities are diffused. As the impurity, an n-type impurity (donor) can be used. As the n-type impurity, for example, phosphorus, arsenic, etc. can be used. Also, as the impurity, a p-type impurity (acceptor) can be used. As the p-type impurity, for example, boron, aluminum, gallium, etc. can be used. Also, as the silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc. can be used. By using silicon containing such impurities, when the semiconductor layer 112 is crystallized using a catalytic element such as nickel, the conductive layer 101 or the conductive layer 104 can be used as a gettering layer that absorbs the catalytic element. Also, as the conductive layer 101 and the conductive layer 104, other than silicon, a metal oxide with a high carrier density may be applied in some cases. Also, a compound semiconductor such as Ge, ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. may be applied in some cases.

[0237] The materials used for the conductive layer 101 and the conductive layer 104 are preferably similar to those used for the semiconductor layer 112. That is, when silicon is used for the semiconductor layer 112, silicon is preferably used for the conductive layer 101 and the conductive layer 104. When a metal oxide is used for the semiconductor layer 112, a conductive metal oxide is preferably used for the conductive layer 101 and the conductive layer 104. In this case, the carrier density of the conductive layer 101 and the conductive layer 104 is preferably higher than that of the semiconductor layer 112.

[0238] Silicon can be used as the semiconductor layer 112. In this case, the silicon can be, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon. Metal oxides other than silicon can also be used as the semiconductor layer 112. Compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe can also be used in some cases.

[0239] Examples of metal oxides that can be used in the semiconductor layer 112 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M of the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, and is more preferably Ga.

[0240] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, or compositions close to these. The term "close composition" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in a metal oxide, the on-state current, field-effect mobility, or the like of a transistor can be increased.

[0241] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0242] The semiconductor layer 112 may be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, or the like. Ga-Zn oxide may also be used. A material that does not contain Zn, such as indium oxide, is preferred because it enhances the affinity with the LSI manufacturing process. On the other hand, a material that contains Zn is preferred because it is easy to increase the crystallinity.

[0243] In particular, it is preferable to use In-Zn oxides in which the atomic ratio of metal elements is In:Zn=4:1, In:Zn=2:1 or close thereto, or In-Sn-Zn oxides in which the atomic ratio of metal elements is In:Sn:Zn=4:0.1:1, In:Sn:Zn=2:0.1:1 or close thereto, since this can suitably increase the field-effect mobility of the transistor.

[0244] In addition to or in addition to indium, the metal oxide may have one or more metal elements having a large period number in the periodic table. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element having a large period number, the field effect mobility of the transistor may be increased. Examples of metal elements having a large period number include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specific examples of the metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0245] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field-effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0246] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by ALD, which has excellent coverage. When the metal oxide is formed by sputtering, the composition of the metal oxide film may differ from the composition of the target. In particular, the content of zinc in the metal oxide film may decrease to about 50% of that of the target.

[0247] In this specification, the content of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, X , A Y , A Z Then, the content of metal element X is A X / (A X +A Y +A Z In addition, the ratio of the number of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic ratio) is B X :B Y :B Z When the metal element X is expressed as B X / (B X +B Y +B Z ) can be shown as

[0248] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0249] By using a metal oxide that does not contain Ga or has a low Ga content for the semiconductor layer 112, a transistor with high reliability against application of a positive bias can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test can be obtained. When a metal oxide that contains Ga is used, it is preferable to set the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0250] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. In other words, a transistor with a small variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0251] In addition, by increasing the Zn content, the metal oxide becomes highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0252] The semiconductor layer 112 may have a stacked structure having two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 112 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used to form the semiconductor layer 112, which can reduce manufacturing costs. Note that a stacked structure in which two or more oxide semiconductor layers having different compositions are stacked may be used. In addition, by using the ALD method, a metal oxide layer having a composition that is continuously different in the thickness direction can be formed. This not only widens the range of design options compared to the case where a film having a fixed composition is used, but also prevents the generation of interface states between two layers having different compositions, which can improve electrical characteristics and reliability.

[0253] It is preferable to use a metal oxide layer having crystallinity for the semiconductor layer 112. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nano-crystal (nc) structure, or the like can be used. By using a metal oxide layer having crystallinity for the semiconductor layer 112, the density of defect states in the semiconductor layer 112 can be reduced, and a highly reliable semiconductor device can be realized.

[0254] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 112, the more the density of defect states in the semiconductor layer 112 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0255] The above description can be referred to for the functional layer 118. Fig. 17 shows an example in which a dielectric material exhibiting ferroelectricity is used.

[0256] It should be noted that a configuration having a charge storage layer may be used instead of the functional layer 118. For example, by using a laminated film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are laminated in this order, the silicon nitride film can be made to function as a charge storage layer. This makes it possible to realize a charge trap type cell transistor. It should be noted that the present invention is not limited to this, and a floating gate type cell transistor can also be applied.

[0257] <Layer 13> 18 shows an example in which a layer 13 is stacked on a layer 12 having a memory string. The layer 13 has a transistor 200 and a capacitor 250.

[0258] The transistor 200 is a transistor having a metal oxide in a channel formation region (OS transistor). The transistor 200 has a pair of gates sandwiching a semiconductor in which a channel is formed. A capacitor 250 is connected to one of a source and a drain of the transistor 200. The transistor 200 has a characteristic of having an extremely small off-state current, and therefore, data (potential) written to the capacitor 250 through the transistor 200 can be held for a long period of time.

[0259] In the layer 13, insulating films such as an insulating layer 210, an insulating layer 212, an insulating layer 214, an insulating layer 216, an insulating layer 220, an insulating layer 222, an insulating layer 240, an insulating layer 244, an insulating layer 241, an insulating layer 242, an insulating layer 246, and an insulating layer 248 are stacked on an insulating layer 384. The insulating layer 212, the insulating layer 216, the insulating layer 240, the insulating layer 241, the insulating layer 246, and the insulating layer 248 function as interlayer insulating films, and the same material as that of the insulating layer 102 can be used. In addition, it is preferable to use an insulating film having a barrier property that prevents diffusion of hydrogen, impurities, and the like for the insulating layer 210, the insulating layer 214, the insulating layer 220, the insulating layer 222, the insulating layer 244, the insulating layer 242, and the like.

[0260] A conductive layer 218 is provided so as to be embedded in the insulating layer 210, the insulating layer 212, the insulating layer 214, and the insulating layer 216. The conductive layer 218 functions as a plug. In FIG. 18, the conductive layer 218 is provided in contact with the conductive layer 386.

[0261] The transistor 200 includes a conductive layer 205 arranged so as to be embedded in the insulating layer 214 and the insulating layer 216, an insulating layer 220 and an insulating layer 222 on the insulating layer 216 and the conductive layer 205, an insulating layer 224 on the insulating layer 222, a semiconductor layer 201 on the insulating layer 224, a pair of conductive layers 204 on the semiconductor layer 201, an insulating layer 240 located on the conductive layer 204 and having a groove reaching the semiconductor layer 201, and an insulating layer 203 and a conductive layer 202 provided so as to be embedded in the insulating layer 240.

[0262] One of the pair of conductive layers 204 functions as a source electrode, and the other functions as a drain electrode. The conductive layer 202 functions as a first gate electrode, and the insulating layer 203 functions as a first gate insulating layer. The conductive layer 205 functions as a second gate electrode, and the insulating layers 220, 222, and 224 function as a second gate insulating layer.

[0263] The insulating layer 224 and the insulating layer 203 in contact with the semiconductor layer 201 are preferably made of an oxide or an oxynitride, such as silicon oxide, silicon oxynitride, aluminum oxide, or hafnium oxide. In addition, a compound containing nitrogen, such as silicon nitride, silicon nitride oxide, or aluminum nitride, may be used. In addition, it is preferable to use an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide, in a single layer or a stacked layer. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by using a high-k material as an insulator that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0264] A laminated film in which a plurality of insulating films are stacked is preferably used as the insulating layer 203. For example, a laminated film in which two, three, or four or more layers of films made of the above-mentioned insulating materials are stacked is preferably used.

[0265] Alternatively, a thin film containing the above-described material exhibiting ferroelectricity may be used as the insulating layer 203. In this case, the transistor 200 can be used as a nonvolatile memory element. In this case, the capacitor 250 may not be used.

[0266] The insulating layer 234 is provided to cover the conductive layer 204 and has a function of suppressing oxidation of the conductive layer 204. At this time, the insulating layer 234 is provided to cover the side surfaces of the semiconductor layer 201 and the insulating layer 224 and to be in contact with the insulating layer 222. As the insulating layer 234, an insulating film having a barrier property that prevents diffusion of hydrogen, impurities, and the like is preferably used.

[0267] The capacitor 250 is provided on the insulating layer 246. The capacitor 250 has a conductive layer 251, a conductive layer 252, and an insulating layer 253 located therebetween. The capacitor 250 is a so-called MIM (Metal-Insulator-Metal) capacitor.

[0268] It is preferable to use a single layer or a multilayer of an insulator containing the above-mentioned high-k material as the insulating layer 253. Alternatively, the above-mentioned material exhibiting ferroelectricity can be used for the insulating layer 253. This allows the capacitance element 250 to be a ferroelectric capacitor, and by combining it with the transistor 200, a nonvolatile memory cell can be realized.

[0269] In addition, a conductive layer 254 functioning as a wiring may be provided over the insulating layer 246. The conductive layer 254 can be formed by processing the same conductive film as the conductive layer 251.

[0270] The conductive layer 254 and the conductive layer 204 are connected through the conductive layer 236 and the conductive layer 238. The conductive layer 236 and the conductive layer 238 function as plugs. The conductive layer 236 and the conductive layer 238 can be formed using a material similar to that of the conductive layer 328 and the conductive layer 330.

[0271] Fig. 19 shows an example in which the configuration of the layer 13 is different from that in Fig. 18. In Fig. 19, a transistor 400a and a transistor 400b are provided in the layer 13. The transistor 400a and the transistor 400b are each a vertical transistor.

[0272] The transistor 400a and the transistor 400b each include a semiconductor layer 401, a conductive layer 402 functioning as a gate electrode, an insulating layer 403 functioning as a gate insulating layer, a conductive layer 404 functioning as one of a source electrode and a drain electrode, and a conductive layer 406 functioning as the other electrode.

[0273] The structure of the transistor 400b will be described. A conductive layer 407 is provided over the insulating layer 216, a conductive layer 406 is provided over the conductive layer 407, and an insulating layer 410 is provided to cover the conductive layer 406. A conductive layer 405 is provided over the insulating layer 410, and a conductive layer 404 is provided over the conductive layer 405. An opening reaching the conductive layer 406 is provided in the conductive layer 404, the conductive layer 405, and the insulating layer 410. The semiconductor layer 401 is in contact with the conductive layer 404 and the conductive layer 406, and is in contact with a side surface of the insulating layer 410 located at the opening. The insulating layer 403 is provided to cover the semiconductor layer 401, and the conductive layer 402 is provided to fill the opening.

[0274] In one or both of the transistors 400a and 400b, the insulating layer 403 functioning as a gate insulating layer can be a thin film containing a material exhibiting ferroelectricity as exemplified in Embodiment 1. In particular, it is preferable to use such a thin film for the insulating layer 403 of the transistor 400b. In this way, the transistor 400b can be used as a nonvolatile memory element.

[0275] The channel length of the transistor 400b can be precisely controlled by the thickness of the insulating layer 410, and therefore the variation in the channel length can be made extremely small compared to planar type transistors. Furthermore, by thinning the insulating layer 410, a transistor with an extremely short channel length can be manufactured. For example, a transistor with a channel length of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured. Therefore, a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure device used in cutting-edge LSI technology.

[0276] Although various semiconductor materials can be used for the semiconductor layer 401, it is preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a large on-current and an extremely small off-current can be realized at low cost. Unless otherwise specified, a preferred structure example in which an oxide semiconductor is used for the semiconductor layer 401 will be described below.

[0277] The conductive layer 404 and the conductive layer 406 are each configured so that the semiconductor layer 401 is in contact with the upper surface thereof. Therefore, when an oxide semiconductor is used for the semiconductor layer 401, the vicinity of the exposed surfaces of the conductive layer 404 and the conductive layer 406 may be oxidized due to the influence of heat applied during or after a film formation process of a semiconductor film to be the semiconductor layer 401, and an insulating oxide film may be formed between the conductive layer 404 and the semiconductor layer 401, resulting in an increase in contact resistance. For this reason, it is preferable to use an oxide conductor containing a conductive oxide for at least the uppermost portions of the conductive layer 404 and the conductive layer 406. This can prevent an increase in contact resistance due to oxidation of the surfaces of the conductive layer 404 and the conductive layer 406. The conductive layer 404 and the conductive layer 406 can also be called an oxide layer, a metal oxide layer, an oxide conductor layer, or the like.

[0278] The conductive layer 405 can be used as one of the source wiring and the drain wiring. Part of the conductive layer 407 can be used as the other of the source wiring and the drain wiring. By providing the conductive layer 405 and the conductive layer 407 in contact with the conductive layer 404 and the conductive layer 406, respectively, in this manner, the electrical resistance of the wiring can be reduced. For the conductive layer 405 and the conductive layer 407, a material having higher conductivity than an oxide conductor, such as a metal, an alloy, or a nitride thereof, is preferably used.

[0279] The semiconductor layer 401 is provided in contact with an inner wall of an opening in the insulating layer 410. It is preferable to use an oxide insulating film for the insulating layer 410. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. The insulating layer 410 preferably has a stacked structure of three or more layers in which an oxide insulating film is sandwiched between insulating films having a barrier property against oxygen (for example, a nitride insulating film). In this way, oxygen contained in the oxide insulating film can be confined in a region surrounded by the pair of nitride insulating films and the semiconductor layer 401, and oxygen in the oxide insulating film can be prevented from being released and reduced during the process; therefore, oxygen can be more efficiently supplied to the semiconductor layer 401.

[0280] The transistor 400a has a structure similar to that of the transistor 400b, except that an insulating layer 414 is used instead of the insulating layer 410 of the transistor 400b, and a conductive layer 402 is used instead of the conductive layer 406 of the transistor 400b.

[0281] The gate electrode of the transistor 400b also serves as one of the source electrode and drain electrode of the transistor 400a.

[0282] The insulating layer 410, the insulating layer 414, and the insulating layer 418 function as interlayer insulating films. For the insulating layer 412, the insulating layer 416, and the like, an insulating film having a barrier property against hydrogen, impurities, and the like is preferably used.

[0283] In the transistor having the above-described structure, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the semiconductor in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or the like. Since the source electrode, the semiconductor, and the drain electrode of the transistor can be provided so as to overlap each other, the occupied area can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (Lateral FET), or the like) in which a semiconductor is arranged on a plane.

[0284] Fig. 20 illustrates an example in which the configuration is partially different from that in Fig. 19. The layer 13 illustrated in Fig. 20 includes a transistor 400 having a similar configuration to the transistor 400a and a capacitor 420 instead of the transistor 400b.

[0285] The capacitor 420 includes a conductive layer 421, a conductive layer 422, and an insulating layer 423 sandwiched between them. The insulating layer 423 functions as a dielectric layer of the capacitor 420. The conductive layer 407 is provided in contact with the conductive layer 421 and functions as a wiring.

[0286] An opening is provided in the insulating layer 410, reaching the conductive layer 407. A conductive layer 421 is provided in contact with an upper surface of the insulating layer 410, a side surface located in the opening, and an upper surface of the conductive layer 407 located at the bottom of the opening. An insulating layer 423 is provided to cover the conductive layer 421. A conductive layer 422 is provided to cover the insulating layer 423.

[0287] The insulating layer 423 is preferably formed of a single layer or a stack of insulators containing the above-mentioned high-k material. Alternatively, the above-mentioned material exhibiting ferroelectricity can be used for the insulating layer 423. In this way, the capacitor 420 can be a ferroelectric capacitor, and a nonvolatile memory cell can be realized in combination with the transistor 400.

[0288] In this way, by stacking a vertical transistor and a vertical capacitor, the area occupied by the memory cell can be made extremely small, which facilitates high integration and realizes a memory device with a large capacity.

[0289] Although the above describes a structure in which the layer 13 is provided over the layer 12, a structure in which the layer 12 is provided over the layer 13 may be used. For example, FIG. 21 shows an example in which the layer 13 including the transistor 200 is disposed under the layer 12. FIG. 22 shows an example in which the layer 13 including the transistors 400a and 400b is disposed under the layer 12. FIG. 23 shows an example in which the layer 13 including the transistor 400 and the capacitor 420 is disposed under the layer 12.

[0290] The above is a description of an example of the cross-sectional structure of a semiconductor device.

[0291] (Embodiment 2) In this embodiment, application examples of a storage device according to one embodiment of the present invention will be described.

[0292] Generally, various storage devices are used in semiconductor devices such as computers depending on the purpose. FIG. 24(A) shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device is located in the hierarchy, the faster the operation speed is required, and the lower the storage device is located in the hierarchy, the larger the storage capacity and the higher the recording density are required. In FIG. 24(A), from the top layer, there are a memory integrated as a register in an arithmetic processing device such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, a storage, and the like. Note that, although an example having up to an L3 cache is shown here, a lower cache may also be included.

[0293] The memory embedded as a register in a processor such as a CPU is used for temporary storage of calculation results, and is accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. The register also has the function of storing setting information for the processor.

[0294] A cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of the main memory, but it is required to operate faster than the main memory. In addition, data that is rewritten in the cache is duplicated and supplied to the main memory.

[0295] The main memory has a function of holding programs, data, etc. read from storage.

[0296] Storage has the function of storing data that needs to be stored for a long time, various programs used by the processor, etc. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. For example, a high-capacity, non-volatile storage device such as 3D NAND can be used.

[0297] Since the storage device according to one embodiment of the present invention has a storage device with a large storage capacity, it can be applied to the hierarchical level where the storage is located in Fig. 24(A). Furthermore, the storage device according to one embodiment of the present invention, which includes both a storage device with a large storage capacity and a storage device with a high operating speed, can be applied to both the hierarchical level where the storage is located and the hierarchical level where the main memory is located.

[0298] Furthermore, a memory device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Therefore, as shown in FIG 24A, the memory device according to one embodiment of the present invention can be favorably used in both the hierarchy where a cache is located and the hierarchy where a main memory is located.

[0299] FIG. 24B shows an example in which an SRAM is used as part of a cache, and an OS memory according to one embodiment of the present invention is used as the other part.

[0300] The lowest level cache can be called a Last Level cache (LLC). Although an LLC is not required to operate faster than higher level caches, it is desirable for the LLC to have a large storage capacity. The OS memory of one embodiment of the present invention has a high operating speed and is capable of retaining data for a long period of time, and therefore can be suitably used for an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to a Final Level cache (FLC).

[0301] For example, as shown in Fig. 24(B), a configuration can be adopted in which an SRAM is used for a higher-level cache (such as an L1 cache or an L2 cache) and an OS memory according to one embodiment of the present invention is used for an LLC. Also, as shown in Fig. 24(B), not only an OS memory but also a DRAM can be applied to the main memory.

[0302] At least a part of the configuration examples illustrated in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0303] (Embodiment 3) In this embodiment, an application example of the storage device of one embodiment of the present invention will be described.

[0304] The storage device of one embodiment of the present invention can be applied to storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, and game consoles). The storage device can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.

[0305] An example of an electronic device including a memory device of one embodiment of the present invention will be described. Note that each of the electronic devices includes an electronic component 700 including a memory device, as illustrated in FIG.

[0306] [mobile phone] 25A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0307] By applying a storage device of one embodiment of the present invention, the information terminal 5500 can store data used by an application or store temporary files generated when an application is executed (e.g., a cache when using a web browser).

[0308] [Wearable devices] 25B shows an information terminal 5900 which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.

[0309] Like the information terminal 5500 described above, a wearable device can store data used in an application or temporary files generated when an application is executed by applying a storage device of one embodiment of the present invention.

[0310] [Information terminal] 25C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0311] The desktop information terminal 5300, like the information terminal 5500 described above, can store data used by an application or temporary files generated when an application is executed by applying a storage device of one embodiment of the present invention.

[0312] In Figures 25(A) to 25(C), smartphones, wearable terminals, and desktop information terminals are described as electronic devices, but other information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0313] [electric appliances] 25D shows an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, and a freezer door 5803. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with the Internet of Things (IoT).

[0314] The storage device of one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the ingredients to and from an information terminal via the Internet, for example. The electric refrigerator-freezer 5800 can store a program and data used by the program, or a temporary file generated when transmitting the information, in the storage device of one embodiment of the present invention.

[0315] In Figure 25(D), an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0316] [Game consoles] 25E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0317] FIG. 25(F) shows a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 is a stationary game machine for home use. The stationary game machine 7500 has a main body 7520 and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or by wire. The shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, the shape may be a shape imitating a gun, a musical instrument, or a musical device. Alternatively, the controller may be provided with one or more of a camera, a depth sensor, a motion sensor, and a microphone instead of a controller, and may be operated by a gesture or voice of a game player.

[0318] Furthermore, the images of the above-mentioned game machines can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0319] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500. In addition, the reduction in power consumption can reduce heat generation from a circuit, and can reduce the influence of heat on the circuit itself, peripheral circuits, and modules.

[0320] Furthermore, by applying a storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500, it is possible to store programs or data used by the programs, or temporary files necessary for calculations that occur during game execution.

[0321] Other examples of game machines to which the storage device of one embodiment of the present invention can be applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0322] [Mobile object] A storage device according to one embodiment of the present invention can be applied to a vehicle, which is a moving object, and to the vicinity of a driver's seat of the vehicle.

[0323] FIG. 25G shows an automobile 5700 as an example of a moving object.

[0324] An instrument panel that provides various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows such information may also be provided around the driver's seat.

[0325] In particular, the display device can display an image from an imaging device (not shown) provided on the automobile 5700 to compensate for, for example, a field of view blocked by a pillar or a blind spot of the driver's seat, thereby improving safety. In other words, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0326] The storage device of one embodiment of the present invention can store a program for performing risk prediction, data used for the program, etc. The storage device of one embodiment of the present invention can store temporary information required for a system for performing automatic driving, road guidance, risk prediction, etc. of the automobile 5700. The storage device of one embodiment of the present invention may be configured to store video of a driving recorder installed in the automobile 5700.

[0327] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, the moving body may be a train, a monorail, a ship, or an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket).

[0328] [camera] The storage device according to one embodiment of the present invention can be applied to a camera.

[0329] 25(H) shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may be configured such that a strobe device, a viewfinder, or the like can be separately attached.

[0330] The storage device of one embodiment of the present invention can be applied to the digital camera 6240. This makes it possible to hold captured image data. Furthermore, temporary data used for the system of the digital camera 6240 can also be held.

[0331] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the digital camera 6240. In addition, the reduction in power consumption can reduce heat generation from a circuit, and the influence of heat on the circuit itself, peripheral circuits, and modules can be reduced.

[0332] [Video camera] The storage device according to one embodiment of the present invention can be applied to a video camera.

[0333] 25(I) shows a video camera 6300 which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0334] By using the storage device of one embodiment of the present invention, a large amount of captured video data can be stored. When recording video captured by the video camera 6300, encoding needs to be performed according to the data recording format. By using the storage device of one embodiment of the present invention, the video camera 6300 can store temporary files generated during encoding.

[0335] [ICD] A storage device according to one embodiment of the present invention can be applied to an implantable cardioverter defibrillator (ICD).

[0336] 25(J) is a schematic cross-sectional view showing an example of an ICD. An ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0337] The ICD body 5400 is surgically placed inside the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0338] The ICD main body 5400 has a function as a pacemaker, and performs pacing on the heart when the heart rate is out of a specified range. In addition, if the heart rate does not improve by pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is performed.

[0339] The ICD main body 5400 needs to constantly monitor the heart rate in order to perform pacing and electric shock appropriately. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. In addition, the ICD main body 5400 can store, for example, heart rate data acquired by the sensor, the number of times pacing treatment was performed, or the time, in the electronic component 700.

[0340] Moreover, the antenna 5404 can receive power, which is then charged in the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can still function, so that the ICD main body 5400 also functions as an auxiliary power source.

[0341] In addition to the antenna 5404 capable of receiving power, an antenna capable of transmitting physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0342] Furthermore, by applying the storage device of one embodiment of the present invention to the ICD main body 5400, data of the acquired organized signal can be held as digital data. The ICD main body 5400 can output the held data in response to a request from an external monitor device. For example, various types of biological information can be managed by a portable information terminal device such as a smartphone.

[0343] [Extension device for PC] A storage device according to one embodiment of the present invention can be applied to computers such as personal computers (PCs) and expansion devices for information terminals.

[0344] 26(A) shows an expansion device 6100 that can be connected to a PC via USB (Universal Serial Bus). The expansion device 6100 can be used as a so-called USB memory. Note that the expansion device 6100 is not limited to a small type, and may be a relatively large expansion device equipped with a cooling fan.

[0345] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with, for example, a circuit that drives the storage device of one embodiment of the present invention. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0346] [SD card] A storage device according to one embodiment of the present invention can be used as an SD card that can be attached to electronic devices such as information terminals or digital cameras.

[0347] FIG. 26(B) is a schematic diagram of the appearance of an SD card, and FIG. 26(C) is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a board 5113. The connector 5112 functions as an interface for connecting to an external device. The board 5113 is housed in the housing 5111. The board 5113 is provided with a memory device and a circuit for driving the memory device. For example, an electronic component 700 and a controller chip 5115 are attached to the board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to the above description, and may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, or the like provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 700.

[0348] The capacity of the SD card 5110 can be increased by providing the electronic component 700 also on the back side of the substrate 5113. A wireless chip having a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and makes it possible to read and write data from and to the electronic component 700.

[0349] [SSD] A storage device according to one embodiment of the present invention can be used as a solid state drive (SSD) that can be attached to electronic devices such as information terminals.

[0350] FIG. 26(D) is a schematic diagram of the appearance of the SSD, and FIG. 26(E) is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a board 5153. The connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 is provided with a storage device and a circuit for driving the storage device. For example, the board 5153 is provided with an electronic component 700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing the electronic component 700 on the back side of the board 5153 as well. A work memory is built into the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 is built with a processor, an ECC (Error-Correcting Code) circuit, and the like. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0351] [Calculator] 26F is an example of a large-scale computer. The computer 5600 includes a rack 5610 and a plurality of rack-mounted computers 5620 stored therein.

[0352] The computer 5620 can have the configuration shown in the perspective view of Fig. 26(G), for example. In Fig. 26(G), the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.

[0353] A PC card 5621 shown in Fig. 26(H) is an example of a processing board including a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that, although semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in Fig. 26(H), for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0354] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0355] The connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be, for example, an interface for supplying power to the PC card 5621, inputting a signal, or the like. Also, for example, the connection terminals 5623, the connection terminal 5624, and the connection terminal 5625 can be interfaces for outputting a signal calculated by the PC card 5621. Examples of the standards of the connection terminals 5623, the connection terminal 5624, and the connection terminal 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Also, when a video signal is output from the connection terminals 5623, the connection terminal 5624, and the connection terminal 5625, examples of the standards of the respective terminals include HDMI (registered trademark).

[0356] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0357] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected to each other by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include a field programmable gate array (FPGA), a GPU, and a CPU.

[0358] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to the terminals by, for example, reflow soldering to wiring provided on the board 5622. An example of the semiconductor device 5628 is a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0359] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference of artificial intelligence, for example.

[0360] By using the storage device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller and consume less power. In addition, the storage device of one embodiment of the present invention consumes less power, so heat generation from a circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the storage device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be improved.

[0361] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings. [Explanation of symbols]

[0362] 11: layer, 12: layer, 13: layer, 21: memory device, 50: insulating layer, 51: conductive layer, 52: conductive layer, 53: conductive layer, 54: conductive layer, 55: conductive layer, 56: plug, 57: conductive layer, 60: memory string, 65: memory cell, 71: curve, 72: curve, 100A: memory string, 100B: memory string, 100D: memory string, 100: memory string, 101: conductive layer, 102_1: insulating layer, 102_i: insulating layer, 102_m: insulating layer, 102: insulating layer, 103_1: conductive layer, 103_n: conductive layer, 103f: conductive film, 103: conductive layer , 104: conductive layer, 105: insulating layer, 106: conductive layer, 107: insulating layer, 108: insulating layer, 109_i: dummy layer, 109: dummy layer, 110: structure, 111: insulating layer, 112: semiconductor layer, 113f: conductive film, 113: conductive layer, 114f: insulating film, 114: insulating layer, 115: dummy layer, 116: recess, 118f: functional film, 118: functional layer, 120: central axis, 121: insulating layer, 125: conductive layer, 126: conductive layer, 127: conductive layer, 141: transistor, 142: transistor, 143: transistor, 200: transistor, 201: semiconductor layer, 202: Conductive layer, 203: insulating layer, 204: conductive layer, 205: conductive layer, 210: insulating layer, 212: insulating layer, 214: insulating layer, 216: insulating layer, 218: conductive layer, 220: insulating layer, 222: insulating layer, 224: insulating layer, 234: insulating layer, 236: conductive layer, 238: conductive layer, 240: insulating layer, 241: insulating layer, 242: insulating layer, 244: insulating layer, 246: insulating layer, 248: insulating layer, 250: capacitance element, 251: conductive layer, 252: conductive layer, 253: insulating layer, 254: conductive layer, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low Resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 384: insulating layer, 386: conductive layer, 400a: transistor, 400b: transistor, 400: transistor, 401: semiconductor layer, 402: conductive layer, 403: insulating layer, 404: conductive layer, 405: conductive layer, 406: conductive layer, 407: conductive layer, 410: insulating layer, 412: insulating layer, 414: insulating layer, 416: insulating layer, 418: insulating layer, 420: capacitance element, 421: conductive layer, 422: conductive layer,423: insulating layer, 700: electronic component, 1000a: semiconductor device, 1000b: semiconductor device, 1000: semiconductor device, 1100: arithmetic processing device, 1150A: semiconductor device, 1150B: semiconductor device, 1150C: semiconductor device, 1189: cache interface, 1190: substrate, 1191: ALU, 1192: ALU controller, 1193: instruction decoder, 1194: interrupt controller, 1195: timing controller, 1196: register, 1197: register controller, 1198: bus interface, 119 9: cache, 5110: SD card, 5111: housing, 5112: connector, 5113: board, 5115: controller chip, 5150: SSD, 5151: housing, 5152: connector, 5153: board, 5155: memory chip, 5156: controller chip, 5200: portable game machine, 5201: housing, 5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main unit, 5302: display unit, 5303: keyboard, 5400: ICD main unit, 5401: battery, 5402: wire, 5403: wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Housing, 5511: Display unit, 5600: Computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door, 590 0: Information terminal, 5901: Housing, 5902: Display unit, 5903: Operation switch, 5904: Operation switch, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Board, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First housing, 6302: Second housing, 6303: Display unit, 6304: Operation switch, 6305: Lens,6306: Connection part, 7500: Stationary game machine, 7520: Main unit, 7522: Controller,

Claims

1. A conductive layer that functions as a gate, A functional layer exhibiting ferroelectricity, A semiconductor layer in which a channel is formed, Having a first insulating layer, The functional layer has a region sandwiched between a conductor that functions as a gate and the first insulating layer. The first insulating layer has a region sandwiched between the functional layer and the semiconductor layer, The first insulator is a high dielectric constant material. Semiconductor equipment.

2. A semiconductor device having a first memory cell and a second memory cell, The aforementioned semiconductor device is A first conductive layer that functions as the gate of the first memory cell, A second conductive layer that functions as the gate of the second memory cell, In the first direction, a second insulating layer is sandwiched between the first conductive layer and the second conductive layer, A semiconductor layer having a channel extending in the first direction, A first insulating layer extending in the first direction, A ferroelectric functional layer having a region sandwiched between a first conductive layer that functions as a gate and a first insulating layer, The first insulating layer has a region sandwiched between the functional layer and the semiconductor layer, The first insulating layer is a high dielectric constant material. Semiconductor equipment.

3. In claim 1, The dielectric constant of the first insulating layer is higher than that of the silicon oxide film. Semiconductor equipment.

4. In claim 2, The dielectric constant of the first insulating layer is higher than that of the silicon oxide film. Semiconductor equipment.

5. In claims 1 to 4, The aforementioned semiconductor is an oxide semiconductor. Semiconductor equipment.

6. In claim 5, The aforementioned oxide semiconductor is an oxide film containing indium. Semiconductor equipment.

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