Vertical resonator type light-emitting element and light-emitting device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- STANLEY ELECTRIC CO LTD
- Filing Date
- 2023-07-06
- Publication Date
- 2026-07-02
Smart Images
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Abstract
Description
[Technical field]
[0001] The present invention relates to a vertical cavity light emitting device and a light emitting device. [Background technology]
[0002] A vertical cavity light emitting device is known as one type of semiconductor laser. For example, Patent Document 1 discloses a vertical cavity surface emitting laser (VCSEL) including a semiconductor structure layer including an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer, with a protrusion formed on the upper surface of the p-type semiconductor layer, an insulating layer formed on the upper surface of the p-type semiconductor layer, and a light-transmitting electrode layer including the insulating layer and formed on the upper surface of the p-type semiconductor layer. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Patent Publication No. 2021-197437 Summary of the Invention [Problem to be solved by the invention]
[0004] In the vertical-cavity surface-emitting laser disclosed in Patent Document 1, for example, if the light-transmitting electrode layer is formed so as to be in direct contact with the side surface of the protruding portion of the p-type semiconductor layer, the side surface is not a completely non-conductive portion, and therefore, a long-term current is passed through the side surface of the protruding portion via the light-transmitting electrode layer, which may result in a decrease in the output of light emitted from the vertical-cavity surface-emitting laser.
[0005] The present invention has been made in consideration of the above-mentioned points, and an object of the present invention is to provide a vertical cavity light emitting device that can maintain a stable light output even when powered for a long period of time. [Means for solving the problem]
[0006] The vertical cavity light emitting device according to the present invention is characterized in having a substrate, a first multilayer film reflector formed on the substrate, a first semiconductor layer having a first conductivity type formed on the first multilayer film reflector, a light emitting layer formed on the first semiconductor layer, and a semiconductor structure layer including a second semiconductor layer formed on the light emitting layer, the second semiconductor layer having a second conductivity type opposite to the first conductivity type, the second semiconductor layer having a protruding portion protruding upward from the center of an upper surface and having insulating properties along a region of the upper surface outside the protruding portion, a first insulating layer having insulating properties formed over a side surface of the protruding portion of the second semiconductor layer, a light-transmitting conductive film formed to cover an upper surface of the second semiconductor layer from the upper surface of the protruding portion to its peripheral portion and electrically connected to the second semiconductor layer, and a second multilayer film reflector formed on the semiconductor structure layer to cover the protruding portion and to constitute a resonator between the first multilayer film reflector and the second multilayer film reflector. [Brief description of the drawings]
[0007] [Figure 1] 1 is a perspective view of a vertical cavity surface emitting laser in accordance with a first embodiment. [Diagram 2] 1 is a top view of a vertical cavity surface emitting laser in accordance with a first embodiment. [Diagram 3] 1 is a cross-sectional view of a vertical cavity surface emitting laser in accordance with a first embodiment. [Figure 4] 1 is an enlarged view of a portion of a cross section of a vertical cavity surface emitting laser in accordance with a first embodiment. [Diagram 5] FIG. 1 is an enlarged view of a portion of a cross section of a vertical-cavity surface-emitting laser according to a conventional example. [Figure 6A] 1 is a graph showing the results of SIMS analysis of a p-type semiconductor layer and a light emitting layer. [Figure 6B] 1 is a graph showing the results of SIMS analysis of a p-type semiconductor layer and a light emitting layer. [Figure 6C] 1 is a graph showing the results of SIMS analysis of a SiO2 layer. [Figure 7] 3A to 3C are diagrams illustrating a part of a method for manufacturing the vertical cavity surface emitting laser according to the first embodiment. [Figure 8]3A to 3C are diagrams illustrating a part of a method for manufacturing the vertical cavity surface emitting laser according to the first embodiment. [Figure 9] 3A to 3C are diagrams illustrating a part of a method for manufacturing the vertical cavity surface emitting laser according to the first embodiment. [Figure 10] 3A to 3C are diagrams illustrating a part of a method for manufacturing the vertical cavity surface emitting laser according to the first embodiment. [Figure 11] FIG. 11 is a top view of a light emitting device according to a second embodiment. [Figure 12] FIG. 11 is a cross-sectional view of a light emitting device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0008] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and the description of the same components will be omitted. EXAMPLES
[0009] The configuration of a vertical cavity surface emitting laser 100 (hereinafter referred to as surface emitting laser 100) according to a first embodiment will be described with reference to Figs. 1 to 4. Fig. 1 is a perspective view of the surface emitting laser 100. Fig. 2 is a top view of the surface emitting laser 100. Fig. 3 is a cross-sectional view taken along line 3-3 of the surface emitting laser 100 shown in Fig. 2, and Fig. 4 is an enlarged view of part A in Fig. 3. Note that the up-down direction in Fig. 3 corresponds to the height direction of the surface emitting laser 100.
[0010] The substrate 11 is a flat, transparent substrate with a rectangular upper surface. The substrate 11 is a growth substrate on which a semiconductor crystal can be grown. The substrate 11 is made of a material that is translucent to light having a blue wavelength, such as undoped gallium nitride (GaN). In the following description, an axis that passes through the center of the upper surface of the substrate 11 and is perpendicular to the upper surface is defined as a central axis CA.
[0011] The first multilayer film reflector 12 is a semiconductor multilayer film reflector made of semiconductor layers grown on the substrate 11. The first multilayer film reflector 12 is a so-called distributed Bragg reflector (DBR) in which high-refractive index semiconductor films having a relatively high refractive index and low-refractive index semiconductor films having a refractive index lower than that of the high-refractive index semiconductor films are alternately laminated on the upper surface of the substrate 11.
[0012] The first multilayer film reflector 12 is formed by, for example, stacking 42 pairs of a high refractive index semiconductor film made of GaN and a low refractive index semiconductor film made of aluminum indium nitride (AlInN) on the upper surface of the substrate 11. The first multilayer film reflector 12 has such a configuration and is reflective to light in the blue wavelength range. A buffer layer (not shown) made of GaN is provided between the substrate 11 and the first multilayer film reflector 12.
[0013] The semiconductor structure layer EM is a laminated structure made up of a plurality of semiconductor layers formed on the first multilayer reflector 12. The semiconductor structure layer EM has an n-type semiconductor layer 13 formed on the first multilayer reflector 12, a light emitting layer 14 formed on the n-type semiconductor layer 13, and a p-type semiconductor layer 15 formed on the light emitting layer 14.
[0014] Hereinafter, the structures of the n-type semiconductor layer 13, the light emitting layer 14, and the p-type semiconductor layer 15 that constitute the semiconductor structure layer EM will be described.
[0015] N-type semiconductor layer 13 as a first semiconductor layer having a first conductivity type is a semiconductor layer formed over the upper surface of first multilayer film reflector 12. N-type semiconductor layer 13 is made of GaN and is doped with silicon (Si) as an n-type impurity.
[0016] The n-type semiconductor layer 13 has a so-called mesa-shaped structure composed of a flat lower portion 13A and a cylindrical upper portion 13B protruding upward from the center of the lower portion 13A along a central axis CA (see FIGS. 1 and 3).
[0017] The light emitting layer 14 is formed over the upper portion 13B of the n-type semiconductor layer 13, and is a semiconductor layer having a quantum well structure in which a well layer made of InGaN and a barrier layer made of GaN are stacked on each other. The light emitting layer 14 is formed so that its light emitting center is brought onto the central axis CA. The light emitting layer 14 emits blue light having a peak wavelength of, for example, 450 nm.
[0018] The p-type semiconductor layer 15 as a second semiconductor layer having a second conductivity type is a semiconductor layer formed over the upper surface of the light emitting layer 14. The p-type semiconductor layer 15 includes a p-type GaN layer doped with p-type impurities and a p-type AlGaN layer doped with p-type impurities. The p-type AlGaN layer is formed between the light emitting layer 14 and the p-type GaN layer, and functions as an electron blocking layer. Note that an undoped GaN layer may be formed between the light emitting layer 14 and the p-type AlGaN layer to prevent diffusion of p-type impurities from the p-type AlGaN layer to the light emitting layer 14.
[0019] The p-type semiconductor layer 15 has, on its upper surface, a protruding portion 15P1 that has a circular upper surface shape and protrudes upward through the central axis CA (see FIG. 3). In other words, the p-type semiconductor layer 15 has a first region 15R1 that is a region that passes through the central axis CA, and an annular second region 15R2 that is a peripheral region of the first region 15R1 and is recessed downward from the first region 15R1.
[0020] Moreover, the p-type semiconductor layer 15 has, on its upper surface, an outer peripheral portion 15P2 that has an annular upper surface shape and protrudes upward from the second region 15R2 along the outer edge of the p-type semiconductor layer 15. In other words, the p-type semiconductor layer 15 has a third region 15R3 that is a peripheral region of the second region 15R2 and protrudes upward from the second region 15R2. That is, the p-type semiconductor layer 15 has, on its upper surface, a recess that surrounds the protruding portion 15P1 and has the second region 15R2 as its bottom surface.
[0021] In the p-type semiconductor layer 15, the second region 15R2, the side surface 15S1 (hereinafter also simply referred to as side surface 15S1) of the protrusion 15P1, and the side surface 15S2 (hereinafter also simply referred to as side surface 15S2) of the outer periphery 15P2 are each a region in which the p-type impurity (Mg) doped into the p-type semiconductor layer 15 is electrically inactivated (see Figures 3 and 4).
[0022] The second region 15R2, side 15S1 and side 15S2 are each formed, for example, by dry etching the upper surface of the flat p-type semiconductor layer so as to leave regions corresponding to the first region 15R1 and the third region 15R3.
[0023] In the p-type semiconductor layer 15 before the protruding portion 15P1 is formed, i.e., in the p-type semiconductor layer 15 before dry etching, the p-type impurities in the upper surface of the p-type semiconductor layer 15 are in an electrically activated state. On the other hand, in the p-type semiconductor layer 15 after dry etching, the p-type impurities in the second region 15R2 and the side surface 15S1 and the side surface 15S2 are in an electrically inactive state due to etching damage.
[0024] Therefore, the second region 15R2, the side surface 15S1, and the side surface 15S2 each function as a high resistance region having a higher electrical resistance than the first region 15R1. In particular, the second region 15R2 functions as a non-conductive region through which electricity hardly passes compared to the side surface 15S1 and the side surface 15S2.
[0025] In addition, the first region 15R1 and the third region 15R3, which are regions of the upper surface of the p-type semiconductor layer 15 that have not been dry etched, function as low-resistance regions having lower electrical resistance than the second region 15R2, the side surface 15S1, and the side surface 15S2.
[0026] The first insulating layer 18 is a transparent coating layer having electrical insulation properties that is formed over the side surface 15S1 of the protruding portion 15P1 and that is formed to cover the edge of the first region 15R1. The first insulating layer 18 is made of a material that is a non-oxide and has a refractive index close to that of the conductive film 21 described below, such as silicon nitride (SiN).
[0027] The second insulating layer 19 is a transparent coating layer having electrical insulation properties and formed to cover the third region 15R3 and the side surface 15S2 of the outer peripheral portion 15P2. The second insulating layer 19 is formed to provide an inclined surface from the third region 15R3 to the second region 15R2. The second insulating layer 19 is formed on the upper surface of the p-type semiconductor layer 15 and separated from the first insulating layer 18. The second insulating layer 19 is made of, for example, silicon dioxide (SiO2).
[0028] In addition, the second insulating layer 19 may be formed from the outer edge of the peripheral portion 15P2 to each side surface of the p-type semiconductor layer 15, the light-emitting layer 14, and the upper portion 13B of the n-type semiconductor layer 13, or may be formed to reach the upper surface of the lower portion 13A of the n-type semiconductor layer 13.
[0029] The conductive film 21 is a light-transmitting conductive film formed so as to cover the upper surface of the p-type semiconductor layer 15 from the first region 15R1 to the third region 15R3 and is electrically connected to the p-type semiconductor layer 15. The conductive film 21 is formed on the p-type semiconductor layer 15 so as to cover the first insulating layer 18 and the second insulating layer 19.
[0030] The conductive film 21 is made of a metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO), that is transparent to the blue light emitted from the light emitting layer 14 of the semiconductor structure layer EM described above.
[0031] The conductive film 21 is formed to have an inclined surface that follows the inclined surface of the above-mentioned second insulating layer 19. By forming the conductive film 21 in this manner, it is expected that the durability against cracks and the like during long-term use will be improved compared to the case where the conductive film 21 is simply formed in a flat plate shape.
[0032] As described above, the conductive film 21 is formed to cover the first insulating layer 18 formed on the side surface 15S1 and the second insulating layer 19 formed on the third region 15R3 and the side surface 15S2. Therefore, the conductive film 21 is electrically insulated from each of the side surface 15S1, the third region 15R3, and the side surface 15S2. In addition, the second region 15R2 has a high resistance due to etching damage, making it difficult for a current to flow through the conductive film 21. Therefore, on the upper surface of the p-type semiconductor layer 15, only the first region 15R1, which is the upper surface of the protruding portion 15P1, is electrically connected to the conductive film 21.
[0033] The n-electrode NE as a first electrode is provided on the upper surface of the lower portion 13A of the n-type semiconductor layer 13, and is a metal electrode with a ring-shaped upper surface shape that is electrically connected to the n-type semiconductor layer 13. In a plan view of the surface-emitting laser 100 seen from above, the n-electrode NE is formed to surround the upper portion 13B of the n-type semiconductor layer 13 while being spaced apart from the upper portion 13B. The n-electrode NE is formed, for example, by laminating titanium (Ti) and aluminum (Al) in this order on the upper surface of the lower portion 13A.
[0034] The p-electrode PE as the second electrode is formed along the outer edge of the upper surface of the conductive film 21 so as to surround the first region 15R1 in a plan view of the surface-emitting laser 100 from above, and is a metal electrode having a ring-shaped upper surface that is electrically connected to the conductive film 21. The p-electrode PE is made of, for example, gold (Au).
[0035] The second multilayer film reflector 23 is a cylindrical dielectric multilayer film reflector made of dielectric layers formed on the upper surface of the conductive film 21. The second multilayer film reflector 23 is formed to cover the first region 15R1 and to be spaced apart from the p-electrode PE in a plan view of the surface-emitting laser 100 seen from above.
[0036] The second multilayer film reflector 23 is a so-called distributed Bragg reflector (DBR) in which a high-refractive index semiconductor film having a relatively high refractive index and a low-refractive index semiconductor film having a lower refractive index than the high-refractive index semiconductor film are alternately stacked on the upper surface of the conductive film 21.
[0037] The second multilayer film reflector 23 is formed, for example, by laminating 10.5 pairs of a high refractive index dielectric film made of niobium pentoxide (Nb2O5) and a low refractive index dielectric film made of SiO2 on the upper surface of the conductive film 21. The second multilayer film reflector 23 has reflectivity for the blue light emitted from the light emitting layer 14 by having such a configuration.
[0038] A transparent dielectric layer (not shown) having a circular upper surface shape may be formed as, for example, a phase adjustment layer between the second multilayer film reflector 23 and the conductive film 21. The dielectric layer is made of, for example, Nb2O5, tantalum pentoxide (Ta2O5), zinc oxide (ZrO2), titanium oxide (TiO2), hafnium oxide (HfO2), or the like.
[0039] In the surface-emitting laser 100, the lower surface of the second multilayer film reflector 23 faces the upper surface of the first multilayer film reflector 12, with the conductive film 21, the first insulating layer 18, and the semiconductor structure layer EM sandwiched therebetween. As a result, the first multilayer film reflector 12 and the second multilayer film reflector 23 form a resonator OC between the first multilayer film reflector 12 and the second multilayer film reflector 23, with the resonator length direction being in a direction perpendicular to the semiconductor structure layer EM (direction perpendicular to the substrate 11).
[0040] In the surface-emitting laser 100, the reflectance of the first multilayer film reflector 12 for blue light is slightly lower than the reflectance of the second multilayer film reflector 23 for blue light. Therefore, part of the blue light resonated in the resonator OC passes through the first multilayer film reflector 12 and the substrate 11 and is extracted to the outside. That is, the light resonated between the first multilayer film reflector 12 and the second multilayer film reflector 23 is emitted downward in FIG.
[0041] An antireflection film (not shown) made of a laminate of Nb2O5 and SiO2 is formed on the lower surface of the substrate 11. The antireflection film is a so-called AR coat that suppresses the blue light emitted from the substrate 11 from being reflected upward in FIG.
[0042] Here, we will explain the operation and optical characteristics of the surface-emitting laser 100. When a voltage is applied to the above-mentioned n-electrode NE and p-electrode PE and a current flows between the n-electrode NE and the p-electrode PE, the current flows in the light-emitting layer 14 of the semiconductor structure layer EM as shown by the thick dashed-dotted arrow in Fig. 3, and when the current reaches a threshold current, which is a predetermined current value, the intensity of the blue light emitted from the light-emitting layer 14 increases rapidly.
[0043] The blue light emitted from the light-emitting layer 14 when the threshold current is reached is repeatedly reflected between the first multilayer film reflector 12 and the second multilayer film reflector 23, i.e., in the resonator OC, and reaches a resonance state (i.e., laser oscillation occurs).
[0044] At this time, in the p-type semiconductor layer 15, most of the current flowing from the p-electrode PE to the conductive film 21 flows to the n-electrode NE via the first region 15R1, which is a low-resistance region. Therefore, in the surface-emitting laser 100, a current is supplied to the light-emitting layer 14 via the first region 15R1, and blue light is emitted from the first region 15R1 along the central axis CA. That is, in the surface-emitting laser 100, the protruding portion 15P1 of the p-type semiconductor layer 15 functions as a current constriction portion that limits the supply range of the current so that the current does not spread any further.
[0045] As described above, the blue light emitted from the light emitting layer 14 and resonated in the resonator OC is partially extracted to the outside through the first multilayer reflector 12 and the substrate 11 because the optical reflectance of the first multilayer reflector 12 is lower than that of the second multilayer reflector 23. In other words, the lower surface of the substrate 11 serves as the light emission surface of the surface emitting laser 100.
[0046] In the cavity OC of the surface-emitting laser 100, the thickness from the lower surface to the upper surface of the p-type semiconductor layer 15 is thicker by the protruding portion 15P1 than the thickness from the lower surface to the second region 15R2 of the p-type semiconductor layer 15. Therefore, the equivalent refractive index in the cavity OC of the surface-emitting laser 100 differs between the cylindrical central region including the protruding portion 15P1 of the p-type semiconductor layer 15 and the cylindrical peripheral region therearound, and the equivalent refractive index in the central region is larger than the equivalent refractive index in the peripheral region.
[0047] In the surface-emitting laser 100, the resonator OC is configured as described above, which suppresses optical loss caused by the standing wave in the central region diverging (radiating) to the peripheral regions. In other words, most of the light remains in the central region, and the laser light is extracted to the outside in this state.
[0048] Therefore, a large amount of light emitted from the light emitting layer 14 is concentrated in the central region around the central axis CA of the resonator OC, so that high-output and high-density laser light can be generated and emitted. That is, the transverse mode (intensity distribution in the transverse cross section of the laser beam) of the laser light emitted from the surface emitting laser 100 can be stabilized.
[0049] Furthermore, the conductive film 21 has a conductive film protruding portion 21P with a flat upper surface on the protruding portion 15P1 of the p-type semiconductor layer. The area of the upper surface of the conductive film protruding portion 21P is preferably larger than the area of the first region 15R1. This allows the second multilayer film reflector 23 formed on the upper surface of the conductive film protruding portion 21P to be formed substantially parallel to the upper surface of the protruding portion 15P1 (first region 15R1), thereby suppressing loss during resonance in the resonator OC.
[0050] [Suppression of decrease in optical output in surface-emitting laser 100] Hereinafter, the suppression of a decrease in the optical output of the surface emitting laser 100 in this embodiment will be described with reference to FIGS.
[0051] In the surface-emitting laser 100 of this embodiment, as described above, the side surface 15S1 of the protruding portion 15P1 is insulated from the conductive film 21 by the first insulating layer 18, the second region 15R2 functions as a non-conductive region, and the third region 15R3 and the side surface 15S2 are insulated from the conductive film 21 by the second insulating layer 19. That is, in the surface-emitting laser 100 of this embodiment, almost no current flows from the conductive film 21 to the second region 15R2, the side surface 15S1, the third region 15R3 and the side surface 15S2.
[0052] Therefore, when a voltage is applied to the n-electrode NE and the p-electrode PE and a current flows between the n-electrode NE and the p-electrode PE, the current flowing in the conductive film 21 flows along the in-plane direction of the upper surface of the p-type semiconductor layer 15 within the conductive film 21, as shown in FIG. 4, passes through the first region 15R1, which is a low-resistance region, and proceeds into the p-type semiconductor layer 15 toward the n-electrode NE.
[0053] Here, the flow of current when energized in a conventional surface-emitting laser will be described with reference to Fig. 5. Fig. 5 is an enlarged view of a cross section of a conventional surface-emitting laser at a location similar to part A in the cross section of the surface-emitting laser 100 shown in Fig. 3. The conventional surface-emitting laser is different from the surface-emitting laser 100 in that the first insulating layer 18 is not formed on the side surface 15S1, but is the same as the surface-emitting laser 100 in other respects.
[0054] During the formation of the protruding portion 15P1 of the p-type semiconductor layer 15, the side surface 15S1 of the protruding portion 15P1 may be less damaged by etching than the second region 15R2, which is the bottom surface of the etching, due to factors such as the etching conditions and environment. In this case, the side surface 15S1 does not become a completely non-conductive portion but becomes a conductive portion with high resistance.
[0055] Therefore, when the first insulating layer 18 is not formed on the side surface 15S1 of the protrusion 15P1 as in the conventional example, that is, when the conductive film 21 is in direct contact with the side surface 15S1, if the side surface 15S1 becomes a high-resistance conductive portion, the current flowing in the conductive film 21 will flow not only through the first region 15R1 but also toward the side surface 15S1.
[0056] In this case, if a current is passed through side 15S1, which is originally highly resistive, for a long period of time, side 15S1 becomes even more resistive, and, for example, as shown in FIG. 5, part of the current flowing in conductive film 21 may be concentrated at corner 15C, which is a high-resistance portion formed by side 15S1 and second region 15R2.
[0057] When the current is concentrated at the corner 15C as described above, the efficiency of current injection into the light emitting layer 14 decreases, which may result in a decrease in the optical output obtained from the surface emitting laser 100. That is, when the surface emitting laser is energized, the current is supposed to flow only through the first region 15R1, but the current also flows through a portion having a higher resistance than the first region 15R1, which may lead to a current loss and a decrease in the optical output.
[0058] In the surface-emitting laser 100 of this embodiment, as described above, the side surface 15S1 and the corner portion 15C of the protrusion 15P1 are covered with the first insulating layer 18, and therefore the side surface 15S1 and the corner portion 15C are insulated from the conductive film 21. Therefore, according to the surface-emitting laser 100, as shown in Fig. 4, the current flowing in the conductive film 21 flows only through the first region 15R1 which is a low-resistance region, and therefore it is possible to prevent the optical output of the surface-emitting laser 100 from decreasing.
[0059] Furthermore, in the surface-emitting laser 100, if only the second insulating layer 19 is formed from the side surface 15S1 of the protrusion 15P1 to the third region 15R3, i.e., if the second insulating layer 19 is in direct contact with the side surface 15S1, a phenomenon may occur in which the efficiency of current injection into the light-emitting layer 14 decreases when current is passed through the surface-emitting laser 100 for a long period of time.
[0060] Specifically, since the second insulating layer 19, which is an oxide, contains hydrogen when it is formed, if a current is passed for a long period of time while the second insulating layer 19 is in direct contact with the side surface 15S1, the residual hydrogen in the second insulating layer 19 may diffuse into the protruding portion 15P1 via the side surface 15S1. This may result in a phenomenon in which the electrical resistance in the protruding portion 15P1 increases and the efficiency of current injection into the light-emitting layer 14 decreases.
[0061] 6A to 6C, the hydrogen concentration in the p-type semiconductor layer when the residual hydrogen in second insulating layer 19 diffuses into the p-type semiconductor layer will be described. Each of Figs. 6A to 6C is a graph showing the results of measuring the concentration of each element in the depth direction (thickness direction) of each of the samples described later by SIMS (Secondary ion mass spectrometry) analysis.
[0062] FIG. 6A shows the concentration profiles of hydrogen (solid line), oxygen (dashed line), silicon (dotted line), and gallium (dashed line) in the depth direction for a sample in which a SiO2 layer is formed directly on a GaN substrate, with the top surface of the sample taken as the reference (0 nm).
[0063] In FIG. 6A, the area indicated by the two-dot chain line shows the concentration in the SiO2 layer, and the area indicated by the one-dot chain line shows the concentration in the substrate. From FIG. 6A, the hydrogen concentration in the SiO2 layer when the SiO2 layer is directly formed on the substrate is 1×10 21 ~2×10 21 atoms / cm 3 In other words, the SiO2 layer alone at the time of film formation is about 1×10 21 atoms / cm 3 It can be seen that the hydrogen concentration is equal to or higher than this.
[0064] FIG. 6B shows the concentration profiles of hydrogen (solid line), aluminum (dashed line) and indium (dotted line) in the depth direction, using a sample in which a SiO2 layer corresponding to the light-emitting layer 14, a p-type semiconductor layer 15 and a second insulating layer 19 were formed in that order and then heat-treated, with the top surface of the p-type semiconductor layer 15 being taken as the reference (0 nm).
[0065] 6B, the region indicated by the two-dot chain line indicates the concentration in p-type semiconductor layer 15, and the region indicated by the one-dot chain line indicates the concentration in light emitting layer 14. From FIG. 6B, the hydrogen concentration in p-type semiconductor layer 15 is about 2×10 19 atoms / cm 3 It can be seen that the above is shown.
[0066] 6C shows concentration profiles of hydrogen (solid line), aluminum (dashed line), and indium (dotted line) in the depth direction when the top surface of p-type semiconductor layer 15 is set as the reference (0 nm) using a sample in which light emitting layer 14 and p-type semiconductor layer 15 are formed in this order. Note that an undoped layer (not shown) made of GaN is formed between the light emitting layer and the p-type semiconductor layer in the figure.
[0067] 6C, the region indicated by the two-dot chain line indicates the concentration in p-type semiconductor layer 15, and the region indicated by the one-dot chain line indicates the concentration in light emitting layer 14. From FIG. 6C, it can be seen that the hydrogen concentration in p-type semiconductor layer 15 is about 1×10 16 atoms / cm 3 It is understood that the above is shown. It is considered that the high concentration of hydrogen present in the film thickness of 0 to 20 nm is due to the influence of impurities (contamination) attached to or mixed into the p-type semiconductor layer 15.
[0068] 6B and 6C, it is considered that when a SiO2 layer is formed on the p-type semiconductor layer 15, hydrogen contained in the SiO2 layer moves into the p-type semiconductor layer 15 by diffusion or the like. As a result, for example, hydrogen that has moved into the p-type semiconductor layer 15 may combine with Mg, which is a dopant in the p-type semiconductor layer 15, to inactivate the Mg, and the electrical resistance in the protruding portion 15P1 may increase. As a result, the efficiency of current injection into the light-emitting layer 14 may decrease.
[0069] In the surface-emitting laser 100, the first insulating layer 18 formed on the protruding portion 15P1 is made of a material that does not contain hydrogen, for example, SiN which is a nitride, so that it is possible to prevent diffusion of hydrogen from the SiO2 layer into the protruding portion 15P1. Therefore, according to the surface-emitting laser 100 of this embodiment, it is possible to prevent a decrease in the efficiency of current injection into the light-emitting layer 14 even when the surface-emitting laser 100 is energized for a long period of time.
[0070] Therefore, according to the surface-emitting laser 100 of this embodiment, even if electricity is applied for a long period of time, it is possible to prevent the optical output of the surface-emitting laser 100 from decreasing. Therefore, according to the surface-emitting laser 100 of this embodiment, the optical output of the laser light emitted from the surface-emitting laser 100 can be stably maintained.
[0071] The average hydrogen concentration in the p-type semiconductor layer 15 as a whole is about 2×10 18 atoms / cm 3 It is preferable that the area of the second insulating layer 19 present on the upper surface of the second region 15R2 is, for example, 40% or less of the area of the second region 15R2. This makes it possible to achieve insulation against the current flowing from the p-electrode PE while suppressing an increase in electrical resistance due to excessive diffusion of hydrogen into the p-type semiconductor layer 15.
[0072] As described above, the first insulating layer 18 has a refractive index equivalent to that of the conductive film 21, and the refractive index of the first insulating layer 18 is preferably within 10% of the refractive index of the conductive film 21. For example, the refractive index of the conductive film 21 made of ITO is approximately 2.1, and the refractive index of the first insulating layer 18 made of SiN is approximately 2.0.
[0073] In the surface-emitting laser 100, as described above, the equivalent refractive index in the resonator OC is adjusted by providing the protruding portion 15P1 in the p-type semiconductor layer 15, thereby controlling the transverse mode of the laser light. Therefore, by using the first insulating layer 18, which has a refractive index as close as possible to that of the conductive film 21, as the insulating layer covering the side surface 15S1, it is possible to control the transverse mode without reducing the current injection efficiency.
[0074] In this embodiment, the upper surface of the p-type semiconductor layer 15 has been described as having the outer periphery 15P2, but the outer periphery 15P2 may not be provided, and the second region 15R2 may be formed up to the outer edge of the p-type semiconductor layer 15. That is, the entire region of the upper surface of the p-type semiconductor layer 15 other than the first region 15R1 may be etched (inactivated).
[0075] Furthermore, when the second region 15R2 is formed up to the outer edge of the p-type semiconductor layer 15 as described above, the entire region other than the first region 15R1 becomes a non-conductive portion, and therefore it is not necessary to form the second insulating layer 19. In this case, the first insulating layer 18 may be formed over the second region 15R2 while covering the side surface 15S1.
[0076] In this embodiment, the first insulating layer 18 is described as covering the outer edge of the first region 15R1 and the side surface 15S1 of the protrusion 15P1, but it is sufficient that the first insulating layer 18 covers only the side surface 15S1, and it does not have to be formed on the outer edge of the first region 15R1.
[0077] In this embodiment, the first insulating layer 18 and the second insulating layer 19 are described as being formed apart from each other on the upper surface of the p-type semiconductor layer 15, but it is sufficient that the first insulating layer 18 covers the side surface 15S1, and an embodiment in which the first insulating layer 18 is in contact with the second insulating layer 19 may be used. That is, an embodiment in which the second insulating layer 19 covers most of the second region 15R2 may be used.
[0078] [Method of forming first insulating layer 18 and second insulating layer 19] Hereinafter, a method for forming the first insulating layer 18 and the second insulating layer 19 on the p-type semiconductor layer 15 of the semiconductor structure layer EM formed by the above-mentioned dry etching will be described with reference to FIGS.
[0079] First, as shown in FIG. 7, a lift-off resist R is formed by patterning on the upper surface of the lower portion 13A of the n-type semiconductor layer 13, on the upper surface of the p-type semiconductor layer 15 in the region excluding the edge of the first region 15R1, the second region 15R2, and the third region 15R3, and an insulating layer made of SiN is formed by deposition, sputtering, or the like.
[0080] Next, the resist R formed on the upper surface of the lower portion 13A of the n-type semiconductor layer 13, the area of the upper surface of the p-type semiconductor layer 15 excluding the edge of the first region 15R1, the second region 15R2, and the third region 15R3 is removed by lift-off, thereby forming a first insulating layer 18 covering the edge and side surface 15S1 of the first region 15R1, as shown in FIG. 8.
[0081] Next, as shown in FIG. 9, a resist R for lift-off is formed by patterning in the first region 15R1 and the region excluding the edge of the second region 15R2 on the side surface 15S2 side, and an insulating layer made of SiO2 is formed by deposition, sputtering, or the like.
[0082] Next, the resist R formed in the first region 15R1 and in the region other than the edge of the second region 15R2 on the side 15S2 side is removed by lift-off, thereby forming a second insulating layer 19 covering the third region 15R3 to the side 15S2 of the outer periphery 15P2, as shown in FIG. 10.
[0083] Thereafter, as shown in FIG. 3, a conductive film 21 and a second multilayer film reflector 23 are formed on the upper surface of the p-type semiconductor layer 15, and an n-electrode NE is formed on the lower portion 13A of the n-type semiconductor layer 13, and a p-electrode PE is formed on the upper surface of the conductive film 21, thereby obtaining the surface-emitting laser 100 in this embodiment.
[0084] In this embodiment, the p-type impurities are inactivated by dry etching of the p-type semiconductor layer, but the method of inactivation is not limited to dry etching. For example, the p-type impurities may be inactivated by ion implantation after removing a small amount of the surface of the p-type semiconductor layer, or by ashing. EXAMPLES
[0085] Next, a light emitting device according to Example 2 will be described with reference to Fig. 11 and Fig. 12. Fig. 11 is a top view of light emitting device 200, and Fig. 12 is a cross-sectional view of light emitting device 200 taken along line 12-12 in Fig. 11. Note that in Fig. 12, the vertical direction is the height direction of light emitting device 200.
[0086] The light emitting device 200 is obtained by flip-chip mounting the surface emitting laser 100 according to the first embodiment on a mounting substrate 31 and packaging the same. The light emitting device 200 includes the mounting substrate 31 on which the surface emitting laser 100 is mounted, a frame 37, and a light-transmitting plate 41. The configuration of the surface emitting laser 100 is the same as that of the first embodiment except for the shape of the p-electrode PE.
[0087] The mounting substrate 31 is a plate-like body having a rectangular upper surface shape. The mounting substrate 31 is made of an insulating material such as ceramics such as aluminum nitride (AlN), aluminum oxide (Al2O3), silicon (Si), or silicon carbide (SiC).
[0088] The mounting substrate 31 is provided with through electrodes 32 and 33 that vertically penetrate the mounting substrate 31. The through electrodes 32 and 33 are formed spaced apart from each other on the mounting substrate 31, and are thus insulated from each other. The through electrodes 32 and 33 are made of, for example, gold (Au).
[0089] In the light emitting device 200, the surface emitting laser 100 is flip-chip mounted on the upper surface of the mounting substrate 31 as described above. Specifically, in the surface emitting laser 100, the n-electrode NE is bonded to the through electrode 32 of the mounting substrate 31 via an n-electrode bonding member 34 made of Au and a bonding member 35 made of Au-Sn eutectic bonding, which extend downward in the figure.
[0090] In addition, in the surface-emitting laser 100, the p-electrode PE extends downward in the figure so that its height from the top surface of the mounting substrate 31 is aligned with that of the n-electrode bonding member 34, and is bonded to the through electrode 33 of the mounting substrate 31 via a bonding member 35.
[0091] The frame 37 is formed along the outer edge of the upper surface of the mounting substrate 31, and has an opening 37O that exposes the upper surface of the mounting substrate 31 and the surface-emitting laser 100 mounted on the upper surface of the mounting substrate 31. In other words, in a plan view of the light-emitting device 200 seen from above, the frame 37 surrounds the surface-emitting laser 100 on the mounting substrate 31. Like the mounting substrate 31, the frame 37 is made of an insulating material such as ceramics such as AlN, Al2O3, Si, or SiC.
[0092] The light-transmitting plate 41 is a transparent plate-like body with a rectangular upper surface. The lower surface of the light-transmitting plate 41 is joined to the frame body 37 via a metal layer 42 made of Au formed on the upper surface of the frame body 37 and a joining member 35. In other words, the light-transmitting plate 41 is held by the frame body 37 so as to cover the surface-emitting laser 100. The light-transmitting plate 41 is made of a material having translucency to the light emitted from the surface-emitting laser 100, such as borosilicate glass.
[0093] In the light emitting device 200, light emitted from the surface emitting laser 100 passes through the light-transmitting plate 41 and is emitted to the outside of the light emitting device 200. That is, in this embodiment, the upper surface of the light-transmitting plate 41 is the light emitting surface of the light emitting device 200.
[0094] In the light emitting device 200 of this embodiment, as in the first embodiment, it is possible to prevent the optical output of the surface emitting laser 100 from decreasing even when the electric current is applied for a long period of time. Therefore, according to the light emitting device 200 of this embodiment, the optical output of the laser light emitted from the light emitting device 200 can be stably maintained. [Explanation of symbols]
[0095] 100 Surface-emitting laser (vertical cavity light-emitting device) 200 Light emitting device 11 Substrate 12 First multilayer mirror 13 n-type semiconductor layer 14 Emitting layer 15 p-type semiconductor layer 18 First insulating layer 19 Second insulating layer 21 Conductive film 23 Second multilayer mirror 31 Mounting board 32, 33 Through electrode 34 n-electrode bonding material 35 Joint materials 37 Frame 41 Translucent plate 42 Metal layer NE n electrode PE p electrode
Claims
1. circuit board and A first multilayer reflecting mirror formed on the substrate, A semiconductor structural layer comprising: a first semiconductor layer having a first conductivity type formed on the first multilayer reflecting mirror; an emissive layer formed on the first semiconductor layer; and a second semiconductor layer formed on the emissive layer, having a protrusion projecting upward from the center of its upper surface and having an insulating portion along the region of the upper surface outside the protrusion, and having a second conductivity type opposite to the first conductivity type; A first insulating layer having insulating properties is formed extending from the edge to the side surface of the upper surface of the protrusion of the second semiconductor layer, A transparent conductive film is formed to cover the upper surface of the second semiconductor layer from the upper surface of the protrusion to its peripheral edge, and is electrically connected to the second semiconductor layer. A second multilayer reflecting mirror is formed on the semiconductor structural layer to cover the protruding portion and to constitute a resonator with the first multilayer reflecting mirror, A vertical resonator type light-emitting element characterized by having the following features.
2. The vertical resonator type light-emitting element according to claim 1, characterized in that the first insulating layer is made of a non-oxide material.
3. The vertical resonator type light-emitting element according to claim 1 or 2, characterized in that the first insulating layer has a refractive index close to that of the conductive film.
4. The conductive film is made of ITO, The vertical resonator type light-emitting element according to claim 3, characterized in that the first insulating layer is made of SiN.
5. The vertical resonator type light-emitting element according to claim 1 or 2, characterized in that the side surface of the protruding portion is a surface formed by etching on the upper surface of the second semiconductor layer.
6. The vertical resonator type light-emitting element according to claim 1 or 2, characterized in that it has an electrically insulating second insulating layer formed in the outer region of the upper surface of the second semiconductor layer, separated from the first insulating layer.
7. The second insulating layer is SiO ２ A vertical resonator type light-emitting element according to claim 6, characterized by comprising the above.
8. A vertical resonator type light-emitting element according to claim 1, having a first electrode formed on the first semiconductor layer and a second electrode formed on the conductive film, A mounting substrate electrically connected to the first electrode and the second electrode, A frame formed on the aforementioned mounting substrate and surrounding the vertical resonator type light-emitting element on the aforementioned mounting substrate, A light-transmitting plate held by the frame so as to cover the vertical resonator type light-emitting element, A light-emitting device characterized by having the following features.