Semiconductor device

Abstract

To provide a structure that enables accurate screening of an insulating film of each part included in a trench gate structure.SOLUTION: It has a top electrode 10 electrically connected to p-type body region 3 and n-type impurity region 4, a gate wiring 12 connected to the gate electrode layer 8, and a shield wiring 13 connected to the shield electrode 7. In such a structure, the top electrode 10, gate wiring 12, and shield wiring 13 are electrically separated from each other.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device including a semiconductor switching element having a double-gate trench gate structure. [Background technology]

[0002] Conventionally, a semiconductor device including a power MOSFET having a double-gate trench gate structure as shown in, for example, Patent Document 1 is known. + n-type substrate - A double-gate trench gate structure is formed on the surface layer of the semiconductor substrate on which the type drift layer is formed. In the double-gate trench gate structure, a shield electrode that is at source potential is disposed on the bottom side of the gate trench via a shield insulating film. A gate electrode layer is also disposed on the upper side of the shield electrode in the trench via a gate insulating film, thereby forming a double gate. An interlayer insulating film (hereinafter referred to as an intermediate insulating film) is formed between the shield electrode and the gate electrode layer, and the shield electrode and the gate electrode layer are insulated by the intermediate insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-38240 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above semiconductor device, the shield electrode is designed to have the same potential as the source potential, that is, the upper electrode equivalent to the source electrode and the source region, and the shield wiring connected to the shield electrode is directly connected to the upper electrode. With such a structure, it was found that when screening is performed to ensure the reliability of the insulating films of each part included in the double-gate trench gate structure, it may not be possible to accurately inspect the quality of the insulating films by applying a voltage to each insulating film.

[0005] Although a power MOSFET has been given as an example of a semiconductor switching element having a double-gate trench gate structure, a similar problem also exists for an IGBT (short for insulated gate bipolar transistor).

[0006] The present disclosure aims to provide a structure that enables accurate screening of insulating films of each part included in a trench gate structure in a semiconductor device including a semiconductor switching element having a double-gate trench gate structure. [Means for solving the problem]

[0007] One aspect of the present disclosure is a method for producing a semiconductor device comprising: A semiconductor device including a semiconductor switching element having a double-gate trench gate structure, The semiconductor switching element is A drift layer (2) of a first conductivity type; a body region (3) of a second conductivity type formed on the drift layer; a first conductivity type impurity region (4) formed in a surface layer portion of the body region within the body region and having a higher impurity concentration than the drift layer; a plurality of trench gate structures in which a shield electrode (7), an intermediate insulating film (9), and a gate electrode layer (8) are sequentially stacked, via an insulating film (6), in a plurality of gate trenches (5) arranged in a stripe shape extending from the impurity region through the body region to the drift layer, forming a double gate; a high-concentration layer (1) of a first or second conductivity type that is formed on the opposite side of the drift layer from the body region and has a higher impurity concentration than the drift layer; an interlayer insulating film (11) disposed on the trench gate structure, the body region, and the impurity region; an upper electrode (10) electrically connected to the body region and the impurity region through a contact hole (11a) formed in the interlayer insulating film and connected to the body region and the impurity region; a gate wiring (12) connected to the gate electrode layer through a contact hole (11b) formed in the interlayer insulating film and connected to the gate electrode layer; a shield wiring (13) connected to the shield electrode through a contact hole (11c) formed in the interlayer insulating film and connected to the shield electrode; a lower electrode (15) electrically connected to the high concentration layer, The upper electrode is electrically isolated from the gate wiring and the shield wiring.

[0008] In this way, in the state of the semiconductor device before being incorporated into the circuit, the upper electrode is electrically isolated from the gate wiring and the shield wiring. That is, the upper electrode is electrically isolated from the gate electrode and the shield electrode. Therefore, the potentials of the upper electrode, the shield electrode and the gate electrode can be individually controlled. Therefore, when screening the insulating film and the intermediate insulating film arranged in the gate trench, it becomes possible to apply a desired voltage to the location to be inspected.

[0009] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a top view layout diagram of the semiconductor device according to the first embodiment of the present disclosure. [Figure 2A] FIG. 2 is a cross-sectional view taken along line IIA-IIA in FIG. [Figure 2B] FIG. 2 is a cross-sectional view taken along the line IIB-IIB in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] 2 is a simplified top surface layout of the semiconductor device shown in FIG. 1, showing a conductor portion on the top surface side in a see-through manner. [Diagram 5] 6 is a cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure cut along the longitudinal direction of a trench gate structure. FIG. [Figure 6] 6 is a top surface layout of the semiconductor device shown in FIG. 5, showing a conductor portion on the top surface side in a see-through manner. [Figure 7] FIG. 13 is a simplified top surface layout of a semiconductor device described in a modified example of the second embodiment, showing a conductor portion on the top surface side in a see-through manner. [Figure 8] FIG. 2 is a top view layout diagram of the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] 9 is a simplified top surface layout of the semiconductor device shown in FIG. 8, showing a conductor portion on the top surface side in a see-through manner. [Figure 10] XX cross-sectional view in FIG. 8. [Figure 11] FIG. 13 is a simplified top surface layout of a semiconductor device described in a modified example of the third embodiment, showing a conductor portion on the top surface side in a see-through manner. [Figure 12] FIG. 13 is a simplified top surface layout of a semiconductor device described in a modified example of the third embodiment, showing a conductor portion on the top surface side in a see-through manner. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following, including other embodiments described below, the same reference numerals will be used to denote the same or equivalent parts in each embodiment.

[0012] (First embodiment) A first embodiment will be described. In this embodiment, a semiconductor device including an n-channel type vertical power MOSFET (hereinafter, simply referred to as MOSFET) having a double-gate trench gate structure will be described as an example. The structure of the semiconductor device according to this embodiment will be described below with reference to Figs. 1 to 4.

[0013] 1 to 3, the width direction of the MOSFET is defined as the x direction, the depth direction of the MOSFET intersecting with the x direction is defined as the y direction, and the thickness direction or depth direction of the MOSFET, that is, the normal direction to the xy plane is defined as the z direction. Note that in Fig. 1, a first pad portion 10b, which will be described later, is omitted in order to make the drawing easier to understand.

[0014] As shown in FIGS. 2A and 2B, the semiconductor device according to this embodiment is a n-type semiconductor device made of a semiconductor material such as silicon having a high impurity concentration. + The semiconductor substrate 1 is made of a semiconductor material. + On the surface of the n-type semiconductor substrate 1, + The n-type semiconductor substrate 1 has a lower impurity concentration than the n-type semiconductor substrate 2. - A type drift layer 2 is formed.

[0015] Also, n - A p-type body region 3 having a relatively low impurity concentration is formed at a desired position in the surface layer of the n-type drift layer 2. The p-type body region 3 is, for example, - The p-type body region 3 is formed by ion implantation of p-type impurities into the p-type drift layer 2, and also functions as a channel layer that forms a channel region. As shown in Fig. 1, the p-type body region 3 is formed between a plurality of trench gate structures, which will be described later, with its longitudinal direction aligned in the y direction.

[0016] The surface layer of the p-type body region 3 is -The n-type impurity region 4 corresponds to a source region and has a higher impurity concentration than the n-type drift layer 2. A contact trench 4a is formed in the n-type impurity region 4, and the p-type body region 3 is exposed at the bottom of the contact trench 4a. The exposed portion of the p-type body region 3 is provided with a p + In addition, an n-type contact region 3a is formed on the side surface of the contact trench 4a in the n-type impurity region 4, and an n-type contact region 3b is formed on the side surface of the contact trench 4a. + A mold contact region 4b is formed.

[0017] Also, n - A plurality of gate trenches 5, each extending longitudinally in one direction, are formed in the surface layer portion of the drift layer 2 between the p-type body regions 3 and the n-type impurity regions 4. The gate trenches 5 are used to form a trench gate structure, and in this embodiment, the gate trenches 5 are arranged in parallel at equal intervals to form a striped layout.

[0018] The gate trench 5 is formed to a position deeper than the p-type body region 3, that is, penetrates the n-type impurity region 4 and the p-type body region 3 from the substrate surface side to an n-type impurity region. - The depth of the gate trench 5 reaches the type drift layer 2. In this embodiment, the width of the gate trench 5 gradually narrows toward the bottom, and the bottom has a rounded shape.

[0019] The inner wall surface of the gate trench 5 is covered with an insulating film 6. The insulating film 6 may be composed of a single film, but in this embodiment, it is composed of a shield insulating film 6a covering a lower portion of the gate trench 5 and a gate insulating film 6b covering an upper portion. The shield insulating film 6a covers the side surfaces of the gate trench 5 from the bottom to the lower portion, and the gate insulating film 6b covers the side surfaces of the upper portion of the gate trench 5. In this embodiment, the shield insulating film 6a is formed thicker than the gate insulating film 6b.

[0020] In addition, within the gate trench 5, a shield electrode 7 and a gate electrode layer 8 made of doped Poly-Si are laminated via an insulating film 6 to form a double gate.

[0021] The shield electrode 7 is fixed to the source potential to reduce the capacitance between the gate and drain, and is formed to improve the electrical characteristics of the MOSFET. In addition, the shield electrode 7 allows two-dimensional depletion between multiple trench gate structures, so that the n-type MOSFET can be realized with a smaller number of n-type ... - Even if the thickness of the n-type drift layer 2 is thin, a desired breakdown voltage can be obtained. - Since the drift layer 2 can be made thin, it is possible to realize a low on-resistance. However, in the semiconductor device described in this embodiment, the shield electrode 7 is separated from the source so that a voltage different from that for the source can be applied thereto. The details of this structure will be described later.

[0022] The gate electrode layer 8 performs a switching operation of the MOSFET, and forms a channel region in the p-type body region 3 on the side surface of the gate trench 5 when a gate voltage is applied.

[0023] An intermediate insulating film 9 is formed between the shield electrode 7 and the gate electrode layer 8, and the shield electrode 7 and the gate electrode layer 8 are insulated by the intermediate insulating film 9. The gate trench 5, insulating film 6, shield electrode 7, gate electrode layer 8, and intermediate insulating film 9 constitute a trench gate structure. The trench gate structure is arranged in a stripe-like layout by arranging a plurality of trench gate structures in the x direction, which is the vertical direction of the paper surface of FIG. 1, or the horizontal direction of the paper surface in FIG. 2A and FIG. 2B, with the y direction being the horizontal direction of the paper surface as the longitudinal direction. An n-type impurity region 4 and the like are formed at positions inside both ends of the longitudinal direction of the trench gate structure, and a cell portion that functions as a MOSFET is constituted in that portion. In addition, both end positions of the trench gate structure that are outside the cell portion are set as the outer periphery.

[0024] Furthermore, as shown in FIG. 3, at both ends in the longitudinal direction of the gate trench 5, i.e., at the outer periphery, the shield electrode 7 is extended to the outside of the gate electrode layer 8. The portion protruding out of the gate trench 5 is exposed from the surface side of the p-type body region 3 and the n-type impurity region 4 as a shield liner 7a. The shield liner 7a is formed not only at both ends in the longitudinal direction of the gate trench 5, but also along the gate trench 5 on both sides of the gate trenches 5 as shown in FIG. 1. Specifically, as shown in FIG. 2A, if the outermost one of the gate trenches 5 is called the end trench 5a, the end trench 5a is filled with the shield electrode 7 and the gate electrode layer 8 is not disposed therein. The shield electrode 7 filling the end trench 5a is extended outward from the end trench 5a toward the outside of the gate trenches 5, and this portion is also called the shield liner 7a. In other words, the shield liner 7a is laid out so as to surround the cell portion.

[0025] At both longitudinal ends of each of the gate trenches 5, a tip portion 9a of the intermediate insulating film 9 is disposed between a portion of the shield electrode 7 extending outward beyond the gate electrode layer 8 and the tip of the gate electrode layer 8. The tip portion 9a insulates the shield electrode 7 from the gate electrode layer 8 even at both longitudinal ends of the gate trench 5.

[0026] An interlayer insulating film 11 made of an oxide film or the like is formed so as to cover the gate electrode layer 8, and an upper electrode 10 corresponding to a source electrode, a gate wiring 12, and a shield wiring 13 are formed on the interlayer insulating film 11. The upper electrode 10 is in contact with the p-type body region 3 and the n-type impurity region 4 through a connection part 10a such as a tungsten (W) plug embedded in a contact hole 11a formed in the interlayer insulating film 11, as shown in FIG. 2. In this way, the upper electrode 10 is electrically connected to the n-type impurity region 4 and the p-type body region 3.

[0027] As shown in FIG. 3, the gate wiring 12 is also electrically connected to the gate electrode layer 8 through a connection portion 12a such as a W plug in a contact hole 11b formed in the interlayer insulating film 11. The shield wiring 13 is also electrically connected to the shield electrode 7 through a connection portion 13a such as a W plug in a contact hole 11c formed in the interlayer insulating film 11. As described above, the shield liner 7a is formed so as to surround a cell portion in which a plurality of trench gate structures are formed and which operates as a MOSFET. However, in the case of this embodiment, the shield wiring 13 is formed on the portions of the shield liner 7a located at both ends of the trench gate structure, and is not formed on the portions of the shield liner 7a extending along the longitudinal direction of the trench gate structure. With this structure, the upper electrode 10 and the shield wiring 13 are electrically separated.

[0028] Further, as shown in FIG. 3, a protective film 14 is formed so as to cover the upper electrode 10, the gate wiring 12, the shield wiring 13, and the interlayer insulating film 11. The upper electrode 10, the gate wiring 12, and the shield wiring 13 are electrically isolated from each other via the protective film 14. This is simplified and illustrated as the structure shown in FIG. 4. That is, the gate wiring 12 is extended between the rectangular upper electrode 10 separated into two, and one shield wiring 13 is extended on each of the outer peripheries located on both sides of the two upper electrodes 10 and the gate wiring 12. The gate wiring 12 and the shield wiring 13 are extended along the x direction, and one end side is extended to the outside of the upper electrode 10 in the x direction. Then, at the one end side, the gate wiring 12 is connected to the second pad portion 12b, and the shield wiring 13 is connected to the third pad portion 13b. Also, as shown in FIG. 3, the upper electrode 10 is connected to the first pad portion 10b. The first pad portion 10b is connected to almost the entire surface of the upper electrode 10, and has a rectangular shape similar to the upper electrode 10 as shown in FIG.

[0029] As shown in FIG. 3 and FIG. 4, the first pad portion 10b is electrically connected to the upper electrode 10 through the first opening 14a formed in the protective film 14. Also, as shown in FIG. 4, the second pad portion 12b is formed in the second opening 14b formed in the protective film 14, and the second pad portion 12b is electrically connected to the gate wiring 12. Similarly, the third pad portion 13b is formed in the third opening 14c formed in the protective film 14, and the third pad portion 13b is electrically connected to the shield wiring 13. The upper electrode 10, the gate wiring 12, and the shield wiring 13 are insulated by the protective film 14, and the first pad portion 10b, the second pad portion 12b, and the third pad portion 13b are also formed at positions physically separated from each other. Therefore, they are electrically separated from each other. In other words, the shield electrode 7 is separated from the source, and a voltage different from that of the source can be applied to the shield electrode 7.

[0030] The semiconductor device of this embodiment is used, for example, by being incorporated in an inverter circuit or the like, and in that case, the first pad portion 10b, the second pad portion 12b, and the third pad portion 13b are electrically connected to the outside of the semiconductor device. At this time, although not shown, the first pad portion 10b and the third pad portion 13b are electrically connected by being joined to the same conductor block via a joining material such as solder. Therefore, in the semiconductor device of this embodiment, although the shield electrode 7 is separated from the source and a voltage different from that of the source can be applied, the shield electrode 7 is fixed to the source potential when incorporated in a circuit.

[0031] On the other hand, n + Of the n-type semiconductor substrate 1 - A lower electrode 15 equivalent to a drain electrode is formed on the surface opposite to the type drift layer 2. This constitutes the basic structure of a MOSFET. A cell section is formed by assembling a plurality of MOSFET cells, and a semiconductor device including the MOSFET having the double-gate trench gate structure of this embodiment is constructed.

[0032] The manufacturing method of the semiconductor device according to this embodiment is basically the same as that of a semiconductor device equipped with a power MOSFET having a conventional double-gate trench gate structure, except that the top surface layout is designed so that the upper electrode 10 and the shield wiring 13 are electrically isolated, and the first pad portion 10b and the third pad portion 13b are also electrically isolated.

[0033] As described above, in the state of the semiconductor device before being incorporated into a circuit, the upper electrode 10 is electrically isolated from the gate wiring 12 and the shield wiring 13. In other words, the upper electrode 10 is electrically isolated from the shield electrode 7 and the gate electrode layer 8.

[0034] This makes it possible to individually control the potentials of the upper electrode 10, the shield electrode 7, and the gate electrode layer 8. This makes it possible to apply a desired voltage to a location to be inspected when screening the insulating film 6 and the intermediate insulating film 9 disposed in the gate trench 5.

[0035] For example, three locations, namely, the shield insulating film 6a, the gate insulating film 6b, and the intermediate insulating film 9, are targeted for screening.

[0036] The shield insulating film 6a is screened to check whether the thickness of the shield insulating film 6a, particularly the thickness of the portion located at the bottom of the gate trench 5, meets the voltage resistance design. In this case, a desired voltage is applied to the lower electrode 15, and a desired voltage, for example, a ground potential, is applied to the shield electrode 7 through the third pad portion 13b. This generates a potential difference between the shield electrode 7 and the lower electrode 15, applying a high electric field to the shield insulating film 6a, and checking whether the shield insulating film 6a has any scratches or foreign matter.

[0037] Also, the gate insulating film 6b is screened to check whether its thickness satisfies the voltage resistance design. In this case, a desired voltage is applied to the gate electrode layer 8 through the second pad portion 12b, and a desired voltage, for example, a ground potential, is applied to the upper electrode 10 through the first pad portion 10b. This generates a potential difference between the gate electrode layer 8 and the n-type impurity region 4, applying an electric field to the gate insulating film 6b, and checking whether the gate insulating film 6b has any scratches or foreign matter.

[0038] Furthermore, screening is also performed on the intermediate insulating film 9 to check whether the thickness of the intermediate insulating film 9 meets the voltage resistance design. In this case, a desired voltage is applied to the gate electrode layer 8 through the second pad portion 12b, and a desired voltage, for example, a ground potential, is applied to the shield electrode 7 through the third pad portion 13b. This generates a potential difference between the gate electrode layer 8 and the shield electrode 7, applying an electric field to the intermediate insulating film 9, and checking whether the intermediate insulating film 9 has any scratches or foreign matter.

[0039] In this manner, different voltages can be applied to the shield electrode 7, gate electrode layer 8, and upper electrode 10, respectively, so that screening of the shield insulating film 6a, gate insulating film 6b, and intermediate insulating film 9 can be performed accurately.

[0040] Here, for example, when screening the gate insulating film 6b, if the shield electrode 7 and the upper electrode 10 are electrically connected and have the same potential, screening may not be performed accurately. When screening the gate insulating film 6b, a potential difference is generated between the n-type impurity region 4 or the upper electrode 10 and the gate electrode layer 8, and when the upper electrode 10 and the shield electrode 7 have the same potential, the same potential difference is also generated between the gate electrode layer 8 and the shield electrode 7. For this reason, if the intermediate insulating film 9 is scratched or contaminated with foreign matter, the thickness of the intermediate insulating film 9 becomes thinner than the thickness of the gate insulating film 6b at that portion, and the thinner portion is screened, making it impossible to perform screening accurately.

[0041] In contrast, in the semiconductor device of this embodiment, the shield electrode 7 and the upper electrode 10 are electrically separated and can be at different potentials. Therefore, when screening the gate insulating film 6b, an electric field can be applied appropriately only to the gate insulating film 6b. For example, by controlling the gate electrode layer 8 and the shield electrode 7 to have the same potential while generating a potential difference between the n-type impurity region 4 or the upper electrode 10 and the gate electrode layer 8, it is possible to apply an electric field to the gate insulating film 6b and prevent an electric field from being applied to the intermediate insulating film 9.

[0042] Therefore, in a semiconductor device including a semiconductor switching element having a double-gate trench gate structure, it is possible to perform accurate screening of the insulating film 6 and intermediate insulating film 9 included in the trench gate structure.

[0043] In the semiconductor device of this embodiment, the gate wiring 12 is disposed at the center position in the longitudinal direction of the trench gate structure. That is, the gate wiring 12 is not connected to the gate electrode layer 8 only at one end in the longitudinal direction of the trench gate structure. Therefore, compared to this structure, the semiconductor device of this embodiment can shorten the distance from the gate wiring 12 to the gate electrode layer 8 located at both ends in the longitudinal direction of the trench gate structure. Therefore, when applying a gate voltage to the gate electrode layer 8 during switching of the MOSFET, it is possible to suppress the occurrence of a time delay until the gate voltage is applied to the gate electrode layer 8 located at both ends in the longitudinal direction of the trench gate structure.

[0044] Second embodiment The second embodiment will be described. This embodiment is different from the first embodiment in the layout of the shield wiring 13 and the like, but is otherwise similar to the first embodiment, so only the differences from the first embodiment will be described.

[0045] 5, in the semiconductor device of this embodiment, only one end side in the longitudinal direction of the trench gate structure, here the left end side in the plane of the paper in Fig. 5, is provided with shield wiring 13 and is connected to a shield liner 7a through a connection part 13a. Meanwhile, the other end side in the longitudinal direction of the trench gate structure, here the right end side in the plane of the paper in Fig. 5, is not provided with shield wiring 13 or connection part 13a.

[0046] 6, in this structure, the gate wiring 12 is extended between two separated rectangular upper electrodes 10, and one shield wiring 13 is extended on the outer periphery of the opposite side of the gate wiring 12 sandwiching one of the upper electrodes 10. The shield wiring 13 is extended along the x direction, with one end side extending further outward than the upper electrode 10 in the x direction, and the one end side is connected to the third pad portion 13b.

[0047] In this way, it is possible to have a structure in which the gate wiring 12 and the second pad portion 12b are arranged on one side of one upper electrode 10, and the shield wiring 13 and the third pad portion 13b are arranged on the other side. Even with such a structure, the same effects as in the first embodiment can be obtained.

[0048] (Modification of the second embodiment) In the second embodiment, the shield wiring 13 and the third pad portion 13b are arranged on the left side of the upper electrode 10 when viewing the semiconductor device from above, and the shield electrode 7 is connected to them via the connection portion 13a, as shown in Figures 5 and 6. In contrast to this, the shield wiring 13 and the third pad portion 13b may be arranged on the right side of the upper electrode 10 when viewing the semiconductor device from above, and the shield electrode 7 may be connected to them via the connection portion 13a, as shown in Figure 7.

[0049] In this case, "viewing the semiconductor device from above" refers to a state in which the second pad portion 12b arranged on the outer side of the upper electrode 10 is positioned below the upper electrode 10.

[0050] Third embodiment A third embodiment will be described. This embodiment is similar to the first embodiment except for the layout of the shield wiring 13, etc., and therefore only the differences from the first embodiment will be described.

[0051] 8 and 9, in this embodiment, not only the gate wiring 12 but also the shield wiring 13 are extended between two separated rectangular upper electrodes 10. The shield wiring 13 is arranged on both sides of the gate wiring 12, and a structure is formed in which two shield wirings 13 and one gate wiring 12 are arranged between the two upper electrodes 10.

[0052] As shown in Fig. 8, the shield liner 7a is formed to surround the cell section. The shield wiring 13 is arranged to intersect with each trench gate structure, for example, near the center position of the cell section, and is arranged to overlap a portion of the shield liner 7a that extends along the end trench 5a. In this portion, the shield wiring 13 and the shield liner 7a are connected via a connection portion 13a, as shown in Figs. 8 and 10. On the other hand, the upper electrode 10 and the gate wiring 12 are arranged to partially overlap a portion of the shield liner 7a that extends along the end trench 5a, but are separated and not connected by the interlayer insulating film 11 shown in Fig. 2A and the like.

[0053] In this manner, it is possible to adopt a structure in which one gate wiring 12 and two shield wirings 13 are arranged so as to be sandwiched between two upper electrodes 10. Even with such a structure, it is possible to obtain the same effects as in the first embodiment.

[0054] (Modification of the third embodiment) In the third embodiment, the shield wiring 13 is provided both between the gate wiring 12 and one of the upper electrodes 10 and between the gate wiring 12 and the other upper electrode 10. That is, the gate wiring 12 is sandwiched between two shield wirings 13, but only one of the shield wirings 13 may be provided. Specifically, as shown in FIG. 11 and FIG. 12, a structure may be used in which one shield wiring 13 is arranged along the gate wiring 12, and the one shield wiring 13 and the gate wiring 12 are sandwiched between two separated upper electrodes 10. In that case, when viewed from above the semiconductor device, the one shield wiring 13 and the third pad portion 13b may be arranged on the right side of the gate wiring 12 and the second pad portion 12b as shown in FIG. 11, or on the left side as shown in FIG. 12.

[0055] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0056] (1) For example, in the above embodiment, a high concentration layer, which is a high concentration n-type impurity layer, is formed in the semiconductor substrate 1, and n - By epitaxially growing the type drift layer 2, the high concentration layer and the n - The n-type drift layer 2 is formed on the substrate. - This is merely an example of a case where a high concentration layer is formed on the opposite side of the p-type drift layer 2 from the p-type body region 3. For example, - Alternatively, the type drift layer 2 may be made of a semiconductor substrate, and a high-concentration layer may be formed on one surface thereof by ion implantation or the like.

[0057] (2) In the above embodiment, the p-type body region 3 arranged between the trench gate structures is formed along the y direction, and the n-type impurity region 4 is also formed along the y direction, but this is merely an example. For example, the n-type impurity region 4 may be divided into a plurality of broken line-shaped regions in the y direction. In other words, it is sufficient that the n-type impurity region 4 is formed in a portion of the surface of the p-type body region 3.

[0058] (3) In the above embodiment, the p-type body region 3 is provided at the center in the x direction with a p + and forming an n-type contact region 3a at the center of the n-type impurity region 4 in the x-direction. + However, this is described as a preferred embodiment, and the location of the contact region 4b may be shifted due to the influence of a mask shift or the like, and the contact region 4b may not be formed.

[0059] (4) In each of the above embodiments, the second pad portion 12b and the third pad portion 13b are disposed on the outside in the same direction with respect to the upper electrode 10. In other words, when the semiconductor device is viewed from above, both the second pad portion 12b and the third pad portion 13b are disposed below the upper electrode 10. However, this is merely one example, and a structure in which the third pad portion 13b is disposed on the outside in the opposite direction with respect to the upper electrode 10 as the second pad portion 12b may also be used.

[0060] For example, in the above embodiment, only the first pad portion 10b connected to the upper electrode 10, the second pad portion 12b connected to the gate wiring 12, and the third pad portion 13b connected to the shield wiring 13 are illustrated. However, the semiconductor device may be provided with a temperature detection element, or the cell portion may be divided into a main cell and a sense cell, and the current flowing to the sense cell side may be sensed. In that case, other pad portions such as a pad portion connected to the temperature detection element and a pad portion for sensing the current in the sense cell may also be arranged. In addition, each of these pad portions is connected to the outside of the semiconductor device via a bonding wire or a lead frame, but not all of them are necessarily connected in the same form. For example, the second pad portion 12b may be electrically connected to the outside of the semiconductor device via a bonding wire, and the first pad portion 10b and the third pad portion 13b may be electrically connected to the outside of the semiconductor device via a conductor block. In this case, if the second pad 12b to be wire-bonded is arranged in the opposite direction to the third pad 13b to be bonded to the conductive block, the first pad 10b and the third pad 13b can be bonded to the conductive block without considering the second pad 12b. This allows the conductive block to be simply rectangular in shape, simplifying its shape.

[0061] (5) In the above embodiment, a MOSFET having an n-channel type trench gate structure in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example of a semiconductor switching element. However, this is merely an example, and a semiconductor switching element having another structure, for example, a MOSFET having a p-channel type trench gate structure in which the conductivity type of each component is inverted from that of an n-channel type, may be used. Furthermore, the present disclosure can be applied to an IGBT having a similar structure in addition to a MOSFET. In the case of an IGBT, it is the same as the MOSFET described in the above embodiment, except that the conductivity type of the semiconductor substrate 1 is changed from n-type to p-type. [Explanation of symbols]

[0062] 1...semiconductor substrate, 2...n - p-type drift layer, 3...p-type body region, 3a...p+ n-type contact region, 4...n-type impurity region, 4a...contact trench, 4b...n + Die contact region, 5...gate trench, 6...insulating film, 6a...shield insulating film, 6b...gate insulating film, 7...shield electrode, 7a...shield liner, 8...gate electrode layer, 9...intermediate insulating film, 10...upper electrode, 10a...connecting portion, 10b...first pad portion, 11...interlayer insulating film, 11a to 11c...contact holes, 12...gate wiring, 12a...connecting portion, 12b...second pad portion, 13...shield wiring, 13a...connecting portion, 13b...third pad portion, 14...protective film, 14a to 14c...first to third openings, 15...lower electrode

Claims

1. A semiconductor device including a semiconductor switching element having a double-gate trench gate structure, The semiconductor switching element is a drift layer (2) of a first conductivity type; a body region (3) of a second conductivity type formed on the drift layer; a first conductivity type impurity region (4) formed in a surface layer portion of the body region within the body region and having a higher impurity concentration than the drift layer; a plurality of trench gate structures in which a shield electrode (7), an intermediate insulating film (9), and a gate electrode layer (8) are sequentially stacked via an insulating film (6) in each of a plurality of gate trenches (5) arranged in a stripe shape with one direction as the longitudinal direction and extending from the impurity region through the body region to the drift layer, forming a double gate; a first or second conductivity type high concentration layer (1) formed on the opposite side of the drift layer from the body region and having a higher impurity concentration than the drift layer; an interlayer insulating film (11) disposed on the trench gate structure, the body region, and the impurity region; an upper electrode (10) electrically connected to the body region and the impurity region through a contact hole (11a) formed in the interlayer insulating film and connected to the body region and the impurity region; a gate wiring (12) connected to the gate electrode layer through a contact hole (11b) formed in the interlayer insulating film and connected to the gate electrode layer; a shield wiring (13) connected to the shield electrode through a contact hole (11c) formed in the interlayer insulating film and connected to the shield electrode; a lower electrode (15) electrically connected to the high concentration layer, the upper electrode is electrically isolated from the gate wiring and the shield wiring, both end positions in the longitudinal direction of the plurality of gate trenches are defined as an outer periphery portion, and the inside of the outer periphery portion is defined as a cell portion, and the body region and the impurity region are formed in the cell portion to configure the semiconductor switching element, The gate electrode is not formed in the outermost end trench (5 a) of the plurality of gate trenches, and the shield electrode is embedded therein; the shield electrode includes, at the outer periphery, a shield liner (7a) having a portion extending outward from the gate electrode layer and protruding outward from the plurality of gate trenches, and a portion extending outward from the end trench toward the outside of the plurality of gate trenches, the gate wiring is provided at a center position of the plurality of gate trenches in a longitudinal direction thereof, and extends in a direction intersecting the plurality of gate trenches; the upper electrodes are disposed on both sides of the gate wiring, the shield wiring extends in a direction intersecting the plurality of gate trenches at least either between the gate wiring and one of the upper electrodes or between the gate wiring and the other of the upper electrodes.

2. a protective film (14) is formed on the interlayer insulating film, the upper electrode, the gate wiring, and the shield wiring; a first pad portion (10b) electrically connected to the upper electrode through a first opening (14a) formed in the protective film; a second pad portion (12b) electrically connected to the gate wiring through a second opening (14b) formed in the protective film; a third pad portion (13b) electrically connected to the shield wiring through a third opening (14c) formed in the protective film, 2. The semiconductor device according to claim 1, wherein said first pad portion, said second pad portion and said third pad portion are electrically isolated from each other.

3. the second pad portion is disposed outside the first pad portion in one direction intersecting the plurality of gate trenches, 3. The semiconductor device according to claim 2, wherein said third pad portion is also disposed further outward than said first pad portion in one direction intersecting said plurality of gate trenches.

4. the second pad portion is disposed outside the first pad portion in one direction intersecting the plurality of gate trenches, 3. The semiconductor device according to claim 2, wherein said third pad portion is disposed further outward than said first pad portion in another direction intersecting said plurality of gate trenches.

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