Receiver circuit, semiconductor device, and communication system

Abstract

To provide a receiver circuit which stabilizes variations in DC potential of the receiver circuit of an AC coupling system.SOLUTION: A receiver circuit 121 of an AC coupling system comprises: a first input end IN1 which inputs a first signal 41 transmitted via a first capacitive element 1; a second input end IN2 which inputs a second signal 42 which is transmitted via a second capacitive element 2 and has the potential changed in a complementary manner with respect to the first signal; a signal output circuit 12 which outputs a first logic signal 51 corresponding to a potential of the first signal and a second logic signal 52 corresponding to the potential of the second signal; and a signal supply circuit 122 which supplies a first guarantee signal 61 of a potential corresponding to a value of the first logic signal to the first input end as a signal guaranteeing the potential of the first signal and supplies a second guarantee signal 62, which has the potential changed in the complementary manner with respect to the first guarantee signal, to the second input end as a signal guaranteeing the potential of the second signal.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a receiving circuit, a semiconductor device, and a communication system. [Background technology]

[0002] Patent Document 1 discloses a receiving circuit that receives data using differential signals, which are balanced signals transmitted by an AC (Alternating Current) coupling method (see FIG. 4 of Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2001-503182 Summary of the Invention [Problem to be solved by the invention]

[0004] In the AC coupling method, a capacitive element that removes DC signals is placed in the transmission path. Therefore, while the data input to the receiving circuit is constantly changing, the charge and discharge of the capacitive element is repeated, causing the potentials of the two signals that change in a complementary manner and are included in the differential signal to change to H level or L level. Therefore, the receiving circuit can operate normally according to the differential signal.

[0005] However, if the input data does not change for a certain period of time, the energy stored in the capacitive element continues to be discharged, and the potentials of the two signals may become approximately the same level. Therefore, the receiving circuit cannot detect the potential of the differential signal, and may malfunction. Thus, the conventional technology has room for improvement in terms of realizing stable operation of the receiving circuit.

[0006] In consideration of the above circumstances, an object of the present disclosure is to provide a receiving circuit capable of achieving stable operation. [Means for solving the problem]

[0007] In order to solve the above problems, the receiving circuit disclosed herein is an AC-coupled receiving circuit having a first input terminal for inputting a first signal transmitted via a first capacitive element and a second input terminal for inputting a second signal transmitted via a second capacitive element and whose potential changes complementarily to the first signal, and is equipped with a signal output circuit for outputting a first logic signal corresponding to the potential of the first signal and a second logic signal corresponding to the potential of the second signal, and a signal supply circuit for supplying a first guarantee signal of a potential corresponding to the value of the first logic signal to the first input terminal as a signal for guaranteeing the potential of the first signal, and for supplying a second guarantee signal of a potential that changes complementarily to the first guarantee signal to the second input terminal as a signal for guaranteeing the potential of the second signal.

[0008] A semiconductor device according to the present disclosure includes the above-described receiving circuit.

[0009] The communication system according to the present disclosure comprises a first semiconductor device having a transmitting circuit that transmits the first signal and the second signal, and a second semiconductor device having the above-mentioned receiving circuit, wherein the first signal is supplied to the receiving circuit via the first capacitive element, and the second signal is supplied to the receiving circuit via the second capacitive element. Effect of the Invention

[0010] According to the present disclosure, it is possible to provide a receiving circuit capable of achieving stable operation. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing a configuration of a display device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating a configuration of a communication system according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a diagram showing a configuration of a signal output circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram for explaining the operation of the signal output circuit. [Diagram 5]FIG. 5 is a timing chart for explaining the operation of the signal output circuit. [Figure 6] FIG. 6 is a timing chart for explaining the operation of the signal output circuit. [Figure 7] FIG. 7 is a diagram showing a communication system according to a comparative example. [Figure 8] FIG. 8 is a timing chart for explaining the operation of the signal output circuit according to the comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and the description thereof will be omitted as appropriate.

[0013] [Embodiment] (display device) 1 is a diagram showing a configuration of a display device according to an embodiment of the present disclosure. The display device 100 may be interpreted as a vehicle display device mounted on an automobile or the like. The display device 100 includes a display panel 10, a timing controller 11, a driver IC (Integrated Circuit) 12, and a gate driver 13.

[0014] The display panel 10 may be interpreted as an image display device such as a liquid crystal display panel, an organic EL (Electro Luminescence) panel, etc. The timing controller 11 may control the display timing of an image on the display panel 10 by controlling a plurality of driver ICs 12 and a gate driver 13. The timing controller 11 may generate a clock signal and supply it to the driver IC 12. The timing controller 11 may supply a scanning control signal synchronized with video data to the gate driver 13.

[0015] The driver IC 12 may be interpreted as a semiconductor device including a receiving circuit, which will be described later. The driver IC 12 controls the lighting state of a plurality of light-emitting elements provided on the display panel 10.

[0016] The gate driver 13 may generate a gate signal based on the signal supplied from the timing controller 11 and supply the gate signal to the display panel 10 .

[0017] The timing controller 11 and the driver IC 12 may constitute a communication system 200. The communication system 200 may be interpreted as a system to which mini-LVDS (Low Voltage Differential Signaling) is applied. Mini-LVDS may be interpreted as an interface standard for connecting a liquid crystal controller and a liquid crystal driver.

[0018] Next, a configuration of a communication system 200 will be described with reference to Fig. 2. Fig. 2 is a diagram showing a configuration of a communication system according to an embodiment of the present disclosure. The communication system 200 includes a timing controller 11 and a signal output circuit 12. The timing controller 11 and the signal output circuit 12 are communicatively connected via a transmission path 3.

[0019] The timing controller 11 includes a transmission circuit 111. The transmission circuit 111 may be interpreted as a circuit that transmits data using a differential signal 4. The differential signal 4 includes two signals that change in a complementary manner. Specifically, the differential signal 4 includes a first signal 41 transmitted through a first capacitive element 1 arranged on the transmission line 3, and a second signal 42 transmitted through a second capacitive element 2 arranged on the transmission line 3. The second signal 42 may be interpreted as a signal whose potential changes in a complementary manner to the first signal 41.

[0020] The signal output circuit 12 includes a receiving circuit 121 and a signal supplying circuit 122 .

[0021] The receiving circuit 121 may be interpreted as an AC-coupled data receiving circuit to which the differential signal 4 transmitted via a capacitive element is supplied. The AC-coupled method may be interpreted as a method for removing the DC component of the input signal and transmitting only the AC component to the receiving circuit 121. The receiving circuit 121 has a first input terminal IN1 for inputting a first signal 41 and a second input terminal IN2 for inputting a second signal 42.

[0022] The receiving circuit 121 outputs a first logic signal 51 corresponding to the potential of the first signal 41 and a second logic signal 52 corresponding to the potential of the second signal 42. Specifically, the receiving circuit 121 amplifies the first signal 41 and the second signal 42, and outputs the first logic signal 51 and the second logic signal 52 having higher voltage levels than the first signal 41 and the second signal 42.

[0023] The first logic signal 51 is transmitted to the display panel 10 shown in FIG.

[0024] The second logic signal 52 is transmitted to the display panel 10 shown in FIG.

[0025] The signal supply circuit 122 may be interpreted as a circuit for guaranteeing the potential of the first signal 41 and the potential of the second signal 42. The signal supply circuit 122 includes a first input terminal S1 for inputting a first logic signal 51, a second input terminal S2 for inputting a second logic signal 52, a first output terminal Q1 for outputting a first guarantee signal, and a second output terminal Q2 for outputting a second guarantee signal.

[0026] The signal supply circuit 122 may supply a first assurance signal having a potential corresponding to the value of the first logic signal 51 to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1 as a signal for guaranteeing the potential of the first signal 41. The signal supply circuit 122 may also supply a second assurance signal, the potential of which changes complementarily to the first assurance signal, to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2 as a signal for guaranteeing the potential of the second signal 42.

[0027] Next, a specific configuration of the signal output circuit 12 will be described with reference to Fig. 3. Fig. 3 is a diagram showing the configuration of a signal output circuit according to an embodiment of the present disclosure.

[0028] As shown in FIG. 3, the receiving circuit 121 includes a first differential amplifier circuit 121a and a second differential amplifier circuit 121b.

[0029] A first signal 41 is input to the first differential amplifier circuit 121a via a first input terminal IN1, and a second signal 42 is input to the first differential amplifier circuit 121a via a second input terminal IN2. The output of the first differential amplifier circuit 121a is input to the second differential amplifier circuit 121b. The second differential amplifier circuit 121b amplifies the input signal and outputs it as a first logic signal 51 and a second logic signal 52.

[0030] When the signal supply circuit 122 supplies a first assurance signal 61 of the first potential VH to the first input terminal IN1 of the receiving circuit 121, the signal supply circuit 122 supplies a second assurance signal 62 of a second potential VL lower than the first potential VH to the second input terminal IN2 of the receiving circuit 121. When the signal supply circuit 122 supplies the first assurance signal 61 of the second potential VL to the first input terminal IN1 of the receiving circuit 121, the signal supply circuit 122 supplies the second assurance signal 62 of the first potential VH to the second input terminal IN2 of the receiving circuit 121. The first potential VH and the second potential VL may be interpreted as reference voltages with suppressed current supply capabilities.

[0031] Specifically, the signal supply circuit 122 includes a voltage dividing circuit 122a and a plurality of switches, including a first switch 122b1, a second switch 122b2, a third switch 122b3, and a fourth switch 122b4.

[0032] The voltage divider circuit 122a may be interpreted as a circuit that generates the first potential VH or the second potential VL by dividing a voltage applied to a resistor disposed between two power supplies (VDD, VSS). By using the voltage divider circuit 122a, it is possible to generate the first potential VH or the second potential VL with a simple configuration by using a power supply common to the two power supplies (VDD, VSS) supplied to the receiving circuit 121.

[0033] The signal supply circuit 122 may include a power supply that outputs the first potential VH or the second potential VL, instead of the voltage dividing circuit 122a including a resistor.

[0034] When the value of the first logic signal 51 is a specific potential, the first switch 122b1 is turned on to supply the first assurance signal 61 of the first potential VH to the first input terminal IN1. Specifically, when the value of the first logic signal 51 applied to the first input terminal S1 is at an H level, the first switch 122b1 is turned on to supply the first assurance signal 61 of the first potential VH to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1.

[0035] When the value of the first logic signal 51 applied to the first input terminal S1 is at the L level, the first switch 122b1 is turned off, thereby stopping the output of the first guarantee signal 61 at the first potential VH.

[0036] When the value of the second logic signal 52 is a specific potential, the second switch 122b2 is turned on to supply the second assurance signal 62 of the first potential VH to the second input terminal IN2. Specifically, when the value of the second logic signal 52 applied to the second input terminal S2 is at an H level, the second switch 122b2 is turned on to supply the second assurance signal 62 of the first potential VH to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2.

[0037] When the value of the second logic signal 52 applied to the second input terminal S2 is at the L level, the second switch 122b2 is turned off, thereby stopping the output of the second guarantee signal 62 at the first potential VH.

[0038] When the value of the second logic signal 52 is a specific potential, the third switch 122b3 is turned on to supply the first assurance signal 61 of the second potential VL to the first input terminal IN1. Specifically, when the value of the second logic signal 52 applied to the second input terminal S2 is at an H level, the third switch 122b3 is turned on to supply the first assurance signal 61 of the second potential VL to the first input terminal IN1 of the receiving circuit 121 via the first output terminal Q1.

[0039] When the value of the second logic signal 52 applied to the second input terminal S2 is at the L level, the third switch 122b3 is turned off, thereby stopping the output of the second guarantee signal 62 at the second potential VL.

[0040] When the value of the first logic signal 51 is a specific potential, the fourth switch 122b4 is turned on to supply the second assurance signal 62 of the second potential VL to the second input terminal IN2. Specifically, when the value of the first logic signal 51 applied to the first input terminal S1 is at an H level, the fourth switch 122b4 is turned on to supply the second assurance signal 62 of the second potential VL to the second input terminal IN2 of the receiving circuit 121 via the second output terminal Q2.

[0041] When the value of the first logic signal 51 applied to the first input terminal S1 is at the L level, the fourth switch 122b4 is turned off, thereby stopping the output of the second guarantee signal 62 at the second potential VL.

[0042] (Signal output circuit operation) Next, the operation of the signal output circuit 12 will be described with reference to Figures 4, 5 and 6. Figure 4 is a diagram for explaining the operation of the signal output circuit.

[0043] State "1" in FIG. 4 represents the following state. (1) The value of the first logic signal 51 applied to the first input terminal S1 is at the H level. (2) The value of the second logic signal 52 applied to the second input terminal S2 is at the L level. (3) The first switch 122b1 is in the on state. (4) The second switch 122b2 is in the off state. (5) The third switch 122b3 is in the off state. (6) The fourth switch 122b4 is in the on state. (7) The potential applied to the first output terminal Q1 is the first potential VH. (8) The potential applied to the second output terminal Q2 is the second potential VL.

[0044] State "2" shown in FIG. 4 represents the following state. (1) The value of the first logic signal 51 applied to the first input terminal S1 is at the L level. (2) The value of the second logic signal 52 applied to the second input terminal S2 is at the H level. (3) The first switch 122b1 is in the off state. (4) The second switch 122b2 is in the on state. (5) The third switch 122b3 is in the on state. (6) The fourth switch 122b4 is in the off state. (7) The potential applied to the first output terminal Q1 is the second potential VL. (8) The potential applied to the second output terminal Q2 is the first potential VH.

[0045] Figures 5 and 6 are timing charts for explaining the operation of the signal output circuit. Figure 5 shows the first logic signal 51, the second logic signal 52, etc. when the data input to the receiving circuit 121, that is, the output data of the transmitting circuit 111, keeps changing. Figure 6 shows the first logic signal 51, the second logic signal 52, etc. when the output data does not change for a certain period of time.

[0046] The first signal 41 input to the first input terminal IN1 and the first logic signal 51 output from the first output terminal OUT1 are in phase. The second signal 42 input to the second input terminal IN2 and the second logic signal 52 output from the second output terminal OUT2 are in phase. The first signal 41 and the second signal 42 are in opposite phase.

[0047] 5 and 6, the following signals are shown in order from top to bottom: (1) The voltage levels of the first signal 41 and the second signal 42, which are data output from the transmission circuit 111. (2) The voltage levels of the first signal 41 and the second signal 42, which are data input to the receiving circuit 121. (3) The voltage level of the first logic signal 51, which is the data output from the first output terminal OUT1. (4) The voltage level of the second logic signal 52, which is the data output from the second output terminal OUT2. (5) The state of the first switch 122b1. (6) The state of the second switch 122b2. (7) The state of the third switch 122b3. (8) The state of the fourth switch 122b4. (9) The voltage level at the first output terminal Q1. (10) The voltage level of the second output terminal Q2. (11) A number corresponding to the “status” shown in Figure 4.

[0048] (When the output data is constantly changing) 5, when the first signal 41 is at H level and the second signal 42 is at L level during the period from time t1 to time 2, the first logic signal 51 is at H level and the second logic signal 52 is at L level, the first switch 122b1 is on and the second switch 122b2 is off. The third switch 122b3 is off and the fourth switch 122b4 is on. As a result, the first potential VH from the voltage dividing circuit 122a is input to the first input terminal IN1 via the first output terminal Q1. The second potential VL from the voltage dividing circuit 122a is input to the second input terminal IN2 via the second output terminal Q2.

[0049] When the first signal 41 is at L level and the second signal 42 is at H level during the period from time t2 to time 3, the first logic signal 51 is at L level and the second logic signal 52 is at H level, the first switch 122b1 is off and the second switch 122b2 is on. The third switch 122b3 is on and the fourth switch 122b4 is off. As a result, the second potential VL from the voltage dividing circuit 122a is input to the first input terminal IN1 via the first output terminal Q1. The first potential VH from the voltage dividing circuit 122a is input to the second input terminal IN2 via the second output terminal Q2.

[0050] If the first signal 41 changes to an H level and the second signal 42 changes to an L level at time t3, then from time t3 to time 4, the first potential VH is input to the first input terminal IN1 and the second potential VL is input to the second input terminal IN2, similar to the period from time t1 to time 2.

[0051] (When the output data does not change for a certain period of time) 6, the output data does not change for a certain period of time from time t2 to time 3. Even when the output data does not change in this way, when the first signal 41 goes to L level and the second signal 42 goes to H level at time t2, the first logic signal 51 goes to L level and the second logic signal 52 goes to H level. As a result, the first switch 122b1 is turned off and the second switch 122b2 is turned on. In addition, the third switch 122b3 is turned on and the fourth switch 122b4 is turned off.

[0052] Therefore, the second potential VL is input to the first input terminal IN1 through the first output terminal Q1. Also, the first potential VH is input to the second input terminal IN2 through the second output terminal Q2. Then, these first potential VH and second potential VL continue to be output until time t3. Specifically, the potential of the first signal 41 transmitted through the first capacitive element 1 and the potential of the second signal 42 transmitted through the second capacitive element 2 are guaranteed until time t3. More specifically, even in a situation where the potentials of the first signal 41 and the second signal 42 input to the receiving circuit 121 may drop due to the energy stored in the capacitive element continuing to be discharged because the input data does not change for a certain period of time, the potentials of the first signal 41 and the second signal 42 input to the receiving circuit 121 can be guaranteed by adding the first potential VH or the second potential VL to these signals.

[0053] (Comparative Example) Fig. 7 is a diagram showing a communication system according to a comparative example. A difference from the communication system 200 shown in Fig. 2 is that the communication system 200A shown in Fig. 7 includes a signal output circuit 12A instead of the signal output circuit 12. The signal output circuit 12A does not include the signal supply circuit 122 shown in Fig. 2, and only includes a receiving circuit 121.

[0054] 8 is a timing chart for explaining the operation of the signal output circuit according to the comparative example, in which the following signals are shown in order from top to bottom: (1) The voltage levels of the first signal 41 and the second signal 42, which are data output from the transmission circuit 111. (2) The voltage levels of the first signal 41 and the second signal 42, which are data input to the receiving circuit 121. (3) The voltage level of the first logic signal 51, which is the data output from the first output terminal OUT1. (4) The voltage level of the second logic signal 52, which is the data output from the second output terminal OUT2.

[0055] As described above, in the AC coupling method, a capacitive element is placed in the transmission path in order to remove DC signals, and therefore the capacitive element is repeatedly charged and discharged while the data input to the receiving circuit 121 continues to change. In this case, the potentials of the two signals that change complementarily to each other and are included in the differential signal 4, that is, the first signal 41 and the second signal 42, change to H level or L level within a certain period of time. Therefore, the receiving circuit 121 can operate normally in accordance with the differential signal 4.

[0056] On the other hand, if the data does not change for a certain period of time, the energy stored in the capacitance element continues to be discharged, and the potentials of the first signal 41 and the second signal 42 may drop and become approximately the same level during the period from time t2a to time t3 in Fig. 8. In other words, the first signal 41 and the second signal 42 may become stuck to each other. As a result, the potentials of the first logic signal 51 and the second logic signal 52 of the receiving circuit 121 also drop, making the output of the receiving circuit 121 unstable.

[0057] (Action and effect) As shown in FIG. 3 , the signal output circuit 12 according to an embodiment of the present disclosure includes a signal supply circuit 122 that supplies a first assurance signal 61 having a potential corresponding to the value of a first logic signal 51 to a first input terminal IN1 as a signal for guaranteeing the potential of a first signal 41, and supplies a second assurance signal 62, the potential of which changes complementarily to the first assurance signal 61, to a second input terminal as a signal for guaranteeing the potential of a second signal 42.

[0058] With this configuration, even in a situation where the potentials of the first signal 41 and the second signal 42 may drop because the data from the transmission circuit 111 does not change for a certain period of time, the potentials of the first signal 41 and the second signal 42 can be guaranteed by the guarantee signal from the signal supply circuit 122. Therefore, since the potentials of the first logic signal 51 and the second logic signal 52 of the reception circuit 121 are guaranteed, accurate data transfer can be achieved even if data is not transmitted between the transmission circuit 111 and the reception circuit 121 for a certain period of time using the AC coupling method.

[0059] Furthermore, when LVDS is applied to the communication system 200 of the present disclosure, high-speed serial transfer can be realized by guaranteeing the potentials of the first logic signal 51 and the second logic signal 52. By realizing high-speed serial transfer, the number of wirings between the transmitting circuit 111 and the receiving circuit 121 can be reduced, and the manufacturing cost of the board associated with the wiring can be reduced. Since LVDS is a differential current mode interface, it has high resistance to external noise and can also reduce crosstalk noise.

[0060] In addition, the following supplementary notes are provided in relation to the above description.

[0061] (Appendix 1) a signal output circuit that outputs a first logic signal corresponding to a potential of the first signal and a second logic signal corresponding to a potential of the second signal; and a signal supply circuit that supplies a first assurance signal of a potential corresponding to a value of the first logic signal to the first input terminal as a signal that guarantees the potential of the first signal, and supplies a second assurance signal of a potential that changes complementarily to the first assurance signal to the second input terminal as a signal that guarantees the potential of the second signal.

[0062] (Appendix 2) The receiving circuit of claim 1, wherein when the signal supply circuit supplies the first assurance signal of a first potential to the first input terminal, it supplies the second assurance signal of a second potential lower than the first potential to the second input terminal, and when the signal supply circuit supplies the first assurance signal of the second potential to the first input terminal, it supplies the second assurance signal of the first potential to the second input terminal.

[0063] (Appendix 3) 3. The receiving circuit according to claim 1, wherein the signal supply circuit includes a voltage divider circuit that generates the first potential or the second potential by dividing a voltage applied to a resistor disposed between two power sources.

[0064] (Appendix 4) The receiving circuit of any one of Appendix 1 to 3, wherein the signal supply circuit comprises: a first switch that is turned on to supply the first assurance signal of the first potential to the first input terminal when the value of the first logic signal is a specific potential; a second switch that is turned on to supply the second assurance signal of the first potential to the second input terminal when the value of the second logic signal is a specific potential; a third switch that is turned on to supply the first assurance signal of the second potential to the first input terminal when the value of the second logic signal is a specific potential; and a fourth switch that is turned on to supply the second assurance signal of the second potential to the second input terminal when the value of the first logic signal is a specific potential.

[0065] (Appendix 5) A semiconductor device comprising the receiving circuit according to any one of claims 1 to 4.

[0066] (Appendix 6) 6. A communication system comprising: a first semiconductor device having a transmitting circuit for transmitting the first signal and the second signal according to any one of Supplementary notes 1 to 5; and a second semiconductor device having a receiving circuit according to any one of Supplementary notes 1 to 5, wherein the first signal is supplied to the receiving circuit via the first capacitive element, and the second signal is supplied to the receiving circuit via the second capacitive element. [Explanation of symbols]

[0067] 1 First Capacitor 2 Second Capacitor 3 Transmission Line 4 Differential Signals 10 Display Panel 11 Timing Controller 12 Signal output circuit 12A signal output circuit 13 Gate Driver 41 First Signal 42 2nd Signal 51 First logic signal 52 Second logic signal 61 First Guarantee Signal 62 Second Guarantee Signal 100 display device 111 Transmitting circuit 121 Receiver circuit 121a First differential amplifier circuit 121b Second differential amplifier circuit 122 Signal supply circuit 122a Voltage divider circuit 122b1 1st switch 122b2 Second switch 122b3 3rd switch 122b4 4th switch 200 Communication Systems 200A Communication System

Claims

1. An AC-coupled receiving circuit, a signal output circuit having a first input terminal for inputting a first signal transmitted via a first capacitive element, and a second input terminal for inputting a second signal transmitted via a second capacitive element, the second signal having a potential that changes complementarily to the first signal, and outputting a first logic signal corresponding to the potential of the first signal and a second logic signal corresponding to the potential of the second signal; a signal supply circuit that supplies a first assurance signal of a potential corresponding to a value of the first logic signal to the first input terminal as a signal to guarantee the potential of the first signal, and supplies a second assurance signal of a potential that changes complementarily to the first assurance signal to the second input terminal as a signal to guarantee the potential of the second signal.

2. The signal supply circuit includes: when the first assurance signal having a first potential is supplied to the first input terminal, the second assurance signal having a second potential lower than the first potential is supplied to the second input terminal; 2 . The receiving circuit according to claim 1 , wherein when the first assurance signal of the second potential is supplied to the first input terminal, the second assurance signal of the first potential is supplied to the second input terminal.

3. 3. The receiving circuit according to claim 2, wherein the signal supply circuit includes a voltage divider circuit that generates the first potential or the second potential by dividing a voltage applied to a resistor disposed between two power sources.

4. The signal supply circuit includes: a first switch that is turned on when the value of the first logic signal is a specific potential, thereby supplying the first assurance signal of the first potential to the first input terminal; a second switch that is turned on when the value of the second logic signal is a specific potential, thereby supplying the second assurance signal of the first potential to the second input terminal; a third switch that is turned on when the value of the second logic signal is a specific potential, thereby supplying the first assurance signal of the second potential to the first input terminal; a fourth switch that is turned on when the value of the first logic signal is a specific potential, to supply the second assurance signal of the second potential to the second input terminal; The receiving circuit of claim 3 .

5. A semiconductor device comprising the receiving circuit according to claim 1.

6. a first semiconductor device having a transmission circuit that transmits the first signal and the second signal; a second semiconductor device having the receiving circuit according to claim 1; a first capacitance element connected to the first capacitive element, and a second capacitance element connected to the second capacitive element, the first signal being supplied to the receiving circuit;

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