Processor

Abstract

To improve the treatment performance of a processor that executes a load instruction that loads multiple pieces of data into multiple registers in a register file at once while suppressing the increase in the circuit scale.SOLUTION: A processor has: an arithmetic pipeline that includes an operator; a load pipeline that reads first data and second data from a memory in parallel and outputs them based on a first load instruction; a selector that selects the second data when the second data is output from the load pipeline and selects the output of the operator when the second data is not output from the load pipeline; and a register file that includes a first port and a second port that receive data from the load pipeline and the selector, respectively, and multiple registers that hold the data received at the first or second port, wherein the first and second data are stored in different registers from each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a processor. [Background technology]

[0002] There is known a processor that executes a single instruction to access multiple locations in a memory area. In this type of processor, a reservation station executes multiple memory accesses based on the decoding of a single multi-data indirect load instruction by a decoder (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-203950 A Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in a load instruction that loads multiple pieces of data into multiple registers of a register file at once, if a pipeline executes multiple flows that load multiple pieces of data, the processing performance of the instruction decreases. Also, when multiple pieces of data are loaded into multiple registers at once, the register file is provided with write ports for the number of pieces of data to be loaded, which increases the circuit scale.

[0005] In one aspect, the present invention aims to improve the processing performance of a processor that executes a load instruction to load a plurality of data items into a plurality of registers of a register file at once, while suppressing an increase in the circuit scale. [Means for solving the problem]

[0006] According to one aspect, a processor has an arithmetic pipeline including an arithmetic unit that executes an arithmetic instruction and outputs arithmetic result data; a load pipeline that reads first data and second data in parallel from a memory based on a first load instruction and outputs the read first data and second data; a selector that selects the second data when the second data is output from the load pipeline and selects the output of the arithmetic unit when the second data is not output from the load pipeline; and a register file including a first port that receives the first data from the load pipeline, a second port that receives data from the selector, and a plurality of registers that hold data received at the first port or the second port, wherein the first data and the second data are stored in mutually different registers. Effect of the Invention

[0007] The processing performance of a processor that executes a load instruction for loading a plurality of pieces of data into a plurality of registers of a register file at once can be improved while suppressing an increase in the circuit scale. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processor in one embodiment. [Diagram 2] 2 is an explanatory diagram showing an overview of an operation when the processor in FIG. 1 executes a first load instruction; FIG. [Diagram 3] FIG. 13 is a block diagram illustrating an example of another processor. [Figure 4] FIG. 4 is a block diagram showing an example of a GPR renaming table of FIG. 3. [Diagram 5] 4 is an explanatory diagram showing an example of an operation when the processor in FIG. 3 executes a load instruction LDP; FIG. [Figure 6] 4 is an explanatory diagram showing an example of pipeline processing of a load store unit when the processor of FIG. 3 executes an LDR instruction and an LDP instruction, respectively. [Figure 7]FIG. 4 is an explanatory diagram illustrating an example of a pipeline related to an LDR instruction executed by the processor of FIG. [Figure 8] 4 is an explanatory diagram showing an example of pipeline processing of an arithmetic instruction executed by the processor of FIG. 3; [Figure 9] FIG. 11 is a block diagram illustrating an example of a processor according to another embodiment. [Figure 10] FIG. 10 is an explanatory diagram illustrating an example of a pipeline related to an LDP instruction executed by the processor of FIG. [Figure 11] 10 is an explanatory diagram showing an example of pipeline processing when an LDP instruction and an arithmetic instruction are executed in parallel in the processor of FIG. 9; FIG. [Figure 12] 10 is an explanatory diagram showing an example of pipeline processing when a plurality of LDP instructions are executed sequentially in the processor of FIG. 9; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. In the following, the same reference numerals as the signal names are used for the signal lines through which the signals are transmitted. Although not limited to this, the processor described below is a superscalar processor, which executes instructions in parallel by pipeline processing. Note that the processor described below may also be a scalar processor.

[0010] 1 shows an example of a processor according to an embodiment. The processor 100 shown in FIG. 1 has a load pipeline 1 including a memory 2, an instruction issuing unit 3, an arithmetic pipeline 4 including an arithmetic unit 5, a selector 6, and a register file 7.

[0011] The register file 7 has a plurality of registers REG (REG0, REG1, ...) and two write ports WP1 and WP2 that receive data to be stored in the registers REG. The write port WP1 is provided for receiving data D1 (load data) output from the load pipeline 1. The write port WP2 is provided for receiving data D2 (load data) output from the load pipeline 1 and the operation result data RSLT output from the operation pipeline 4.

[0012] The data D1 is an example of the first data, and the data D2 is an example of the second data. The write port WP1 is an example of the first port, and the write port WP2 is an example of the second port.

[0013] The bit width of the data received by each of the write ports WP1 and WP2 is equal to the bit width of one register REG. That is, the bit width of each of the data D1 and D2 output from the load pipeline 1 and the operation result data RSLT output from the operation pipeline 4 is equal to the bit width of each register REG. Hereinafter, the data held in one register REG is also referred to as one unit of data.

[0014] The load pipeline 1 receives a first load instruction or a second load instruction. The first load instruction is an instruction to update the values ​​of two registers REG with one instruction. The second load instruction is an instruction to update the value of one register REG with one instruction. Based on the first load instruction, the load pipeline 1 reads two units of data D1 and D2 from the memory 2, outputs the data D1 to the write port WP1, and outputs the data D2 to the selector 6. Based on the second load instruction, the load pipeline 1 reads one unit of data D1 from the memory 2 and outputs the data D1 to the write port WP1.

[0015] The instruction issuing unit 3 sequentially issues operation instructions to the operation pipeline 4. The operation pipeline 4 executes the operation instructions sequentially received from the instruction issuing unit 3 by an arithmetic unit 5, and outputs operation result data RSLT, which is the execution result of the operation, to a selector 6.

[0016] When the selector 6 receives data selection information, it selects the data D2 output from the load pipeline 1 and outputs it to the write port WP2. When the selector 6 does not receive data selection information, it selects the operation result data RSLT output from the operation pipeline 4 and outputs it to the write port WP2.

[0017] The data D1 and D2 supplied to the write ports WP1 and WP2 are stored in the two registers REG specified by the first load instruction, respectively. The operation result data RSLT2 supplied to the write port WP2 is stored in the register REG specified by the operation instruction.

[0018] 2 shows an overview of the operation when the processor 100 of FIG. 1 executes a first load instruction. For example, the first load instruction is written in mnemonic as "LDP X1,X2,[X10]" as an example. The code LDP indicates the instruction code of the first load instruction. The codes X1 and X2 indicate a register REG that stores two units of data read from the memory 2. In this example, the code X1 indicates the register REG1, and the code X2 indicates the register REG2. The code [X10] indicates the register REG that holds the address of the storage area of ​​the memory 2 from which the data D1 and D2 are read.

[0019] The load pipeline 1 executing the first load instruction reads two units of data D1, D2 (lower data and upper data) from the memory 2. Furthermore, the load pipeline 1 outputs a data selection signal to the selector 6 to cause the selector 6 to select the data D2 at the timing when the data D2 is read from the memory 2. As a result, the data D1 is stored in the register REG1 via the write port WP1, and the data D2 is stored in the register REG2 via the selector 6 and the write port WP2. That is, the data D1 and D2 are stored in mutually different registers REG1 and REG2.

[0020] As described above, in this embodiment, the processor 100 has the selector 6 between the arithmetic pipeline 4 and the write port WP2 that is dedicated to writing the arithmetic result data RSLT to the register REG. This allows the write port WP2 to be used for writing the data D2 read from the memory 2 based on the first load instruction to the register REG. As a result, the two registers REG can be updated with two units of data D1 and D2 read from the memory 2 by the first load instruction without providing a new write port for the data D2 of the first load instruction. Therefore, the processing performance of the processor 100 that executes the first load instruction to load multiple pieces of data D1 and D2 into multiple registers REG of the register file 7 at once can be improved while suppressing an increase in the circuit scale.

[0021] Depending on the processor specifications, there may be multiple pipelines for memory access instructions or arithmetic instructions, in which case the number of write ports in the register file 7 increases according to the number of pipelines. For this reason, increasing the number of write ports in the register file 7 leads to an increase in the amount of circuitry.

[0022] Fig. 3 shows an example of another processor. The processor 200 shown in Fig. 3 has an instruction cache 10, an instruction buffer 20, an instruction decoder 30, and a GPR renaming table 40. The processor 200 also has a reservation station 50 (RSE: Reservation Station for Execution), a reservation station 60 (RSA: Reservation Station for Address), an execution unit 70, and a load store unit 80.

[0023] The execution unit 70 includes a fixed-point arithmetic unit 72, a register GPR (General Purpose Register) 74, and an address generation unit 76. The load store unit 80 includes a load store queue 82 and a data cache 84.

[0024] The register GPR includes multiple entries each holding data. Hereinafter, each of the multiple entries included in the register GPR may be referred to as a GPR. Although not limited thereto, the size of each entry in the register GPR is 64 bits. The register GPR is an example of a register file, and the multiple entries included in the register GPR are an example of a register.

[0025] The reservation stations 50 and 60 are also referred to as an RSE and an RSA, respectively. Instead of the reservation stations 50 and 60, a reservation station that integrates the functions of an RSE and an RSA may be provided.

[0026] The instruction cache 10 is, for example, a primary cache that holds instructions transferred from a memory such as a secondary cache or a main memory. The instruction cache 10 outputs the instructions it holds to an instruction buffer 20. The instructions held by the instruction cache 10 are arithmetic instructions and memory access instructions, etc. The memory access instructions are store instructions or load instructions. The instruction buffer 20 accumulates the instructions transferred from the instruction cache 10, and sequentially outputs the accumulated instructions to the instruction decoder 30 in order.

[0027] The instruction decoder 30 decodes an instruction received from the instruction buffer 20. When the instruction decoder 30 decodes an arithmetic instruction, it outputs the write physical register number WP-GPRN, the write logical register number W-GPRN, and the read logical register number R-GPRN to the GPR renaming table 40. When the instruction decoder 30 decodes an arithmetic instruction, it outputs the write physical register number WP-GPRN and the instruction code ICD to the RSE.

[0028] When the instruction decoder 30 decodes a load instruction, it outputs the write physical register number WP-GPRN and the write logical register number W-GPRN to the GPR renaming table 40. When the instruction decoder 30 decodes a load instruction, it outputs the write physical register number WP-GPRN and the instruction code ICD to the RSA.

[0029] When the instruction decoder 30 decodes a store instruction, it outputs the read logical register number R-GPRN to the GPR renaming table 40. When the instruction decoder 30 decodes a store instruction, it outputs the instruction code ICD to the RSA.

[0030] For example, the instruction decoder 30 obtains the write physical register number WP-GPRN by using a method called a free list method, which can prevent the write physical register number WP-GPRN from being used simultaneously by multiple instructions.

[0031] The GPR renaming table 40 has entries whose number corresponds to the number of logical registers (operands) that can be specified in an arithmetic instruction or memory access instruction written in a program executed by the processor 200.

[0032] The GPR renaming table 40 associates the number of a logical register specified by an arithmetic instruction with the number of an entry (physical register) of the register GPR used by the fixed-point arithmetic unit 72. The GPR renaming table 40 also associates the number of a logical register specified by a memory access instruction with the number of an entry (physical register) of the register GPR used by the address generation arithmetic unit 76.

[0033] For example, the GPR renaming table 40 updates the entries of the GPR renaming table 40 based on the write physical register number WP-GPRN and the write logical register number W-GPRN received from the instruction decoder 30. In addition, the GPR renaming table 40 outputs the read physical register number RP-GPRN to the RSE and RSA based on the read logical register number R-GPRN received from the instruction decoder 30.

[0034] The write physical register number WP-GPRN indicates the number of the entry (physical register) of the register GPR where the operation result data RLST is updated, or the number of the entry (physical register) of the register GPR where data is updated by a load instruction. The write logical register number W-GPRN indicates the number of the logical register written in the instruction corresponding to the write physical register number WP-GPRN.

[0035] The read physical register number RP-GPRN indicates the number of the entry (physical register) of the register GPR that holds the data used in the operation, or the number of the entry (physical register) of the register GPR from which data is read by a store instruction. The read logical register number R-GPRN indicates the number of the logical register written in the instruction corresponding to the read physical register number RP-GPRN.

[0036] The RSE accumulates arithmetic instructions and speculatively issues the accumulated arithmetic instructions out of order to the arithmetic execution unit 70 in an executable order. The output of the RSE is connected to the register GPR and the fixed-point arithmetic unit 72. The RSE outputs an instruction code ICD to the fixed-point arithmetic unit 72 to execute the arithmetic instruction, and outputs a write physical register number WP-GPRN and a read physical register number RP-GPRN to the register GPR.

[0037] The fixed-point arithmetic unit 72 reads data DT1 used in the calculation from an entry of the register GPR based on a calculation instruction received from the RSE, and stores calculation result data RSLT in the entry of the register GPR.

[0038] The RSA accumulates memory access instructions (load instructions or store instructions) and speculatively issues the accumulated arithmetic instructions out of order to the arithmetic execution unit 70 in an executable order. The output of the RSA that accumulates the memory access instructions is connected to the register GPR and the address generation calculator 76. The RSA then outputs an instruction code ICD for executing the memory access instruction to the address generation calculator 76, and outputs a write physical register number WP-GPRN and a read physical register number RP-GPRN to the register GPR.

[0039] The address generation calculator 76 refers to the register GPR based on the memory access command received from the RSA, reads data DT2 from the register GPR, and generates an access address by performing addition processing on the read data DT2, etc. The address generation calculator 76 outputs the generated access address to the load store unit 80.

[0040] The load store unit 80 accumulates the access addresses received from the address generation calculator 76 in a load store queue 82, and sequentially uses the accumulated access addresses to access the data cache 84. When the memory access instruction is a load instruction, a data LDT is read from the data cache 84, and the data LDT is output to one of the entries of the register GPR and the fixed-point calculator 72. When the memory access instruction is a store instruction, a data SDT to be stored held in one of the entries of the register GPR is written to the data cache 84.

[0041] Fig. 4 shows an example of the GPR renaming table 40 of Fig. 3. For example, the GPR renaming table 40 has 32 entries corresponding to the number of logical registers that can be specified by an operand included in an arithmetic instruction. Each entry has an area for storing a physical register number WP-GPRN. The number of physical registers that can be specified by the physical register number WP-GPRN is more than 32.

[0042] The instruction decoder 30 stores the write physical register number WP-GPRN in an entry of the GPR renaming table 40 corresponding to the write logical register number W-GPRN indicating the logical register specified by the instruction. The instruction decoder 30 also outputs the read logical register number R-GPRN to the selector 41 of the GPR renaming table 40.

[0043] The GPR renaming table 40 reads the write physical register number WP-GPRN from the entry indicated by the read logical register number R-GPRN. The GPR renaming table 40 outputs the read write physical register number WP-GPRN to the RSA or RSE as the read physical register number RP-GPRN.

[0044] The RSE sequentially stores in its entries the instructions (instruction code ICD, write physical register number WP-GPRN, read physical register number RP-GPRN) received from the instruction decoder 30 and the GPR renaming table 40. The RSE then outputs the instructions stored in the entries to the fixed-point arithmetic unit 72 (FIG. 3) in the order in which they can be executed.

[0045] The RSA sequentially stores in its entries the instructions (instruction code ICD, write physical register number WP-GPRN, read physical register number RP-GPRN) received from the instruction decoder 30 and the GPR renaming table 40. The RSA then outputs the instructions stored in the entries to the address generation calculator 76 (FIG. 3) in the order in which they can be executed.

[0046] Fig. 5 shows an example of an operation when the processor 200 in Fig. 3 executes a load instruction LDP. The load instruction LDP is an instruction that updates the values ​​of two registers REG with one instruction, similar to the first load instruction shown in Fig. 2, and is written as "LDP X1, X2, [X10]" as an example of a mnemonic.

[0047] The processor 200 divides the LDP instruction into two flows f1 and f2 and processes them. In flow f1 ("LDP_f1 X1, [X10]"), the processor 200 reads the first 64 bits of data from the data cache 84 using the address stored in X10 (e.g., GPR10). The processor 200 stores the read data in GPR1. In flow f2 ("LDP_f2 X2, [X10+8]"), the processor 200 reads the second 64 bits of data from the data cache 84 using an address 8 bytes (64 bits) ahead of the value stored in X10. The processor 200 stores the read data in GPR2.

[0048] In the execution of the LDP instruction shown in Figure 5, the load instruction that loads 8 bytes is actually executed twice. Therefore, the IPC (Instruction Per Cycle), which is the number of instructions processed per cycle, is 0.5, half of the IPC=1 when loading 16 bytes with one LDP instruction.

[0049] Fig. 6 shows an example of pipeline processing of the load store unit 80 when the processor 200 of Fig. 3 executes an LDR instruction and an LDP instruction. In Fig. 6, for example, one time indicates one cycle.

[0050] The LDR instruction is a load instruction that reads 8 bytes of data from the data cache 84 in one pipeline operation and stores it in a GPR. The LDP instruction is a load instruction that reads 16 bytes of data from the data cache 84 in two pipeline operations and stores it in two GPRs.

[0051] In the pipeline of the load store unit 80, five stages, A cycle, T cycle, M cycle, B cycle, and R cycle, are executed in sequence, and data read from the data cache 84 is stored in the GPR. The processing contents of the A cycle, T cycle, M cycle, B cycle, and R cycle are explained in Fig. 7. The symbol GPR shown in the pipeline of Fig. 6 indicates that the data is held in the GPR, not that the pipeline is being processed.

[0052] In a pipeline, multiple load instructions can be executed with some overlapping, as long as the same stage is not executed at the same timing. Figure 6(a) shows an example in which two LDR instructions are executed consecutively. In Figure 6(a), one LDR instruction can be processed per cycle, so the IPC is "1".

[0053] Figure 6(b) shows an example in which one LDP instruction is divided into two flows (f1, f2) and executed. Since one LDP instruction runs the pipeline twice, it can only be executed once every two cycles, resulting in an IPC of "0.5".

[0054] Fig. 7 shows an example of a pipeline for an LDR instruction executed by the processor 200 of Fig. 3. In Fig. 7, the P cycle is a cycle in which the RSA issues an LDR instruction. The PT cycle is a cycle in which a read address RAD, which is included in the LDR instruction issued in the P cycle and indicates the register GPR from which data is read, is transferred to the register GPR. The B cycle is a cycle in which data RDT, which is used in an operation to generate an address, is read from the register GPR.

[0055] Cycle A is a cycle in which the address generation calculator 76 operates using the data RDT read in cycle B to generate a memory address MAD. Note that the calculation for generating an address by the address generation calculator 76 may add an immediate value to the data read from GPR (X10), such as "LDR X1, [X10, #8]". The memory address MAD is transferred to the load store unit 80.

[0056] The T cycle is a cycle in which the memory address MAD generated in the A cycle is used to read tag data TAGD from the tag area TAG of the data cache 84. The tag data TAGD includes information indicating whether or not data in the memory area indicated by the memory address MAD exists in the data area DT of the data cache 84.

[0057] The M cycle is a cycle (tag match) for determining whether the data to be loaded exists in the data area DT of the data cache 84 (cache hit or cache miss) based on the tag data TAGD. In the M cycle, data WATDT is read from the data area DT of the data cache 84 in parallel with the tag match. For example, in the 4-way set associative data cache 84, data WAYDT of the 4 ways are read from the data area DT as data candidates.

[0058] The B cycle is a cycle in which one of the four ways is selected using the result of the tag match, and the data of the selected way is output as the load data LDT. For example, the load data LDT is 64 bits (8 bytes). The R cycle is a cycle in which the load data LDT is transferred to the execution unit 70 and stored in the register GPR.

[0059] Fig. 8 shows an example of pipeline processing of an arithmetic instruction executed by the processor 200 of Fig. 3. In the pipeline processing of an arithmetic instruction, the P cycle is a cycle in which the RSE issues an arithmetic instruction. The PT cycle is a cycle in which a read address RAD, which is included in the arithmetic instruction issued in the P cycle and indicates an entry in the register GPR from which data is read, is transferred to the register GPR, and the arithmetic instruction is transferred to the fixed-point arithmetic unit 72.

[0060] The B cycle is a cycle for reading data RDT used for the operation from the register GPR. The X cycle is a cycle for operating the fixed-point arithmetic unit 72 using the data RDT read in the B cycle to execute the operation and generate operation result data RSLT. The operation result data RSLT is, for example, 64 bits (8 bytes) and is stored in one of the entries of the GPR.

[0061] FIG. 9 shows an example of a processor in another embodiment. The same or similar elements as those in FIG. 3 are given the same reference numerals, and detailed description is omitted. The processor 100A shown in FIG. 9 has the same configuration and function as the processor 200 in FIG. 3, except that it has a reservation station 50A, an arithmetic execution unit 70A, and a load store unit 80A instead of the reservation station 50, the arithmetic execution unit 70, and the load store unit 80 in FIG. 3. Hereinafter, the reservation station 50A is also referred to as an RSE. The instruction set architecture of the processor 100A may be, for example, an instruction set architecture of ARM.

[0062] The operation execution unit 70A has a fixed-point arithmetic unit 72, a register GPR 74A, and an address generation operation unit 76A. The register GPR 74A has a plurality of entries that hold data. Hereinafter, each entry is also referred to as a GPR, and the data held by each entry is also referred to as one unit of data. Although not limited thereto, for example, one unit is 8 bytes (64 bits). The address generation operation unit 76A outputs inhibition information INHB that inhibits the RSE from issuing an operation instruction.

[0063] The load store unit 80A has a load store queue 82A and a data cache 84A. The load store unit 80A has a function of reading two units (16 bytes) of data from the data cache 84A and transferring the data as load data LDT[127:0] to the execution unit 70A when executing an LDP instruction.

[0064] As described with reference to FIG. 5 and the like, the LDP instruction is a load instruction that simultaneously reads 16 bytes of data from the data cache 84A and stores them in two entries of the register GPR. The load instruction LDP is an example of a first load instruction. The processor 100A can execute the LDP instruction in one pipeline operation. An example of the pipeline of the execution unit 70A and the load store unit 80A is shown in FIG. 10.

[0065] Fig. 10 shows an example of a pipeline for an LDP instruction executed by the processor 100A of Fig. 9. Elements that are the same as or similar to those in Fig. 7 are given the same reference numerals, and detailed description thereof will be omitted.

[0066] In Fig. 10, the operation of the address generation calculator 76A generating the memory address MAD when the LDP instruction is executed is omitted. The operation of the operation execution unit 70A when the address generation calculator 76A generates the memory address MAD is similar to the operation of the operation execution unit 70 in Fig. 7. When the LDP instruction is executed, the operation execution unit 70A executes the P cycle, the PT cycle, the B cycle, and the A cycle, and generates the memory address MAD from the address generation calculator 76A.

[0067] When the address generation calculator 76A executes the LDP instruction, it generates the memory address MAD and outputs the inhibition information INHB to the RSE. The RSE inhibits the issuance of an operation instruction in the cycle following the cycle in which it receives the inhibition information INHB.

[0068] The load pipeline of the load store unit 80A has a T cycle, an M cycle, a B cycle, and an R cycle, similar to Fig. 7. The operation pipeline during operation execution by the operation execution unit 70A has a PT cycle, a B cycle, and an X cycle, similar to Fig. 8.

[0069] The load store unit 80A has a function of reading two units of load data LDT[127:0] from the data cache 84A. The load store unit 80A also has a function of transmitting information INF indicating the execution of the LDP instruction in the pipeline when the LDP instruction is executed, and outputting it as data selection information DSEL. Therefore, the way select of the load store unit 80A selects two ways corresponding to two units of data when the LDP instruction is executed. Other configurations and functions of the load store unit 80A are similar to those of the load store unit 80 in FIG. 7.

[0070] The operation execution unit 70A has a selector 73 that selects either the load data LDT[127:64] from the load store unit 80A or the operation result data RSLT[63:0] from the fixed-point arithmetic unit 72, and outputs the selected data to the register GPR. The register GPR has write ports WP1 and WP2, similar to the register file 7 in Fig. 2. The write port WP1 receives the load data LDT[63:0] from the load store unit 80A, and the write port WP2 receives the load data LDT[127:64] or the operation result data RSLT[63:0] from the selector 73.

[0071] When the selector 73 receives the data selection information DSEL (for example, when the data selection information DSEL is at a valid level), it selects the load data LDT[127:64] and outputs it to the write port WP2. When the selector 73 does not receive the data selection information DSEL (for example, when the data selection information DSEL is at an invalid level), it selects the operation result data RSLT[63:0] and outputs it to the write port WP2.

[0072] FIG. 11 shows an example of pipeline processing in the case where an LDP instruction and an arithmetic instruction are executed in parallel in the processor 100A of FIG. 9. Detailed explanations of operations similar to those in FIG. 6 to FIG. 8 are omitted. The LDP instruction is executed using eight cycles from the P cycle to the R cycle, as in FIG. 7. The arithmetic instruction is executed using four cycles from the P cycle to the X cycle, as in FIG. 8. In FIG. 11, it is assumed that an add instruction ADD is executed as the arithmetic instruction. The number at the end of the add instruction ADD indicates the execution order of the add instruction ADD. In FIG. 11, one time also indicates one cycle.

[0073] In Fig. 11, the load pipeline that executes the load instruction LDP and the operation pipeline that executes the operation instruction operate in parallel. The operation pipeline executes the operation instruction every cycle except the cycle after the inhibition information INHB is output from the load pipeline.

[0074] The load pipeline that receives the LDP instruction at time=1 outputs the memory address MAD in cycle A, which is executed at time=4, and outputs the inhibition information INHB to the RSE. The RSE does not issue an arithmetic instruction in the next cycle after receiving the inhibition information INHB. Therefore, the RSE issues addition instructions ADD1-ADD4 in sequence from time=1 to time=4, and then issues the next addition instruction ADD5 one cycle later at time=6. The arithmetic pipeline that does not receive an arithmetic instruction executes dummy arithmetic using invalid information from time=5 to time=8.

[0075] By having the calculation pipeline execute a dummy calculation, even when the issuance of a calculation instruction is suppressed, the calculation pipeline does not need to be stopped, so that the calculation instruction already being processed in the calculation pipeline can be executed normally.

[0076] At time=8, the load pipeline outputs load data LDT[127:0], and outputs data selection information DSEL of a valid level to the selector 73. That is, based on the LDP instruction, the load pipeline outputs data selection information DSEL to the selector 73 in synchronization with the timing at which the load data LDT[127:0] is output to the selector 73. At time=8 when the selector 73 receives the data selection information DSEL of a valid level, it selects the load data LDT[127:64] output from the load pipeline and outputs it to the write port WP2 of the register GPR.

[0077] This allows two units of load data LDT[127:64], [63:0] to be written simultaneously to two entries of the register GPR using the write port WP1 and the write port WP2 for the operation result data RSLT. Therefore, two entries of the register GPR can be updated by two units of load data LDT[127:64], [63:0] by the LDP instruction without providing a new write port for the load data LDT[127:64]. As a result, it is possible to suppress an increase in the circuit scale of the register GPR. In addition, it is possible to suppress the invalid operation result data RSLT due to a dummy operation by the operation pipeline from being stored in the GPR.

[0078] Also, it is possible to suppress only the execution of the add instruction ADD that generates the operation result data RSLT that conflicts with the load data LDT[127:64] in the selector 73. In other words, it is possible to execute the add instruction ADD that generates the operation result data RSLT that does not conflict with the load data LDT[127:64] without suppressing it, thereby suppressing malfunction of the processor 100A.

[0079] For example, the address generation calculator 76A outputs the inhibition information INHB at the timing when an operation instruction for outputting the operation result data RLST is issued when the load data LDT[127:64] by the LDP instruction is output to the selector 73, thereby inhibiting the issuance of the operation instruction. In other words, the output timing of the inhibition information INHB to the RSE is set so that the number of cycles from the output of the inhibition information INHB to the output of the load data LDT is equal to the number of cycles from the issuance of the operation instruction to the output of the operation result data RSLT.

[0080] That is, the inhibition information INHB is output in a cycle obtained by subtracting the number of execution cycles of the calculation instruction (four cycles in FIG. 11) from the cycle in which the load data LDT is output. Therefore, for example, when the calculation cycle is five cycles, the inhibition information INHB is output in the B cycle, and when the calculation cycle is three cycles, the inhibition information INHB is output in the T cycle.

[0081] As a result, it is possible to prevent the load data LDT[127:64] and the operation result data RSLT from competing with each other at time=8 when the load data LDT[127:64] by the LDP instruction is output from the load pipeline. That is, even when the write port WP2 is shared by the load data LDT[127:64] and the operation result data RSLT, it is possible to prevent data from being written to the register GPR at the same time, thereby preventing malfunction of the processor 100A.

[0082] Fig. 12 shows an example of pipeline processing in the case where multiple LDP instructions are executed sequentially in the processor 100A of Fig. 9. Detailed description of operations similar to those in Figs. 6 to 8 and 11 will be omitted. In Fig. 12, the load pipeline receives an LDP instruction from the RSE every cycle and executes the LDP instructions sequentially. The numbers at the end of the LDP instructions indicate the execution order of the LDP instructions. For each LDP instruction, the load pipeline outputs inhibition information INHB in cycle A and outputs valid data selection information DSEL in cycle R.

[0083] The inhibition information INHB is used to inhibit issuance of an arithmetic instruction from the RSE, and does not affect the LDP instruction issued from the RSA. Therefore, the RSA can issue an LDP instruction every cycle, and the load pipeline can execute an LDP instruction every cycle. Therefore, an LDP instruction that updates two units of data in two entries in the register GPR can be executed with IPC="1". As a result, an LDP instruction that simultaneously updates two entries in the register GPR can be executed without increasing the write port of the GPR, and the data load processing performance can be improved compared to the processor 200 of FIG. 3 while suppressing an increase in the circuit size.

[0084] For example, the LDP instruction may be used for so-called spill / fill processing, in which data in the GPR register is temporarily saved to memory, the freed GPR area is used for another purpose, and data is written from memory back to the GPR register as needed. For this reason, LDP instructions are often executed consecutively, and throughput is important. As shown in Figure 6, if the LDP instruction is divided into two flows and executed as a normal LDR instruction, the expected throughput may not be achieved.

[0085] As described above, this embodiment can also achieve the same effects as the above-mentioned embodiment. For example, a selector 73 is provided between the output of the fixed-point arithmetic unit 72 and the write port WP2 of the register GPR, which outputs either the operation result data RSLT or the load data LDT[127:64] from the load store unit 80A to the port WP2. This allows two units of load data LDT[127:64], [63:0] by the LDP instruction to be written simultaneously to two entries of the register GPR without providing a new write port WP. Therefore, the processing performance of the processor 100A that executes the LDP instruction can be improved while suppressing an increase in the circuit scale of the processor 100A.

[0086] Furthermore, in this embodiment, the address generation calculator 76A outputs inhibition information INHB that inhibits the issuance of an operation instruction that outputs the operation result data RLST in a cycle in which the load data LDT[127:64] by the LDP instruction is output to the selector 73. For example, the output timing of the inhibition information INHB to the RSE is set so that the number of cycles from the output of the inhibition information INHB to the output of the load data LDT is equal to the number of cycles from the issuance of the operation instruction to the output of the operation result data RSLT. This makes it possible to inhibit simultaneous writing of data to the register GPR even when the write port WP2 is shared by the load data LDT[127:64] and the operation result data RSLT, thereby preventing malfunction of the processor 100A.

[0087] By having the calculation pipeline execute a dummy calculation based on the inhibition information INHB, even when the issuance of a calculation instruction is inhibited, the calculation pipeline does not need to be stopped, so that the calculation instruction already being processed in the calculation pipeline can be executed normally.

[0088] The load store unit 80A outputs the data selection information DSEL to the selector 73 in the cycle in which it outputs the load data LDT[127:64] read from the data cache 84A based on the LDP instruction. This allows the selector 73 to select the load data LDT[127:64] and output it to the write port WP2 in accordance with the timing at which the load store unit 80A outputs the load data LDT[127:64].

[0089] When the LDP instruction is executed, the load store unit 80A transmits information INF indicating the execution of the LDP instruction in the pipeline and outputs it as data selection information DSEL. This makes it possible to generate the data selection information DSEL by sequentially transmitting the LDP instruction issued by the RSA in the load store unit 80A without preparing a special circuit such as a generation circuit that generates a data selection signal.

[0090] Furthermore, by improving the processing performance of the processor described above, it is possible to improve the processing performance of systems such as servers in which the processor is installed, and to shorten the time required for scientific and technological calculations, deep learning, various simulations, etc.

[0091] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims cover the features and advantages of the embodiments as described above without departing from the spirit and scope of the claims. In addition, any improvements and modifications can be easily made by a person having ordinary skill in the art. Therefore, it is not intended to limit the scope of the inventive embodiments to the above, and appropriate improvements and equivalents within the scope of the embodiments disclosed can be used. [Explanation of symbols]

[0092] 1. Road Pipeline 2. Memory 3. Command issuing department 4. Computation Pipeline 5 Arithmetic unit 6 Selectors 7 Register File 10 Instruction Cache 20 Instruction Buffer 30 Instruction Decoder 40 GPR Renaming Table 50 Reservation Station (RSE) 60 Reservation Station (RSA) 70 Calculation execution unit 72 Fixed-point arithmetic unit 74 Registers (GPR) 76 Address generation calculator 80 Load Store Unit 82 Load Store Queue 84 Data Cache 100, 100A, 200 Processors D1, D2 data LDT Data REG Register RSLT calculation result data SDT Data WP1, WP2 light ports

Claims

1. an operation pipeline including an operation unit that executes an operation instruction and outputs operation result data; a load pipeline that reads first data and second data in parallel from a memory based on a first load instruction and outputs the read first data and second data; a selector that selects the second data when the second data is output from the load pipeline, and selects an output of the arithmetic unit when the second data is not output from the load pipeline; a register file including a first port for receiving the first data from the load pipeline, a second port for receiving data from the selector, and a plurality of registers for holding data received at the first port or the second port; The first data and the second data are stored in different registers. Processor.

2. an instruction issuing unit that issues the operation instruction, The load pipeline outputs inhibition information to the instruction issue unit to inhibit issuance of the operation instruction that outputs the operation result data to the selector in the same cycle as the cycle in which the second data is output to the selector based on the first load instruction. The processor of claim 1 .

3. The output timing of the inhibition information to the instruction issue unit is set so that the number of cycles from the output of the inhibition information to the output of the second data to the selector is equal to the number of cycles from the issuance of the operation instruction to the output of the operation result data to the selector. The processor of claim 2 .

4. The operation pipeline, which is inhibited from issuing the operation instruction from the instruction issuing unit, executes a dummy operation. A processor according to claim 2 or claim 3.

5. The load pipeline outputs, to the selector, data selection information for causing the selector to select the second data in a cycle in which the load pipeline outputs the second data to the selector. A processor according to any one of claims 1 to 3.

6. The load pipeline generates data selection information using information indicating execution of the first load instruction transmitted within the load pipeline. The processor of claim 5 .

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