Exposure device, image formation apparatus and manufacturing method

Abstract

To provide a highly reliable exposure device with improved resistance to the intrusion of outside air.SOLUTION: An exposure device comprises: a plurality of light-emitting chips which are arranged in a staggered pattern along a reference line parallel to the axial direction of a photoreceptor, and each have a silicon substrate and a light-emitting element array being an array of organic EL elements formed on a first surface of the silicon substrate; and a rod lens array which forms an image of the light emitted from the light-emitting element arrays of the plurality of light-emitting chips onto the surface of the photoreceptor. A distance between a first side of the silicon substrate of each light-emitting chip which is parallel to the reference line and closer to the reference line, and the light-emitting element array of the light-emitting chip is equal to or greater than 20 micrometers.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to an exposure apparatus, an image forming apparatus, and a manufacturing method. [Background technology]

[0002] In an electrophotographic image forming apparatus, an electrostatic latent image is formed on a photoconductor by exposing the photoconductor to light as it is rotated, and the electrostatic latent image is developed with toner to form an image. In particular, a solid-state exposure type exposure device that uses a rod lens array to focus light from an array of light-emitting elements on the surface of a photoconductor is attracting attention because it is easier to reduce the size, noise level, and cost compared to a laser scanning type exposure device.

[0003] Patent Document 1 discloses a solid-state exposure type exposure device that employs inorganic light-emitting diodes as light-emitting elements. In the exposure device of Patent Document 1, a plurality of light-emitting chips, each having a light-emitting element array, are arranged in a staggered pattern parallel to the axial direction of the photoconductor to eliminate gaps between the light-emitting chips. Patent Document 2 discloses a solid-state exposure type exposure device that employs organic EL (Electro Luminescence) elements. In the exposure device of Patent Document 2, a plurality of light-emitting chips are also arranged in a staggered pattern parallel to the axial direction of the photoconductor. Organic EL elements are superior to inorganic LEDs in that they consume less power. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-183436 A [Patent Document 2] Patent Publication No. 2021-35765 Summary of the Invention [Problem to be solved by the invention]

[0005] When multiple light-emitting chips are arranged in a staggered pattern along a certain reference line, there will be some gaps between the light-emitting element arrays of the light-emitting chips located at odd numbers from one end and the light-emitting element arrays of the light-emitting chips located at even numbers in a direction perpendicular to the reference line. By making this gap as small as possible, it is possible to efficiently capture light into the rod lens array. However, the inventor has found a problem that if the gaps between the light-emitting element arrays are made small, the distance between the edge of the light-emitting chip and the light-emitting element array becomes insufficient, and the risk of moisture and oxygen from the outside air entering from the edge causing deterioration of the organic EL element increases. The deteriorated organic EL element does not emit light even though a driving current is supplied, and is in a so-called non-lighting state. Non-lighting can not only be detected as an initial defect during the manufacture of the device, but can also increase after the device has started to be used.

[0006] An object of the present invention is to provide a highly reliable exposure apparatus with improved resistance to the intrusion of outside air. [Means for solving the problem]

[0007] According to one aspect, there is provided an exposure device comprising: a plurality of light-emitting chips arranged in a staggered pattern along a reference line parallel to the axial direction of a photosensitive body, the plurality of light-emitting chips each having a silicon substrate and a light-emitting element array which is an array of organic EL (Electro Luminescence) elements formed on a first surface of the silicon substrate; and a rod lens array which forms an image of light from the light-emitting element array of the plurality of light-emitting chips on a surface of the photosensitive body, wherein a distance between a first side of the silicon substrate of each light-emitting chip which is parallel to and closer to the reference line and the light-emitting element array of the light-emitting chip is 20 micrometers or more. There is also provided an image forming device including the exposure device and the photosensitive body.

[0008] According to another aspect, there is provided a manufacturing method for manufacturing a light-emitting chip used in an exposure device that exposes a photosensitive body with light from a plurality of light-emitting chips, the manufacturing method including: forming a plurality of light-emitting element arrays, each of which is an array of organic EL (Electro Luminescence) elements, spaced apart from each other on a first surface of a silicon substrate; forming a plurality of sealing films made of an insulating inorganic material on the first surface of the silicon substrate so as to cover each of the plurality of light-emitting element arrays; and cutting the silicon substrate along cutting lines located in non-sealing areas that are not covered by the plurality of sealing films. Effect of the Invention

[0009] According to the present invention, it is possible to provide a highly reliable exposure apparatus having improved resistance to the intrusion of outside air. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram showing a schematic configuration of an image forming apparatus according to an embodiment; [Diagram 2] FIG. 2 is an explanatory diagram of a configuration of a photoconductor and an exposure head according to the embodiment. [Diagram 3] FIG. 4 is an explanatory diagram of the configuration of a printed circuit board of an exposure head according to an embodiment. [Figure 4] 1A and 1B are explanatory diagrams of a light-emitting chip and a light-emitting element array in the light-emitting chip according to an embodiment. [Diagram 5] FIG. 1 is a cross-sectional view showing an example of the configuration of a light-emitting device according to an embodiment. [Figure 6] FIG. 4 is a circuit diagram showing a control configuration of an exposure apparatus according to an embodiment. [Figure 7] 6 is a signal chart related to access to a register of a light emitting chip according to an embodiment; [Figure 8] 11 is a signal chart related to the transmission of image data to a light-emitting chip according to an embodiment; [Figure 9] FIG. 2 is a functional block diagram showing a detailed circuit configuration of the light-emitting chip according to an embodiment. [Figure 10]FIG. 13 is an explanatory diagram of multiple exposure using light-emitting elements arranged in a stepped pattern. [Figure 11] FIG. 2 is a plan view showing an example of a configuration of a light-emitting chip according to an embodiment. [Figure 12] FIG. 2 is a partial cross-sectional view showing an example of a configuration of a light-emitting chip according to an embodiment. [Figure 13] 1 is a flowchart showing an example of a flow of a method for manufacturing a light-emitting chip according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0012] <1. Schematic configuration of image forming apparatus> 1 shows an example of a schematic configuration of an image forming apparatus 1 according to an embodiment. The image forming apparatus 1 includes a reading unit 100, an image creating unit 103, a fixing unit 104, and a conveying unit 105. The reading unit 100 optically reads an original placed on a platen and generates read image data. The image creating unit 103 forms an image on a sheet based on the read image data generated by the reading unit 100, or based on print image data received from an external device via a network, for example.

[0013] The image forming unit 103 includes image forming units 101a, 101b, 101c, and 101d. The image forming units 101a, 101b, 101c, and 101d form black, yellow, magenta, and cyan toner images, respectively. The image forming units 101a, 101b, 101c, and 101d have the same configuration, and are collectively referred to as the image forming unit 101 below. The photoconductor 102 of the image forming unit 101 is rotated clockwise in the figure during image formation. The charger 107 charges the photoconductor 102. The exposure head 106 exposes the photoconductor 102 to light to form an electrostatic latent image on the surface of the photoconductor 102. The developer 108 develops the electrostatic latent image on the photoconductor 102 with toner to form a toner image. The toner image formed on the surface of the photoconductor 102 is transferred to a sheet transported on a transfer belt 111. By transferring the toner images of the four photoconductors 102 onto a sheet in an overlapping manner, a color image containing four color components, namely black, yellow, magenta, and cyan, can be formed.

[0014] The conveying unit 105 controls the feeding and conveying of the sheet. Specifically, the conveying unit 105 feeds the sheet from a designated unit among the internal storage units 109a and 109b, the external storage unit 109c, and the manual feed unit 109d to the conveying path of the image forming apparatus 1. The fed sheet is conveyed to the registration roller 110. The registration roller 110 conveys the sheet onto the transfer belt 111 at an appropriate timing so that the toner image of each photoconductor 102 is transferred onto the sheet. As described above, the toner image is transferred onto the sheet while the sheet is being conveyed on the transfer belt 111. The fixing unit 104 fixes the toner image onto the sheet by heating and pressing the sheet onto which the toner image has been transferred. After the toner image is fixed, the sheet is discharged to the outside of the image forming apparatus 1 by the discharge roller 112. An optical sensor 113 is disposed at a position opposite the transfer belt 111. Optical sensor 113 optically reads the test chart formed on transfer belt 111 by image forming unit 101. When an error in the image formation range is detected for the test chart read by optical sensor 113, image controller 700 (described later) performs control to compensate for the error when a subsequent job is executed.

[0015] Although an example in which a toner image is directly transferred from each photoconductor 102 to a sheet on the transfer belt 111 has been described here, the toner image may be indirectly transferred from each photoconductor 102 to a sheet via an intermediate transfer body. Also, although an example in which a color image is formed using toners of multiple colors has been described here, the technology according to the present disclosure is also applicable to an image forming apparatus that forms a monochrome image using toners of a single color.

[0016] <2. Exposure head configuration example> 2(A) and 2(B) show the photoconductor 102 and the exposure head 106. The exposure head 106 has a light emitting element array 201, a printed circuit board 202 on which the light emitting element array 201 is mounted, a rod lens array 203, and a housing 204 that supports the printed circuit board 202 and the rod lens array 203. The photoconductor 102 has a cylindrical shape. The exposure head 106 is disposed such that its longitudinal direction is parallel to the axial direction D1 of the photoconductor 102, and the surface on which the rod lens array 203 is attached faces the surface of the photoconductor 102. While the photoconductor 102 rotates in the circumferential direction D2, the light emitting element array 201 of the exposure head 106 emits light, and the rod lens array 203 forms an image of the light on the surface of the photoconductor 102.

[0017] Fig. 3(A) and Fig. 3(B) show an example of the configuration of the printed circuit board 202. Fig. 3(A) shows the surface on which the connector 305 is mounted, and Fig. 3(B) shows the surface on which the light-emitting element array 201 is mounted (the surface opposite to the surface on which the connector 305 is mounted). Fig. 4 shows a schematic diagram of the light-emitting chip 400 and the array of the light-emitting elements 602 in the light-emitting chip 400.

[0018] In this embodiment, the light-emitting element array 201 has a plurality of light-emitting elements arranged two-dimensionally. The light-emitting element array 201 includes, as a whole, N columns of light-emitting elements in the axial direction D1 of the photoconductor and M rows in the circumferential direction D2, where M and N are integers of 2 or more. In the example of FIG. 3B, the light-emitting element array 201 is divided into 20 light-emitting chips 400-1 to 400-20, each of which includes a subset of the entire plurality of light-emitting elements. The light-emitting chips 400-1 to 400-20 are arranged in a staggered pattern along a reference line 310 parallel to the axial direction D1. The light-emitting chips 400-1 to 400-20 are also collectively referred to as light-emitting chips 400. As shown in FIG. 3B, the range occupied by all the light-emitting elements of the 20 light-emitting chips in the axial direction D1 is wider than the range occupied by the maximum width W0 of the input image data. Therefore, some light-emitting elements located at both ends in the axial direction D1 may not be used to expose the photoconductor 102 unless an error in the image formation range is detected. Each light-emitting chip 400 on the printed circuit board 202 is connected to the image controller 700 (FIG. 6) via a connector 305. In the following description, for convenience of explanation, the side with the smaller branch number of the light-emitting chips 400-1 to 400-20 arranged along the axial direction D1 may be referred to as the "left" and the side with the larger branch number as the "right". For example, the light-emitting chip 400-1 is the leftmost light-emitting chip 400, and the light-emitting chip 400-20 is the rightmost light-emitting chip. The reference line 310 is parallel to the axial direction D1 and passes through the midpoint between the odd-numbered light-emitting chips 400-1, 400-3, ... and the even-numbered light-emitting chips 400-2, 400-4, ... in the circumferential direction D2.

[0019] The number J (J=N / 20) of the light-emitting elements 602 arranged in each row of one light-emitting chip 400 may be equal to, for example, 748 (J=748). Meanwhile, the number M of the light-emitting elements 602 arranged in each column of one light-emitting chip 400 may be equal to, for example, 4 (M=4). That is, in the exemplary embodiment, each light-emitting chip 400 has a total of 2992 (=748×4) light-emitting elements 602, with 748 in the axial direction D1 and 4 in the circumferential direction D2. The interval P between the center points of the light-emitting elements 602 adjacent to each other in the circumferential direction D2 is Cmay be, for example, about 21.16 μm, corresponding to a resolution of 1200 dpi. The distance between the center points of adjacent light emitting elements 602 in the axial direction D1 may also be about 21.16 μm, in which case 748 light emitting elements 602 occupy a length of about 15.8 mm in the axial direction D1. Note that, for convenience of explanation, FIG. 4 shows an example in which the light emitting elements 602 are completely arranged in a lattice in each light emitting chip 400, but the M (M=4) light emitting elements 602 in each row may be arranged in a stepped or partially stepped manner. The stepped arrangement of the light emitting elements 602 will be further described later.

[0020] FIG. 5 is a cross-sectional view showing an example of the configuration of a light-emitting element 602. A plurality of lower electrodes 504 are formed on the light-emitting substrate 402, which is a silicon substrate. A gap of length d is provided between two adjacent lower electrodes 504. A light-emitting layer 506 is provided on the lower electrode 504, and an upper electrode 508 is provided on the light-emitting layer 506. The upper electrode 508 is one common electrode for the plurality of lower electrodes 504. When a voltage is applied between the lower electrode 504 and the upper electrode 508, a current flows from the lower electrode 504 to the upper electrode 508, causing the light-emitting layer 506 to emit light. Therefore, one lower electrode 504 and a partial region of the light-emitting layer 506 and the upper electrode 508 corresponding to the lower electrode 504 constitute one light-emitting element 602. That is, in this embodiment, the light-emitting substrate 402 includes a plurality of light-emitting elements 602.

[0021] An organic EL film is used for the light-emitting layer 506. That is, the light-emitting element 602 is an organic EL element. The upper electrode 508 is composed of a transparent electrode such as indium tin oxide (ITO) so as to transmit the emission wavelength of the light-emitting layer 506. Note that in this embodiment, the entire upper electrode 508 transmits the emission wavelength of the light-emitting layer 506, but it is not necessary for the entire upper electrode 508 to transmit the emission wavelength. Specifically, it is sufficient that a partial region through which light from each light-emitting element 602 passes transmits the emission wavelength.

[0022] In FIG. 5, one continuous light-emitting layer 506 is formed, but a plurality of light-emitting layers 506 each having a width equivalent to the width W of the lower electrode 504 may be formed on the lower electrode 504. In FIG. 5, the upper electrode 508 is formed as one common electrode for the plurality of lower electrodes 504, but a plurality of upper electrodes 508 each having a width equivalent to the width W of the lower electrode 504 may be formed corresponding to each of the lower electrodes 504. In addition, the first plurality of lower electrodes 504 of the lower electrodes 504 of each light-emitting chip 400 may be covered by the first light-emitting layer 506, and the second plurality of lower electrodes 504 may be covered by the second light-emitting layer 506. Similarly, the first upper electrode 508 may be commonly formed corresponding to the first plurality of lower electrodes 504 of the lower electrodes 504 of each light-emitting chip 400, and the second upper electrode 508 may be commonly formed corresponding to the second plurality of lower electrodes 504. In such a configuration, one lower electrode 504 and the region of the light emitting layer 506 and upper electrode 508 corresponding to the lower electrode 504 constitute one light emitting element 602 .

[0023] FIG. 6 is a circuit diagram related to a control configuration for controlling the light-emitting chip 400. The image controller 700 is a control circuit that communicates with the printed circuit board 202 via a plurality of signal lines (wires). The image controller 700 has a CPU 701, a clock generating unit 702, an image data processing unit 703, a register access unit 704, and a light-emitting control unit 705. The light-emitting control unit 705 terminates the signal line between the image controller 700 and the printed circuit board 202. The n-th light-emitting chip 400-n (n is an integer from 1 to 20) on the printed circuit board 202 is connected to the light-emitting control unit 705 via a signal line DATAn and a signal line WRITEn. The signal line DATAn is used to transmit image data from the image controller 700 to the light-emitting chip 400-n. The signal line WRITEn is used for the image controller 700 to write control data to the register of the light-emitting chip 400-n.

[0024] One signal line CLK, one signal line SYNC, and one signal line EN are further provided between the light-emitting control unit 705 and each light-emitting chip 400. The signal line CLK is used to transmit a clock signal for transmitting data on the signal lines DATAn and WRITEn. The light-emitting control unit 705 outputs a clock signal generated based on a reference clock signal from the clock generating unit 702 to the signal line CLK. The signals transmitted to the signal lines SYNC and EN will be described later.

[0025] The CPU 701 controls the entire image forming apparatus 1. The image data processing unit 703 performs image processing on image data received from the reading unit 100 or an external device to generate binary bitmap image data for controlling the on / off of the light emission of the light emitting element 602 of the light emitting chip 400 on the printed circuit board 202. The image processing here may include, for example, raster conversion, tone correction, color conversion, and halftone processing. The image data processing unit 703 transmits the generated image data to the light emission control unit 705 as input image data. The register access unit 704 receives control data to be written to the register in each light emitting chip 400 from the CPU 701 and transmits it to the light emission control unit 705.

[0026] FIG. 7 shows the transition of the signal level of each signal line when control data is written to the register of the light-emitting chip 400. An enable signal that is at high level during communication and indicates that communication is in progress is output to the signal line EN. The light-emitting control unit 705 transmits a start bit to the signal line WRITEn in synchronization with the rising edge of the enable signal. Next, the light-emitting control unit 705 transmits a write identification bit indicating a write operation, and then transmits the address of the register to which the control data is to be written (4 bits in this example) and the control data (8 bits in this example). When writing to the register, the light-emitting control unit 705 sets the frequency of the clock signal transmitted to the signal line CLK to, for example, 3 MHz.

[0027] FIG. 8 shows the transition of the signal level of each signal line when image data is transmitted to each light-emitting chip 400. A periodic line synchronization signal indicating the exposure timing of each line on the photoconductor 102 is output to the signal line SYNC. If the circumferential speed of the photoconductor 102 is 200 mm / s and the resolution in the circumferential direction is 1200 dpi (approximately 21.16 μm), the line synchronization signal is output at a period of approximately 105.8 μs. The light-emitting control unit 705 transmits image data to the signal lines DATA1 to DATA20 in synchronization with the rising edge of the line synchronization signal. In this embodiment, since each light-emitting chip 400 has 2992 light-emitting elements 602, it is necessary to transmit image data indicating the light emission / non-light emission of each of the total 2992 light-emitting elements 602 to each light-emitting chip 400 within a period of approximately 105.8 μs. Therefore, in this example, as shown in FIG. 8, when transmitting image data, the light-emitting control unit 705 sets the frequency of the clock signal transmitted to the signal line CLK to 30 MHz.

[0028] FIG. 9 is a functional block diagram showing a detailed circuit configuration of one light-emitting chip 400 (n-th light-emitting chip 400-n). The light-emitting chip 400 has nine pads 408-1 to 408-9, a circuit unit 406, and a light-emitting element array 410. The pads 408-1 and 408-2 are connected to a power supply voltage VCC by a power supply line. Power is supplied from this power supply voltage VCC to each circuit of the circuit unit 406 of the light-emitting chip 400. The pads 408-3 and 408-4 are connected to the ground by a ground line. Each circuit of the circuit unit 406 and the upper electrode 508 are connected to the ground via the pads 408-3 and 408-4. The signal line CLK is connected to the transfer unit 1003, the register 1102, and the latch units 1004-001 to 1004-748 via the pad 408-5. The signal lines SYNC and DATAn are connected to the transfer unit 1003 via pads 408-6 and 408-7. The signal lines EN and WRITEn are connected to a register 1102 via pads 408-8 and 408-9. The register 1102 stores control data indicating the magnitude of the drive current to be supplied to each light-emitting element 602, for example.

[0029] The transfer unit 1003 receives input image data including a series of pixel values ​​each indicating the emission or non-emission of one light emitting element 602 from a signal line DATAn in synchronization with a clock signal from a signal line CLK, starting from a line synchronization signal from a signal line SYNC. The transfer unit 1003 performs serial-to-parallel conversion on the series of pixel values ​​serially received from the signal line DATAn in units of M (for example, M=4) pixel values. For example, the transfer unit 1003 has four cascaded D flip-flops, and parallelizes pixel values ​​DATA-1, DATA-2, DATA-3, and DATA-4 input over four clocks, and outputs the parallelized pixel values ​​to the latch units 1004-0001 to 1004-748. The transfer unit 1003 further has four D flip-flops for delaying the line synchronization signal, and outputs a first latch signal to the latch unit 1004-001 via a signal line LAT1 at a timing delayed by four clocks from the input of the line synchronization signal.

[0030] The kth latch unit 1004-k (k is an integer from 1 to 748) holds the four pixel values ​​DATA-1, DATA-2, DATA-3, and DATA-4 input from the transfer unit 1003 at the same time as the kth latch signal is input, by using a latch circuit. In addition, except for the last-stage latch unit 1004-748, the kth latch unit 1004-k delays the kth latch signal by four clocks and outputs the (k+1)th latch signal to the latch unit 1004-(k+1) via the signal line LAT(k+1). Then, the kth latch unit 1004-k continues to output a drive signal based on the four pixel values ​​held by the latch circuit to the current drive unit 1104 during the signal period of the kth latch signal. For example, there is a delay of four clocks between the timing when the first latch signal is input to the latch unit 1004-1 and the timing when the second latch signal is input to the latch unit 1004-2. Therefore, the latch unit 1004-1 outputs drive signals based on the 1st, 2nd, 3rd and 4th pixel values ​​to the current driver 1104, whereas the latch unit 1004-2 outputs drive signals based on the 5th, 6th, 7th and 8th pixel values ​​to the current driver 1104. Generally speaking, the latch unit 1004-k outputs drive signals based on the (4k-3), (4k-2), (4k-1) and (4k)th pixel values ​​to the current driver 1104. Therefore, in the embodiment shown in FIG. 9, 748 latch units 1004-001 to 1004-748 output 2992 drive signals for controlling the driving of 2992 (=748×4) light emitting elements 602 in approximately parallel to the current driver 1104. Each drive signal is a binary signal indicating a high level or a low level.

[0031] The current driver 1104 has 2992 light emission driver circuits respectively corresponding to the 2992 light emitting elements 602 of the light emitting element array 410. Each light emission driver circuit passes a drive current of a magnitude indicated by the control data in the register 1102 to the light emitting layer 506 of the corresponding light emitting element 602 while the corresponding drive signal indicates a high level indicating that light emission is on. This causes the light emitting element 602 to emit light with a targeted amount of light. Note that the control data may indicate one individual current value for each light emitting element 602, may indicate one current value for each group of the light emitting elements 602, or may indicate one current value common to all the light emitting elements 602.

[0032] <3. Control of multiple exposure> 4 shows an example in which the light-emitting elements 602 in each light-emitting chip 400 are completely arranged in a lattice pattern, but the M light-emitting elements 602 in each row may be arranged in a stepped pattern at a constant pitch. FIG. 10 is an explanatory diagram of multiple exposure using light-emitting elements arranged in a stepped pattern. Here, an example of the arrangement of light-emitting elements in the light-emitting chip 400-1 when M=4 is partially shown. R in the figure j_m (j={0,1,...,J-1}, m={0,1,2,3}) represents the light emitting element 602 in the j-th column from the left in the axial direction and in the m-th row from the top in the circumferential direction. C As described above, the axial spacing between two adjacent light-emitting elements among the M light-emitting elements in each row, i.e., the axial pitch P A may be approximately 5 μm, which corresponds to a resolution of 4800 dpi.

[0033] By arranging the four light-emitting elements in each row in a stepped manner in this manner, any two adjacent light-emitting elements among the four light-emitting elements occupy areas that partially overlap in the axial direction. Then, the four light-emitting elements in the row corresponding to each pixel position of the input image data sequentially emit light while the photoconductor 102 is rotating, forming spots corresponding to each pixel position on the surface of the photoconductor 102. In the example of Figure 10, when the pixel value at the left end of the i-th line of the input image data indicates that light is on, the light-emitting element R0_0 , R 0_1 , R 0_2 , R 0_3 is a line L on the surface of the photoconductor 102. i As a result, the line L i In the same manner, when the jth pixel value from the left of the i-th line of the input image data indicates that light is emitted, the light-emitting element R j_0 , R j_1 , R j_2 , R j_3 is a line L on the surface of the photoconductor 102. i As a result, the line L i The jth spot area from the left of is multiplexed and the corresponding spot SP j is formed.

[0034] 10, just as two adjacent rows of light-emitting elements occupy a partially overlapping area, two rows of light-emitting elements located at the boundary between two adjacent light-emitting chips 400 also occupy a partially overlapping area in the axial direction. That is, of the two adjacent light-emitting chips 400, the light-emitting elements in the rightmost row of the left light-emitting chip 400 and the light-emitting elements in the leftmost row of the right light-emitting chip 400 also occupy a partially overlapping area in the axial direction. The axial pitch P of the light-emitting elements across all 20 light-emitting chips 400 A is constant at about 5 μm. By sequentially emitting light at appropriate times from the four light-emitting elements in each row of these light-emitting chips 400, a smooth line of an electrostatic latent image can be formed on the surface of the photoconductor 102, which is made up of a series of spots that are partially overlapping each other with a constant spot spacing. As a result of such lines being continuously formed in the circumferential direction, a two-dimensional electrostatic latent image is created.

[0035] <4. Improved resistance to outside air intrusion> As described with reference to FIG. 3B and FIG. 4, when the light emitting chips 400-1 to 400-20 are arranged in a staggered manner along the reference line 310, a gap G is generated between the light emitting element array on one side of the reference line 310 and the light emitting element array on the other side in a direction perpendicular to the reference line 310. The smaller this gap G is, the more efficient the light from the light emitting element array is taken into the rod lens array 203. However, if the gap G is too small, a sufficient distance cannot be provided between the side (first side) that is parallel to the reference line 310 and closer to the reference line 310 among the four sides of each light emitting chip 400 and is closer to the reference line 310 and the light emitting element array. In FIG. 4, this distance is indicated by the symbol L. The inventors have found a problem that if the distance L is not large enough, moisture and oxygen contained in the outside air that enters the inside of the chip from the first side easily reach the light emitting element array, which increases the risk of causing deterioration of the light emitting element 602. In particular, when manufacturing a light-emitting chip by forming an array of organic EL elements on a silicon substrate, even if the light-emitting element array is covered with a sealing film, if the spacing L is less than 20 μm, light-emitting elements may become unlit after the light-emitting chip is manufactured.

[0036] Therefore, in this embodiment, each light emitting chip 400 is manufactured so that the distance L between the first side of each light emitting chip 400 and the light emitting element array 410 of the light emitting chip 400 is 20 μm or more. Typically, the light emitting element array 410 of each light emitting chip 400 is formed on the first surface of the silicon substrate 402 and covered with a sealing film made of an insulating inorganic material. This protects the light emitting layer 506, which is an organic EL film, from substances that cause deterioration. The sealing film may be, for example, a thin film of silicon oxide, silicon nitride, or aluminum oxide, or a laminate of two or more of them.

[0037] Additionally, each light emitting chip 400 may further include a metal film formed between the silicon substrate 402 and the sealing film so as to at least partially surround the light emitting element array 410 on the first surface of the silicon substrate 402. The material of the metal film may be, for example, aluminum, copper, titanium, or chromium, or any combination thereof, so as to prevent the intrusion of degradation-causing substances as much as possible by having high adhesion with the sealing film. The presence of the metal film around the light emitting element array 410 prevents most of the moisture and oxygen that enter the interface between the silicon substrate 402 and the sealing film from further penetrating inside the chip.

[0038] Fig. 11 is a plan view showing an example of the configuration of a light emitting chip 400 according to an embodiment. Fig. 12 is a partial cross-sectional view of the cross section taken along line AA in Fig. 11, as viewed from an axial direction D1. A direction D3 is perpendicular to the axial direction D1 and the circumferential direction D2.

[0039] In the illustrated embodiment, the silicon substrate 402 of the light emitting chip 400 has a first surface 402a and a second surface 402b, and a light emitting element array 410, which is a two-dimensional array of light emitting elements (organic EL elements) 602, is formed on the first surface 402a. The region (light emitting element region) on the first surface 402a where the light emitting element array 410 is formed is biased toward a first side 403 of the light emitting chip 400, not toward the center in the circumferential direction D2. The first side 403 is a side that is parallel to the reference line 310 and located in the vicinity of the reference line 310 when the light emitting chip 400 is disposed on the printed circuit board 202.

[0040] Also, on the first surface 402a, the metal film 411 is formed so as to at least partially surround the light emitting element array 410. FIG. 11 shows an example in which the strip-shaped metal film 411 surrounding the light emitting element array 410 is missing at a plurality of places on the opposite side of the first side 403. However, the metal film 411 may completely surround the light emitting element array 410. The missing portion of the metal film 411 may be used for wiring the pads 408-1 to 408-9, for example. Also, FIG. 12 shows an example in which the metal film 411 is completely covered with the sealing film 413. However, a part of the metal film 411 may be exposed to the outside without being covered with the sealing film 413. Although not shown in FIG. 11 and FIG. 12, inside the inner periphery of the metal film 411, further components constituting the circuit unit 406 of the light emitting chip 400 are arranged.

[0041] The light emitting element array 410 and the metal film 411 are covered with a sealing film 413. However, the silicon substrate 402 of the light emitting chip 400 has a non-sealing region 414 that is not covered with the sealing film 413 at least between the metal film 411 and the first side 403. In the example of Fig. 11, the non-sealing region 414 exists on all four sides of the silicon substrate 402. The presence of the non-sealing region 414 prevents the sealing film 413 from cracking or peeling when the light emitting chip 400 is cut out from the silicon wafer in a dicing process.

[0042] 11 and 12 also show the interval L between the light emitting element array 410 and the first side 403 of the light emitting chip 400. As described above, by setting the interval L to 20 μm or more, the light emitting element 602 of the light emitting element array 410 can be sufficiently protected from the outside air that penetrates into the boundary surface between the silicon substrate 402 and the sealing film 413. The interval between the light emitting element array 410 and the other three sides of the light emitting chip 400 may also be 20 μm or more. Furthermore, by setting the interval L to 200 μm or less, sufficient efficiency of light capture into the rod lens array 203 can be ensured. Note that stealth dicing using a laser is known as a method for reducing chipping in the dicing process. When the light emitting chip 400 is cut out from a silicon wafer by stealth dicing, by setting the interval L to 30 μm or more, a sufficient interval from the edge to the light emitting element array can be ensured even if deposition blurring or chipping of the organic EL element occurs.

[0043] Fig. 13 is a flow chart showing an example of the flow of a manufacturing method for manufacturing the light-emitting chip 400 used in the above-mentioned exposure head 106. The manufacturing method shown in Fig. 13 can be realized by a processor of some semiconductor manufacturing device executing a computer program. Note that the symbol 'S' in the figure indicates a processing step.

[0044] First, in S101, cutting lines for dicing are defined in a grid pattern on the first surface of the silicon wafer. Each of the sections surrounded by the cutting lines defined here becomes a substrate constituting each light emitting chip 400. Next, in S102, a light emitting element region is defined in each section at a distance of at least 20 μm from the cutting lines. As a result, a plurality of light emitting element regions are arranged at intervals from each other on the first surface. Preferably, the distance between the cutting lines and the light emitting element regions may be 30 μm or more.

[0045] Next, in S103, a metal film 411 at least partially surrounding the light-emitting element region is formed in each section of the first surface of the silicon wafer. Next, in S104, an array (light-emitting element array 410) of organic EL elements 602 each including a lower electrode 504, a light-emitting layer 506, and an upper electrode 508 is formed in each light-emitting element region. Next, in S105, the remaining components constituting the circuit unit 406 of the light-emitting chip 400 are formed.

[0046] Next, in S106, a plurality of sealing films 413 that cover the plurality of light emitting element arrays 410 are formed on the first surface. Each of the sealing films 413 formed here covers the corresponding light emitting element array 410 as well as the metal film 411 surrounding the light emitting element array 410. For example, the sealing film 413 may be formed by an atomic layer deposition (ALD) method that has excellent performance in covering a stepped structure. However, in each section, a non-sealing region 414 is left around the sealing film 413. For example, the sealing film 413 may be formed while masking the non-sealing region 414. Alternatively, the non-sealing region 414 may be formed by removing a part of the sealing film 413 formed over the entire surface (while masking other regions) by dry etching or wet etching. Typically, each sealing film 413 is formed in a shape that does not overlap the cutting lines defined in a lattice shape in S101.

[0047] Next, in S107, the silicon wafer is cut (e.g., stealth dicing) along cutting lines located in the non-sealed region 414 to cut out a plurality of light emitting chips 400. Next, in S108, the cut out plurality of light emitting chips 400 are packaged individually. Although not shown in Fig. 13, the exposure head 106 can be manufactured through further steps of arranging the light emitting chips 400 on the printed circuit board 202, connecting the light emitting chips 400 to the image controller 700, and mounting the printed circuit board 202 and the rod lens array 203 on the housing 204.

[0048] It should be noted that the processing steps shown in FIG. 13 do not necessarily have to be performed in the order shown. For example, the formation of the light emitting element array in each section may be performed before the formation of the metal film. Also, some of the processing steps shown in the figure may be omitted, and other processing steps may be added.

[0049] <5. Summary> Various embodiments of the technology according to the present disclosure have been described in detail above with reference to FIGS. 1 to 13. According to the above-described embodiment, the exposure device includes a plurality of light-emitting chips arranged in a staggered pattern along a reference line parallel to the axial direction of a photoconductor, and a rod lens array that focuses light from the light-emitting element array of the plurality of light-emitting chips on the surface of the photoconductor. The light-emitting element array of each light-emitting chip is an array of organic EL elements formed on a first surface of a silicon substrate. The distance between the first side of the silicon substrate of each light-emitting chip that is parallel to the reference line and closer to the reference line and the light-emitting element array of the light-emitting chip is 20 micrometers or more. In this way, by ensuring a sufficient distance between the edge of the light-emitting chip and the light-emitting element array, it is possible to improve resistance to intrusion of outside air from the edge into the chip, and provide a highly reliable exposure device.

[0050] In this specification, specific numerical values ​​are used for explanation, but these specific numerical values ​​are merely examples, and the present invention is not limited to the specific numerical values ​​used in the embodiments. Specifically, the number of light-emitting chips provided on one printed circuit board is not limited to 20, and may be any number equal to or greater than 1. In addition, the size of the light-emitting element array of each light-emitting chip 400 is not limited to 4 rows and 748 columns, and may be any other size. In addition, the circumferential pitch and axial pitch of the light-emitting elements are not limited to about 21.16 μm and about 5 μm, and may be any other value.

[0051] <6. Other embodiments> The above-mentioned embodiment can also be realized in the form of a process in which a program for realizing one or more functions is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) for realizing one or more functions.

[0052] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0053] 1: image forming apparatus, 102: photoconductor, 106: exposure head, 203: rod lens array, 310: reference line, 400-1 to 400-20: light emitting chips, 402: silicon substrate, 402a: first surface, 402b: second surface, 403: first side, 410: light emitting element array, 411: metal film, 413: sealing film, 414: non-sealed area, 602: light emitting element (organic EL element), D1: axial direction, D2: circumferential direction, L: interval

Claims

1. a plurality of light emitting chips arranged in a staggered pattern along a reference line parallel to an axial direction of a photoconductor, each of the light emitting chips having a light emitting element array that is an array of organic EL (Electro Luminescence) elements formed on a silicon substrate and a first surface of the silicon substrate; a rod lens array that focuses light from the light emitting element array of the plurality of light emitting chips on a surface of the photoconductor; Equipped with a distance between a first side of the silicon substrate of each light-emitting chip, the first side being parallel to the reference line and closer to the reference line, and the light-emitting element array of the light-emitting chip is 20 micrometers or more; Exposure equipment.

2. Each of the plurality of light emitting chips includes: a sealing film made of an insulating inorganic material that covers the light emitting element array of the light emitting chip; The exposure apparatus of claim 1 , further comprising:

3. Each of the plurality of light emitting chips includes: a metal film formed between the silicon substrate and the sealing film so as to at least partially surround the light emitting element array on the first surface of the silicon substrate; The exposure apparatus of claim 2 , further comprising:

4. The exposure apparatus according to claim 3 , wherein the silicon substrate of each of the plurality of light emitting chips has a non-sealing area that is not covered by the sealing film between the metal film and the first side.

5. The exposure apparatus according to claim 1 , wherein the distance between the first side of each of the plurality of light-emitting chips and the light-emitting element array of that light-emitting chip is 30 micrometers or more.

6. An exposure apparatus according to any one of claims 1 to 5, The photoreceptor; An image forming apparatus comprising:

7. A manufacturing method for manufacturing a light-emitting chip used in an exposure device that exposes a photoconductor with light from a plurality of light-emitting chips, comprising: forming a plurality of light emitting element arrays, each of which is an array of organic EL (Electro Luminescence) elements, spaced apart from one another on a first surface of a silicon substrate; forming a plurality of sealing films made of an insulating inorganic material on the first surface of the silicon substrate so as to cover the plurality of light emitting element arrays, respectively; cutting the silicon substrate along cutting lines located in non-sealing regions not covered by the plurality of sealing films; A manufacturing method comprising:

8. Before forming the sealing films on the first surface of the silicon substrate, a plurality of metal films are formed on the first surface so as to at least partially surround each of the plurality of light emitting element arrays, Each of the plurality of sealing films covers a corresponding light emitting element array and a metal film. The method of claim 7.

9. The method according to claim 7 , wherein a distance between the cutting line and an array of light emitting elements in a section defined by the cutting line on the first surface of the silicon substrate is 20 micrometers or more.

10. The method according to claim 9 , wherein the distance between the cutting line and the light-emitting element array in the section defined by the cutting line on the first surface of the silicon substrate is 30 micrometers or more.

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