Field effect transistor

Abstract

To suppress recovery current in a field effect transistor with a deep layer.SOLUTION: In a field effect transistor, when a semiconductor substrate is viewed from the top, a plurality of contact layers are arranged in each inter-trench region with spaced portions in a specific direction parallel to the plurality of trenches, and when the semiconductor substrate is viewed from the top, a plurality of deep layers are arranged in each inter-trench region with spaced portions in the specific direction. In each inter-trench region, each of the spaced portions of the contact layer is arranged above the corresponding deep layer. In each inter-trench region, each of the spaced portions of the deep layer is arranged below the corresponding contact layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a field effect transistor.

[0002] The field effect transistor disclosed in Patent Document 1 has a trench-type gate electrode. The field effect transistor also has a p-type deep layer (also called a base region lower electric field shield region) extending downward from a p-type body layer (also called a base region). The deep layer extends to a position lower than the lower end of the trench. A p-type contact layer is provided on the deep layer, connecting the body layer and the source electrode. The contact layer is provided to stabilize the potential of the body layer. The deep layer is provided to reduce the electric field strength of the gate insulating film in the trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-267570 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the potential of the source electrode increases, a forward voltage is applied to the pn junction at the interface between the body layer and the drift layer. As a result, the diode formed by this pn junction turns on, and holes flow from the body layer into the drift layer. When the potential of the source electrode then decreases, the holes in the drift layer flow to the source electrode via the deep layer, the body layer, and the contact layer. The current generated by the holes flowing to the source electrode in this way is called a recovery current. When the recovery current flows, a surge voltage occurs in the field effect transistor. In the field effect transistor of Patent Document 1, a high recovery current is likely to occur. In this specification, a technology is proposed to suppress the recovery current in a field effect transistor having a deep layer. [Means for solving the problem]

[0005] The field effect transistor disclosed in this specification includes a semiconductor substrate made of a compound semiconductor and having a plurality of trenches on its upper surface, a plurality of gate electrodes each disposed in a corresponding one of the trenches and insulated from the semiconductor substrate by a gate insulating film, and a source electrode in contact with the upper surface of the semiconductor substrate. The semiconductor substrate includes a plurality of n-type source layers, a plurality of p-type contact layers, a p-type body layer, an n-type drift layer, and a plurality of p-type deep layers. Each semiconductor region located between the plurality of trenches in the semiconductor substrate is an inter-trench region. Each of the source layers is disposed in the corresponding one of the inter-trench regions, in contact with the source electrode, and in contact with the corresponding one of the gate insulating films. Each of the contact layers is disposed in the corresponding one of the inter-trench regions, in contact with the source electrode. A plurality of the contact layers are provided in each of the inter-trench regions. When the semiconductor substrate is viewed from above, the plurality of contact layers are disposed in each of the inter-trench regions with a gap therebetween in a specific direction parallel to the plurality of trenches. The body layer has a lower p-type impurity concentration than each of the contact layers, is distributed across the multiple inter-trench regions, is disposed below each of the source layers and each of the contact layers, and is in contact with the gate insulating film. The drift layer is distributed across the lower regions of the multiple inter-trench regions, is in contact with the body layer from below in each of the inter-trench regions, and is in contact with the gate insulating film. Each of the deep layers extends from the body layer to a position lower than the lower end of each of the trenches. When the semiconductor substrate is viewed from above, the multiple deep layers are arranged in each of the inter-trench regions with gaps in the specific direction. In each of the inter-trench regions, each of the gaps of the contact layer is disposed above the corresponding deep layer. In each of the inter-trench regions, each of the gaps of the deep layer is disposed below the corresponding contact layer.

[0006] In this field effect transistor, the gap of the contact layer is disposed above the deep layer, and the gap of the deep layer is disposed below the contact layer. This reduces the area where the contact layer and the deep layer overlap in the vertical direction. Therefore, the resistance of the path from the drift layer through the deep layer, the body layer, and the contact layer to the source electrode (i.e., the path through which the recovery current flows) is high. Therefore, this field effect transistor can suppress the recovery current. [Brief description of the drawings]

[0007] [Figure 1] 3A and 3B are perspective views showing an xz section and a yz section of a switching element. [Diagram 2] FIG. 4 is an xz cross-sectional view of a switching element at a position not including a deep layer. [Diagram 3] FIG. 13 is an xz cross-sectional view of a switching element at a position including a deep layer. [Figure 4] FIG. 4 is a yz cross-sectional view of the switching element at a position that does not include the trench. [Diagram 5] FIG. 2 is a plan view of the upper surface of a semiconductor substrate. [Figure 6] 4 is a graph showing impurity concentration distributions in a contact region, a body region, and a source region. [Figure 7] 6 is a graph showing the drain current and drain voltage during recovery operation. [Figure 8] Graph showing the relationship between depth D and surge voltage. [Figure 9] 6 is a plan view of a switching element according to a first modified example, corresponding to FIG. 5; [Figure 10] 1 is a graph showing the relationship between width W and the reduction rate of surge voltage. [Figure 11] 6 is a plan view of a switching element according to a second modified example, corresponding to FIG. 5; FIG. [Figure 12] 7 is a plan view of a switching element according to a third modified example, corresponding to FIG. 5; FIG. [Figure 13] 7 is a plan view of a switching element according to a fourth modified example, corresponding to FIG. 5; FIG. [Figure 14] FIG. 11 is a plan view of a switching element according to a fifth modified example, corresponding to FIG. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In one example embodiment disclosed in the present specification, when the semiconductor substrate is viewed from above, each of the deep layers may intersect with each of the trenches.

[0009] According to this configuration, the electric field strength in the gate insulating film can be further reduced.

[0010] In one embodiment disclosed in the present specification, the contact layers and the deep layers do not need to overlap when the semiconductor substrate is viewed from above. In this case, the width of the gap of the contact layers can be made wider than the width of the deep layers, and the width of the gap of the deep layers can be made wider than the width of the contact layers.

[0011] According to this configuration, the recovery current can be suppressed more effectively.

[0012] In one example embodiment disclosed in the present specification, in each inter-trench region, the gap of the deep layer may have a first gap that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second gap that does not overlap with the contact layer when the semiconductor substrate is viewed from above.

[0013] In one example embodiment disclosed in the present specification, in the thickness direction of the semiconductor substrate, a lower end of each of the contact layers may be located at the same position as or higher than a lower end of each of the source layers.

[0014] According to this configuration, depletion of the contact layer can be suppressed, so that the recovery current can be suppressed more effectively.

[0015] The MOSFET 10 (metal-oxide-semiconductor field effect transistor) of the embodiment shown in FIG. 1 has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, one direction parallel to the upper surface 12a of the semiconductor substrate 12 (one direction perpendicular to the z direction) is referred to as the x direction, and a direction perpendicular to the x direction and the z direction is referred to as the y direction. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). The semiconductor substrate 12 may be made of other compound semiconductors such as gallium nitride and gallium oxide. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 5, the plurality of trenches 14 extend long along the y direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x direction. Hereinafter, each semiconductor region within a range sandwiched between the trenches 14 is referred to as an inter-trench region 50.

[0016] As shown in FIGS. 1 to 3, the inner surface (i.e., the side surface and the bottom surface) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present. A drain electrode 24 is disposed on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0017] The semiconductor substrate 12 has a plurality of source layers 30 , a plurality of contact layers 32 , a body layer 34 , a plurality of deep layers 36 , a plurality of trench lower layers 35 , a drift layer 38 , and a drain layer 40 .

[0018] Each contact layer 32 is a p-type layer having a high p-type impurity concentration. As shown in FIGS. 1, 2, 4, and 5, each contact layer 32 is disposed in an inter-trench region 50. Each contact layer 32 is disposed in a range including the upper surface 12a of the semiconductor substrate 12. A plurality of contact layers 32 are provided in each inter-trench region 50. Each contact layer 32 is disposed in a position not in contact with the trench 14. In each inter-trench region 50, a plurality of contact layers 32 are arranged at intervals along the y direction (i.e., a direction parallel to the trench 14 on the upper surface 12a). Hereinafter, a region between the contact layers 32 in the y direction is referred to as an interval portion 33. Each contact layer 32 is in ohmic contact with the source electrode 22.

[0019] Each source layer 30 is an n-type layer having a high n-type impurity concentration. As shown in FIGS. 1 to 5, each source layer 30 is disposed in an inter-trench region 50. Each source layer 30 is provided in a range including the upper surface 12a of the semiconductor substrate 12, where the contact layer 32 is not provided. That is, each source layer 30 is provided in a region adjacent to the trench 14 and in the gap portion 33. The source layer 30 contacts the side surface of the contact layer 32. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 contacts the gate insulating film 16 at the top of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 via the gate insulating film 16.

[0020] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. As shown in FIGS. 1 to 3, the body layer 34 is distributed across a plurality of inter-trench regions 50. The body layer 34 is disposed below the plurality of source layers 30 and the plurality of contact layers 32. The body layer 34 contacts the plurality of source layers 30 and the plurality of contact layers 32 from below. The body layer 34 contacts the gate insulating film 16 on the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 via the gate insulating film 16.

[0021] As shown in FIGS. 1 and 4, each deep layer 36 is a p-type layer protruding downward from the lower surface of the body layer 34. Each deep layer 36 extends from the lower surface of the body layer 34 to a position lower than the lower end of each trench 14. When the semiconductor substrate 12 is viewed from above as shown in FIG. 5, each deep layer 36 extends long in the x direction and intersects with the trench 14 at an angle of about 90 degrees. That is, each deep layer 36 is distributed across a plurality of inter-trench regions 50. When the semiconductor substrate 12 is viewed from above, the plurality of deep layers 36 are arranged at intervals in the y direction. Hereinafter, the region between the deep layers 36 in the y direction is referred to as an interval portion 37. As shown in FIG. 3, each deep layer 36 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Each deep layer 36 faces the gate electrode 18 via the gate insulating film 16.

[0022] 1 to 3, each trench lower layer 35 is a p-type layer disposed in the lower part of the corresponding trench 14. Each trench lower layer 35 extends long along the longitudinal direction (i.e., the y direction) of the corresponding trench 14 and intersects with each deep layer 36. Each trench lower layer 35 contacts the gate insulating film 16 at the bottom surface of the corresponding trench 14.

[0023] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than the source layer 30. The drift layer 38 is distributed across the lower portions of the multiple inter-trench regions 50. The drift layer 38 contacts the multiple deep layers 36 and the multiple trench lower layers 35 from below. The drift layer 38 is distributed up to each of the intervals 37 between the multiple deep layers 36. In each of the intervals 37, the drift layer 38 contacts the side surfaces of the multiple deep layers 36 and the side surfaces of the multiple trench lower layers 35. The drift layer 38 extends into each of the inter-trench regions 50 through each of the intervals 37. In each of the inter-trench regions 50, the drift layer 38 contacts the body layer 34 from below. In each of the inter-trench regions 50, the drift layer 38 contacts the gate insulating film 16. That is, the drift layer 38 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34 .

[0024] The drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in a range including the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0025] 5 shows the positional relationship between the contact layer 32 and the deep layer 36 when the semiconductor substrate 12 is viewed from above. In each inter-trench region 50, each of the gaps 33 of the contact layer 32 is disposed above the corresponding deep layer 36. Also, in each inter-trench region 50, each of the gaps 37 of the deep layer 36 is disposed below the corresponding contact layer 32. Each contact layer 32 is disposed at a position that does not overlap with the deep layer 36 when the semiconductor substrate 12 is viewed from above.

[0026] As shown in FIG. 2, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30. FIG. 6 shows the impurity concentration distribution in the z direction in the source layer 30, the contact layer 32, and the body layer 34. The lower end 30a of the source layer 30 is defined as a position where the n-type impurity concentration and the p-type impurity concentration are the same. In the body layer 34 (i.e., the p-type region below the source layer 30), the p-type impurity concentration is distributed in a normal distribution shape having a peak value P1. In this specification, the contact layer 32 is defined as a p-type layer having a p-type impurity concentration higher than the peak value P1. Therefore, the lower end 32a of the contact layer 32 is defined as a position having the same p-type impurity concentration as the peak value P1. As shown in FIG. 6, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30.

[0027] Next, the operation of the MOSFET 10 will be described. When a potential equal to or higher than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. The channel connects the source layer 30 and the drift layer 38. When the potential of the drain electrode 24 is higher than the potential of the source electrode 22, electrons flow from the source layer 30 to the drain layer 40 via the channel and the drift layer 38. That is, the MOSFET 10 is turned on. When the potential of each gate electrode 18 is reduced to a value lower than the gate threshold, the channel disappears and the flow of electrons stops. That is, the MOSFET 10 is turned off. When the MOSFET 10 is turned off, a depletion layer extends from the body layer 34 to the drift layer 38. In addition, a depletion layer also extends from the deep layer 36 and the trench lower layer 35 to the drift layer 38. The depletion layer extending from the deep layer 36 and the trench lower layer 35 promotes depletion in the semiconductor region around the lower end of the trench 14. This suppresses electric field concentration in the gate insulating film 16.

[0028] Also, a potential higher than that of the drain electrode 24 may be applied to the source electrode 22. When a potential higher than that of the drain electrode 24 is applied to the source electrode 22, a diode formed by a pn junction at the interface between the p-type layer (i.e., a p-type layer formed by the body layer 34, the trench lower layer 35, and the deep layer 36) and the drift layer 38 is turned on. That is, holes flow from the p-type layer to the drift layer 38, and electrons flow from the drift layer 38 to the p-type layer. Thereafter, when the voltage applied to the MOSFET 10 is changed and the potential of the source electrode 22 becomes lower than the potential of the drain electrode 24, a recovery operation occurs in the diode. FIG. 7 shows the change in the drain-source voltage Vds and the drain current Ids during the recovery operation. In the recovery operation, a depletion layer develops from the pn junction at the interface between the p-type layer and the drift layer 38 into the drift layer, and holes in the drift layer 38 are discharged to the source electrode 22 via the p-type layer. As a result, a recovery current IR flows as shown in FIG. 7. As a result, a surge voltage Vak occurs between the source electrode 22 and the drain electrode 24. In this embodiment, since the deep layer 36 protrudes toward the drift layer 38, holes are likely to flow from the drift layer 38 into the deep layer 36 during recovery operation. Therefore, as shown by an arrow 100 in FIG. 4, holes are discharged from the drift layer 38 to the source electrode 22 through the deep layer 36, the body layer 34, and the contact layer 32. In this embodiment, since the contact layer 32 does not exist above the deep layer 36, holes that have passed through the deep layer 36 move laterally in the body layer 34 and then flow to the contact layer 32. Therefore, the resistance of the path through which the holes flow is high. Therefore, the recovery current IR is suppressed, and the surge voltage Vak is suppressed.

[0029] In addition, in the recovery operation, the depletion layer also extends from the pn junction into the p-type layer. Holes discharged from the depleted p-type layer to the source electrode 22 also constitute the recovery current. In the body layer 34, the depletion layer extends from the pn junction toward the upper side. When the depletion layer reaches the lower end 30a of the source layer 30, the depletion layer stops extending upward. In this embodiment, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30, so that the depletion layer is prevented from extending into the contact layer 32. Therefore, the high concentration holes in the contact layer 32 are prevented from being discharged to the source electrode 22 as the recovery current. This further suppresses the recovery current and the surge voltage. FIG. 8 shows the relationship between the depth D of the contact layer 32 and the surge voltage Vak. In FIG. 8, the depth D means the relative position in the z direction of the lower end 32a of the contact layer 32 with respect to the lower end 30a of the source layer 30. The depth D being positive means that the lower end 32a of the contact layer 32 is located higher than the lower end 30a of the source layer 30. As shown in Fig. 8, the greater the depth D (i.e., the higher the lower end 32a of the contact layer 32 is located), the more the surge voltage Vak is suppressed.

[0030] As described above, the MOSFET 10 of the embodiment can suppress the recovery current.

[0031] In the above embodiment, the lower end 32a of the contact layer 32 is located above the lower end 30a of the source layer 30. However, in the thickness direction of the semiconductor substrate 12, the lower end 32a of the contact layer 32 may be located at the same position as the lower end 30a of the source layer 30. That is, the depth D may be zero. As shown in FIG. 8, even when the depth D is zero, the surge voltage Vak is suppressed more than when the depth D is negative.

[0032] In the above embodiment, the contact layer 32 does not exist on the deep layer 36. However, as shown in FIG. 9, a part 32x of the contact layer 32 may be disposed on the deep layer 36. That is, when the semiconductor substrate 12 is viewed from above, the part 32x of the contact layer 32 may overlap the deep layer 36. FIG. 10 shows the relationship between the width W (see FIG. 9) of the overlapping part of the contact layer 32 and the deep layer 36 and the reduction rate of the surge voltage Vak. The width W being negative means that the contact layer 32 and the deep layer 36 do not overlap. In addition, in FIG. 10, the width Wd means the width of the deep layer 36 in the y direction (see FIG. 9). W=1 / 2Wd means that the interval portion 33 does not exist. As shown in FIG. 10, even when the width W is positive, the surge voltage Vak decreases as the width W decreases from 1 / 2Wd. In this way, even if a portion 32x of the contact layer 32 overlaps with the deep layer 36, by disposing the spacing portion 33 on the upper part of the deep layer 36, the resistance of the path of the recovery current can be increased, and the recovery current can be suppressed.

[0033] In the above embodiment, the contact layer 32 is provided for each gap 37 of the deep layer 36. However, as shown in Fig. 11, the number of contact layers 32 may be less than the number of gaps 37 in each inter-trench region 50. That is, in Fig. 11, the gap 37 has a first gap 37a that overlaps with the contact layer 32 when the semiconductor substrate 12 is viewed from above, and a second gap 37b that does not overlap with the contact layer 32 when the semiconductor substrate 12 is viewed from above. In this case, the contact layers 32 may be disposed in an evenly distributed manner.

[0034] In the above embodiment, the source layer 30 is provided in the entire area where the contact layer 32 does not exist in the surface layer portion near the upper surface 12a. However, the distribution range of the source layer 30 may be narrower. FIGS. 12 and 13 show an example in which the distribution range of the source layer 30 is narrower than that of FIG. 5. In FIGS. 12 and 13, the hatched area R indicates an area on the upper surface 12a where neither the contact layer 32 nor the source layer 30 is arranged. In the area R, the body layer 34 is in contact with the source electrode 22 on the upper surface 12a. In FIG. 12, the source layer 30 is provided only in an area adjacent to the trench 14. In FIG. 13, the body layer 34 (i.e., the area R) is provided in an area adjacent to the end of the contact layer 32 in the x direction, and the source layer 30 is provided in the other area.

[0035] In the above embodiment, each deep layer 36 extends long in the x direction when the semiconductor substrate 12 is viewed from above. However, as shown in FIG. 14, each deep layer 36 may be provided distributed in the x direction when the semiconductor substrate 12 is viewed from above. In FIG. 14, the deep layers 36 are provided distributed in the x direction so that each deep layer 36 exists in each inter-trench region 50. In each inter-trench region 50, the deep layers 36 are arranged at intervals in the y direction. The configuration of FIG. 14 can also suppress the recovery current.

[0036] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A field effect transistor, A semiconductor substrate made of a compound semiconductor and having a plurality of trenches on an upper surface thereof; a plurality of gate electrodes each disposed in a corresponding one of the trenches and insulated from the semiconductor substrate by a gate insulating film; a source electrode in contact with an upper surface of the semiconductor substrate; having the semiconductor substrate has a plurality of n-type source layers, a plurality of p-type contact layers, a p-type body layer, an n-type drift layer, and a plurality of p-type deep layers; Each semiconductor region located between the plurality of trenches in the semiconductor substrate is an inter-trench region; Each of the source layers is disposed in a corresponding one of the inter-trench regions, contacts the source electrode, and contacts a corresponding one of the gate insulating films; Each of the contact layers is disposed in a corresponding one of the inter-trench regions and contacts the source electrode; A plurality of the contact layers are provided in each of the inter-trench regions, When the semiconductor substrate is viewed from above, in each of the inter-trench regions, a plurality of the contact layers are arranged at intervals in a specific direction parallel to the plurality of trenches, the body layer has a p-type impurity concentration lower than that of each of the contact layers, is distributed across the plurality of inter-trench regions, is disposed below each of the source layers and each of the contact layers, and is in contact with the gate insulating film; the drift layer is distributed across lower regions of the plurality of inter-trench regions, is in contact with the body layer from below in each of the inter-trench regions, and is in contact with the gate insulating film; each of the deep layers extends from the body layer to a position lower than a lower end of each of the trenches; When the semiconductor substrate is viewed from above, a plurality of the deep layers are arranged in the inter-trench regions at intervals in the specific direction, In each of the inter-trench regions, each of the gaps of the contact layer is disposed above a corresponding one of the deep layers; In each of the inter-trench regions, each of the gaps of the deep layer is disposed below a corresponding one of the contact layers. Field effect transistor. (Configuration 2) 2. The field effect transistor of claim 1, wherein each of the deep layers intersects each of the trenches when viewed from above the semiconductor substrate. (Configuration 3) 3. The field effect transistor according to claim 1, wherein the contact layers and the deep layers do not overlap each other when viewed from above the semiconductor substrate. (Configuration 4) A field effect transistor according to any one of configurations 1 to 3, wherein in each inter-trench region, the spacing of the deep layer has a first spacing that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second spacing that does not overlap with the contact layer when the semiconductor substrate is viewed from above. (Configuration 5) 5. The field effect transistor according to any one of configurations 1 to 4, wherein, in a thickness direction of the semiconductor substrate, a lower end of each of the contact layers is located at the same position as or higher than a lower end of each of the source layers.

[0037] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0038] 12: semiconductor substrate, 14: trench, 18: gate electrode, 30: source layer, 32: contact layer, 33: gap, 34: body layer, 36: deep layer, 37: gap, 50: inter-trench region

Claims

1. A field effect transistor, A semiconductor substrate (12) made of a compound semiconductor and having a plurality of trenches (14) formed on an upper surface thereof; a plurality of gate electrodes (18) each disposed in a corresponding one of the trenches and insulated from the semiconductor substrate by a gate insulating film; A source electrode (22) in contact with the upper surface of the semiconductor substrate; having The semiconductor substrate has a plurality of n-type source layers (30), a plurality of p-type contact layers (32), a p-type body layer (34), an n-type drift layer (38), and a plurality of p-type deep layers (36); Each semiconductor region located between a plurality of the trenches in the semiconductor substrate is an inter-trench region (50); Each of the source layers is disposed in a corresponding one of the inter-trench regions, contacts the source electrode, and contacts a corresponding one of the gate insulating films; when one of the trenches arranged on both sides of each of the inter-trench regions is defined as a first trench and the other is defined as a second trench, in each of the inter-trench regions, the source layer has a first portion that contacts the gate insulating film on a side surface of the first trench and a second portion that contacts the gate insulating film on a side surface of the second trench, Each of the contact layers is disposed in a corresponding one of the inter-trench regions and contacts the source electrode; A plurality of the contact layers are provided in each of the inter-trench regions, When the semiconductor substrate is viewed from above, in each of the inter-trench regions, a plurality of the contact layers are arranged with intervals (33) in a specific direction parallel to the plurality of trenches, In each of the inter-trench regions, a plurality of the contact layers are disposed between the first portion and the second portion; the body layer has a p-type impurity concentration lower than that of each of the contact layers, is distributed across the plurality of inter-trench regions, is disposed below each of the source layers and each of the contact layers, and is in contact with the gate insulating film; the drift layer is distributed across lower regions of the plurality of inter-trench regions, is in contact with the body layer from below in each of the inter-trench regions, and is in contact with the gate insulating film; each of the deep layers extends from the body layer to a position lower than a lower end of each of the trenches; When the semiconductor substrate is viewed from above, a plurality of the deep layers are arranged in the inter-trench regions with intervals (37) in the specific direction, In each of the inter-trench regions, each of the gaps of the contact layer is disposed above a corresponding one of the deep layers; In each of the inter-trench regions, each of the gaps of the deep layer is disposed below a corresponding one of the contact layers. Field effect transistor.

2. The first portion extends along the first trench over a range of a plurality of the contact layers arranged with the intervals in the specific direction, the second portion extends along the second trench over a range of the plurality of contact layers arranged at intervals in the specific direction; 2. The field effect transistor of claim 1.

3. 2. The field effect transistor according to claim 1, wherein each of said deep layers intersects each of said trenches when said semiconductor substrate is viewed from above.

4. 3. The field effect transistor according to claim 1, wherein the contact layers and the deep layers do not overlap each other when the semiconductor substrate is viewed from above.

5. 3. A field effect transistor as described in claim 1 or 2, wherein in each inter-trench region, the gap of the deep layer has a first gap (37a) that overlaps with the contact layer when the semiconductor substrate is viewed from above, and a second gap (37b) that does not overlap with the contact layer when the semiconductor substrate is viewed from above.

6. 3. The field effect transistor according to claim 1, wherein a lower end (32a) of each of said contact layers is located at the same position as or above a lower end (30a) of each of said source layers in a thickness direction of said semiconductor substrate.

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