Semiconductor device

Abstract

To provide a semiconductor device having a structure in which a withstand voltage or a withstand capacity does not decrease.SOLUTION: A semiconductor device includes a plurality of trench portions that are provided from an upper surface 21 of a semiconductor substrate 10 to a lower side of a base region 14 and include a gate trench portion and a dummy trench portion, a first lower end region 202 of a second conductivity type provided in contact with the lower ends of two or more trench portions including the gate trench portion, a well region 11 of a second conductivity type that is disposed at a position different from the first lower end region in top view, is provided from the upper surface of the semiconductor substrate to the lower side of the base region, and has a doping concentration higher than that of the base region, and a second lower end region 205 of a second conductivity type that is provided between the first lower end region and the well region in top view, the first lower end region and the well region being provided to be separated from each other, and the second lower end region 205 being provided in contact with the lower ends of one or more trench portions including the gate trench portion.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, a structure is known in which a P-type floating region separated from a P-type well region is provided at the bottom of a gate trench (see, for example, Patent Document 1). Patent Document 1: JP 2019-91892 A Problem to be Solved

[0003] It is preferable that the breakdown voltage or withstand voltage of the semiconductor device is not reduced.

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and including a drift region of a first conductivity type. Any of the above semiconductor devices may include a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate. Any of the above semiconductor devices may include a plurality of trench portions including a gate trench portion and a dummy trench portion, which are provided from the upper surface of the semiconductor substrate to below the base region. Any of the above semiconductor devices may include a first lower end region of a second conductivity type provided in contact with lower ends of two or more trench portions including the gate trench portion. Any of the above semiconductor devices may include an isolation region that does not overlap with the first lower end region in a top view. In any of the above semiconductor devices, the isolation region may include a second lower end region of a second conductivity type provided in contact with lower ends of one or more trench portions including the gate trench portion.

[0005] In any of the semiconductor devices described above, the number of the trench portions that one of the second lower end regions contacts may be smaller than the number of the trench portions that one of the first lower end regions contacts.

[0006] In any of the semiconductor devices described above, one of the second lower end regions may be in contact with a lower end of one of the gate trench portions, and may not be in contact with the lower ends of the gate trench portions other than that gate trench portion.

[0007] In any of the semiconductor devices described above, one of the first lower end regions may be in contact with lower ends of a plurality of the gate trench portions and a plurality of the dummy trench portions.

[0008] In any of the above semiconductor devices, one of the second lower end regions may be in contact with a lower end of one of the gate trench portions, and may not be in contact with the lower end of the trench portion arranged adjacent to that gate trench portion.

[0009] In any of the above semiconductor devices, one of the second lower end regions may be in contact with a lower end of one of the gate trench portions and also in contact with a lower end of the dummy trench portion arranged adjacent to the gate trench portion.

[0010] Any of the above semiconductor devices may include a well region of a second conductivity type arranged at a position different from the first lower end region in a top view, provided from the upper surface of the semiconductor substrate to below the base region, and having a doping concentration higher than that of the base region. Any of the above semiconductor devices may include a third lower end region of the second conductivity type arranged in contact with a lower end of the dummy trench portion. In any of the above semiconductor devices, the dummy trench portion with which the third lower end region is in contact may be arranged next to the gate trench portion with which the second lower end region is in contact. In any of the above semiconductor devices, the third lower end region may be separated from all of the first lower end region, the second lower end region, and the well region.

[0011] In any of the semiconductor devices described above, a plurality of the second lower end regions may be arranged apart from one another along a longitudinal direction of the gate trench portion.

[0012] In any of the semiconductor devices described above, the isolation region may be sandwiched between two of the first lower end regions in a top view.

[0013] In any of the above semiconductor devices, the gate trench portion may have a gate insulating film and a gate conductive portion insulated from the semiconductor substrate by the gate insulating film. In any of the above semiconductor devices, the gate conductive portion in at least one of the gate trench portions in contact with the second lower end region may be shorter in a depth direction than the gate conductive portion of the gate trench portion in contact with the first lower end region.

[0014] In any of the above semiconductor devices, two or more of the dummy trench portions not in contact with the first lower end region and the second lower end region may be arranged in succession next to the gate trench portion in contact with the first lower end region. Any of the above semiconductor devices may include a fourth lower end region of the second conductivity type provided in contact with lower ends of the two or more dummy trench portions arranged in succession.

[0015] In any of the above semiconductor devices, the gate trench portion may have a gate insulating film and a gate conductive portion insulated from the semiconductor substrate by the gate insulating film. In any of the above semiconductor devices, in at least one of the gate trench portions in contact with the second lower end region, the gate conductive portion at a position in contact with the gate insulating film may be longer in a depth direction than the gate conductive portion at a position farthest from the gate insulating film.

[0016] In any of the semiconductor devices described above, at least one of the gate trench portions in contact with the second lower end region may be shorter in a depth direction than the gate trench portion in contact with the first lower end region.

[0017] In any of the above semiconductor devices, at least one of the first lower end regions may be provided in contact with a lower end of the dummy trench portion. In any of the above semiconductor devices, the isolation region may include one or more of the dummy trench portions. In any of the above semiconductor devices, at least one of the dummy trench portions in the isolation region may be longer in a depth direction than the dummy trench portion in contact with the first lower end region.

[0018] Any of the above semiconductor devices may include an emitter region of a first conductivity type exposed on the upper surface of the semiconductor substrate, provided in contact with the gate trench portion, and having a doping concentration higher than that of the drift region. Any of the above semiconductor devices may include contact regions of a second conductivity type exposed on the upper surface of the semiconductor substrate, arranged alternately with the emitter regions along a longitudinal direction of the gate trench portion, and having a doping concentration higher than that of the base region. In any of the above semiconductor devices, the second lower end region may be arranged to overlap the emitter region in a top view.

[0019] Any of the above semiconductor devices may include a collector region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate.

[0020] Any of the above semiconductor devices may include a source region of a first conductivity type exposed on the upper surface of the semiconductor substrate, provided in contact with the gate trench portion, and having a doping concentration higher than that of the drift region. Any of the above semiconductor devices may include contact regions of a second conductivity type exposed on the upper surface of the semiconductor substrate, arranged alternately with the source regions along a longitudinal direction of the gate trench portion, and having a doping concentration higher than that of the base region. In any of the above semiconductor devices, the second lower end region may be arranged to overlap the source region in a top view.

[0021] Any of the above semiconductor devices may include a drain region of a first conductivity type provided in contact with the lower surface of the semiconductor substrate.

[0022] In any of the above semiconductor devices, the second lower end regions may be provided for two or more of the gate trench portions, the second lower end regions being separated from each other.

[0023] In a second aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and including a drift region of a first conductivity type. Any of the above semiconductor devices may include a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate. Any of the above semiconductor devices may include a plurality of trench portions including a gate trench portion and a dummy trench portion, which are provided from the upper surface of the semiconductor substrate to below the base region. Any of the above semiconductor devices may include a second lower end region of a second conductivity type provided in contact with a lower end of one or more trench portions including the gate trench portion. In any of the above semiconductor devices, the gate trench portion in contact with the second lower end region may be shorter in the depth direction than at least one other of the gate trench portions.

[0024] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0025] [Figure 1] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of an area D in FIG. [Diagram 3] FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2. [Figure 4] 2 is a diagram showing an example of the arrangement of a well region 11 and a first lower end region 202 in a top view. FIG. [Diagram 5] FIG. 5 is a diagram showing an example of the ff cross section in FIG. [Figure 6] 13 is a diagram showing another example of the arrangement of the gate trench portions 40 and the dummy trench portions 30. FIG. [Figure 7]13 is a diagram showing an example of the distribution of the electric field in the X-axis direction at the depth position of the bottom end of the trench portion. FIG. [Figure 8] 13 is a diagram showing another example of the second lower end region 205. FIG. [Figure 9A] 2 is an enlarged view of the vicinity of the first lower end region 202 and the second lower end region 205. FIG. [Figure 9B] FIG. 9B is a diagram showing an example of the forming process of FIG. 9A. [Figure 10] 13 is a diagram showing another example of the configuration of the separation region 204. FIG. [Figure 11] 13 is a diagram showing an example of distribution of doping concentrations in the first lower end region 202, the second lower end region 205, and the third lower end region 207 in the Z-axis direction. FIG. [Figure 12] FIG. 2 is a diagram showing another example of the separation region 204. [Figure 13] FIG. 2 is a diagram showing another example of the separation region 204. [Figure 14] FIG. 5 is a diagram showing an example of the gg cross section in FIG. [Figure 15] FIG. 6 is a diagram showing an example of the hh cross section in FIG. [Figure 16] FIG. 6 is a diagram showing an example of the hh cross section in FIG. [Figure 17] 2A to 2C are diagrams illustrating some steps in a manufacturing method of the semiconductor device 100. [Figure 18] FIG. 17 is a diagram illustrating an example of a lower end region forming step S1704. [Figure 19] FIG. 5 is a diagram showing an example of the jj cross section in FIG. [Figure 20] FIG. 13 is a diagram showing another example of the ff cross section. [Figure 21] 13 is a diagram showing another example of the structure of the separation region 204. FIG. [Figure 22] 13 is a diagram showing another example of the structure of the separation region 204. FIG. [Diagram 23] 13 is a diagram showing another example of the structure of the separation region 204. FIG. [Figure 24] 13 is a diagram showing another example of the structure of the separation region 204. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0027] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0028] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0029] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0030] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0031] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0032] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0033] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0034] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor.

[0035] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants contained almost uniformly in the ingot during the manufacture of the ingot that is the basis of the semiconductor substrate. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donors in this example are phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 A higher oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be between 90% and 100% of the chemical concentration. A non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 10 / cm 3 That's it, 5 x 10 12 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 12 / cm 3 The concentrations in the present invention may be values ​​at room temperature. For example, the values ​​at room temperature may be values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0036] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0037] In this specification, the chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, in an N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may be the acceptor concentration. In this specification, the doping concentration in an N-type region may be referred to as the donor concentration, and the doping concentration in a P-type region may be referred to as the acceptor concentration.

[0038] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. In cases where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom count notation may be omitted.

[0039] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0040] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0041] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0042] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end sides 162 in a top view. When simply referred to as a top view in this specification, it means a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of end sides 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either of the end sides 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0043] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted in FIG. 1 . The active portion 160 may refer to a region overlapped by the emitter electrode in a top view. In addition, a region sandwiched between the active portions 160 in a top view may also be included in the active portion 160.

[0044] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). The active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0045] In FIG. 1, the region in which the transistor section 70 is arranged is marked with the symbol "I", and the region in which the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0046] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring to be described later may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0047] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0048] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an end edge 162. The vicinity of the end edge 162 refers to the region between the end edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0049] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0050] The gate wiring in this example has a peripheral gate wiring 130 and an active side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0051] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0052] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, the variation in wiring length from the gate pad 164 for each region of the semiconductor substrate 10 can be reduced.

[0053] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to a gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0054] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 is provided extending in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 sandwiching the active portion 160, so as to cross the active portion 160 at approximately the center in the Y-axis direction. When the active portion 160 is divided by the active side gate wiring 131, the transistor portion 70 and the diode portion 80 may be arranged alternately in the X-axis direction in each divided region.

[0055] Furthermore, the semiconductor device 100 may include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 160.

[0056] In the present example, semiconductor device 100 includes an edge termination structure 90 between active portion 160 and edge 162 when viewed from above. Edge termination structure 90 in the present example is disposed between peripheral gate wiring 130 and edge 162. Edge termination structure 90 relieves electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf that are provided in an annular shape surrounding active portion 160.

[0057] 2 is an enlarged view of region D in FIG. 1. Region D is a region including a transistor section 70, a diode section 80, and an active side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of a semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0058] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with oblique lines.

[0059] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0060] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0061] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the range in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like, below the region made of aluminum or the like. Furthermore, the emitter electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.

[0062] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width to an area where it does not overlap with the active side gate wiring 131. The well region 11 in this example is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0063] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0064] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) extending along an extension direction perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0065] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0066] In the transistor section 70, the dummy trench section 30 is provided between the respective straight line portions 39 of the gate trench section 40. One dummy trench section 30 may be provided between the respective straight line portions 39, or a plurality of dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight line shape extending in the extension direction, and may have a straight line portion 29 and a tip section 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both a straight line dummy trench section 30 without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0067] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends in the Y-axis direction of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. That is, at the ends in the Y-axis direction of each trench portion, the bottoms in the depth direction of each trench portion are covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottoms of each trench portion.

[0068] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, when the term "mesa portion" is simply used, it refers to each of the mesa portion 60 and the mesa portion 61.

[0069] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active side gate wiring 131 is defined as the base region 14-e. In FIG. 2, the base region 14-e is shown at one end in the extension direction of each mesa portion, but the base region 14-e is also provided at the other end of each mesa portion. In each mesa portion, at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0070] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0071] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact region 15 and the emitter region 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portion (the Y-axis direction).

[0072] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0073] No emitter region 12 is provided in the mesa portion 61 of the diode portion 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In a region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0074] A contact hole 54 is provided above each mesa portion. The contact hole 54 is disposed in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be disposed in the center of the arrangement direction of the mesa portions 60 (X-axis direction).

[0075] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0076] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed to a deep position, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0077] Fig. 3 is a diagram showing an example of an ee cross section in Fig. 2. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0078] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described in FIG. 2.

[0079] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and is in contact with the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0080] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0081] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0082] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0083] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0084] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. In other words, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0085] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, an accumulation region 16 may be provided below the base region 14.

[0086] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have a concentration peak having a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0087] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be provided at the same depth position as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0088] In the transistor portion 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0089] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. The elements serving as the donor and acceptor of each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0090] At least one gate trench portion 40 and at least one dummy trench portion 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion is provided from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doped regions. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed in the order of forming the doped region and then the trench portion. A case where the trench portion is formed and then the doped region is formed between the trench portions is also included in the case where the trench portion penetrates the doped region.

[0091] As described above, the transistor portion 70 is provided with the gate trench portion 40 and the dummy trench portion 30. The diode portion 80 is provided with the dummy trench portion 30, but is not provided with the gate trench portion 40. In this example, the boundary between the diode portion 80 and the transistor portion 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0092] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0093] The gate conductive portion 44 may be provided longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0094] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0095] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross section) convex downward. In this specification, the depth position of the lower end of the gate trench portion 40 is designated as Zt.

[0096] The semiconductor device 100 of this example includes a P-type first lower end region 202 provided in contact with the lower end of the trench portion. The doping concentration of the first lower end region 202 may be equal to or lower than the doping concentration of the base region 14. The doping concentration of the first lower end region 202 of this example is lower than the doping concentration of the base region 14. The P-type dopant may be boron or aluminum.

[0097] The first lower end region 202 is disposed away from the base region 14. Between the first lower end region 202 and the base region 14, an N-type region (at least one of the accumulation region 16 and the drift region 18 in this example) is provided.

[0098] The first lower end region 202 is provided continuously so as to contact the lower ends of two or more trench portions in the X-axis direction. In other words, the first lower end region 202 is provided so as to cover the mesa portion between the trench portions. The first lower end region 202 may cover multiple mesa portions. The first lower end region 202 in this example is provided so as to contact the lower ends of two or more trench portions including the gate trench portion 40.

[0099] The first lower end region 202 may be in contact with the lower ends of two or more trench portions in each transistor portion 70. The first lower end region 202 may also be in contact with the lower ends of two or more gate trench portions 40 in each transistor portion 70. The first lower end region 202 may also be in contact with the lower ends of two or more dummy trench portions 30 in each transistor portion 70. The first lower end region 202 may be in contact with the lower ends of all trench portions in at least one transistor portion 70. The first lower end region 202 may also be in contact with the lower ends of all gate trench portions 40 in at least one transistor portion 70.

[0100] The first lower end region 202 may be in contact with the lower ends of two or more trench portions in each diode portion 80. The first lower end region 202 may be in contact with the lower ends of all of the trench portions in at least one diode portion 80.

[0101] The first lower end region 202 is provided extending in the Y-axis direction. The length of the first lower end region 202 in the Y-axis direction is shorter than the length of the trench portion in the Y-axis direction. Furthermore, the length of the first lower end region 202 in the Y-axis direction may be 50% or more, 70% or more, or 90% or more of the length of the trench portion in the Y-axis direction.

[0102] Providing the first lower end region 202 can suppress a rise in potential near the lower end of the trench portion when the semiconductor device 100 is turned on. This can reduce the gradient (dv / dt) of the waveform of the emitter-collector voltage when turned on, thereby reducing noise in the voltage or current waveform during switching.

[0103] The potential of the first lower end region 202 is different from the potential of the emitter electrode 52. As described above, the first lower end region 202 is disposed apart from the base region 14 connected to the emitter electrode 52 in the Z-axis direction. The first lower end region 202 is also disposed apart from the well region connected to the emitter electrode 52 in a top view. The active section 160 may have a portion in which the first lower end region 202 is not provided in at least one of the X-axis direction and the Y-axis direction. The first lower end region 202 may be an electrically floating region that is not connected to any electrode.

[0104] 4 is a diagram showing an example of the arrangement of well regions 11 and first lower end regions 202 in a top view. The first lower end region 202 in this example is provided in the active section 160. The first lower end region 202 may be provided in 50% or more of the area of ​​the active section 160 in a top view, or may be provided in 70% or more of the area, or may be provided in 90% or more of the area.

[0105] A well region 11 is provided below the gate wiring shown in Fig. 1. In top view, the well region 11 and the first lower end region 202 are disposed at different positions. As shown in Fig. 4, the well region 11 may be disposed so as to surround the first lower end region 202 in top view. As shown in Fig. 4, when the first lower end region 202 is divided into a plurality of regions, the well region 11 may surround each of the first lower end regions 202.

[0106] In a top view, a separation region 204 is provided between the well region 11 and the first lower end region 202. The separation region 204 does not overlap with the first lower end region 202 in a top view. The separation region 204 is a region that separates the first lower end region 202 from other regions. The separation region 204 in this example includes an N-type region that separates the well region 11 and the first lower end region 202. The N-type region is, for example, the drift region 18. The N-type region is arranged so as to surround the first lower end region 202 in a top view. The well region 11 is arranged so as to surround the separation region 204 in a top view. In FIG. 4, the separation region 204 is hatched with oblique lines. By providing the separation region 204 between the well region 11 and the first lower end region 202, it is possible to prevent the first lower end region 202 from having the same potential as the well region 11. This prevents the first lower end region 202 from reaching the emitter potential, allowing the transistor section 70 and the diode section 80 to operate.

[0107] In this example, the separation region 204 is provided in the entire region of the active unit 160 where the first lower end region 202 is not provided. As shown in Fig. 19, when there is a portion inside the active unit 160 where the first lower end region 202 is not provided, the separation region 204 may also be provided in that portion. The separation region 204 arranged inside the active unit 160 may be surrounded by the first lower end region 202 in a top view.

[0108] Fig. 5 is a diagram showing an example of the ff cross section in Fig. 4. The ff cross section is an XZ plane passing through the first lower end region 202, the isolation region 204, and the well region 11. In other words, the ff cross section is an XZ plane in the vicinity of the boundary between the active portion 160 and the well region 11. Note that Fig. 5 shows the structure of the semiconductor substrate 10, and omits configurations such as electrodes and insulating films disposed above and below the semiconductor substrate 10. Also, in Fig. 5, the gate trench portion 40 is given the symbol G, and the dummy trench portion 30 is given the symbol E.

[0109] The ff cross section shown in FIG. 5 includes the transistor portion 70 arranged at the end in the X-axis direction among the multiple transistor portions 70. The structure of the transistor portion 70 is the same as that of the transistor portion 70 described in FIG. 2 and FIG. 3. In FIG. 5, one dummy trench portion 30 is arranged between two gate trench portions 40 as in G / E / G / E / ··, but two dummy trench portions 30 may be arranged between two gate trench portions 40 as in G / E / E / G / E / E / ··. The arrangement of the gate trench portions 40 and the dummy trench portions 30 may have another structure. In addition, the multiple trench portions of the isolation region 204 may be arranged at regular intervals in the X-axis direction. The intervals between the trench portions of the isolation region 204 may be the same as the intervals between the trench portions of the transistor portion 70.

[0110] A first lower end region 202 is provided at the lower end of the trench portion of the transistor portion 70. Of the gate trench portions 40(G) to which the emitter region 12 is provided adjacent, the center of the gate trench portion 40(G) disposed at the end furthest in the X-axis direction is defined as the end portion of the transistor portion 70 in the X-axis direction. The first lower end region 202 may extend further outward in the X-axis direction than the transistor portion 70. In other words, the first lower end region 202 may extend to a region in which no gate structure including the gate trench portion 40 and the emitter region 12 is provided.

[0111] The well region 11 is provided from the upper surface 21 of the semiconductor substrate 10 to below the base region 14. The well region 11 is a P+ type region having a higher doping concentration than the base region 14.

[0112] In top view, the region between the first lower end region 202 and the well region 11 is the isolation region 204. One or more trench portions are provided in the isolation region 204. In this example, the isolation region 204 is provided with one or more gate trench portions 40 and one or more dummy trench portions 30. The arrangement of the trench portions in the isolation region 204 in the X-axis direction may be the same as or different from that of the transistor portion 70.

[0113] A base region 14 is provided in the mesa portion of the separation region 204. A contact region 15 may be provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10. An emitter region 12 may be provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10. An accumulation region 16 may or may not be provided in the mesa portion of the separation region 204. For example, among the mesa portions of the separation region 204, the accumulation region 16 may be provided in one or more mesa portions closest to the transistor portion 70.

[0114] The first lower end region 202 in this example is a P-type region having a lower doping concentration than the well region 11. The first lower end region 202 is disposed in at least a portion of the transistor section 70. The first lower end region 202 in this example extends toward the well region 11 side beyond the end of the transistor section 70. In another example, the first lower end region 202 may terminate at the end of the transistor section 70, or may terminate inside the transistor section 70.

[0115] The isolation region 204 has one or more second lower end regions 205. The second lower end region 205 is a region of a second conductivity type provided in contact with the lower end of one or more trench portions including the gate trench portion 40. The second lower end region 205 may have a doping concentration higher than, lower than, or the same as that of the first lower end region 202.

[0116] The second lower end region 205 may be provided continuously along the extension direction (Y-axis direction) of the trench portion. The length of the second lower end region 205 in the Y-axis direction may be the same as the length of the first lower end region 202 in the Y-axis direction, or may be 80% or more and 120% or less of the length of the first lower end region 202 in the Y-axis direction. The second lower end region 205 may be provided discretely along the extension direction (Y-axis direction) of the trench portion.

[0117] The second lower end region 205 is provided between the first lower end region 202 and the well region 11 in a top view. The second lower end region 205 in this example is provided between the first lower end region 202 and the well region 11 in the X-axis direction. The second lower end region 205 is provided separately from the first lower end region 202 and the well region 11. An N-type region such as the drift region 18 is provided between the second lower end region 205 and the first lower end region 202 in a top view. An N-type region such as the drift region 18 is provided between the second lower end region 205 and the well region 11 in a top view. In addition, when a plurality of second lower end regions 205 are provided, an N-type region such as the drift region 18 is provided between two second lower end regions 205 in a top view.

[0118] In the X-axis direction, the distance between the first lower end region 202 and the second lower end region 205 may be greater or smaller than the width of the mesa portion in the separation region 204. In addition, in the X-axis direction, the distance between two adjacent second lower end regions 205 may be greater or smaller than the width of the mesa portion in the separation region 204. In addition, in the X-axis direction, the distance between the well region 11 and the second lower end region 205 may be greater or smaller than the width of the mesa portion in the separation region 204.

[0119] The potential of the second lower end region 205 is different from the potential of the emitter electrode 52. The second lower end region 205 is disposed apart in the Z-axis direction from the base region 14 connected to the emitter electrode 52. The second lower end region 205 is also disposed apart from the well region 11 connected to the emitter electrode 52 in a top view. The second lower end region 205 may be an electrically floating region that is not connected to any electrode.

[0120] As described above, by providing the first lower end region 202, it is possible to suppress the potential rise near the lower end of the trench portion when the semiconductor device 100 is turned on. Therefore, it is possible to reduce the gradient (dv / dt) of the waveform of the emitter-collector voltage when the semiconductor device 100 is turned on, and to reduce noise in the voltage or current waveform during switching. Furthermore, by providing the separation region 204, it is possible to separate the first lower end region 202 from the well region 11, and it is possible to operate the transistor portion 70 and the diode portion 80. On the other hand, an imbalance occurs in the electric field near the lower end of the trench portion between the region where the first lower end region 202 exists and the region where it does not exist. In particular, the electric field is concentrated near the lower end of the gate trench portion 40 where the first lower end region 202 is not provided, making it easier for avalanche to occur, and the clamp withstand capability and latch-up withstand capability are reduced.

[0121] In contrast, in the semiconductor device 100, the second lower end region 205 is provided at the lower end of at least one gate trench portion 40 in the isolation region 204. This makes it possible to alleviate electric field concentration near the lower end of the gate trench portion 40 in the isolation region 204. As a result, the withstand voltage or withstand capacity of the semiconductor device 100 can be improved.

[0122] The second lower end region 205 may be provided for each of two or more gate trench portions 40 in the isolation region 204. The second lower end regions 205 are separated from each other. In the example of FIG. 5, the second lower end region 205 is provided at the lower end of all the gate trench portions 40 in the isolation region 204. In this example, each second lower end region 205 is in contact with the lower end of one gate trench portion 40 and is not in contact with the lower ends of the other gate trench portions 40 other than the one gate trench portion 40. In the example of FIG. 5, each second lower end region 205 is in contact with the lower end of one gate trench portion 40 and is not in contact with the lower ends of the other trench portions. The width of the second lower end region 205 in the X-axis direction may be smaller than, the same as, or larger than the width of the gate trench portion 40 in the X-axis direction. It is preferable that the second lower end region 205 covers the lowest portion of the gate trench portion 40 (the bottom surface of the gate trench portion 40).

[0123] The second lower end region 205 may have a portion provided at the same depth position as the first lower end region 202. In other words, the range in the Z-axis direction in which the second lower end region 205 is provided and the range in the Z-axis direction in which the first lower end region 202 is provided may at least partially overlap. At least one of the drift region 18 and the accumulation region 16 may be disposed between the second lower end region 205 and the base region 14.

[0124] FIG. 6 is a diagram showing another arrangement example of the gate trench portion 40 and the dummy trench portion 30. In the active portion 160 of this example, two dummy trench portions 30 are provided between two gate trench portions 40. Moreover, the gate trench portions 40 are not continuously arranged in the X direction. That is, one gate trench portion 40 and two dummy trench portions 30 are alternately arranged. The other structures are similar to the examples described in FIG. 1 to FIG. 5. In this example, the second lower end region 205 is provided in one or more gate trench portions 40 of the isolation region 204.

[0125] 5 and 6, the number of trench portions that one second lower end region 205 contacts is smaller than the number of trench portions that one first lower end region 202 contacts. For example, in the example of Fig. 6, one second lower end region 205 contacts one trench portion, whereas one first lower end region 202 contacts multiple trench portions. One first lower end region 202 may contact the lower ends of multiple gate trench portions 40 and multiple dummy trench portions 30.

[0126] FIG. 7 is a diagram showing an example of distribution of the electric field in the X-axis direction at the depth position of the lower end of the trench portion. FIG. 7 shows the electric field distribution when the transistor portion 70 is turned off for a current of 5 times or more (6 times in this example) the rated current. In FIG. 7, the position in the X-axis direction of the lower end of the gate trench portion 40 is indicated by symbol G, and the position in the X-axis direction of the lower end of the dummy trench portion 30 is indicated by symbol E. Also, the positions in the X-axis direction where the first lower end region 202 and the second lower end region 205 are provided are shown typically. Note that the solid line in FIG. 7 shows the electric field distribution when the first lower end region 202 and the second lower end region 205 are provided as shown in FIG. 6, and the dashed line shows the electric field distribution when only the first lower end region 202 is provided without providing the second lower end region 205.

[0127] 7, the electric field is large at the lower end of the trench portion not covered by the first lower end region 202. In particular, the electric field concentration at the lower end of the gate trench portion 40(G) is remarkable. Therefore, the electric field is concentrated near the lower end of the gate trench portion 40, making avalanche more likely to occur, and the clamp resistance and latch-up resistance are reduced.

[0128] In contrast, by providing the second lower end region 205, the electric field in the vicinity of the lower end of the gate trench portion 40 can be reduced as shown by the solid line in Fig. 7. This allows the withstand voltage and withstand capability of the semiconductor device 100 to be improved.

[0129] FIG. 8 is a diagram showing another example of the second lower end region 205. The second lower end region 205 of this example is in contact with the lower end of one gate trench portion 40, and is also in contact with the lower end of the dummy trench portion 30 arranged next to the gate trench portion 40 in the X-axis direction. In the example of FIG. 8, the second lower end region 205 is in contact with the lower end of one gate trench portion 40 and the lower ends of the two dummy trench portions 30 that sandwich the gate trench portion 40 in the X-axis direction. The second lower end region 205 is not provided below the mesa portion 60 sandwiched between the adjacent dummy trench portions 30. That is, the second lower end regions 205 provided in the adjacent dummy trench portions 30 are separated. In a top view, an N-type region is provided between the two separated second lower end regions 205. The N-type region is, for example, the drift region 18. This configuration can also reduce electric field concentration near the bottom ends of the dummy trenches 30. This allows the semiconductor device 100 to have a further improved breakdown voltage and withstand voltage.

[0130] 9A is an enlarged view of the vicinity of the first lower end region 202 and the second lower end region 205. In this example, the second lower end region 205 is in contact with the lower ends of multiple trench portions. The doping concentration of the second lower end region 205 at the lower end of the gate trench portion 40 is defined as Dg. The doping concentration Dg is the integral I of the doping concentration of the second lower end region 205 on a mm line that passes through the lowest point of the gate trench portion 40 and is parallel to the Z axis. D It may be an average value obtained by dividing g by the width T2 in the depth direction from the top to the bottom of the second bottom end region 205, or it may be a maximum value. Similarly, the doping concentration of the second bottom end region 205 at the bottom end of the dummy trench portion 30 is defined as Dd. The doping concentration Dd is the integral I of the doping concentration of the second bottom end region 205 on a line kk that passes through the lowest point of the dummy trench portion 30 and is parallel to the Z axis. D It may be an average value obtained by dividing d by the width T2 in the depth direction from the upper end to the lower end of the second lower end region 205, or it may be a maximum value.

[0131] The doping concentration Dg may be greater than the doping concentration Dd. D g is the integral ID 7, the electric field is more likely to concentrate in the gate trench portion 40 than in the dummy trench portion 30, so the doping concentration Dg or the integral value I D By making g relatively large, the electric field concentration in the gate trench portion 40 can be alleviated, and the withstand voltage and withstand capability of the semiconductor device 100 can be improved.

[0132] The doping concentration of the first lower end region 202 at the lower end of the gate trench portion 40 is defined as D1. The doping concentration D1 is the integral I of the doping concentration of the first lower end region 202 on a line ii that passes through the lowest point of the gate trench portion 40 and is parallel to the Z axis. D It may be an average value or a maximum value obtained by dividing 1 by the width T1 in the depth direction from the upper end to the lower end of the first lower end region 202. The first lower end region 202 may have the same doping concentration at the lower end of the gate trench portion 40 and the lower end of the dummy trench portion 30.

[0133] The doping concentration Dg may be greater than the doping concentration D1. D g is the integral I D 1. This can alleviate the electric field concentration in the gate trench portion 40 in the isolation region 204. The doping concentration Dg can be twice or more, five times or more, or ten times or more, as high as the doping concentration D1. The doping concentration Dd can be lower than the doping concentration D1. The integral value I D g is the integral I D It may be 2 times or more, 5 times or more, or 10 times or more of 1. In addition, the integral value I D d is the integral value I D 1. With this configuration, the electric field at the bottom end of each trench portion can be easily made uniform. The doping concentration Dd may be 0.5 times or less, 0.2 times or less, or 0.1 times or less of the doping concentration D1. The integral value I D d is the integral value I D It may be 0.5 times or less of 1, may be 0.2 times or less, or may be 0.1 times or less.

[0134] Also, the number of trench parts that one first lower end region 202 contacts is q. In the example of FIG. 8, q is an integer equal to or greater than 4. The sum of the doping concentrations at the lower ends of the trench parts of one first lower end region 202 is Dsum1. Similarly, the number of trench parts that one second lower end region 205 contacts is r. In the example of FIG. 8, r is 3. The sum of the doping concentrations at the lower ends of the trench parts of one second lower end region 205 is Dsum2. Dsum2 / r may be smaller than Dsum1 / q. In other words, the average value of the doping concentrations at the lower ends of the trench parts that contact one second lower end region 205 may be smaller than the average value of the doping concentrations at the lower ends of the trench parts that contact one first lower end region 202. In addition, in each trench portion of one first lower end region 202, the sum of the integral values ​​of the doping concentration of the first lower end region 202 on a mm line that passes through the lowest point of each trench portion and is parallel to the Z axis is defined as I D sum1. Similarly, the number of trench portions that contact one second lower end region 205 is r. In the example of FIG. 8, r is 3. In each trench portion of one second lower end region 205, the sum of the integral values ​​of the doping concentrations of the first lower end region 202 on a mm line that passes through the lowest point of each trench portion and is parallel to the Z axis is defined as I D Let's call it sum2. D sum2 / r is I D sum1 / q. In other words, the integral value of the doping concentration of each trench portion in contact with one second lower end region 205 may be smaller than the integral value of the doping concentration of each trench portion in contact with one first lower end region 202.

[0135] FIG. 9B is a diagram showing an example of the forming process of FIG. 9A. As an example, the first lower end region 202 is formed by injecting a P-type dopant at a constant first dose into the lower ends of the gate trench portion 40 and the dummy trench portion 30. By subjecting the semiconductor substrate 10 to heat treatment after the P-type dopant is injected, the P-type dopant at the lower ends of each trench portion is diffused in the X-axis direction to form a continuous first lower end region 202. The P-type dopant is introduced below the trench portion by ion implantation or the like. The P-type dopant spreads in the depth direction (Z-axis direction) and the lateral direction (X-axis direction) by heat treatment. The P-type dopant that spreads laterally from below the adjacent trench portions overlaps at the center of the mesa portion. As a result, as shown in FIG. 9B, the doping concentration of the first lower end region 202 is slightly lower at the center of the mesa portion. Furthermore, the lateral end of the first lower end region 202 may extend to the dummy trench portion 30 located at the −X-axis direction end on the isolation region 204 side, or to the mesa portion.

[0136] On the other hand, in the isolation region 204, a P-type dopant may be implanted at a constant first dose into the lower end of the gate trench portion 40. By subjecting the semiconductor substrate 10 to a heat treatment after the P-type dopant is implanted, the P-type dopant implanted into the lower end of the gate trench portion 40 diffuses in the X-axis direction and reaches the lower end of the dummy trench portion 30. In this case, the average value of the doping concentration at the lower end of each trench portion of the second lower end region 205 becomes smaller than the average value of the doping concentration at the lower end of each trench portion of the first lower end region 202. With this configuration, it is possible to prevent the second lower end region 205 from spreading too much in the X-axis direction and connecting with the first lower end region 202 or the well region 11.

[0137] Fig. 10 is a diagram showing another configuration example of the separation region 204. The separation region 204 of this example differs from the separation region 204 described with reference to Figs. 1 to 9B in that it includes a third lower end region 207. The other structures are similar to any of the separation regions 204 described with reference to Figs. 1 to 9B.

[0138] The third lower end region 207 is provided for one or more dummy trench portions 30 in the isolation region 204. The third lower end region 207 is provided in contact with the lower end of the dummy trench portion 30, and is not in contact with the lower end of the trench portion adjacent to the dummy trench portion 30. The third lower end region 207 is provided separate from the first lower end region 202, the second lower end region 205, and the well region 11. An N-type region such as the drift region 18 is provided between the third lower end region 207 and the first lower end region 202, the second lower end region 205, and the well region 11.

[0139] The potential of the third lower end region 207 is different from the potential of the emitter electrode 52. The third lower end region 207 is disposed apart in the Z-axis direction from the base region 14 connected to the emitter electrode 52. The third lower end region 207 is also disposed apart from the well region 11 connected to the emitter electrode 52 in a top view. The third lower end region 207 may be an electrically floating region that is not connected to any electrode.

[0140] The dummy trench portion 30 to which the third lower end region 207 contacts is disposed next to the gate trench portion 40 to which the second lower end region 205 contacts. In this example, the second lower end region 205 is provided in all the gate trench portions 40 in the isolation region 204, and the third lower end region 207 is provided in all the dummy trench portions 30 in the isolation region 204. This example also makes it possible to alleviate electric field concentration at the lower ends of the trench portions in the isolation region 204.

[0141] 11 is a diagram showing an example of the distribution of doping concentrations in the Z-axis direction of the first lower end region 202, the second lower end region 205, and the third lower end region 207. The doping concentration distribution of the first lower end region 202 is a distribution on line aa (see FIG. 10) that passes through the lowest point of the gate trench portion 40 and is parallel to the Z-axis. The doping concentration distribution of the second lower end region 205 is a distribution on line bb (see FIG. 10) that passes through the lowest point of the gate trench portion 40 and is parallel to the Z-axis. The doping concentration distribution of the third lower end region 207 is a distribution on line cc (see FIG. 10) that passes through the lowest point of the dummy trench portion 30 and is parallel to the Z-axis.

[0142] The peak value of the doping concentration of the first lower end region 202 is Da, the peak value of the doping concentration of the second lower end region 205 is Db, and the peak value of the doping concentration of the third lower end region 207 is Dc. The peak value Db may be greater than the peak value Da. The peak value Db may be twice or more, five times or more, or ten times or more, of the peak value Da. The peak value Da may be greater than the peak value Dc. The doping concentration Da may be twice or more, five times or more, or ten times or more, of the doping concentration Dc. The pn junction with the drift region 18 may be located in the second lower end region 205 closest to the lower surface 23 (+Z axis direction side), and the third lower end region 207 closest to the upper surface 21 (-Z axis direction side).

[0143] In addition, the integral value obtained by integrating the doping concentration of the first lower end region 202 from the lower end of the gate trench portion 40 to the upper end of the drift region 18 is Ia, the integral value obtained by integrating the doping concentration of the second lower end region 205 from the lower end of the gate trench portion 40 to the upper end of the drift region 18 is Ib, and the integral value obtained by integrating the doping concentration of the third lower end region 207 from the lower end of the dummy trench portion 30 to the upper end of the drift region 18 is Ic. The integral value Ib may be larger than the integral value Ia. The integral value Ib may be twice or more, five times or more, or ten times or more, of the integral value Ia. The integral value Ia may be larger than the integral value Ic. The integral value Ia may be twice or more, five times or more, or ten times or more, of the integral value Ic.

[0144] The doping concentration distribution at the ii line in Fig. 9A may be the same as the doping concentration distribution at the aa line in this example. The doping concentration distribution at the mm line in Fig. 9A may be the same as the doping concentration distribution at the bb line in this example. The doping concentration distribution at the kk line in Fig. 9A may be the same as the doping concentration distribution at the cc line in this example.

[0145] Fig. 12 is a diagram showing another example of the separation region 204. The separation region 204 of this example differs from the examples described in Fig. 1 to Fig. 11 in the arrangement of the second lower end region 205. The other structures are similar to any of the examples described in Fig. 1 to Fig. 11.

[0146] In the isolation region 204 of this example, the second lower end region 205 is not provided at the lower end of at least one gate trench portion 40. That is, at least the lower end of the gate trench portion 40 is in contact with an N-type region such as the drift region 18. In the isolation region 204, an emitter region 12 may be provided in a mesa portion in contact with a gate trench portion 40 in which the second lower end region 205 is not provided. This makes it easier to supply electrons to the drift region 18 when the gate trench portion 40 in which the second lower end region 205 is not provided is turned on. This makes it possible to increase the carrier concentration in the drift region 18 and reduce the on-resistance.

[0147] Of the gate trench portions 40 in the isolation region 204, the lower end of the gate trench portion 40 closest to the first lower end region 202 may be in contact with the drift region 18. This allows electrons to be supplied near the transistor portion 70.

[0148] 13 is a diagram showing another example of the isolation region 204. In the semiconductor substrate 10 of this example, two gate trench portions 40 and two dummy trench portions 30 are alternately arranged. That is, the semiconductor substrate 10 has two gate trench portions 40 arranged adjacent to each other in the X-axis direction without a dummy trench portion 30 therebetween, and two dummy trench portions 30 arranged adjacent to each other without a gate trench portion 40 therebetween. The structure other than the arrangement of the trench portions is the same as any of the examples described in FIG. 1 to FIG. 12.

[0149] In the present example, the isolation region 204 does not have a second lower end region 205 at the lower end of at least one gate trench portion 40. In this example, of the two gate trench portions 40 arranged in succession, one gate trench portion 40 has a second lower end region 205, and the other gate trench portion 40 does not have a second lower end region 205. With this configuration, it is possible to maintain the electron supply function while alleviating the electric field concentration in a pair of gate trench portions 40. Of the pair of gate trench portions 40, the second lower end region 205 is provided in the gate trench portion 40 farther from the transistor portion 70, and the second lower end region 205 may not be provided in the gate trench portion 40 closer to the transistor portion 70. This allows electrons to be supplied relatively close to the transistor portion 70 while alleviating the electric field concentration.

[0150] 14 is a diagram showing an example of the gg cross section in FIG. 4. The gg cross section is a YZ plane passing through the first lower end region 202 and the well region 11. The gg cross section passes through the mesa portion of the transistor portion 70. However, in FIG. 14, the position of the gate trench portion 40 projected onto the gg cross section is shown by a dashed line. Note that FIG. 14 shows the structure of the semiconductor substrate 10, and the configuration of electrodes, insulating films, etc. arranged above and below the semiconductor substrate 10 is omitted.

[0151] In this cross section, too, an isolation region 204 is provided between the transistor portion 70 and the well region 11. However, the isolation region 204 in this cross section is not provided with a second lower end region 205 and a third lower end region 207. A drift region 18 is provided between the first lower end region 202 and the well region 11.

[0152] The emitter regions 12 and the contact regions 15 are alternately arranged along the Y-axis direction on the upper surface 21 of the transistor section 70. The contact regions 15 are provided on the upper surface 21 of the isolation region 204.

[0153] In this example, the accumulation region 16 is provided extending toward the well region 11 side beyond the end of the transistor portion 70. In another example, the accumulation region 16 may terminate at the end of the transistor portion 70, or may terminate inside the transistor portion 70.

[0154] In this example, the first lower end region 202 extends further toward the well region 11 than the end of the transistor portion 70. In another example, the first lower end region 202 may terminate at the end of the transistor portion 70, or may terminate inside the transistor portion 70. The accumulation region 16 may extend further toward the well region 11 than the first lower end region 202.

[0155] The separation region 204 may overlap with the accumulation region 16 in a top view. That is, an end of the accumulation region 16 may be inside the separation region 204 in a top view. In another example, the separation region 204 may not overlap with the accumulation region 16 in a top view. That is, an end of the accumulation region 16 may be inside (on the -Y axis direction side) the separation region 204 in a top view. The separation region 204 may be provided so as not to overlap with the transistor portion 70 in the cross section. In another example, the separation region 204 may overlap with the transistor portion 70 in the cross section.

[0156] FIG. 15 is a diagram showing an example of the hh cross section in FIG. 5. The hh cross section is a YZ plane passing through the second lower end region 205 and the well region 11. The position of the hh cross section in the Y-axis direction is the same as the gg cross section shown in FIG. 14. The hh cross section passes through the mesa portion of the isolation region 204. However, in FIG. 15, the position of the gate trench portion 40 projected onto the hh cross section is shown by a dashed line. Note that FIG. 15 shows the structure of the semiconductor substrate 10, and the configurations of electrodes, insulating films, etc. arranged above and below the semiconductor substrate 10 are omitted.

[0157] In the semiconductor substrate 10 in this cross section, a second lower end region 205 is provided instead of the first lower end region 202 in the cross section shown in Fig. 14. In addition, a contact region 15 is continuously provided on the upper surface 21 of the semiconductor substrate 10. The other structures are similar to the example described in Fig. 14. In the Y-axis direction, the distance between the second lower end region 205 and the well region 11 may be the same as the distance between the first lower end region 202 and the well region 11, or may be larger or smaller.

[0158] Fig. 16 is a diagram showing another example of the hh cross section. In the hh cross section of this example, the structure of the upper surface 21 of the semiconductor substrate 10 is similar to that of the gg cross section shown in Fig. 14. That is, the emitter regions 12 and the contact regions 15 are alternately arranged along the Y-axis direction.

[0159] In this example, a plurality of second lower end regions 205 are arranged discretely apart from each other along the longitudinal direction (Y-axis direction) of the gate trench portion 40. The structure on the upper surface 21 of the semiconductor substrate 10 and the arrangement of the second lower end regions 205 are the same as the example of FIG. 15. By arranging the second lower end regions 205 along the Y-axis direction, electric field concentration can be alleviated, while the electron supply function can be maintained by arranging the second lower end regions 205 discretely. Note that it is preferable that the first lower end regions 202 are arranged continuously in the Y-axis direction as shown in FIG. 14. This makes it possible to reduce noise in the voltage or current waveform during switching over a wide range of the transistor portion 70 and the diode portion 80.

[0160] Each second lower end region 205 may be arranged so as to overlap with the emitter region 12 (or the source region 212) in a top view. The second lower end region 205 may be provided for each emitter region 12 (or source region 212). Each second lower end region 205 may be arranged so as to cover the entire Y-axis direction of the corresponding emitter region 12 (or source region 212). Since an electron current flows toward the emitter region 12, a relatively large current flows below the emitter region 12. By providing the second lower end region 205 below the emitter region 12, the electric field in the region where a large current flows can be suppressed, and the withstand voltage of the region can be improved.

[0161] 15 and 16, the structure in the Y-axis direction of the second lower end region 205 in the vicinity of the gate trench portion 40 has been described, but the second lower end region 205 in other regions also has a similar structure in the Y-axis direction. In addition, the third lower end region 207 may also have a structure in the Y-axis direction similar to the second lower end region 205 described in FIG. 15 and FIG.

[0162] Fig. 17 is a diagram showing some steps of a method for manufacturing the semiconductor device 100. In the method for manufacturing the semiconductor device 100, the components described in Fig. 1 to Fig. 16 are formed. The steps shown in Fig. 17 include a doping region forming step S1700, a trench forming step S1702, a bottom end region forming step S1704, and a trench structure forming step S1706.

[0163] In the doping region formation step S1700, a doping region is formed on the upper surface 21 side of the semiconductor substrate 10. The doping region includes, for example, at least one of the well region 11, the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16. The drift region 18 may be a region that remains without these doping regions being formed.

[0164] In the trench formation step S1702, trenches are formed in the upper surface 21 of the semiconductor substrate 10. The trenches are grooves for forming each trench portion. Each trench is formed to a depth that reaches from the upper surface 21 to the drift region 18. In the trench formation step S1702, at least the conductive portion in the trench is not formed. An insulating film in the trench may or may not be formed.

[0165] In the lower end region forming step S1704, the first lower end region 202 and the second lower end region 205 are formed. In the lower end region forming step S1704, the third lower end region 207 may also be formed. In the lower end region forming step S1704, P-type dopant ions may be implanted into the semiconductor substrate 10 through the trench. In the lower end region forming step S1704, P-type dopant ions may be implanted from the upper surface 21 of the semiconductor substrate 10 with the portions other than the trench masked. This makes it possible to easily implant P-type dopant ions into the region adjacent to the lower end of the trench. In the doping region forming step S1700 and the lower end region forming step S1704, the semiconductor substrate 10 is heat-treated after the dopant is implanted.

[0166] In the trench structure forming step S1706, a conductive portion and an insulating film are formed inside each trench. In the trench structure forming step S1706, the insulating film may be formed by thermally oxidizing the inner wall of the trench. In the trench structure forming step S1706, the conductive portion may be formed by filling the trench with a conductive material such as polysilicon in the inside of the trench in which the insulating film has been formed.

[0167] 18 is a diagram illustrating an example of the bottom region forming step S1704. The bottom region forming step S1704 of this example has a first injection step S1801 and a second injection step S1802. Either the first injection step S1801 or the second injection step S1802 may be performed first, or they may be performed simultaneously.

[0168] In the first implantation step S1801, a predetermined concentration ( / cm 2In the first implantation step S1801 of this example, the P-type dopant ions are implanted from the bottom of each of the trenches 45 in the gate trench portion 40 and the dummy trench portion 30.

[0169] In the second implantation step S1802, P-type dopant ions are implanted into the region in which the isolation region 204 is to be formed. In the second implantation step S1802 of this example, the P-type dopant ions are implanted from the bottom of each trench 45 of the gate trench portion 40. The dose amount per unit area (ions / cm 2 ) in the second implantation step S1802 is 2 ) is the dose (ions / cm 2 ) in the first implantation step S1801. 2 ) may be the same as or different from the dose amount. When the first implantation step S1801 and the second implantation step S1802 are performed simultaneously, the dose amounts are the same. In the first implantation step S1801 and the second implantation step S1802, the regions other than the trench 45 may be masked by a mask 300. The dopant implanted through the trench 45 is diffused by heat treatment. This makes it possible to form a first lower end region 202 that is continuous in the XY plane. Also, depending on the conditions of the heat treatment, it is possible to control whether or not the second lower end region 205 is formed up to the lower end of the adjacent trench 45.

[0170] The manufacturing method may further include a third implantation step to form a third lower end region 207. When the doping concentration of the third lower end region 207 is made different from the doping concentration of the second lower end region 205, the third implantation step is performed in a process different from the second implantation step S1802.

[0171] 19 is a diagram showing an example of the jj cross section in FIG. 4. The jj cross section is an XZ plane passing through the active section 160. The semiconductor device 100 of this example has a separation region 204 inside the active section 160. The structure of the separation region 204 is similar to that of the separation region 204 in any of the aspects described in this specification. The separation region 204 is provided with one or more second lower end regions 205.

[0172] The separation region 204 in this example is sandwiched between two first lower end regions 202 in top view. In the example of FIG. 19, the separation region 204 is sandwiched between two first lower end regions 202 in the X-axis direction. A plurality of second lower end regions 205 may be provided in the separation region 204. As shown in FIG. 19, the separation region 204 may be provided between two transistor units 70 in the X-axis direction. The transistor unit 70 may be provided between the two separation regions 204 in the X-axis direction.

[0173] Fig. 20 is a diagram showing another example of the ff cross section, which also shows the structure above the upper surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is a MOSFET.

[0174] The semiconductor device 100 has an N+ type drain region 222 provided in contact with the lower surface 23 of the semiconductor substrate 10, instead of the collector region 22 in each example described in this specification. Also, the emitter region 12 and the emitter electrode 52 in each example described in this specification function as the source region 212 and the source electrode 252. The source region 212 and the source electrode 252 have the same structure as the emitter region 12 and the emitter electrode 52. Also, the collector electrode 24 (see FIG. 3, etc.) in each example described in this specification functions as a drain electrode. The semiconductor substrate 10 may be a SiC (silicon carbide) substrate.

[0175] The semiconductor substrate 10 may have a step (concave portion) at an end portion in a top view. The well region 11 may be formed in the step. The well region 11 may function as a JTE (Junction Termination Extension).

[0176] 21 is a diagram showing another structural example of the isolation region 204. The isolation region 204 of this example may be applied to any of the semiconductor devices 100 of the aspects described in this specification. In this example, the gate conductive portion 44 of at least one of the gate trench portions 40 in contact with the second lower end region 205 is shorter in the depth direction than the gate conductive portion 44 of the gate trench portion 40 in contact with the first lower end region 202. The gate conductive portions 44 of all of the gate trench portions 40 in contact with the second lower end region 205 may be shorter in the depth direction than the gate conductive portion 44 of the gate trench portion 40 in contact with the first lower end region 202.

[0177] The length of the gate conductive portion 44 of the gate trench portion 40 in contact with the second lower end region 205 may be 90% or less, 80% or less, or 70% or less of the length of the gate conductive portion 44 of the gate trench portion 40 in contact with the first lower end region 202. However, the gate conductive portion 44 of the gate trench portion 40 in contact with the second lower end region 205 may be provided below the base region 14. In this example, the gate insulating film 42 at the lower end of the gate trench portion 40 in contact with the second lower end region 205 is thicker in the depth direction than the gate insulating film 42 at the lower end of the gate trench portion 40 in contact with the first lower end region 202.

[0178] According to this example, the gate insulating film 42 at the lower end of the gate trench portion 40 in contact with the second lower end region 205 can be made thicker, thereby further increasing the breakdown voltage of the gate trench portion 40. The length in the depth direction of the gate trench portion 40 in contact with the first lower end region 202 and the gate trench portion 40 in contact with the second lower end region 205 may be the same or different.

[0179] In at least one of the gate trench portions 40 in contact with the second lower end region 205, the center of the lower surface of the gate conductive portion 44 may have an upwardly convex shape. That is, the length of the gate conductive portion 44 at the position where the gate conductive portion 44 is in contact with the gate insulating film 42 is greater than the length of the position farthest from the gate insulating film 42 in the X-axis direction (i.e., the center position of the gate conductive portion 44 in the X-axis direction). With this structure, the length of the channel formed in the base region 14 in the depth direction can be secured, and the electric field intensity at the bottom of the gate trench portion can be alleviated, and breakdown of the gate insulating film, hot carrier injection, etc. can be suppressed, thereby improving the reliability of the gate insulating film. The length of the gate conductive portion 44 at the position where the gate conductive portion 44 is in contact with the gate insulating film 42 may be 1.05 times or more, 1.1 times or more, or 1.2 times or more of the length of the gate conductive portion 44 at the position farthest from the gate insulating film 42.

[0180] In the gate trench portion 40 in contact with the first lower end region 202, the center of the lower surface of the gate conductive portion 44 may have a downwardly convex shape. In another example, the gate trench portion 40 in contact with the first lower end region 202 may also have an upwardly convex shape in the center of the lower surface of the gate conductive portion 44.

[0181] FIG. 22 is a diagram showing another structural example of the isolation region 204. The isolation region 204 of this example may be applied to any of the semiconductor devices 100 of the aspects described in this specification. In this example, at least one of the gate trench portions 40 in contact with the second lower end region 205 is shorter in the depth direction than the gate trench portion 40 in contact with the first lower end region 202. All of the gate trench portions 40 in contact with the second lower end region 205 may be shorter in the depth direction than the gate trench portion 40 in contact with the first lower end region 202. With this structure, the electric field concentration at the lower end of the gate trench portion 40 in the isolation region 204 can be further alleviated. In this example, the drift region 18 is interposed between the second lower end region 205 and the base region 14 in the depth direction. In other words, the drift region 18 is in contact with the gate trench portion 40 on the upper side of the second lower end region 205. However, the second lower end region 205 and the base region 14 may be connected directly or indirectly via another P-type semiconductor region.

[0182] The length of the gate trench portion 40 in contact with the second lower end region 205 may be 0.9 times or less, 0.8 times or less, or 0.7 times or less, the length of the gate trench portion 40 in contact with the first lower end region 202. However, the gate trench portion 40 in contact with the second lower end region 205 is formed below the base region 14. The gate trench portion 40 in contact with the second lower end region 205 may be shorter in the depth direction than the dummy trench portion 30 adjacent thereto in the X-axis direction. The length of the dummy trench portion 30 may be the same as or different from the length of the gate trench portion 40 in contact with the first lower end region 202. The length of the gate trench portion 40 in contact with the second lower end region 205 may be 0.9 times or less, 0.8 times or less, or 0.7 times or less, the length of the adjacent dummy trench portion 30.

[0183] FIG. 23 is a diagram showing another example of the structure of the isolation region 204. The isolation region 204 of this example may be applied to any of the semiconductor devices 100 of the aspects described in this specification. In this example, at least one of the dummy trench portions 30 of the isolation region 204 is longer in the depth direction than the dummy trench portion 30 in contact with the first lower end region 202. All of the dummy trench portions 30 of the isolation region 204 may be longer in the depth direction than the dummy trench portion 30 in contact with the first lower end region 202. With such a structure, the electric field concentration at the lower end of the gate trench portion 40 in the isolation region 204 can be further alleviated. The length of the dummy trench portion 30 of the isolation region 204 may be 1.1 times or more, 1.2 times or more, or 1.3 times or more, the length of the dummy trench portion 30 in contact with the first lower end region 202. The dummy trench portion 30 of the isolation region 204 may be formed shallower than the well region 11.

[0184] The gate trench portion 40 in contact with the second lower end region 205 may be shorter in the depth direction than the dummy trench portion 30 adjacent to it in the X-axis direction. The length of the gate trench portion 40 in contact with the second lower end region 205 may be the same as or different from the length of the gate trench portion 40 in contact with the first lower end region 202. The length of the gate trench portion 40 in contact with the second lower end region 205 may be 0.9 times or less, 0.8 times or less, or 0.7 times or less of the length of the adjacent dummy trench portion 30.

[0185] FIG. 24 is a diagram showing another structural example of the isolation region 204. The isolation region 204 of this example may be applied to any of the aspects of the semiconductor device 100 described in this specification. In the isolation region 204 of this example, two or more dummy trench portions 30 that are not in contact with the first lower end region 202 and the second lower end region 205 are continuously arranged next to the gate trench portion 40 that is in contact with the first lower end region 202. The isolation region 204 of this example further includes a fourth lower end region 214 of the second conductivity type that is provided in contact with the lower ends of the two or more dummy trench portions 30. The depth position and doping concentration of the fourth lower end region 214 may be the same as those of the first lower end region 202. The fourth lower end region 214 may be arranged between the first lower end region 202 and the second lower end region 205 in the X-axis direction. The fourth bottom end region 214 is separate from both the first bottom end region 202 and the second bottom end region 205 .

[0186] In this example, the drift region 18 is interposed between the second lower end region 205 and the base region 14 in the depth direction. In the separation region 204, an emitter region 12 (or a source region 212) may be provided in a mesa portion in contact with the gate trench portion 40. According to this example, at least a part of the separation region 204 can also be operated as a transistor portion. A second lower end region 205 is provided at the lower end of the gate trench portion 40. The second lower end region 205 may be sandwiched between two fourth lower end regions 214 in the X-axis direction. Note that a part of the second lower end region 205 and the base region 14 may be directly connected or indirectly connected via another P-type semiconductor region.

[0187] The gate trench portion 40 and the second lower end region 205 in the isolation region 204 are similar to any of the examples described in this specification. In the example of FIG. 24, the gate trench portion 40 and the second lower end region 205 described in FIG. 22 are provided. This makes it possible to alleviate electric field concentration in the gate trench portion 40. In addition, since the second lower end region 205 and the fourth lower end region 214 are located at different depth positions, the second lower end region 205 and the fourth lower end region 214 can be easily separated from each other, and a current path can be easily secured.

[0188] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0189] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0190] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 45 trench, 52 emitter a gate electrode, 54 contact hole, 60, 61 mesa portion, 70 transistor portion, 80 diode portion, 81 extension region, 82 cathode region, 90 edge termination structure portion, 100 semiconductor device, 130 peripheral gate wiring, 131 active side gate wiring, 160 active portion, 162 edge, 164 gate pad, 202 first bottom end region, 204 isolation region, 205 second bottom end region, 207 third bottom end region, 212 source region, 214 fourth bottom end region, 222 drain region, 252 source electrode, 300 mask

Claims

1. A semiconductor substrate having an upper surface and a lower surface, A drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a high-concentration region which is an emitter region or a source region of a first conductivity type having a doping concentration higher than that of the drift region and is provided between the base region and the upper surface of the semiconductor substrate; A plurality of trench portions; A semiconductor device provided with A transistor portion including a transistor element; an outer region provided outside the transistor portion; Equipped with In the outer region, the trench portion includes a first gate trench portion that does not contact the high concentration region, and a first dummy trench portion that is longer in a depth direction than the first gate trench portion. Semiconductor device.

2. The transistor portion includes, as the trench portion, a second gate trench portion in contact with the high concentration region, and a second dummy trench portion that is shorter in a depth direction than the first dummy trench portion. The semiconductor device according to claim 1 .

3. A well region of a second conductivity type arranged at a position different from that of the transistor portion when viewed from above, When viewed from above, the outer region is provided between the transistor portion and the well region.

3. The semiconductor device according to claim 1 or 2.

4. The transistor portion is provided with, as the trench portion, a second gate trench portion in contact with the high concentration region, and a second dummy trench portion having a length equal to that of the second gate trench portion in a depth direction. The semiconductor device according to claim 1 .

5. The transistor portion includes a second gate trench portion as the trench portion, the second gate trench portion being in contact with the high concentration region and having a length equal to that of the first gate trench portion in a depth direction. The semiconductor device according to claim 1 .

6. The depth of the first dummy trench portion is shallower than that of the well region. The semiconductor device according to claim 3 .

7. The deepest depth position of the first dummy trench portion is in contact with a first conductivity type region.

3. The semiconductor device according to claim 1 or 2.

8. The transistor portion includes, as the trench portion, a second dummy trench portion having a length equal to that of the first gate trench portion in a depth direction. The semiconductor device according to claim 1 .

9. The transistor portion includes, as the trench portion, a second gate trench portion that is in contact with the high concentration region and is shorter in a depth direction than the first dummy trench portion. The semiconductor device according to claim 1 .

10. When viewed from above, the transistor portion and the outer region are provided in contact with each other, and the outer region and the well region are provided in contact with each other. The semiconductor device according to claim 3 .

11. The outer region is provided with a plurality of the first gate trench portions.

3. The semiconductor device according to claim 1 or 2.

12. The plurality of first gate trench portions are provided adjacent to each other. The semiconductor device according to claim 11.

13. The outer region is provided with a plurality of the first dummy trench portions.

3. The semiconductor device according to claim 1 or 2.

14. The first dummy trench portions are provided on either side of the first gate trench portion. The semiconductor device according to claim 13.

15. The outer region is provided with a plurality of the first gate trench portions, The first dummy trench portions are provided with the first gate trench portions interposed therebetween. The semiconductor device according to claim 14.

16. The deepest depth position of the first gate trench portion is in contact with a region of a first conductivity type.

3. The semiconductor device according to claim 1 or 2.

17. The transistor portion is provided with a second gate trench portion in contact with the high concentration region and a second dummy trench portion as the trench portion, The distance between the second gate trench portion and the second dummy trench portion is the same as the distance between the first gate trench portion and the first dummy trench portion.

3. The semiconductor device according to claim 1 or 2.

18. The first dummy trench portion is provided between the first gate trench portion and the second gate trench portion. The semiconductor device according to claim 17.

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