Switch device
Patent Information
- Application Number
- JP2023129405
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-08-08
- Publication Date
- 2025-02-21
Smart Images
Figure 2025024985000001_ABST
Abstract
Description
[Technical field]
[0001] An embodiment of the present invention relates to a switch device. [Background technology]
[0002] MIMO (Multiple Input Multiple Output) is known as a technology used in wireless communication. A transceiver that supports MIMO includes multiple antennas and multiple switch circuits. The transceiver uses a phase switch device to generate multiple transmission signals having different phases from a common signal, and transmits the multiple transmission signals from multiple antennas. The transceiver includes the same number of phase switch devices as the number of antennas.
[0003] Improved MIMO performance can be achieved by increasing the number of antennas. The more antennas there are, the more phase switch devices are required. Therefore, in order to efficiently manufacture the transceiver, it is required that the components in each phase switch device be easily connected. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] Patent No. 5983773 Summary of the Invention [Problem to be solved by the invention]
[0005] The present invention aims to provide a switch device in which the internal components can be easily connected. [Means for solving the problem]
[0006] A switch device according to an embodiment includes a first semiconductor chip, a second semiconductor chip, a first delay circuit, a first conductor, and a second conductor, each of the first and second semiconductor chips including a first side, a second side and a third side opposing each other, a first terminal, a second terminal facing the second side, a third terminal facing the third side, a fourth terminal and a fifth terminal aligned along the first side, and a sixth terminal, the sixth terminal connecting the first terminal and the second terminal while the sixth terminal receives a first voltage, the fourth terminal receives a second voltage, and the fifth terminal receives a third voltage, and the first terminal connects the third terminal while the sixth terminal receives a fourth voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the second voltage. The first delay circuit supplies a signal obtained by delaying a signal at an input terminal connected to the second terminal of the first semiconductor chip to the third terminal of the second semiconductor chip. The first conductor is connected to the fourth terminal of the first semiconductor chip and the fifth terminal of the second semiconductor chip. The second conductor is connected to the fifth terminal of the first semiconductor chip and the fourth terminal of the second semiconductor chip. The first side of the first semiconductor device faces the first side of the second semiconductor device. The sixth terminal of the first semiconductor device is connected to a terminal receiving the first voltage. The sixth terminal of the second semiconductor device is connected to a terminal receiving the fourth voltage. [Brief description of the drawings]
[0007] [Figure 1] FIG. 1 shows functional blocks of a transmitting / receiving device including a switch device of the first embodiment and connections between the functional blocks. [Diagram 2] FIG. 2 shows functional blocks of the switch device of the first embodiment and connections between the functional blocks. [Diagram 3] FIG. 3 shows components of the switch circuit of the switch device of the first embodiment and connections of the components. [Figure 4] FIG. 4 shows the relationship between the input and output of a logic circuit included in the switch device of the first embodiment. [Diagram 5]FIG. 5 shows an example of the structure of the switch circuit of the switch device of the first embodiment. [Figure 6] FIG. 6 shows an example of a portion of the structure of the switch device of the first embodiment. [Figure 7] FIG. 7 shows an example of the structure of a switch circuit of the switch device according to the second embodiment. [Figure 8] FIG. 8 shows an example of a portion of the structure of the switch device according to the second embodiment. [Figure 9] FIG. 9 shows an example of the structure of a switch circuit of a switch device according to the third embodiment. [Figure 10] FIG. 10 shows an example of a portion of the structure of the switch device according to the third embodiment. [Figure 11] FIG. 11 shows an example of the structure of a switch circuit of a switch device according to the fourth embodiment. [Figure 12] FIG. 12 shows an example of a part of the structure of the switch device according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0008] Hereinafter, the embodiments will be described with reference to the drawings. In an embodiment or different embodiments, a plurality of components having substantially the same functions and configurations may be distinguished from each other by adding an additional number or letter to the end of the reference numeral. In the embodiment following a certain described embodiment, the differences from the described embodiment will be mainly described. All descriptions of one embodiment are applicable to the description of another embodiment, unless expressly or obviously excluded.
[0009] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via an element that is constantly or selectively conductive.
[0010] Hereinafter, an embodiment will be described using an XYZ Cartesian coordinate system. The positive direction of the vertical axis of the figure may be referred to as the upper side, and the negative direction as the lower side. The positive direction of the horizontal axis of the figure may be referred to as the right side, and the negative direction as the left side. That is, in a plan view showing an XY plane (XY plane view (hereinafter the same)), the upper side indicates the +Y direction, the lower side indicates the -Y direction, the right side indicates the +X direction, and the left side indicates the -X direction.
[0011] 1. First embodiment 1.1.Configuration (Structure) Fig. 1 shows functional blocks and connections of the functional blocks of a transceiver including a switch device of the first embodiment. As shown in Fig. 1, the transceiver 10 includes a data processing circuit 1, a transceiver 2, an amplifier circuit 3, multiple switch devices 4, and multiple antennas 5. Fig. 1 shows an example of four switch devices and four antennas, and the following description is based on this example.
[0012] The data processing circuit 1 is a circuit that generates data to be transmitted by the transmitting / receiving device 10. The data processing circuit 1 may be realized as a single semiconductor chip, or may be a circuit formed on a semiconductor substrate.
[0013] The transceiver 2 generates a signal to be transmitted by the transmitting / receiving device 10. The transceiver 2 receives data from the data processing circuit 1 and modulates the data to generate a transmission signal. The transceiver 2 may be realized as a single semiconductor chip, or may be a circuit formed on a semiconductor substrate.
[0014] The amplifier circuit 3 is a circuit that amplifies a signal received by the amplifier circuit 3. The amplifier circuit 3 receives a transmission signal from the transceiver 2 and amplifies the received transmission signal for transmission. The amplifier circuit 3 may be realized as a single semiconductor chip, or may be a circuit formed on a semiconductor substrate.
[0015] Each switch device 4 is a circuit that changes the phase of a signal received by the switch device 4. The switch device 4 receives a signal from the amplifier circuit 3, and changes the phase of the received signal by one magnitude that is dynamically selected from a plurality of phases. Each switch device 4 is realized as a device including a semiconductor chip, and is, for example, a semiconductor device (or a semiconductor module) that includes a semiconductor chip, a resin that seals the semiconductor chip, and a terminal for electrical connection to the outside.
[0016] Each antenna 5 wirelessly transmits the signal received by the antenna 5 to the outside of the transmitting / receiving device 10. Each antenna 5 is connected to one switch device 4.
[0017] Fig. 2 shows the functional blocks and connections of the functional blocks of the switch device of the first embodiment. As shown in Fig. 2, the switch device 4 includes two switch circuits 11 (11a and 11b), a plurality of delay circuits 12 (12a, 12b, 12c, and 12d), and a control circuit 13. Fig. 2 shows an example of four delay circuits 12, and the following description is based on this example.
[0018] The switch circuit 11 includes a terminal RFC and a plurality of terminals RF (RF1, RF2, RF3, and RF4). The number of the terminals RF matches the number of the delay circuits 12. Based on the control of the control circuit 13, the switch circuit 11 electrically connects the terminal RFC to one of the terminals RF1, RF2, RF3, and RF4 that is dynamically selected.
[0019] The switch circuits 11a and 11b are the same switch circuit. The switch circuit 11a is connected to the amplifier circuit 3 at a terminal RFC. The switch circuit 11a is connected to the input terminal of the delay circuit 12a at a terminal RF1. The switch circuit 11a is connected to the input terminal of the delay circuit 12b at a terminal RF2. The switch circuit 11a is connected to the input terminal of the delay circuit 12c at a terminal RF3. The switch circuit 11a is connected to the input terminal of the delay circuit 12d at a terminal RF4.
[0020] The switch circuit 11b is connected to one antenna 5 at a terminal RFC. The switch circuit 11b is connected to an output terminal of the delay circuit 12d at a terminal RF1. The switch circuit 11b is connected to an output terminal of the delay circuit 12c at a terminal RF2. The switch circuit 11b is connected to an output terminal of the delay circuit 12b at a terminal RF3. The switch circuit 11b is connected to an output terminal of the delay circuit 12a at a terminal RF4.
[0021] The delay circuit 12 is a circuit that delays a signal received at an input terminal by a predetermined phase and outputs the delayed signal from an output terminal. The delay circuits 12a, 12b, 12c, and 12d delay the received signal by mutually different phases.
[0022] The control circuit 13 is a circuit that controls the operation of the switch device 4. The control circuit 13 generates a control signal for controlling the switch circuit 11 based on the operation to be performed by the switch device 4, i.e., the amount of signal delay based on the operation, and outputs the control signal.
[0023] Fig. 3 shows components and connections of the components of the switch circuit of the switch device of the first embodiment. As shown in Fig. 3, the switch circuit 11 includes switches SW1, SW2, SW3, and SW4, and a logic circuit 111. In addition to including terminals RFC, RF1, RF2, RF3, and RF4 as described above with reference to Fig. 2, the switch circuit 11 also includes terminals LS, V1, V2, TVDD, and TGND.
[0024] The switch SW1 receives a control signal SC1 and electrically connects or disconnects both ends of the switch SW1 based on the control signal SC1. The switch SW1 is connected between a terminal RFC and a terminal RF1. The switch SW1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
[0025] The switch SW2 receives a control signal SC2 and electrically connects or disconnects both ends of the switch SW2 based on the control signal SC2. The switch SW2 is connected between the terminal RFC and the terminal RF2. The switch SW2 is, for example, a MOSFET.
[0026] The switch SW3 receives a control signal SC3 and electrically connects or disconnects both ends of the switch SW3 based on the control signal SC3. The switch SW3 is connected between the terminal RFC and the terminal RF3. The switch SW3 is, for example, a MOSFET.
[0027] The switch SW4 receives a control signal SC4 and electrically connects or disconnects both ends of the switch SW4 based on the control signal SC4. The switch SW4 is connected between the terminal RFC and the terminal RF4. The switch SW4 is, for example, a MOSFET.
[0028] The logic circuit 111 generates control signals SC1, SC2, SC3, and SC4 based on the voltages received at the terminals LS, V1, and V2. The logic circuit 111 may be configured in any manner as long as it can generate the control signals SC1, SC2, SC3, and SC4, which will be described later with reference to Fig. 4, based on the voltages received at the terminals LS, V1, and V2. The logic circuit 111 includes, for example, a plurality of logic gates.
[0029] 4 shows the relationship between the input and output by the logic circuit included in the switch device of the first embodiment. Each of the terminals V1 and V2 receives a dynamically selected one of two voltages of different magnitudes. One voltage is called the "0" voltage and is labeled "0" in FIG. 4. The other voltage is called the "1" voltage and is labeled "1" in FIG. 4.
[0030] Each of the control signals SC1, SC2, SC3, and SC4 has one of two different magnitudes. In FIG. 4 and the following description, the control signals SC1, SC2, SC3, and SC4 are referred to as having an ON level when the control signal SC1 has a voltage that keeps the switch SW1 on, the control signal SC2 has a voltage that keeps the switch SW2 on, the control signal SC3 has a voltage that keeps the switch SW3 on, and the control signal SC4 has a voltage that keeps the switch SW4 on. The control signals SC1, SC2, SC3, and SC4 are referred to as having an OFF level when the control signal SC1 has a voltage that keeps the switch SW1 off, the control signal SC2 has a voltage that keeps the switch SW2 off, the control signal SC3 has a voltage that keeps the switch SW3 off, and the control signal SC4 has a voltage that keeps the switch SW4 off. In FIG. 4, the ON level is denoted as "ON". In FIG. 4, the OFF level is denoted as "OFF".
[0031] While the terminal LS receives the ground voltage GND, the terminal V1 receives the "0" voltage, and the terminal V2 receives the "0" voltage, the control signal SC1 has the "ON" level, the control signal SC2 has the "OFF" level, the control signal SC3 has the "OFF" level, and the control signal SC4 has the "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF1 among the terminals RF1, RF2, RF3, and RF4 via the switch SW1 that is on. In other words, the terminal RF1 is selected.
[0032] While the terminal LS receives the ground voltage GND, the terminal V1 receives the "0" voltage, and the terminal V2 receives the "1" voltage, the control signal SC1 has the "OFF" level, the control signal SC2 has the "ON" level, the control signal SC3 has the "OFF" level, and the control signal SC4 has the "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF2 among the terminals RF1, RF2, RF3, and RF4 via the switch SW2 that is on. In other words, the terminal RF2 is selected.
[0033] While the terminal LS receives the ground voltage GND, the terminal V1 receives the voltage "1", and the terminal V2 receives the voltage "0", the control signal SC1 has the "OFF" level, the control signal SC2 has the "OFF" level, the control signal SC3 has the "ON" level, and the control signal SC4 has the "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF3 among the terminals RF1, RF2, RF3, and RF4 via the switch SW3 that is on. In other words, the terminal RF3 is selected.
[0034] While the terminal LS receives the ground voltage GND, the terminal V1 receives the voltage "1", and the terminal V2 receives the voltage "1", the control signal SC1 has the "OFF" level, the control signal SC2 has the "OFF" level, the control signal SC3 has the "OFF" level, and the control signal SC4 has the "ON" level. Therefore, the terminal RFC is connected to only the terminal RF4 among the terminals RF1, RF2, RF3, and RF4 via the switch SW4 that is on. In other words, the terminal RF4 is selected.
[0035] While the terminal LS receives the power supply voltage VDD, the terminal V1 receives the "0" voltage, and the terminal V2 receives the "0" voltage, the control signal SC1 has the "OFF" level, the control signal SC2 has the "OFF" level, the control signal SC3 has the "OFF" level, and the control signal SC4 has the "ON" level. Therefore, the terminal RFC is connected to only the terminal RF4 among the terminals RF1, RF2, RF3, and RF4 via the switch SW4 that is on. In other words, the terminal RF4 is selected.
[0036] While the terminal LS receives the power supply voltage VDD, the terminal V1 receives the "0" voltage, and the terminal V2 receives the "1" voltage, the control signal SC1 has the "OFF" level, the control signal SC2 has the "ON" level, the control signal SC3 has the "OFF" level, and the control signal SC4 has the "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF2 among the terminals RF1, RF2, RF3, and RF4 via the switch SW2 that is on. In other words, the terminal RF2 is selected.
[0037] While the terminal LS receives the power supply voltage VDD, the terminal V1 receives the voltage "1", and the terminal V2 receives the voltage "0", the control signal SC1 has the "OFF" level, the control signal SC2 has the "OFF" level, the control signal SC3 has the "ON" level, and the control signal SC4 has the "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF3 among the terminals RF1, RF2, RF3, and RF4 via the switch SW3 that is on. In other words, the terminal RF3 is selected.
[0038] While the terminal LS receives the power supply voltage VDD, the terminal V1 receives the "1" voltage, and the terminal V2 receives the "1" voltage, the control signal SC1 has the "ON" level, the control signal SC2 has the "OFF" level, the control signal SC3 has the "OFF" level, and the control signal SC4 has the "OFF" level. Therefore, the terminal RFC is connected to only the terminal RF1 among the terminals RF1, RF2, RF3, and RF4 via the switch SW1 that is on. In other words, the terminal RF1 is selected.
[0039] Fig. 5 shows an example of the structure of the switch circuit of the switch device of the first embodiment. The switch circuit 11 is realized as a semiconductor device 21. In Fig. 5 and subsequent figures, elements shown in transparent form are indicated by dashed lines.
[0040] 5, the semiconductor device 21 extends along the XY plane and has a quadrilateral shape. For example, the semiconductor device 21 has a rectangular shape.
[0041] The semiconductor device 21 includes terminals RFC, RF1, RF2, RF3, RF4, LS, V1, V2, TVDD, TGND, and TN. The terminals RFC, RF1, RF2, RF3, RF4, LS, V1, V2, TVDD, TGND, and TN are disposed on the lower surface of the semiconductor device 21, i.e., the surface on the side in the -Z direction. The terminals RFC, RF1, RF2, RF3, RF4, LS, V1, V2, TVDD, TGND, and TN are arranged along the edge of the semiconductor device 21. In one example, six terminals are arranged at intervals along each side of the semiconductor device 21. The following description is based on this example.
[0042] Of the four sides of the semiconductor device 21, the side facing the terminal RFC is referred to as a first side L1. The second side L2 faces the first side L1. In one example, the first side L1 and the second side L2 are aligned in the +X direction. Of the four sides of the semiconductor device 21, the side facing the terminal RF1 is referred to as a third side L3. The third side L3 faces the fourth side L4. In one example, the fourth side L4 and the third side L3 are aligned in the +Y direction.
[0043] In one example, the terminal RFC is arranged fourth from the third side L3.
[0044] The terminals V1, V2, LS, and TVDD face the second side L2. The terminals V1 and V2 are adjacent to each other. In one example, the terminal V1 is disposed fourth from the third side L3, and the terminal V2 is disposed fifth from the third side L3. The terminals LS and TVDD may occupy any of the remaining terminal positions among the multiple terminals arranged along the second side L2.
[0045] The terminals RF1 and RF2 face the third side L3. The terminals RF1 and RF2 may occupy any position among a plurality of terminals arranged along the third side L3. In one example, the terminal RF1 is disposed second from the first side L1, and the terminal RF2 is disposed fifth from the first side L1.
[0046] Terminals RF3 and RF4 face the fourth side L4. Terminal RF3 is disposed near the side of the first side L1 or the second side L2 to which terminal RF2 is closer. Based on an example in which terminal RF1 is disposed second from the first side L1 and terminal RF2 is disposed fifth from the first side L1, terminal RF3 is disposed closer to the second side L2 than to the first side L1. In one example, terminals RF3 and RF2 are aligned in the +Y direction.
[0047] The terminal RF4 is disposed near the side of the first side L1 or the second side L2 to which the terminal RF1 is closer. Based on an example in which the terminal RF1 is disposed second from the first side L1 and the terminal RF2 is disposed fifth from the first side L1, the terminal RF4 is disposed closer to the first side L1 than the second side L2. In one example, the terminals RF4 and RF1 are aligned in the +Y direction.
[0048] The terminal TN occupies a position other than the terminals RFC, V1, V2, LS, TVDD, and TGND. In one example, the terminal TN functions as a ground terminal.
[0049] The terminal TGND has a quadrilateral shape, and in one example, has a rectangular shape. The terminal TGND is disposed in the center of the semiconductor device 21.
[0050] Fig. 6 shows an example of a part of the structure of the switch device of the first embodiment, and illustrates the arrangement of the components of the switch device along the XY plane. As shown in Fig. 5, the switch device 4 includes semiconductor devices 21 (21a and 21b), a printed wiring board 23, and wirings W1, W2, W3, W4, W7, W8, W11, W12, W13, W14, W15, W16, W17, and W18.
[0051] The printed wiring board 23 is a board including an insulating substrate. The printed wiring board 23 extends along the XY plane. The printed wiring board 23 may include a plurality of insulator layers and a conductor having a pattern between the insulator layers. The control circuit 13 (not shown) is also disposed on the printed wiring board 23.
[0052] The semiconductor device 21a realizes the switch circuit 11a. The semiconductor device 21b realizes the switch circuit 11b. The semiconductor device 21 is disposed on the surface (upper surface) of the printed wiring board 23 on the +Z direction side. The lower surface of the semiconductor device 21 faces the printed wiring board 23. The semiconductor device 21a and the semiconductor device 21b are aligned in the +X direction.
[0053] The semiconductor devices 21a and 21b face in opposite directions to each other, that is, the third side L3 of the semiconductor device 21a faces the +Y direction, and the third side L3 of the semiconductor device 21b faces the -Y direction.
[0054] Terminals V1 and V2 of the semiconductor device 21a are connected to the control circuit 13 by wiring (not shown) provided on the printed wiring board 23, and receive a voltage from the control circuit 13.
[0055] The terminal TVDD receives the power supply voltage VDD. One of the terminal TVDD of the semiconductor device 21a and the terminal TVDD of the semiconductor device 21b is connected to a node that supplies the power supply voltage VDD by a wiring (not shown) provided on the printed wiring board 23. The terminal TVDD of the semiconductor device 21a and the terminal TVDD of the semiconductor device 21b are connected by a wiring (not shown) provided on the printed wiring board 23.
[0056] The terminal TGND receives the ground voltage GND. The terminal TGND of the semiconductor device 21a and the terminal TGND of the semiconductor device 21b are connected to a node that supplies the ground voltage GND by separate wiring (not shown) provided on the printed wiring board 23. Alternatively, one of the terminal TGND of the semiconductor device 21a and the terminal TGND of the semiconductor device 21b may be connected to a node that supplies the ground voltage GND, and the terminal TGND of the semiconductor device 21a and the terminal TGND of the semiconductor device 21b may be connected to each other by a wiring provided on the printed wiring board 23.
[0057] The delay circuits 12a, 12b, 12c, and 12d are arranged on the upper surface of the printed wiring board 23. The delay circuits 12a, 12b, 12c, and 12d are arranged in this order in the -Y direction. The set of the delay circuits 12a, 12b, 12c, and 12d is arranged between the semiconductor devices 21a and 21b.
[0058] The wires W1, W2, W3, W4, W7, W8, W11, W12, W13, W14, W15, W16, W17, and W18 are linear conductors. W1, W2, W3, W4, W7, W8, W11, W12, W13, W14, W15, W16, W17, and W18 are disposed on the upper surface of the printed wiring board 23.
[0059] One end of the wiring W1 overlaps with the terminal LS of the semiconductor device 21a and is in contact with the terminal LS of the semiconductor device 21a. The other end of the wiring W1 overlaps with the terminal TGND of the semiconductor device 21a and is in contact with the terminal TGND of the semiconductor device 21a. As a result, the voltage of the terminal LS of the semiconductor device 21a is fixed to the ground voltage GND.
[0060] One end of the wiring W2 overlaps with the terminal LS of the semiconductor device 21b and is in contact with the terminal LS of the semiconductor device 21b. The other end of the wiring W2 overlaps with the terminal TVDD of the semiconductor device 21b and is in contact with the terminal TVDD of the semiconductor device 21b. As a result, the voltage of the terminal LS of the semiconductor device 21b is fixed to the power supply voltage VDD.
[0061] One end of the wiring W3 overlaps with the terminal RFC of the semiconductor device 21a and is in contact with the terminal RFC of the semiconductor device 21a. The other end of the wiring W3 is connected to the amplifier circuit 3.
[0062] The wiring W4 has one end overlapping the terminal RFC of the semiconductor device 21b and in contact with the terminal RFC of the semiconductor device 21b. The other end of the wiring W4 is connected to the amplifier circuit 3.
[0063] One end of the wiring W11 overlaps with and is in contact with the terminal RF1 of the semiconductor device 21a, and the other end of the wiring W11 is connected to the input terminal of the delay circuit 12a.
[0064] One end of the wiring W12 is connected to the output terminal of the delay circuit 12a, and the other end of the wiring W12 overlaps with and is in contact with the terminal RF4 of the semiconductor device 21b.
[0065] One end of the wiring W13 overlaps with and is in contact with the terminal RF2 of the semiconductor device 21a. The other end of the wiring W13 is connected to the input terminal of the delay circuit 12b.
[0066] One end of the wiring W14 is connected to the output terminal of the delay circuit 12b. The other end of the wiring W14 overlaps with and is in contact with the terminal RF3 of the semiconductor device 21b.
[0067] The semiconductor devices 21a and 21b have terminals in the arrangement described above with reference to Fig. 5, facing in opposite directions, and having the relationship between the inputs (voltages at terminals LS, V1, and V2) and outputs (control signals SC1, SC2, SC3, and SC4) described above with reference to Fig. 4. Therefore, the pair of terminals RF1 of the semiconductor device 21a and terminal RF4 of the semiconductor device 21b, which are connected to each other via the delay circuit 12a, is located outside the pair of terminals RF2 of the semiconductor device 21a and terminal RF3 of the semiconductor device 21b, which are connected to each other via the delay circuit 12b. This allows the wiring W11 to extend from the terminal RF1 of the semiconductor device 21a to the input end of the delay circuit 12a without crossing the wiring W11 and the wiring W13, and allows the wiring W13 to extend from the terminal RF2 of the semiconductor device 21a to the input end of the delay circuit 12b. Furthermore, the wiring W12 can extend from the output terminal of the delay circuit 12a to the terminal RF4 of the semiconductor device 21b without intersecting with the wiring W12 and the wiring W14 can extend from the output terminal of the delay circuit 12b to the terminal RF3 of the semiconductor device 21b.
[0068] The shapes of the wiring W11 and the wiring W13 along the XY plane can be any shape as long as they do not intersect. The shapes of the wiring W12 and the wiring W14 along the XY plane can be any shape as long as they do not intersect. Fig. 6 shows an example in which each of the wirings W11, W12, W13, and W14 has an L-shape, but one or more of the wirings W11, W12, W13, and W14 may be bent at two or more points.
[0069] One end of the wiring W15 overlaps with and is in contact with the terminal RF3 of the semiconductor device 21a. The other end of the wiring W15 is connected to the input terminal of the delay circuit 12c.
[0070] One end of the wiring W16 is connected to the output terminal of the delay circuit 12c. The other end of the wiring W16 overlaps with the terminal RF2 of the semiconductor device 21b and is in contact with the terminal RF2 of the semiconductor device 21b.
[0071] One end of the wiring W17 overlaps with and is in contact with the terminal RF4 of the semiconductor device 21a The other end of the wiring W17 is connected to the input terminal of the delay circuit 12d.
[0072] One end of the wiring W18 is connected to the output terminal of the delay circuit 12d. The other end of the wiring W18 overlaps with and is in contact with the terminal RF1 of the semiconductor device 21b.
[0073] The semiconductor devices 21a and 21b have terminals in the arrangement described above with reference to Fig. 5, facing in opposite directions, and having the relationship between the inputs (voltages at terminals LS, V1, and V2) and outputs (control signals SC1, SC2, SC3, and SC4) described above with reference to Fig. 4. Therefore, the pair of terminals RF4 of the semiconductor device 21a and terminal RF1 of the semiconductor device 21b, which are connected to each other via the delay circuit 12d, is located outside the pair of terminals RF3 of the semiconductor device 21a and terminal RF2 of the semiconductor device 21b, which are connected to each other via the delay circuit 12c. This allows the wiring W15 to extend from the terminal RF3 of the semiconductor device 21a to the input terminal of the delay circuit 12c without crossing the wiring W15 and the wiring W17, and allows the wiring W17 to extend from the terminal RF4 of the semiconductor device 21a to the input terminal of the delay circuit 12d. Furthermore, the wiring W16 can extend from the output terminal of the delay circuit 12c to the terminal RF2 of the semiconductor device 21b without intersecting with the wiring W18, and the wiring W18 can extend from the output terminal of the delay circuit 12d to the terminal RF1 of the semiconductor device 21b.
[0074] The shapes of the wiring W15 and the wiring W17 along the XY plane can be any shape as long as they do not intersect. The shapes of the wiring W16 and the wiring W18 along the XY plane can be any shape as long as they do not intersect. Fig. 6 shows an example in which each of the wirings W15, W16, W17, and W18 has an L-shape, but one or more of the wirings W15, W16, W17, and W18 may be bent at two or more points.
[0075] One end of the wiring W7 overlaps with the terminal V1 of the semiconductor device 21a and is in contact with the terminal V1 of the semiconductor device 21a. The other end of the wiring W7 overlaps with the terminal V2 of the semiconductor device 21b and is in contact with the terminal V2 of the semiconductor device 21b. The wiring W7 allows the terminal V1 of the semiconductor device 21a and the terminal V2 of the semiconductor device 21b to receive the same voltage.
[0076] One end of the wiring W8 overlaps with the terminal V2 of the semiconductor device 21a and is in contact with the terminal V2 of the semiconductor device 21a. The other end of the wiring W8 overlaps with the terminal V1 of the semiconductor device 21b and is in contact with the terminal V1 of the semiconductor device 21b. The wiring W8 allows the terminal V2 of the semiconductor device 21a and the terminal V1 of the semiconductor device 21b to receive the same voltage.
[0077] The semiconductor device 21 has the relationship between the input (voltages of terminals LS, V1, and V2) and the output (control signals SC1, SC2, SC3, and SC4) described above with reference to FIG. 4. Therefore, with respect to the connection between the terminal V1 and the terminal V2, the configuration of FIG. 2 is realized by connecting the terminal V2 of the semiconductor device 21a to the terminal V1 of the semiconductor device 21b and connecting the terminal V1 of the semiconductor device 21a to the terminal V2 of the semiconductor device 21b. The semiconductor device 21 has terminals arranged as described above with reference to FIG. 5 and facing in opposite directions. Therefore, with respect to the positional relationship in the Y direction between the terminals V1 and V2, the terminal V2 of the semiconductor device 21a and the terminal V1 of the semiconductor device 21b, which are connected to each other, are located on the same side (the -Y direction side), and the terminal V1 of the semiconductor device 21a and the terminal V2 of the semiconductor device 21b, which are connected to each other, are located on the same side (the +Y direction side). This allows wiring W7 to extend from terminal V1 of semiconductor device 21a to terminal V2 of semiconductor device 21b without intersecting with wiring W8, and allows wiring W8 to extend from terminal V2 of semiconductor device 21a to terminal V1 of semiconductor device 21b.
[0078] The shapes of the wiring W7 and the wiring W8 along the XY plane can be any shape as long as they do not intersect. Fig. 6 shows an example in which each of the wiring W7 and the wiring W8 has a shape in which two L-shapes are connected, but one or both of the wiring W7 and the wiring W8 may be bent at three or more points.
[0079] 6, a signal path is formed between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b, which is dynamically determined based on the voltages applied to the terminals V1 and V2, as can be seen from FIG. 4 and described below. As described above, the terminal LS of the semiconductor device 21a is connected to the terminal TGND, and the terminal LS of the semiconductor device 21b is connected to the terminal TVDD. Therefore, it should be noted that in the semiconductor device 21a, the terminal LS receives the ground voltage GND, and in the semiconductor device 21b, the terminal LS receives the power supply voltage VDD.
[0080] When the semiconductor device 21a receives a "0" voltage at both the terminals V1 and V2, the control signal SC1 has an on level in the semiconductor device 21a, and the terminals RFC and RF1 are connected. Since the semiconductor device 21a receives a "0" voltage at both the terminals V1 and V2, the semiconductor device 21b receives a "0" voltage at both the terminals V1 and V2. Therefore, in the semiconductor device 21b, the control signal SC4 has an on level, and the terminals RFC and RF4 are connected. Therefore, a signal path is formed between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b via the wiring W11, the delay circuit 12a, and the wiring W12. A signal path via the set of the wiring W13, the delay circuit 12b, and the wiring W14, a signal path via the set of the wiring W15, the delay circuit 12c, and the wiring W16, and a signal path via the set of the wiring W17, the delay circuit 12d, and the wiring W18 are not formed.
[0081] When the semiconductor device 21a receives a "0" voltage at the terminal V1 and a "1" voltage at the terminal V2, the control signal SC2 has an on level in the semiconductor device 21a, and the terminals RFC and RF2 are connected. Since the semiconductor device 21a receives a "0" voltage at the terminal V1 and a "1" voltage at the terminal V2, the semiconductor device 21b receives a "1" voltage at the terminal V1 and a "0" voltage at the terminal V2. Therefore, in the semiconductor device 21b, the control signal SC3 has an on level, and the terminals RFC and RF3 are connected. Therefore, a signal path is formed between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b via the wiring W13, the delay circuit 12b, and the wiring W14. A signal path via the set of wiring W11, delay circuit 12a, and wiring W12, a signal path via the set of wiring W15, delay circuit 12c, and wiring W16, and a signal path via the set of wiring W17, delay circuit 12d, and wiring W18 are not formed.
[0082] When the semiconductor device 21a receives a "1" voltage at the terminal V1 and a "0" voltage at the terminal V2, the control signal SC3 has an on level in the semiconductor device 21a, and the terminals RFC and RF3 are connected. Since the semiconductor device 21a receives a "1" voltage at the terminal V1 and a "0" voltage at the terminal V2, the semiconductor device 21b receives a "0" voltage at the terminal V1 and a "1" voltage at the terminal V2. Therefore, in the semiconductor device 21b, the control signal SC2 has an on level, and the terminals RFC and RF2 are connected. Therefore, a signal path is formed between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b via the wiring W15, the delay circuit 12c, and the wiring W16. A signal path via the set of wiring W11, delay circuit 12a, and wiring W12, a signal path via the set of wiring W13, delay circuit 12b, and wiring W14, and a signal path via the set of wiring W17, delay circuit 12d, and wiring W18 are not formed.
[0083] When the semiconductor device 21a receives a "1" voltage at both the terminals V1 and V2, the control signal SC4 has an on level in the semiconductor device 21a, and the terminals RFC and RF4 are connected. Since the semiconductor device 21a receives a "1" voltage at both the terminals V1 and V2, the semiconductor device 21b receives a "1" voltage at both the terminals V1 and V2. Therefore, in the semiconductor device 21b, the control signal SC1 has an on level, and the terminals RFC and RF1 are connected. Therefore, a signal path is formed between the terminal RFC of the semiconductor device 21a and the terminal RFC of the semiconductor device 21b via the wiring W17, the delay circuit 12d, and the wiring W18. A signal path via the set of the wiring W11, the delay circuit 12a, and the wiring W12, a signal path via the set of the wiring W13, the delay circuit 12b, and the wiring W14, and a signal path via the set of the wiring W15, the delay circuit 12c, and the wiring W16 are not formed.
[0084] According to the first embodiment, as described below, a switch device with simple internal connections can be provided.
[0085] As in the first embodiment, a switch device having the same function as the switch device 4 can be realized by using two identical semiconductor devices. At this time, depending on the logical operation that the semiconductor device performs on the input (corresponding to the voltages of the terminals V1 and V2 in the first embodiment), it is necessary to connect the same inputs of the two semiconductor devices to each other. That is, a semiconductor device having the same terminals as the semiconductor device 21 and performing a logical operation different from the logical operation performed by the semiconductor device 21 can be used in place of the semiconductor device 21 in FIG. 6. Then, the terminals V1 of the two semiconductor devices are connected to each other, and the terminals V2 of the two semiconductor devices are connected to each other. Since the semiconductor device 21 faces in the opposite direction and faces each other at the side of the terminals V1 and V2, the arrangement order of the terminals V1 and V2 in the +Y direction of the semiconductor device 21a is different from the arrangement order of the terminals V1 and V2 in the +Y direction of the semiconductor device 21b. For this reason, the wiring that connects the terminals V1 to each other and the wiring that connects the terminals V2 to each other need to cross. To cross the wiring, vias are required inside the printed wiring board. However, the manufacture of such a structure is complicated.
[0086] According to the first embodiment, the switch device 4 includes two identical semiconductor devices 21a and 21b that realize the switch circuit 11 and connect the terminal RFC to the terminal RF1, RF2, RF3, or RF4 based on the combination of the voltages at the terminals V1 and V2. When the semiconductor device 21 receives a "0" voltage at the terminal V1 and a "1" voltage at the terminal V2, the semiconductor device 21a connects the terminal RFC to the terminal RF2, and the semiconductor device 21b connects the terminal RFC to the terminal RF3. When the semiconductor device 21 receives a "1" voltage at the terminal V1 and a "0" voltage at the terminal V2, the semiconductor device 21a connects the terminal RFC to the terminal RF3, and the semiconductor device 21b connects the terminal RFC to the terminal RF2. The semiconductor devices 21a and 21b face each other in the opposite directions and face each other at the sides of the terminals V1 and V2, and the terminal V1 of the semiconductor device 21a is connected to the terminal V2 of the semiconductor device 21b, and the terminal V2 of the semiconductor device 21a is connected to the terminal V1 of the semiconductor device 21b. As a result, by forming a signal path from the terminal RF2 of the semiconductor device 21a to the terminal RF3 of the semiconductor device 21b and a signal path from the terminal RF3 of the semiconductor device 21a to the terminal RF2 of the semiconductor device 21b, two signal paths can be selected by applying a "0" voltage to the terminal V1 of the semiconductor device 21a and a "1" voltage to the terminal V2 of the semiconductor device 21a, or by applying a "1" voltage to the terminal V1 of the semiconductor device 21a and a "0" voltage to the terminal V2 of the semiconductor device 21a. Thus, by using two identical devices, a switch device 4 that switches between two signal paths is realized.
[0087] Furthermore, as described above, when the semiconductor device 21 receives different voltages at the terminals V1 and V2, the semiconductor device 21a selects the terminal RF2 and the semiconductor device 21b selects the terminal RF3, or the semiconductor device 21a selects the terminal RF3 and the semiconductor device 21b selects the terminal RF2. To realize such an operation, the terminal V1 of the semiconductor device 21a is connected to the terminal V2 of the semiconductor device 21b, and the terminal V2 of the semiconductor device 21a is connected to the terminal V1 of the semiconductor device 21b. Therefore, the wirings W7 and W8 do not need to cross. Therefore, a switch device 4 with simple internal connections can be realized.
[0088] 2. Second embodiment The second embodiment is based on the first embodiment and relates to the arrangement of the terminal TVDD.
[0089] 7 shows an example of the structure of a switch circuit of a switch device according to the second embodiment. The switch circuit 11 of a switch device 4B according to the second embodiment is realized as a semiconductor device 21B. As shown in FIG. 7, a terminal TVDD is disposed between a terminal V1 and a terminal V2.
[0090] FIG. 8 shows an example of a part of the structure of the switch device of the second embodiment, and shows the arrangement of the components of the switch device along the XY plane. As shown in FIG. 8, based on the arrangement of the terminal TVDD between the terminal V1 and the terminal V2, the terminal V1 and the terminal V2 are not adjacent to each other and have a gap. Depending on the arrangement of the terminal V1 and the terminal V2, the terminal V1 of the semiconductor device 21Ba and the terminal V2 of the semiconductor device 21Bb are aligned in the +X direction, and the terminal V2 of the semiconductor device 21Ba and the terminal V1 of the semiconductor device 21Bb are aligned in the +X direction. FIG. 8 shows such an example. Based on the arrangement shown as an example in FIG. 8, the wirings W7B and W8B in the second embodiment have a straight line shape.
[0091] The switch device 4B further includes a wiring W21. The wiring W21 is a conductor having a linear shape and is disposed on the upper surface of the printed wiring board 23. One end of the wiring W21 overlaps with the terminal TVDD of the semiconductor device 21a and is in contact with the terminal TVDD of the semiconductor device 21a. The other end of the wiring W21 overlaps with the terminal TVDD of the semiconductor device 21b and is in contact with the terminal TVDD of the semiconductor device 21b. In one example, the wiring W21 has a shape in which two L-shapes are connected.
[0092] According to the second embodiment, the same advantages as those of the first embodiment can be obtained. Moreover, according to the second embodiment, the terminal TVDD is disposed between the terminal V1 and the terminal V2. Therefore, the wiring W21 can be provided without intersecting with the wirings W7B and W8B. Therefore, a switch device 4B with simple internal connections can be realized.
[0093] 3. Third embodiment The third embodiment is based on the second embodiment, but differs from the second embodiment in the positions of the terminals V1 and V2.
[0094] Fig. 9 shows an example of the structure of a switch circuit of a switch device of the third embodiment. A switch circuit 11 of a switch device 4C of the third embodiment is realized as a semiconductor device 21C. As shown in Fig. 9, terminals V1 and V2 face a first side L1 and sandwich a terminal RFC. In one example, the terminal V1 is located at the end in the +Y direction among the multiple terminals lined up along the first side L1, and the terminal V2 is located at the end in the -Y direction among the multiple terminals lined up along the first side L1.
[0095] 10 shows an example of a part of the structure of the switch device of the third embodiment, and illustrates the arrangement of the components of the switch device along the XY plane. As shown in FIG. 10, the switch device 4C does not include the wires W7B and W8B, but includes the wires W24 and W25. The wires W24 and W25 are conductors having a linear shape and are arranged on the upper surface of the printed wiring board 23.
[0096] One end of the wiring W24 overlaps with the terminal V1 of the semiconductor device 21Ca and is in contact with the terminal V1 of the semiconductor device 21Ca. The other end of the wiring W24 overlaps with the terminal V2 of the semiconductor device 21Cb and is in contact with the terminal V2 of the semiconductor device 21Cb. The wiring W24 is located outside the region consisting of the pair of the semiconductor devices 21Ca and 21Cb, and is disposed in the +Y direction from the wiring W11, the delay circuit 12a, and the wiring W12.
[0097] One end of the wiring W25 overlaps with the terminal V2 of the semiconductor device 21Ca and is in contact with the terminal V2 of the semiconductor device 21Ca. The other end of the wiring W25 overlaps with the terminal V1 of the semiconductor device 21Cb and is in contact with the terminal V1 of the semiconductor device 21Cb. The wiring W25 is located outside the region consisting of the pair of the semiconductor devices 21Ca and 21Cb, and is disposed in the -Y direction from the wiring W17, the delay circuit 12d, and the wiring W18.
[0098] According to the third embodiment, the same advantages as those of the first and second embodiments can be obtained. According to the third embodiment, the terminals V1 and V2 face the first side L1 and sandwich the terminal RFC. Therefore, the terminals V1 and V2 are not located in the area surrounded by the semiconductor devices 21Ca and 21Cb, the wirings W11, W12, W17, and W18, and the delay circuits 12a and 12d. Therefore, the wiring connecting the terminal V1 of the semiconductor device 21Ca and the control circuit 13, and the wiring connecting the terminal V2 of the semiconductor device 21Ca and the control circuit 13 do not need to intersect with any of the wirings W11, W12, W13, W14, W15, W16, W17, and W18. Therefore, signals transmitted through the wirings W11, W12, W13, W14, W15, W16, W17, and W18 are not affected by the voltage transmitted through the wiring connecting the terminal V1 of the semiconductor device 21Ca and the control circuit 13 and the wiring connecting the terminal V2 of the semiconductor device 21Ca and the control circuit 13. That is, the signals transmitted through the wirings W11, W12, W13, W14, W15, W16, W17, and W18 are prevented from being subjected to noise.
[0099] 4. Fourth embodiment The fourth embodiment is based on the third embodiment, but differs from the third embodiment in the position of the terminal TVDD.
[0100] FIG. 11 shows an example of the structure of a switch circuit of a switch device of the fourth embodiment. The switch circuit 11 of a switch device 4D of the fourth embodiment is realized as a semiconductor device 21D. As shown in FIG. 11, the semiconductor device 21D includes a terminal TVDD2. The terminal TVDD2 is connected to the terminal TVDD inside the switch device 4D. The terminals TVDD and TVDD2 face the first side L1. The terminal TVDD is disposed between the terminal RFC and the terminal V2. The terminal TVDD2 is disposed between the terminal V1 and the terminal RFC. The positions of the terminal TVDD and the terminal TVDD2 may be interchanged.
[0101] 12 shows an example of a part of the structure of the switch device of the fourth embodiment, and illustrates the arrangement of the components of the switch device along the XY plane. As shown in FIG. 12, the switch device 4D does not include the wires W2 and W21, but includes the wires W27 and W29. The wires W27 and W29 are conductors having a linear shape and are arranged on the upper surface of the printed wiring board 23.
[0102] The wiring W27 is disposed between the printed wiring board 23 and the semiconductor device 21Db. One end of the wiring W27 overlaps with and is in contact with the terminal LS of the semiconductor device 21Db. The other end of the wiring W27 overlaps with and is in contact with the terminal TVDD of the semiconductor device 21Db.
[0103] One end of the wiring W29 overlaps with the terminal TVDD of the semiconductor device 21Da and is in contact with the terminal TVDD of the semiconductor device 21Da. The other end of the wiring W29 overlaps with the terminal TVDD2 of the semiconductor device 21Db and is in contact with the terminal TVDD2 of the semiconductor device 21Db. The wiring W29 is located outside the region consisting of the pair of the semiconductor devices 21Da and 21Db, and is disposed in the -Y direction from the wiring W25.
[0104] The wiring W29 may be in contact with the terminal TVDD2 of the semiconductor device 21Da and the terminal TVDD of the semiconductor device 21Db. In this case, the wiring W29 is located outside the region consisting of the pair of the semiconductor devices 21Da and 21Db, and is arranged in the +Y direction from the wiring W24.
[0105] According to the fourth embodiment, the same advantages as those of the first to third embodiments can be obtained. Moreover, the semiconductor device 21D of the fourth embodiment includes a terminal TVDD2, and the terminals TVDD and TVDD2 face the first side L1. Therefore, in the switch device 4D, the terminals TVDD and TVDD2 are not located in the area surrounded by the semiconductor devices 21Da and 21Db, the wirings W11, W12, W17, and W18, and the delay circuits 12a and 12d. Therefore, the signals transmitted through the wirings W11, W12, W13, W14, W15, W16, W17, and W18 are not affected by the voltage transmitted through the wiring connecting the terminal TVDD of the semiconductor device 21Da and the control circuit 13. That is, the signals transmitted through the wirings W11, W12, W13, W14, W15, W16, W17, and W18 are suppressed from receiving noise.
[0106] The terminals TVDD2 and V1 may be interchanged, and the terminals TVDD and V2 may be interchanged. In this case, the wiring W25 is disposed in the -Y direction of the wiring W29.
[0107] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]
[0108] 10...Transmitting and receiving device, 1...Data processing circuit, 2...Transceiver, 3...Amplification circuit, 4...Switch device, 5…Antenna, 11...Switch circuit, 12...Delay circuit, 13...Control circuit, 21...Semiconductor device, 111...Logic circuits, 23...Printed wiring board, RFC, RF1, RF2, RF3, RF4, TGND, TVDD, TN...terminals W1, W2, W3, W4, W7, W8, W11, W12, W13, W14, W15, W16, W17, W18…Wiring
Claims
1. A first semiconductor device and a second semiconductor device, each of the first semiconductor device and the second semiconductor device comprising: a first side, a second side and a third side opposing each other, a first terminal, a second terminal facing the second side, a third terminal facing the third side, a fourth terminal and a fifth terminal arranged along the first side, and a sixth terminal; connecting the first terminal and the second terminal while the sixth terminal receives a first voltage, the fourth terminal receives a second voltage, and the fifth terminal receives a third voltage; a first semiconductor device and a second semiconductor device connecting the first terminal and the third terminal while the sixth terminal receives a fourth voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the second voltage; a first delay circuit that supplies a signal obtained by delaying a signal at an input terminal connected to the second terminal of the first semiconductor device to the third terminal of the second semiconductor device; a first conductor connected to the fourth terminal of the first semiconductor device and the fifth terminal of the second semiconductor device; a second conductor connected to the fifth terminal of the first semiconductor device and the fourth terminal of the second semiconductor device; Equipped with the first side of the first semiconductor device faces the first side of the second semiconductor device, the sixth terminal of the first semiconductor device is connected to a terminal receiving the first voltage; the sixth terminal of the second semiconductor device is connected to a terminal receiving the fourth voltage; Switch device.
2. A first semiconductor device and a second semiconductor device, each of the first semiconductor device and the second semiconductor device comprising: a first side, a second side and a third side opposing each other, a fourth side opposing the first side, a first terminal, a second terminal facing the second side, a third terminal facing the third side, a fourth terminal and a fifth terminal arranged along the first side, and a sixth terminal; connecting the first terminal and the second terminal while the sixth terminal receives a first voltage, the fourth terminal receives a second voltage, and the fifth terminal receives a third voltage; a first semiconductor device and a second semiconductor device connecting the first terminal and the third terminal while the sixth terminal receives a fourth voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the second voltage; a first delay circuit that supplies a signal obtained by delaying a signal at an input terminal connected to the second terminal of the first semiconductor device to the third terminal of the second semiconductor device; a first conductor connected to the fourth terminal of the first semiconductor device and the fifth terminal of the second semiconductor device; a second conductor connected to the fifth terminal of the first semiconductor device and the fourth terminal of the second semiconductor device; Equipped with the fourth side of the first semiconductor device faces the fourth side of the second semiconductor device, the sixth terminal of the first semiconductor device is connected to a terminal receiving the first voltage; the sixth terminal of the second semiconductor device is connected to a terminal receiving the fourth voltage; Switch device.
3. a second delay circuit that supplies a signal obtained by delaying a signal at an input terminal connected to the third terminal of the first semiconductor device to the second terminal of the second semiconductor device; Each of the first semiconductor device and the second semiconductor device is connecting the first terminal and the third terminal while the sixth terminal receives the first voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the second voltage; connecting the first terminal and the second terminal while the sixth terminal receives the fourth voltage, the fourth terminal receives the second voltage, and the fifth terminal receives the third voltage; The switch device according to claim 1 or 2.
4. Each of the first semiconductor device and the second semiconductor device is a seventh terminal facing the second side and an eighth terminal facing the third side, connecting the first terminal and the seventh terminal while the sixth terminal receives the first voltage, the fourth terminal receives the second voltage, and the fifth terminal receives the second voltage, and while the sixth terminal receives the fourth voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the third voltage; connecting the first terminal and the eighth terminal while the sixth terminal receives the first voltage, the fourth terminal receives the third voltage, and the fifth terminal receives the third voltage, and while the sixth terminal receives the fourth voltage, the fourth terminal receives the second voltage, and the fifth terminal receives the second voltage; The switch device according to claim 3.
5. a third delay circuit that supplies a signal obtained by delaying a signal at an input terminal connected to the seventh terminal of the first semiconductor device to the eighth terminal of the second semiconductor device; a fourth delay circuit that supplies a signal obtained by delaying a signal at an input terminal connected to the eighth terminal of the first semiconductor device to the seventh terminal of the second semiconductor device; Further comprising: The switch device according to claim 4.
6. each of the first semiconductor device and the second semiconductor device further includes a ninth terminal receiving the fourth voltage and disposed between the fourth terminal and the fifth terminal; a third conductor connected to the ninth terminal of the first semiconductor device and the ninth terminal of the second semiconductor device; The switch device according to claim 1 .
7. each of the first semiconductor device and the second semiconductor device further includes a ninth terminal facing the fourth side and receiving the fourth voltage; a third conductor connected to the ninth terminal of the first semiconductor device and the ninth terminal of the second semiconductor device; The switch device according to claim 2 .
8. each of the first semiconductor device and the second semiconductor device further includes a ninth terminal facing the first side and receiving the fourth voltage; a third conductor connected to the ninth terminal of the first semiconductor device and the ninth terminal of the second semiconductor device; The switch device according to claim 2 .
Citation Information
Patent Citations
Deburring apparatus
JP1984083773A