Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a technology that can improve reliability of a semiconductor device.SOLUTION: A semiconductor device comprises: a drift layer; a body region that is provided between a source region and a contact region, and has a second conductivity type in which second conductivity type impurity density is lower than the contact region; and a channel layer that is provided on a part corresponding to at least the contact region, of an inner surface of a trench arriving at the drift layer by penetrating through the source region, the contact region and the body region, and has lower crystal defects than the contact region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] A semiconductor device has been proposed in which a channel layer is formed by epitaxial growth on the inner surface of a trench in a source region (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-259896 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the configuration of Patent Document 1, a source region is provided between a gate insulating film and a contact region, and the gate insulating film and the contact region are not in contact with each other. However, in a configuration in which the contact region has a stripe shape in a plan view, the gate insulating film and the contact region are in contact with each other.

[0005] Generally, a contact region has many crystal defects because it is formed by ion implantation of a high concentration of impurities. Therefore, in a configuration in which a gate insulating film and a contact region are in contact with each other, the electric field of the gate voltage is locally concentrated at the interface between the crystal defect part of the contact region and the gate insulating film, and defects due to the crystal defect part of the contact region occur in the gate insulating film. As a result, a leak current occurs in the semiconductor device, and the reliability of the semiconductor device is reduced.

[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique capable of improving the reliability of a semiconductor device. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure includes a drift layer having a first conductivity type, a source region having the first conductivity type selectively provided above the drift layer, a contact region having a second conductivity type selectively provided above the drift layer, a body region having the second conductivity type provided between the drift layer and each of the source region and the contact region, the body region having a lower impurity concentration of the second conductivity type than the contact region, a channel layer provided on at least a portion of an inner surface of a trench that penetrates the source region, the contact region, and the body region to reach the drift layer, the channel layer having fewer crystal defects than the contact region, a gate insulating film provided along the inner surface of the trench, and a gate electrode provided on the gate insulating film in the trench. Effect of the Invention

[0008] According to the present disclosure, the channel layer, which has fewer crystal defects than the contact region, is provided on at least a portion of the inner surface of the trench that corresponds to the contact region, thereby improving the reliability of the semiconductor device. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 4] 11A to 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Diagram 5] 11A to 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 6] 11A to 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Figure 7] 11A to 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are illustrative, and not all features are necessarily required. In addition, in the following description, the same or similar symbols are used for similar components in multiple embodiments, and different components are mainly described. In addition, in the following description, specific positions and directions such as "upper", "lower", "left", "right", "front" or "rear" do not necessarily have to match the positions and directions in actual implementation. In addition, a certain part having a higher concentration than another part means, for example, that the average concentration of a certain part is higher than the average concentration of another part. Conversely, a certain part having a lower concentration than another part means, for example, that the average concentration of a certain part is lower than the average concentration of another part. In addition, in the following description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0011] <Embodiment 1> Fig. 1 is a plan view showing the configuration of a semiconductor device according to the first embodiment, Fig. 2 is a cross-sectional view taken along the line A-A' in Fig. 1, and Fig. 3 is a cross-sectional view taken along the line B-B' in Fig. 1. The semiconductor device according to the first embodiment is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited to a MOSFET as described later.

[0012] As shown in Figures 2 and 3, the semiconductor device of the first embodiment includes an n-type semiconductor substrate 1, an n-type drift layer 2, a p-type body region 3, an n-type source region 4 (see Figure 2), a p-type contact region 5 (see Figure 3), a channel layer 7, a gate insulating film 8, a gate electrode 9, an interlayer insulating film 10, a source electrode 11, a p-type bottom protection region 12, a p-type connection region 13 (see Figure 3), and a drain electrode 14.

[0013] 2 and 3, the drift layer 2 is, for example, an epitaxial layer provided on the upper surface of the semiconductor substrate 1. The drift layer 2 is not limited to this, and may be the semiconductor substrate 1, or may be the semiconductor substrate 1 and an epitaxial layer. In the first embodiment, the semiconductor substrate 1, the drift layer 2, the body region 3, the source region 4, and the contact region 5 contain silicon carbide, but may contain silicon or a wide band gap semiconductor other than silicon carbide (for example, GaN and diamond).

[0014] 2 and 3, each of the source region 4 and the high-concentration p-type contact region 5 is selectively provided above the drift layer 2. As shown in Fig. 1, the source region 4 and the contact region 5 have a stripe shape in a plan view.

[0015] 2 and 3, the body region 3 is provided between the drift layer 2 and each of the source region 4 and the contact region 5. The body region 3 is provided at a position deeper than each of the source region 4 and the contact region 5 and shallower than the bottom of a trench 6 described later. The p-type impurity concentration of the body region 3 is lower than the p-type impurity concentration of the contact region 5.

[0016] A trench 6 penetrating the source region 4, the contact region 5, and the body region 3 to reach the drift layer 2 is provided in the source region 4, the contact region 5, and the body region 3. As shown in FIG 1, in a plan view, the trench 6 extends in a direction intersecting with the extension directions of the source region 4 and the contact region 5.

[0017] 2 and 3, the channel layer 7 is provided on at least a portion of the inner surface of the trench 6 that corresponds to the contact region 5. In the first embodiment, the channel layer 7 is configured to cover the entire inner surface of the trench 6 including the side and bottom surfaces, and parts of the upper surfaces of the source region 4 and the contact region 5. The thickness of the channel layer 7 in the extension direction of the contact region 5, that is, the thickness of the channel layer 7 between the contact region 5 and the gate insulating film 8, is, for example, 500 nm or less.

[0018] The channel layer 7 has fewer crystal defects than the contact region 5. Such a channel layer 7 can be formed, for example, by epitaxial growth with fewer crystal defects after ion implantation for forming the contact region 5 is performed.

[0019] The channel layer 7 may have an n-type or p-type conductivity, or may not have a conductivity type. The channel layer 7 having an n-type or p-type may be formed by epitaxial growth using an n-type or p-type impurity. Alternatively, as described in the second embodiment, the channel layer 7 having an n-type or p-type may be formed by forming an epitaxial layer by epitaxial growth, and then performing ion implantation into the epitaxial layer, which has fewer crystal defects than the ion implantation into the contact region 5. The crystal defects can be measured using, for example, X-rays, cathodoluminescence light, and secondary electrons.

[0020] The gate insulating film 8 is, for example, an oxide film, and is provided along the inner surface of the trench 6. In the examples of Fig. 2 and Fig. 3, the gate insulating film 8 is provided on the channel layer 7, but it may be provided on the channel layer 7 and on the inner surface of the trench 6 where the channel layer 7 is not provided.

[0021] The gate electrode 9 is a conductive member such as polysilicon, and is provided on the gate insulating film 8 in the trench 6. The interlayer insulating film 10 covers the gate electrode 9 to such an extent that the gate electrode 9 can be electrically connected to the outside, thereby insulating the gate electrode 9 from the channel layer 7 and the source electrode 11. The source electrode 11 is electrically connected to the source region 4 and the contact region 5. The source electrode 11 may include, for example, a silicide film 11a that is ohmic-connected to the source region 4 and the contact region 5.

[0022] The bottom protection region 12 is provided at the bottom of the trench 6. For example, the p-type impurity concentration of the bottom protection region 12 is higher than the p-type impurity concentration of the body region 3. The connection region 13 electrically connects the body region 3 and the bottom protection region 12. The drain electrode 14 is provided on the lower surface of the semiconductor substrate 1.

[0023] In a conventional semiconductor device, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 9, a channel is formed in the body region 3 adjacent to the gate insulating film 8, and a current flows between the source electrode 11 and the drain electrode 14 via the channel. In such a semiconductor device, increasing the channel density reduces power loss during current flow. In order to increase the channel density, it is effective to narrow the distance between adjacent trenches 6. However, narrowing the distance between the trenches 6 narrows the width of the mesa between the trenches 6, making it difficult to form the source region 4 and the contact region 5.

[0024] Therefore, in the present embodiment 1, the source region 4 and the contact region 5 have a stripe shape as shown in Fig. 1. With such a configuration, even if the interval between the trenches 6 is narrowed, the source region 4 and the contact region 5 can be easily formed, and the power loss during current flow can be reduced.

[0025] However, in a configuration in which the source region 4 and the contact region 5 have a stripe shape, the gate insulating film 8 and the contact region 5 are in contact with each other. In general, the contact region 5 having a high impurity concentration is formed by high-dose ion implantation. In high-dose ion implantation, a large number of crystal defects occur in the implanted region and the region through which the ions have passed. Although the crystal defects disappear to some extent by heating (annealing), they do not disappear completely, and therefore a large number of crystal defects remain in the contact region 5.

[0026] For this reason, in a configuration in which the gate insulating film 8 and the contact region 5 are in contact with each other, the electric field of the gate voltage is locally concentrated at the interface between the gate insulating film 8 and the crystal defect portion of the contact region 5, and defects due to the crystal defect portion of the contact region 5 occur in the gate insulating film 8. As a result, a leak current occurs in the semiconductor device, causing a problem of reduced reliability of the semiconductor device.

[0027] In contrast, in the present embodiment 1, the channel layer 7, which has fewer crystal defects than the contact region 5, is provided on at least a portion of the inner surface of the trench 6 that corresponds to the contact region 5. This configuration makes it possible to prevent the electric field of the gate voltage from concentrating locally at the interface between the crystal defect portion of the contact region 5 and the gate insulating film 8, and to prevent defects caused by the crystal defect portion from occurring in the gate insulating film 8. This makes it possible to improve the reliability of the semiconductor device.

[0028] In addition, when the channel layer 7 has the same p-type as the body region 3, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 9, a channel is formed in the same manner as in the body region 3, forming a normally-off semiconductor switching element. On the other hand, when the channel layer 7 has n-type and the thickness of the channel layer 7 is thin, or when the n-type impurity concentration of the channel layer 7 is low, a depletion layer due to a pn junction formed by the channel layer 7 and the body region 3 extends to the channel layer 7. Therefore, when the channel layer 7 has n-type, a channel is formed in the same manner as when the channel layer 7 has p-type, forming a normally-off semiconductor switching element. From the above, whether the channel layer 7 has n-type or p-type, or has no conductivity type, it is possible to perform switching operations similar to those of conventional semiconductor switching elements.

[0029] <Manufacturing method> A method for manufacturing a semiconductor device according to the first embodiment will be described below. First, an n-type epitaxial layer, a part of which becomes the drift layer 2, is formed by epitaxial growth on the upper surface of an n-type semiconductor substrate 1. Then, a body region 3, a source region 4, and a contact region 5 are formed on the upper part of the epitaxial layer by ion implantation. Note that the order of ion implantation for forming the body region 3, the source region 4, and the contact region 5 may be changed as appropriate.

[0030] Next, a trench 6 is formed by etching, penetrating the source region 4, the contact region 5, and the body region 3 to reach the drift layer 2. To etch the trench 6, a silicon oxide film (not shown) is deposited on the upper surfaces of the source region 4 and the contact region 5, and the silicon oxide film is patterned using photolithography and reactive ion etching. The trench 6 is formed by reactive ion etching using the patterned silicon oxide film as a mask. The depth of the trench 6 is equal to or greater than the depth of the lower part of the body region 3. After the trench 6 is formed, a bottom protection region 12 is formed by ion implantation, and a connection region 13 is formed, for example, by oblique ion implantation, which will be described later.

[0031] After removing the silicon oxide film used as a mask in forming the trench 6, a channel layer 7, which is an epitaxial layer, is formed by epitaxial growth on at least a portion of the inner surface of the trench 6 that corresponds to the contact region 5. In the first embodiment, the channel layer 7 is formed so as to cover the entire inner surface of the trench 6 including the side and bottom surfaces, and a portion of the upper surfaces of the source region 4 and the contact region 5. When the thickness of the channel layer 7 between the contact region 5 and the gate insulating film 8 is 500 nm or less, the characteristics of the semiconductor device can be improved and the time required to form the channel layer 7 can be shortened.

[0032] Next, annealing is performed using a heat treatment device (not shown) to activate the impurities ion-implanted in the above process. Then, an insulating film and a conductive member are formed on the top surface of the structure obtained so far. Then, by patterning or etch-back, a gate insulating film 8 is formed from the insulating film, and a gate electrode 9 is formed from the conductive member.

[0033] Then, an insulating film covering the gate electrode 9 is formed on the upper surface of the structure obtained thus far, and the insulating film is patterned to form an interlayer insulating film 10 having contact holes exposing the source region 4 and the contact region 5.

[0034] Next, a source electrode 11 electrically connected to the source region 4 and the contact region 5 is formed. As a method for forming the source electrode 11, for example, first, a metal film mainly composed of Ni is formed on the interlayer insulating film 10 and on the source region 4 and the contact region 5 in the contact hole. Then, the metal of the metal film reacts with the silicon carbide of the source region 4 and the contact region 5 by heat treatment to form a silicide film 11a which is an ohmic electrode. Then, the unreacted metal film remaining on the interlayer insulating film 10 and the like is removed by wet etching. Then, an electrode member such as an Al alloy is deposited on the interlayer insulating film 10 and the silicide film 11a to form the source electrode 11 including the silicide film 11a.

[0035] Finally, an electrode member such as an Al alloy is deposited on the lower surface of the semiconductor substrate 1 to form a drain electrode 14. With the above steps, the semiconductor device according to the first embodiment is completed.

[0036] <Summary of the first embodiment> According to the first embodiment as described above, the channel layer 7 having fewer crystal defects than the contact region 5 is provided on at least a portion of the inner surface of the trench 6 corresponding to the contact region 5. This configuration can prevent the electric field of the gate voltage from concentrating locally on the interface between the crystal defect portion of the contact region 5 and the gate insulating film 8, and prevent defects caused by the crystal defect portion from occurring in the gate insulating film 8. This can improve the reliability of the semiconductor device. Furthermore, the gate voltage during the on-operation of the semiconductor device can be increased by improving the reliability of the semiconductor device, and the channel resistance can be reduced by mitigating the electric field strength in the vertical direction of the two-dimensional gas in the channel.

[0037] In the first embodiment, the channel layer 7, which has fewer crystal defects than the body region 3, is provided on the inner surface of the trench 6 in a portion corresponding to the contact region 5 and the body region 3. With this configuration, the reliability of the semiconductor device can be further improved.

[0038] Moreover, in the first embodiment, the channel layer 7 covers a part of the upper surface of the contact region 5. With such a configuration, it is possible to suppress the leakage current.

[0039] In addition, the recovery of crystal defects when a silicon carbide semiconductor is heated is smaller than the recovery of crystal defects when silicon is heated. Therefore, when the body region 3 and the contact region 5 contain silicon carbide as in the present embodiment 1, the number of crystal defects in the body region 3 and the contact region 5 increases, so that providing the channel layer 7 is particularly effective.

[0040] <Embodiment 2> In the second embodiment, after forming an epitaxial layer on the inner surface of the trench 6, n-type or p-type impurities are implanted into the side surface of the epitaxial layer by one or more oblique ion implantations to form the channel layer 7. In the oblique ion implantation, ion implantation is performed in a state where the semiconductor substrate 1 is tilted so that the side surface of the epitaxial layer in the trench 6 faces the ion implantation direction of the ion implantation device. By performing the oblique ion implantation to form the channel layer 7 under conditions where the impurity concentration of the channel layer 7 is one order of magnitude lower than the impurity concentration of the contact region 5, the channel layer 7 has fewer crystal defects than the contact region 5.

[0041] By performing patterning by photolithography, an impurity may be implanted into a portion of the side surface of the channel layer 7, or different impurities may be implanted into multiple portions of the side surface of the channel layer 7.

[0042] 4, in the A-A' cross section including the source region 4, the channel layer 7 may be formed by implanting n-type impurities into the side surface of the epitaxial layer 7a in the trench 6. With this configuration, the JFET resistance between the body region 3 and the bottom protection region 12 can be reduced.

[0043] 5, in the B-B' cross section including the contact region 5, the channel layer 7 may be formed by implanting p-type impurities into the side surface of the epitaxial layer 7a in the trench 6. With this configuration, the body region 3 and the bottom protection region 12 are electrically connected to each other, thereby improving the switching operation of the semiconductor device.

[0044] Also, a portion having n-type may be formed by ion-implanting both a p-type impurity and an n-type impurity having a higher dose than the p-type impurity. Similarly, a portion having p-type may be formed by ion-implanting both an n-type impurity and a p-type impurity having a higher dose than the n-type impurity.

[0045] <Summary of the second embodiment> According to the second embodiment as described above, the channel layer 7 is formed by implanting n-type or p-type impurities into the side surface of the epitaxial layer 7a in the trench 6 by one or more oblique ion implantations. The process variation of the channel layer 7 formed by the oblique ion implantation can be reduced more than the process variation of the channel layer 7 formed without the oblique ion implantation, so that the variation of the threshold voltage and the on-resistance of the semiconductor device can be reduced. In addition, the reduction of the JFET resistance and the improvement of the switching operation can be expected.

[0046] <Embodiment 3> In the second embodiment, the channel layer 7 is formed by implanting n-type or p-type impurities into the side surface of the epitaxial layer 7a in the trench 6 by one or more oblique ion implantations. In the third embodiment, the one or more oblique ion implantations are multiple oblique ion implantations performed at different ion implantation angles.

[0047] For example, as shown in FIG. 6, in the A-A' cross section including the source region 4, n-type impurities with a low impurity concentration may be implanted in the side of the epitaxial layer 7a from the entrance side of the trench 6 to the bottom side. Then, n-type impurities with a high impurity concentration may be implanted in the portion 7b of the side of the epitaxial layer 7a on the entrance side of the trench 6 to form a channel layer 7 including the portions 7b and 7c. According to this configuration, the portion 7b of the channel layer 7 adjacent to the source region 4 can achieve the same function as the source region 4, so that the current path can be widened, and as a result, the on-resistance can be reduced. Also, a depletion layer can be formed in the portion 7c of the channel layer 7 adjacent to the body region 3, and a normally-off semiconductor switching element can be formed.

[0048] For example, as shown in FIG. 7, in the B-B' cross section including the contact region 5, p-type impurities may be implanted into the side of the epitaxial layer 7a from the entrance side of the trench 6 to the bottom side. Then, n-type impurities having a high impurity concentration may be implanted into the portion 7d of the side of the epitaxial layer 7a on the entrance side of the trench 6 to form the channel layer 7 including the portions 7d and 7e. According to this configuration, the portion 7d of the channel layer 7 adjacent to the contact region 5 can realize the same function as the source region 4, so that the current path can be widened, and as a result, the on-resistance can be reduced. In addition, the portion 7e of the channel layer 7 adjacent to the body region 3 electrically connects the body region 3 and the bottom protection region 12, so that the switching operation of the semiconductor device can be improved.

[0049] <Summary of the Third Embodiment> According to the third embodiment as described above, the one or more oblique ion implantations are multiple oblique ion implantations performed at different ion implantation angles. This configuration can increase the degree of freedom in designing the channel layer 7. In addition, for example, the portions 7b and 7d of the channel layer 7 on the inlet side of the trench 6 can achieve the same function as the source region 4, so that the current path can be widened, and as a result, the on-resistance can be reduced.

[0050] <Modification> In the above description, the semiconductor device is a MOSFET, but may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting - IGBT). For example, in the B-B' cross section including the contact region 5, when the channel layer 7 is formed by injecting p-type impurities, the channel layer 7 has a function similar to that of the connection region 13. For this reason, although both the channel layer 7 and the connection region 13 are provided in the second and third embodiments, the connection region 13 may not be provided. In addition, when both the channel layer 7 and the connection region 13 are provided as in the second and third embodiments, the channel layer 7 and the connection region 13 may be formed simultaneously.

[0051] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0052] Various aspects of the present disclosure are summarized below as appendices.

[0053] (Appendix 1) a drift layer having a first conductivity type; a source region having the first conductivity type, the source region being selectively provided above the drift layer; a contact region having a second conductivity type, the contact region being selectively provided above the drift layer; a body region having the second conductivity type, the body region being provided between the drift layer and each of the source region and the contact region, and having a lower impurity concentration of the second conductivity type than the contact region; a channel layer provided on at least a portion of an inner surface of a trench that penetrates the source region, the contact region, and the body region to reach the drift layer, the channel layer having fewer crystal defects than the contact region; a gate insulating film provided along the inner surface of the trench; a gate electrode provided on the gate insulating film in the trench; A semiconductor device comprising:

[0054] (Appendix 2) 2. The semiconductor device according to claim 1, The contact region has a stripe shape in a plan view.

[0055] (Appendix 3) The semiconductor device according to claim 1 or 2, The semiconductor device, wherein the body region and the contact region include silicon carbide.

[0056] (Appendix 4) A semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, a thickness of the channel layer between the contact region and the gate insulating film is 500 nm or less.

[0057] (Appendix 5) A semiconductor device according to any one of claims 1 to 4, The channel layer has the first conductivity type or the second conductivity type.

[0058] (Appendix 6) A semiconductor device according to any one of claims 1 to 5, The channel layer covers a portion of an upper surface of the contact region.

[0059] (Appendix 7) forming, by ion implantation, a source region having a first conductivity type, which is selectively provided above a drift layer having a first conductivity type, a contact region having a second conductivity type, which is selectively provided above the drift layer, and a body region having the second conductivity type, which is provided between the drift layer and each of the source region and the contact region, and has a lower impurity concentration of the second conductivity type than the contact region; forming a trench penetrating the source region, the contact region, and the body region to reach the drift layer; forming a channel layer having fewer crystal defects than the contact region on at least a portion of an inner surface of the trench that corresponds to the contact region; forming a gate insulating film along the inner surface of the trench; forming a gate electrode on the gate insulating film in the trench; A manufacturing method of a semiconductor device comprising:

[0060] (Appendix 8) A method for manufacturing the semiconductor device according to claim 7, comprising the steps of: The step of forming the channel layer includes: forming an epitaxial layer on the interior surface of the trench; implanting impurities of the first conductivity type or the second conductivity type into the sidewall of the epitaxial layer by one or more tilted ion implantations; A method for manufacturing a semiconductor device comprising the steps of:

[0061] (Appendix 9) A method for manufacturing the semiconductor device according to claim 8, comprising the steps of: The one or more tilted ion implantations are a plurality of tilted ion implantations performed at different ion implantation angles. [Explanation of symbols]

[0062] 2 drift layer, 3 body region, 4 source region, 5 contact region, 6 trench, 7 channel layer, 7a epitaxial layer, 8 gate insulating film, 9 gate electrode.

Claims

1. a drift layer having a first conductivity type; a source region having the first conductivity type, the source region being selectively provided above the drift layer; a contact region having a second conductivity type, the contact region being selectively provided above the drift layer; a body region having the second conductivity type, the body region being provided between the drift layer and each of the source region and the contact region, and having a lower impurity concentration of the second conductivity type than the contact region; a channel layer provided on at least a portion of an inner surface of a trench that penetrates the source region, the contact region, and the body region to reach the drift layer, the channel layer having fewer crystal defects than the contact region; a gate insulating film provided along the inner surface of the trench; a gate electrode provided on the gate insulating film in the trench; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, The contact region has a stripe shape in a plan view.

3. 3. The semiconductor device according to claim 1, The body region and the contact region include silicon carbide.

4. 3. The semiconductor device according to claim 1, The semiconductor device, wherein the thickness of the channel layer between the contact region and the gate insulating film is 500 nm or less.

5. 3. The semiconductor device according to claim 1, The channel layer has the first conductivity type or the second conductivity type.

6. 3. The semiconductor device according to claim 1, The channel layer covers a portion of an upper surface of the contact region.

7. forming, by ion implantation, a source region having a first conductivity type, which is selectively provided above a drift layer having a first conductivity type, a contact region having a second conductivity type, which is selectively provided above the drift layer, and a body region having the second conductivity type, which is provided between the drift layer and each of the source region and the contact region, and has a lower impurity concentration of the second conductivity type than the contact region; forming a trench penetrating the source region, the contact region, and the body region to reach the drift layer; forming a channel layer having fewer crystal defects than the contact region on at least a portion of an inner surface of the trench that corresponds to the contact region; forming a gate insulating film along the inner surface of the trench; forming a gate electrode on the gate insulating film in the trench; A manufacturing method of a semiconductor device comprising:

8. 8. The method for manufacturing a semiconductor device according to claim 7, The step of forming the channel layer includes: forming an epitaxial layer on the interior surface of the trench; implanting impurities of the first conductivity type or the second conductivity type into the side of the epitaxial layer by one or more tilted ion implantations; A method for manufacturing a semiconductor device comprising the steps of:

9. 9. The method of manufacturing a semiconductor device according to claim 8, The one or more tilted ion implantations are a plurality of tilted ion implantations performed at different ion implantation angles.

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