Display device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- JAPAN DISPLAY INC
- Filing Date
- 2023-08-09
- Publication Date
- 2026-06-16
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
[Technical field]
[0001] The present embodiment relates to a display device. [Background technology]
[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. For this type of display device, technology that enables improvement of yield and reliability is required. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]
[0004] An object of the present invention is to provide a display device that can achieve improved yield or improved reliability. [Means for solving the problem]
[0005] A display device according to one embodiment includes a substrate having a display region for displaying an image and a peripheral region around the display region, a plurality of display elements each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage, the plurality of display elements being arranged in the display region, a first partition wall arranged in the display region and between adjacent display elements, a first dam portion arranged in the peripheral region, protruding above the substrate and surrounding the display region, and a second partition wall overlapping at least a portion of the first dam portion in a plan view. The first partition wall and the second partition wall each include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. [Brief description of the drawings]
[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of the display device for explaining the structure of the peripheral region. [Diagram 5] FIG. 5 is an enlarged plan view of a portion of the peripheral region. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along the line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an enlarged portion of FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of a display device according to a first modified example. [Figure 9] FIG. 9 is a schematic cross-sectional view of a display device according to a second modified example. [Figure 10] FIG. 10 is a schematic cross-sectional view of a display device according to a third modified example. [Figure 11] FIG. 11 is a schematic plan view of a display device according to a fourth modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.
[0008] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of a plane that includes the X-direction and the Y-direction. Moreover, viewing various elements parallel to the Z-direction is called planar view.
[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.
[0010] 1 is a diagram showing an example of the configuration of a display device DSP according to an embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.
[0011] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to being circular, and may be other shapes such as rectangular, square, or elliptical.
[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.
[0013] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board that supplies voltages and signals for driving the display device DSP is connected.
[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.
[0015] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example of Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.
[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.
[0017] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.
[0018] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.
[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and a column in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG.
[0020] A rib 5 is disposed in the display area DA. The rib 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio.
[0021] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.
[0022] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib 5 surrounds each of these display elements DE1, DE2, and DE3.
[0023] A conductive partition wall 6A (first partition wall) is disposed on the rib 5. The partition wall 6A entirely overlaps with the rib 5 and has the same planar shape as the rib 5. That is, the partition wall 6A has openings in each of the subpixels SP1, SP2, and SP3. From another perspective, the rib 5 and the partition wall 6A are lattice-shaped in plan view and surround each of the subpixels SP1, SP2, and SP3. The partition wall 6A serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.
[0024] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes unevenness caused by the circuit layer 11.
[0025] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.
[0026] The partition wall 6A includes a conductive lower portion 61 disposed on the rib 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6A is called an overhang shape.
[0027] In the example of FIG. 3, the lower part 61 has a bottom layer 63 arranged on the rib 5 and a shaft layer 64 arranged on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.
[0028] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6A.
[0029] The display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. The display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. The display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.
[0030] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.
[0031] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located around the partition wall 6A (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located around the partition wall 6A (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located around the partition wall 6A (a part that constitutes the display element DE3).
[0032] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6A around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6A around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6A around the subpixel SP3.
[0033] 3, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6A. Also, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6A.
[0034] The sealing layers SE11, SE12, and SE13 (first sealing layer) are covered with a resin layer RS1 (first resin layer). The resin layer RS1 is covered with a sealing layer SE2 (second sealing layer). The sealing layer SE2 is covered with a resin layer RS2 (second resin layer). The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously at least over the entire display area DA, and a part of them extends into the peripheral area SA.
[0035] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).
[0036] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.
[0037] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).
[0038] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.
[0039] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of light-emitting layers.
[0040] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.
[0041] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.
[0042] For example, the upper portion 62 of the partition wall 6A has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. The metal material forming the lower layer may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the upper layer may be, for example, ITO or IZO. The upper portion 62 may have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.
[0043] A common voltage is supplied to the partition 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.
[0044] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.
[0045] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.
[0046] 4 is a schematic plan view of the display device DSP for explaining the structure of the peripheral area SA. The display device DSP includes a dam structure DS arranged in the peripheral area SA. In the example of FIG. 4, the dam structure DS includes annular dam portions DM1, DM2, DM3, and DM4.
[0047] The dam portion DM1 surrounds the display area DA. The dam portion DM2 surrounds the dam portion DM1. The dam portion DM3 surrounds the dam portion DM2. The dam portion DM4 surrounds the dam portion DM3.
[0048] Each of the dam portions DM1, DM2, DM3, and DM4 has an arc-shaped curved portion CV and straight portions ST connected to both ends of the curved portion CV. The curved portion CV is, for example, concentric with the display area DA. The straight portions ST are, for example, located between the display area DA and the terminal portion T, and extend parallel to the X direction.
[0049] The shapes of the dam parts DM1, DM2, DM3, and DM4 are not limited to the example in Fig. 4. The number of dam parts included in the dam structure DS may be three or less, or may be five or more.
[0050] 5 is an enlarged plan view of a portion of the peripheral area SA. In addition to the dam structure DS, partition walls 6B, 6C, and 6D are further arranged in the peripheral area SA. The partition wall 6B overlaps at least a portion of the dam portion DM1 in a plan view. The partition wall 6C overlaps at least a portion of the dam portion DM3 in a plan view. The partition wall 6D overlaps at least a portion of the dam portion DM4 in a plan view. The dam portions DM3 and DM4 are examples of the first and second dam portions, respectively, and the partition walls 6C and 6D are examples of the second and third partition walls, respectively.
[0051] The partition walls 6B, 6C, and 6D are formed by the same process as the partition wall 6A shown in Figures 2 and 3, and have the same structure as the partition wall 6A. That is, the partition walls 6B, 6C, and 6D have a lower portion 61 and an upper portion 62. Furthermore, the lower portion 61 of the partition walls 6B, 6C, and 6D has a bottom layer 63 and an axis layer 64.
[0052] For example, the partition walls 6B, 6C, and 6D, together with the dam portions DM1, DM2, DM3, and DM4, surround the display area DA. The partition wall 6B is wider than the partition walls 6C and 6D, and is connected to the above-mentioned partition wall 6A. That is, a common voltage is applied to the partition wall 6B.
[0053] Both of the partition walls 6C and 6D are spaced apart from the partition wall 6B. A dam portion DM2 is interposed between the partition walls 6B and 6C. In the example of Fig. 5, the dam portion DM2 is not covered by any of the partition walls 6B, 6C, and 6D.
[0054] The dam portion DM3 has an inner surface IF1 on the display area DA side (left side in the figure) and an outer surface OF1 opposite the inner surface IF1. The dam portion DM4 has an inner surface IF2 on the display area DA side and an outer surface OF2 opposite the inner surface IF2.
[0055] 5, the partition 6C overlaps with the outer surface OF1 but does not overlap with the inner surface IF1. The partition 6D is wider than the partition 6C and overlaps with both the inner surface IF2 and the outer surface OF2.
[0056] FIG. 6 is a schematic cross-sectional view of the display device DSP taken along the line VI-VI in FIG. 5. FIG. 7 is a schematic cross-sectional view enlarging the vicinity of the dam parts DM3 and DM4 in FIG. 6. The circuit layer 11 shown in FIG. 3 has inorganic insulating layers 31, 32, and 33 formed of an inorganic insulating material, an organic insulating layer 34 formed of an organic insulating material, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is disposed on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is disposed on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is disposed on the organic insulating layer 34 and is covered by the organic insulating layer 12.
[0057] Dam portions DM1, DM2, DM3, and DM4 all protrude above the substrate 10. In the example of Fig. 6, dam portion DM1 is formed of organic insulating layers 12 and 34. Dam portions DM2, DM3, and DM4 are also formed of organic insulating layers 12 and 34. That is, in this embodiment, dam portions DM1, DM2, DM3, and DM4 are mainly formed of an organic insulating material.
[0058] A power supply line PW to which a common voltage is applied is disposed below the dam portions DM1 and DM2. The power supply line PW has a first wiring W1 formed by a metal layer 42 and a second wiring W2 formed by a metal layer 43.
[0059] 6, the first wiring W1 and the second wiring W2 are in contact with each other at a contact portion CN1 located between the dam portions DM1 and DM2. In each of the dam portions DM1 and DM2, a portion of the second wiring W2 is located between the organic insulating layers 12 and 34.
[0060] The peripheral area SA further includes a conductive relay layer RL and an inorganic insulating layer 7. The relay layer RL is formed of the same material and process as the above-mentioned lower electrodes LE1, LE2, and LE3. The inorganic insulating layer 7 is formed of the same inorganic insulating material and process as the above-mentioned rib 5.
[0061] The relay layer RL is located closer to the display area DA side (left side in the figure) than the dam portion DM1, and covers the organic insulating layer 12. The relay layer RL is in contact with the second wiring W2 of the power supply line PW at the contact portion CN2 located near the dam portion DM1. The inorganic insulating layer 7 continuously covers the relay layer RL and the dam portions DM1, DM2, DM3, and DM4.
[0062] The above-mentioned partition walls 6B, 6C, and 6D are disposed on the inorganic insulating layer 7. In the example of FIG. 6, the end E1 of the partition wall 6B is located between the dam portions DM1 and DM2. The partition wall 6B contacts the relay layer RL at the contact portion CN3. The inorganic insulating layer 7 is open at the contact portion CN3. The contact portion CN3 is located, for example, between the contact portion CN2 and the display area DA.
[0063] One end of the partition wall 6C is located above the upper surface of the dam member DM3, and the other end is located between the dam members DM3 and DM4. That is, the partition wall 6C faces the outer side surface OF1 of the dam member DM3 via the inorganic insulating layer 7, but does not face the inner side surface IF1 of the dam member DM3.
[0064] One end of the partition wall 6D is located between the dam portions DM3 and DM4, and the other end is located outside the dam portion DM4. That is, the partition wall 6D faces both the inner surface IF2 and the outer surface OF2 of the dam portion DM4 with the inorganic insulating layer 7 interposed therebetween.
[0065] The partition 6B is covered by a laminated film FL. The laminated film FL is covered by a sealing layer SE1. The laminated film FL includes an organic layer OR, an upper electrode UE covering the organic layer OR, and a cap layer CP covering the upper electrode UE. The partitions 6C and 6D are separated from each other by a gap G. The gap G is located in a valley between the dam portions DM3 and DM4.
[0066] The laminated film FL is any one of the laminated films FL1, FL2, and FL3 shown in FIG. 3. The sealing layer SE1 is any one of the sealing layers SE11, SE12, and SE13 shown in FIG. 3. When the laminated film FL is the laminated film FL1, the organic layer OR, the upper electrode UE, and the cap layer CP correspond to the organic layer OR1, the upper electrode UE1, and the cap layer CP1, respectively. When the laminated film FL is the laminated film FL2, the organic layer OR, the upper electrode UE, and the cap layer CP correspond to the organic layer OR2, the upper electrode UE2, and the cap layer CP2, respectively. When the laminated film FL is the laminated film FL3, the organic layer OR, the upper electrode UE, and the cap layer CP correspond to the organic layer OR3, the upper electrode UE3, and the cap layer CP3, respectively.
[0067] When manufacturing the display device DSP, the laminated films FL1, FL2, and FL3 are formed in sequence by a photolithography process. The sealing layers SE11, SE12, and SE13 are also patterned together with the laminated films FL1, FL2, and FL3 by these photolithography processes. The organic layers OR1, OR2, and OR3, the upper electrodes UE1, UE2, and UE3, and the cap layers CP1, CP2, and CP3 are formed by deposition. In addition, the sealing layers SE11, SE12, and SE13 are formed by CVD (Chemical Vapor Deposition).
[0068] For example, the laminated film FL may be formed first or last among the laminated films FL1, FL2, and FL3, and the sealing layer SE1 may be formed first or last among the sealing layers SE11, SE12, and SE13.
[0069] 6, the end E2 of the laminated film FL and the end E3 of the sealing layer SE1 are located above the dam portion DM3. Moreover, these ends E2 and E3 are located above the partition wall 6C.
[0070] As shown in FIG. 7, the partition walls 6C and 6D include a lower portion 61 and an upper portion 62 similar to the partition wall 6A. The lower portion 61 of the partition walls 6C and 6D includes a bottom layer 63 and an axis layer 64. In each of the partition walls 6C and 6D, the upper portion 62 protrudes from the side surface of the axis layer 64. The same is true for the partition wall 6B. That is, the ends of the partition walls 6B, 6C, and 6D are overhanging like the partition wall 6A shown in FIG. 3. Therefore, as shown in FIGS. 6 and 7, the stacked film FL is divided near the ends of the partition walls 6B and 6C. The sealing layer SE1 continuously covers the divided stacked film FL.
[0071] Above the sealing layer SE1, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Fig. 3 are arranged. The resin layer RS1 covers the sealing layer SE1. The dam portions DM1 and DM2 serve to hold back the resin layer RS1 before it hardens during the manufacture of the display device DSP.
[0072] 6, the end E4 of the resin layer RS1 is located between the display area DA and the partition wall 6C. More specifically, the end E4 is located above the dam portion DM2. However, the position of the end E4 is not limited to this example.
[0073] The sealing layer SE2 covers the end E4 of the resin layer RS1. The sealing layer SE2 is in contact with the sealing layer SE1 in a region outside the end E4 (to the right in the figure). In the example of Fig. 6, the end E5 of the sealing layer SE2 is located above the dam portion DM4. The sealing layer SE2 covers the end E2 of the stacked film FL, the end E3 of the sealing layer SE1, a part of the partition wall 6C, and a part of the partition wall 6D.
[0074] The dam portions DM3 and DM4 serve to hold back the resin layer RS2 before hardening during the manufacture of the display device DSP. In this embodiment, the end E6 of the resin layer RS2 is located between the end E4 of the resin layer RS1 and the end E5 of the sealing layer SE2. More specifically, the end E6 is located above the dam portion DM4. The resin layer RS2 covers the sealing layer SE2 above the dam portion DM3. However, the position of the end E6 is not limited to this example. The resin layer RS2 covers the sealing layer SE2 above the dam portion DM3 and the partition wall 6C.
[0075] The laminated film FL formed by deposition may have poor adhesion to the base. Therefore, there is a possibility that the laminated film FL and the sealing layer SE1 covering it may peel off during the manufacture of the display device DSP. Such peeling is likely to occur on the upper surfaces of the dam portions DM1, DM2, DM3, and DM4.
[0076] In contrast, in this embodiment, the partition wall 6C is disposed above the dam portion DM3. Since the adhesion between the laminated film FL and the partition wall 6C is relatively excellent, peeling of the laminated film FL can be suppressed. In addition, since the end of the partition wall 6C is in an overhanging shape, the laminated film FL is divided during deposition. As a result, the laminated film FL is divided into small pieces, which also suppresses peeling of the laminated film FL.
[0077] Before patterning the laminated film FL, the laminated film FL (any of the laminated films FL1, FL2, and FL3) is formed over the entire substrate 10. Therefore, the laminated film FL is temporarily present above the dam portion DM4. In this regard, in the present embodiment, a partition wall 6D is disposed above the dam portion DM4. This makes it possible to suppress peeling of the laminated film FL above the dam portion DM4 as well.
[0078] In addition, in this embodiment, the wall for holding back the uncured resin layer RS2 is higher than when the inorganic insulating layer 7 and the partition walls 6C and 6D are not disposed above the dam portions DM3 and DM4, and this makes it possible to prevent the resin layer RS2 from overflowing outside the dam portions DM3 and DM4.
[0079] In this embodiment, the resin layer RS1 is surrounded by the sealing layers SE1 and SE2. This prevents moisture from penetrating into the resin layer RS1. The end E4 of the resin layer RS1 is located above the dam portion DM2. In this case, if a partition is placed above the dam portion DM2 and this partition causes a shape defect in the sealing layers SE1 and SE2, the sealing of the resin layer RS1 may be incomplete. In contrast, in this embodiment, since no partition is placed near the dam portion DM2, the sealing layers SE1 and SE2 can be formed well. As a result, the penetration of moisture into the resin layer RS1 can be effectively prevented.
[0080] In this embodiment, the laminated film FL is divided at the ends of the partition walls 6B and 6C, thereby blocking the path of moisture infiltration through the laminated film FL.
[0081] In addition, in this embodiment, the partitions 6C, 6D are spaced apart via a gap G. If the partitions 6C, 6D were connected, a floating conductive layer with a large area would be disposed in the peripheral region SA. In this case, there is a possibility that electrostatic breakdown would occur due to the conductive layer. In contrast, if the partitions 6C, 6D are spaced apart as in this embodiment, the occurrence of electrostatic breakdown can be suppressed.
[0082] In this way, according to the present embodiment, peeling of the laminated film FL can be suppressed, and the yield of the display device DSP can be improved. In addition, infiltration of moisture and electrostatic breakdown into the display device DSP can be suppressed, and the reliability of the display device DSP can be improved.
[0083] The configuration disclosed in this embodiment can be modified in various ways. Some modified examples are disclosed below.
[0084] 8 is a schematic cross-sectional view of a display device DSP according to a first modification. In the example of this figure, the end E1 of the partition wall 6B is located between the display area DA and the dam portion DM1. More specifically, the end E1 is located between the display area DA and the contact portion CN2.
[0085] In the example of Fig. 6, the end E1 is located between the dam portions DM1 and DM2. In this case, if the distance between the dam portions DM1 and DM2 is narrow, the resist placed during patterning of the inorganic insulating layer 7 may have a defective shape. That is, the resist is unlikely to be filled below the upper portion 62 at the end of the partition wall 6B. With the configuration of Fig. 8, the above-mentioned defective shape of the resist can be suppressed, and the inorganic insulating layer 7 can be formed satisfactorily.
[0086] 6, the end E2 of the laminated film FL and the end E3 of the sealing layer SE1 are located above the dam portion DM3. In this configuration, for example, if the end E6 of the resin layer RS2 does not reach the dam portion DM4 and is blocked by the dam portion DM3, and the sealing layer SE2 is also formed only up to the vicinity of the dam portion DM3, the end E2 may be exposed to the atmosphere. In this case, a moisture path may be formed that runs from the end E2 through the laminated film FL toward the display area DA.
[0087] 8, the ends E2 and E3 are located between the display area DA and the partition wall 6C. More specifically, the ends E2 and E3 are located between the display area DA and the end E4 of the resin layer RS1, and are covered by the resin layer RS1. With this configuration, the end E2 of the laminated film FL is not exposed from the resin layer RS2, regardless of the position of the end E6 of the resin layer RS2. Therefore, moisture intrusion through the laminated film FL is suppressed, and the reliability of the display device DSP can be improved.
[0088] 9 is a schematic cross-sectional view of a display device DSP according to a second modification. In the example of this figure, one end of the partition wall 6D is located above the dam part DM4, and the other end is located outside the dam part DM4 (on the right side in the figure). That is, the partition wall 6D faces the outer side surface OF2 of the dam part DM4 via the inorganic insulating layer 7, but does not face the inner side surface IF2.
[0089] 10 is a schematic cross-sectional view of a display device DSP according to a third modified example. In the example of this figure, one end of the partition wall 6D is located between the dam parts DM3 and DM4, and the other end is located above the dam part DM4. That is, the partition wall 6D faces the inner side surface IF2 of the dam part DM4 via the inorganic insulating layer 7, but does not face the outer side surface OF2. With this configuration, the partition wall 6D is not disposed outside the dam part DM4 (on the right side in the figure), so that it is possible to narrow the area outside the dam part DM4.
[0090] 11 is a schematic plan view of a display device DSP according to a fourth modification. In the example of this figure, the substrate 10, the display area DA, and the dam parts DM1, DM2, DM3, and DM4 are rectangular. In this way, even if the substrate 10 and the display area DA are not circular, the configurations shown in FIGS. 6 to 10 can be applied to the peripheral area SA.
[0091] All display devices that can be implemented by those skilled in the art through appropriate design modifications based on the display devices described above as the embodiments of the present invention belong to the scope of the present invention as long as they include the gist of the present invention.
[0092] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of each of the above-mentioned embodiments, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.
[0093] Furthermore, with regard to other effects and advantages brought about by the aspects described in each of the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately conceived by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]
[0094] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...sub-pixel, DE1, DE2, DE3...display element, LE1, LE2, LE3...lower electrode, OR, OR1, OR2, OR3...organic layer, UE, UE1, UE2, UE3...upper electrode, SE1, SE11, SE12, SE13, SE2...sealing layer, DM1, DM2, DM3, DM4...dam portion, RS1, RS2...resin layer, 5...rib, 6A, 6B, 6C, 6D...partition wall, 61...lower part, 62...upper part.
Claims
1. A substrate having a display area for displaying an image and a peripheral area surrounding the display area, A plurality of display elements are arranged in the display area, each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode that emits light in response to the application of a voltage. A first partition wall is arranged in the display area and between adjacent display elements, The first dam portion is arranged in the peripheral region, protruding above the substrate and surrounding the display area, A second bulkhead overlaps with at least a portion of the first dam section in a plan view, Equipped with, The first partition and the second partition each include a conductive lower portion and an upper portion having an end protruding from the side surface of the lower portion. Display device.
2. The first dam section is formed of an organic insulating material. The display device according to claim 1.
3. It further comprises an inorganic insulating layer made of an inorganic insulating material and located below the second partition wall, The inorganic insulating layer covers the first dam section. The display device according to claim 2.
4. The laminated film further comprises the organic layer and the upper electrode, and includes a first sealing layer covering the laminated film. A portion of the laminated film and the first sealing layer is arranged in the peripheral region. The display device according to claim 1.
5. The first sealing layer further comprises a first resin layer covering the first sealing layer, The end of the first resin layer is located between the display area and the second partition wall. The display device according to claim 4.
6. The ends of the laminated film and the first sealing layer are located between the display area and the second partition wall and are covered by the first resin layer. The display device according to claim 5.
7. The invention further comprises a second sealing layer covering the first resin layer, The second sealing layer is in contact with the first sealing layer in a region outside the edge of the first resin layer. The display device according to claim 5.
8. The invention further comprises a second resin layer covering the second sealing layer, The second resin layer covers the second sealing layer above the first dam section. The display device according to claim 7.
9. A second dam section is arranged in the peripheral region, protruding above the substrate and surrounding the display area, A third bulkhead, including the lower and upper parts, which overlaps with at least a portion of the second dam section in a plan view, Furthermore, The display device according to claim 1.