Printed circuit board

Abstract

To provide a printed circuit board in which the cavity can be formed deeper, and the depth can be adjusted easily.SOLUTION: A circuit board includes a first insulating layer 111, a first wiring layer 121 disposed on a first surface S1 of the first insulating layer 111, a second wiring layer 122 disposed on a second surface S2 of the first insulating layer 111, a second insulating layer 112 disposed on the first insulating layer 111, a third wiring layer 123 disposed on a fourth surface S4 of the second insulating layer 112, a first cavity C1 penetrating at least a part of the first insulating layer 111 from the first surface S1 or the second surface S2, and a second cavity C2 penetrating at least a part of the second insulating layer 112 and connected to the first cavity C1. The first and second cavities are different in inclination of a wall surface. The depth of the first cavity C1 is smaller than the thickness of the first insulating layer 111 and is larger than the thickness of each of the first and second wiring layers.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] As the performance of smartphones improves, the thickness of the components mounted on the package substrate increases, but the thickness of the set needs to be reduced or maintained, which requires the formation of a cavity of considerable depth in the package substrate. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objects of the present invention is to provide a printed circuit board in which the depth of a cavity can be easily adjusted, such as by allowing a cavity to be formed deeper. [Means for solving the problem]

[0004] One of several solutions proposed throughout this invention is the use of laser machining and metal etching methods together to form a number of interconnected cavities.

[0005] For example, a printed circuit board according to one example includes a first insulating layer having a first surface and a second surface facing each other in a first direction, a first wiring layer arranged on the first surface side of the first insulating layer, a second wiring layer arranged on the second surface side of the first insulating layer, a second insulating layer having a third surface and a fourth surface facing each other in the first direction and arranged on the first insulating layer such that the third surface is connected to the second surface, a third wiring layer arranged on the fourth surface side of the second insulating layer, a first cavity penetrating at least a portion of the first insulating layer from the first surface or the second surface in the first direction, and a second cavity penetrating at least a portion of the second insulating layer in the first direction and connected to the first cavity, wherein the inclinations of the wall surfaces of the first and second cavities are different, and the depth of the first cavity based on the first direction may be smaller than the thickness of the first insulating layer and larger than each of the thicknesses of the first and second wiring layers.

[0006] For example, a printed circuit board according to one example may include a first insulating layer having a first cavity, first and second wiring layers respectively disposed on an upper surface and a lower surface of the first insulating layer, a second insulating layer disposed on the lower surface of the first insulating layer, covering at least a portion of the second wiring layer, and having a second cavity connected to the first cavity, and a third wiring layer disposed on the lower surface of the second insulating layer, wherein the first cavity is disposed at a level between the first and second wiring layers, and no wiring layer is disposed between the first and second wiring layers. Effect of the Invention

[0007] Among the various advantages of the present invention, one advantage is that it provides a printed circuit board in which the cavity depth can be easily adjusted, for example by forming a deeper cavity. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a printed circuit board. [Figure 4] FIG. 4 is a cross-sectional view that illustrates a modification of the printed circuit board of FIG. [Figure 5a] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5b] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5c] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5d] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5e] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5f] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5g] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5h] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5i] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 5j] 5A to 5C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 3 and FIG. 4. [Figure 6] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 7] FIG. 7 is a cross-sectional view that illustrates a modification of the printed circuit board of FIG. [Figure 8a] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6 and FIG. 7. [Figure 8b] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6 and FIG. 7. [Figure 8c]8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6 and FIG. 7. [Figure 8d] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6 and FIG. 7. [Figure 8e] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6 and FIG. 7. [Figure 8f] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6 and FIG. 7. [Figure 8g] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6 and FIG. 7. [Figure 8h] 8A to 8C are cross-sectional views illustrating steps in a manufacturing process of the printed circuit board of FIG. 6 and FIG. 7. [Figure 9] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 10] FIG. 11 is a cross-sectional view showing a schematic diagram of yet another example of a printed circuit board; [Figure 11] FIG. 11 is a cross-sectional view showing a schematic diagram of yet another example of a printed circuit board; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0010] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0011] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0012] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0013] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0014] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0015] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0016] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0017] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0018] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0019] Printed Circuit Board FIG. 3 is a cross-sectional view that illustrates an example of a printed circuit board.

[0020] Referring to the drawings, the printed circuit board 100A according to an example may include a first insulating layer 111 having a first surface S1 and a second surface S2 facing each other in a first direction, a first wiring layer 121 disposed on the first surface S1 of the first insulating layer 111, a second wiring layer 122 disposed on the second surface S2 of the first insulating layer 111, a second insulating layer 112 having a third surface S3 and a fourth surface S4 facing each other in the first direction and disposed on the first insulating layer 111 such that the third surface S3 is connected to the second surface S2, a third wiring layer 123 disposed on the fourth surface S4 of the second insulating layer 112, a first cavity C1 penetrating a part of the first insulating layer 111 from the second surface S2 in the first direction, and a second cavity C2 penetrating the second insulating layer 112 in the first direction and connected to the first cavity C1. The first and second cavities C1 and C2 may have different inclinations of the walls. With respect to the first direction, the depth of the first cavity C1 may be smaller than the thickness of the first insulating layer 111 and may be larger than each of the thicknesses of the first and second wiring layers 121, 122. In the first direction, the first cavity C1 may be disposed at a level between the first and second wiring layers 121, 122, or no wiring layer may be disposed between the first and second wiring layers 121, 122.

[0021] For example, the first cavity C1 may be formed by etching a metal embedded in the first insulating layer 111, and the second cavity C2 may be formed by laser processing in the second insulating layer 112. Therefore, the first and second cavities C1 and C2 may have different inclinations of the wall surface. For example, the second cavity C2 may have a larger inclination of the wall surface than the first cavity C1. For example, the first cavity C1 may have a substantially vertical wall surface, and the second cavity C2 may have a tapered wall surface in which the width on the side connected to the first cavity C1 in the cross section is smaller than the width on the opposite side. In this case, the first and second cavities C1 and C2 may be connected to each other, so that the overall depth of the cavity can be made deeper, and the depth of the cavity can be easily adjusted. In addition, the second cavity C2 may have a larger average width on the cross section than the first cavity C1. Therefore, the entrance of the cavity can be wider, and as a result, it can be easier to mount components in the cavity. Also, the first cavity C1 can be formed by etching a metal block formed separately from the first and second wiring layers 121 and 122, and therefore can be thinner than the thickness of the first insulating layer 111 but thicker than the thickness of the first and second wiring layers 121 and 122. Also, it can be disposed at a level between the first and second wiring layers 121 and 122. As a result, the first cavity C1 can be formed to have various thicknesses within a meaningful range. Therefore, it can be easier to adjust the depth of the cavity.

[0022] Meanwhile, the printed circuit board 100A according to an example may further include a first resist layer 141 having a fifth surface S5 and a sixth surface S6 facing each other in a first direction, disposed on the second insulating layer 112 such that the fifth surface S5 is connected to the fourth surface S4, and having a first opening h1 exposing at least a part of the third wiring layer 123, and a third cavity C3 penetrating the first resist layer 141 in the first direction and connected to the second cavity C2. The second and third cavities C2 and C3 may have different inclinations of the walls. For example, the third cavity C3 may have a smaller inclination of the walls than the second cavity C2. For example, the third cavity C3 may have a substantially vertical wall, or may have a tapered wall in which the width on the side connected to the second cavity C2 in the cross section is smaller than the width on the opposite side. In this case, the first to third cavities C1, C2, and C3 are connected to each other, so that the overall depth of the cavities can be made deeper, and the cavity depth can be adjusted more easily. Also, the third cavity C3 can have a larger average width on the cross section than the second cavity C2. Therefore, the cavity entrance can be made wider, and as a result, it can be easier to mount components in the cavity. Also, the third cavity C3 can be formed in a process separate from the first and second cavities C1 and C2, so that the cavity depth can be adjusted more easily.

[0023] Meanwhile, the printed circuit board 100A according to an example may further include a first via layer 131 penetrating the first insulating layer 111 in the first direction and connecting at least a portion of each of the first and second wiring layers 121, 122 to each other, and a second via layer 132 penetrating the second insulating layer 112 in the first direction and connecting at least a portion of each of the second and third wiring layers 122, 123 to each other. In addition, the printed circuit board 100A may further include a plurality of build-up insulating layers 113 arranged on the first surface S1 side of the first insulating layer 111, a plurality of build-up wiring layers 121, 124 including the above-mentioned first wiring layer 121, each arranged on or within the plurality of build-up insulating layers 113 in the first direction, and a plurality of build-up via layers 133 each penetrating at least one of the plurality of build-up insulating layers 113 in the first direction. Also, the second resist layer 142 may be disposed on the plurality of build-up insulating layers 113 and having an opening h2 exposing at least a portion of the outermost build-up wiring layer 124, for example, the lowermost build-up wiring layer 124, based on the first direction, among the plurality of build-up wiring layers 121, 124. In this manner, the printed circuit board 100A according to an example may have a multi-layer coreless substrate structure. The bottom surface of the first cavity C1 may be disposed at a level between the first surface S1 and the second surface S2 of the first insulating layer 111.

[0024] The components of the example printed circuit board 100A are described in more detail below with reference to the drawings.

[0025] The first and second insulating layers 111 and 112 and the plurality of build-up insulating layers 113 may each include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or a glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymeric materials may be used. The first and second insulating layers 111 and 112 and the plurality of build-up insulating layers 113 may include the same insulating material or may include different insulating materials. They may have a boundary with each other, or may be integrated to the extent that the boundary is unclear. Based on the first direction, the first insulating layer 111 may be thicker than the second insulating layer 112, but is not limited thereto.

[0026] The first to third wiring layers 121, 122, 123 and the plurality of build-up wiring layers 121, 124 may each include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. The first to third wiring layers 121, 122, 123 and the plurality of build-up wiring layers 121, 124 may each perform various functions according to the design. For example, they may include a signal pattern, a power pattern, a ground pattern, and the like. These patterns may each have various forms, such as a line, a plane, and a pad. The first to third wiring layers 121, 122, 123 and the plurality of build-up wiring layers 121, 124 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). It may include a sputtering layer instead of the electroless plating layer (or chemical copper), or it may include both the electroless plating layer (or chemical copper) and the sputtering layer, if necessary.

[0027] Each of the first and second via layers 131 and 132 and the plurality of build-up via layers 133 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but is not limited thereto. Each of the first and second via layers 131 and 132 and the plurality of build-up via layers 133 may include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along a wall surface of a via hole. The microvia may be arranged in a stacked type and / or staggered type. The microvias of the first and second via layers 131 and 132 and the plurality of build-up via layers 133 may perform various functions depending on the design of the layer. For example, the vias may include ground vias, power vias, signal vias, etc. The third and fourth via layers 133, 134 may include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively. A sputtering layer may be formed instead of the electroless plating layer, and both may be included. The microvias of the first and second via layers 131, 132 may have tapered shapes in the same direction as each other. The microvias of the multiple build-up via layers 133 may have tapered shapes in the same direction as each other. The microvias of the first and second via layers 131, 132 and the multiple build-up via layers 133 may have tapered shapes in opposite directions to each other.

[0028] The first and second resist layers 141 and 142 may each include, but are not limited to, a liquid or film type solder resist, and may also include other types of insulating materials such as ABF, etc. The first and second resist layers 141 and 142 may have first and second openings h1 and h2, respectively, and a surface treatment layer may be formed on the patterns exposed through the first and second openings h1 and h2, if necessary.

[0029] FIG. 4 is a cross-sectional view that illustrates a schematic modification of the printed circuit board of FIG.

[0030] Referring to the drawings, the printed circuit board 100B according to the modified example may further include a fourth cavity C4 that penetrates from the first cavity C1 through another part of the first insulating layer 111 in the first direction and is connected to the first cavity C1 in the printed circuit board 100A according to the above example. The fourth cavity C4 may expose at least one of the plurality of build-up wiring layers 121, 124, for example, at least a part of the first wiring layer 121. The first and fourth cavities C1, C4 may have different inclinations of the wall surface. For example, the fourth cavity C4 may have a larger inclination of the wall surface than the first cavity C1. For example, the first cavity C1 may have a substantially vertical wall surface, and the fourth cavity C4 may have a tapered wall surface in which the width on the side connected to the first cavity C1 in the cross section is larger than the width on the opposite side. In this case, the first to fourth cavities C1, C2, C3, and C4 are connected to each other, so that the overall depth of the cavities can be made deeper, and the cavity depth can be adjusted more easily. Also, the first cavity C1 can have a larger average width on the cross section than the fourth cavity C4. Therefore, the cavity can become wider toward the entrance, which makes it easier to mount components in the cavity. Also, the fourth cavity C4 can be formed in a process separate from the first cavity C1, so that the cavity depth can be adjusted more easily.

[0031] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, so that a duplicated description thereof will be omitted.

[0032] 5a to 5j are cross-sectional views illustrating steps of a manufacturing method for the printed circuit board of FIG. 3 and FIG.

[0033] 5a, a metal block 320 is formed on both sides of a detached carrier 310 based on a first direction. Copper foil may be disposed on both sides of the detached carrier 310, and the metal block 320 may be formed by, for example, electrolytic plating using the copper foil as a seed layer.

[0034] Referring to FIG. 5b, a first insulating layer 111 is formed on both sides of the detached carrier 310 to embed the metal block 320. The first insulating layer 111 may be formed to be thicker than the metal block 320. The first insulating layer 111 may be formed by a lamination process. In addition, a first wiring layer 121 is formed on the first insulating layer 111 by a plating process. For example, the first wiring layer 121 may be formed by using an additive process (AP), semi-AP (SAP), modified SAP (MSAP), tenting (TT), etc.

[0035] 5c, a plurality of build-up insulating layers 113, a plurality of build-up wiring layers 121, 124, and a plurality of build-up via layers 133 are formed on a first insulating layer 111. The build-up insulating layer 113, the plurality of build-up wiring layers 121, 124, and the plurality of build-up via layers 133 may be formed by a build-up process. The build-up insulating layer 113 may be formed by a lamination process. The plurality of build-up wiring layers 121, 124, and the plurality of build-up via layers 133 may be formed by a plating process, and at this time, a laser drill or a mechanical drill may be used for via hole processing.

[0036] 5d, the manufactured laminate is separated from the detachment carrier 310. At this time, the copper foil of the detachment carrier 310 may remain on the laminate, if necessary.

[0037] 5e, a build-up process is further performed to form a second wiring layer 122 and a first via layer 131 in the first insulating layer 111. In addition, a build-up wiring layer 124 and a build-up via layer 133 are further formed on the outermost side of the laminate.

[0038] 5f, a build-up process is further performed to form a second insulating layer 112 on the first insulating layer 111. In addition, a third wiring layer 123 and a second via layer 132 are formed in the second insulating layer 112.

[0039] 5g, first and second resist layers 141, 142 are formed on both sides of the laminate. The first and second resist layers 141, 142 can be formed by coating or lamination. Next, the first and second openings h1, h2 and the third cavity C3 are formed in the first and second resist layers 141, 142. The first and second openings h1, h2 and the third cavity C3 can be formed by laser processing, but are not limited to this, and other methods such as an etching method may be used.

[0040] 5h, a second cavity C2 is formed in the second insulating layer 112. The second cavity C2 can be formed by laser processing. For example, the second cavity C2 can be formed by laser processing the second insulating layer 112 exposed from the third cavity C3, and the metal block 320 embedded in the first insulating layer 111 can be exposed.

[0041] 5i, a first cavity C1 is formed in the first insulating layer 111. The first cavity C1 may be formed by etching away the metal block 320. Through a series of processes, the printed circuit board 100A according to the above example may be manufactured.

[0042] Referring to Fig. 5j, a fourth cavity C4 is formed in the first insulating layer 111. The fourth cavity C4 can be formed by laser processing. For example, the fourth cavity C4 can be formed by processing the first insulating layer 111 exposed from the first to third cavities C1, C2, and C3 with a laser to expose a part of the first wiring layer 121. Through a series of processes, the printed circuit board 100B according to the above-mentioned modified example can be manufactured.

[0043] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example and the printed circuit board 100B according to the modified example thereof, and therefore, a duplicated description thereof will be omitted.

[0044] FIG. 6 is a cross-sectional view that illustrates a schematic diagram of another example of a printed circuit board.

[0045] Referring to the drawings, the printed circuit board 100C according to another example may have different shapes of the first to third wiring layers 121, 122, 123 and the first and second cavities C1, C2 in the printed circuit board 100A according to the above example. For example, the first wiring layer 121 may be embedded on the first surface S1 side of the first insulating layer 111, and the second wiring layer 122 may be disposed on the second surface S2 of the first insulating layer 111. In addition, the first cavity C1 may penetrate a part of the first insulating layer 111 from the first surface S1 in the first direction, and the second cavity C2 may penetrate the second insulating layer 112 in the first direction and further penetrate another part of the first insulating layer 111 from the second surface S2 to the first cavity C1, and be connected to the first cavity C1. However, similarly, the wall surfaces of the first and second cavities C1, C2 may have different inclinations, and the depth of the first cavity C1 based on the first direction may be smaller than the thickness of the first insulating layer 111 and larger than the respective thicknesses of the first and second wiring layers 121, 122.

[0046] In addition, in the printed circuit board 100B according to another example, the plurality of build-up insulating layers 113-1, 113-2, 113-3, the plurality of build-up wiring layers 121, 124-1, 124-2, and the plurality of build-up via layers 133-1, 133-2, 133-3 in the printed circuit board 100A according to the above example may have a multi-layer core substrate structure, rather than a multi-layer coreless substrate structure. For example, the plurality of build-up insulating layers 113-1, 113-2, 113-3 may include a core insulating layer 113-1 in the center, and the core insulating layer 113-1 may be formed of CCL (Copper Clad Laminate) or other core insulating material. Based on the first direction, the core insulating layer 113-1 may be thicker than each of the other build-up insulating layers 113-2, 113-3. Also, the plurality of build-up via layers 133-1, 133-2, and 133-3 may include a core via layer 133-1 penetrating the core insulating layer 113-1, and the core via layer 133-1 may include a through via. The through via may be formed by filling a through hole with the above-mentioned metal material, or may include a PTH (Plated Through Hole) in which the above-mentioned metal material is conformally formed on the wall surface of the through hole by plating and an insulating material is filled inside. The through via may have a rectangular or hourglass shape in cross section, but is not limited thereto. The bottom surface of the first cavity C1 may be provided through an exposed surface of the plurality of build-up insulating layers 113.

[0047] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, so that a duplicated description thereof will be omitted.

[0048] FIG. 7 is a cross-sectional view that illustrates a schematic modification of the printed circuit board of FIG.

[0049] Referring to the drawings, the printed circuit board 100D according to the modified example may further include a fourth cavity C4 that penetrates at least one of the plurality of build-up insulating layers 113-2 among the plurality of build-up insulating layers 113-1, 113-2, and 113-3 in the first direction and is connected to the first cavity C1 in the printed circuit board 100C according to the other example. The fourth cavity C4 may expose at least a part of at least one of the plurality of build-up wiring layers 121, 124-1, and 124-2. The first and fourth cavities C1 and C4 may have different inclinations of the wall surface. For example, the fourth cavity C4 may have a larger inclination of the wall surface than the first cavity C1. For example, the first cavity C1 may have a substantially vertical wall surface, and the fourth cavity C4 may have a tapered wall surface in which the width on the side connected to the first cavity C1 in the cross section is larger than the width on the opposite side.

[0050] The other contents are substantially the same as those described in the above-mentioned example printed circuit board 100A and its modified example printed circuit board 100B, and the above-mentioned other example printed circuit board 100C, so duplicated explanations will be omitted.

[0051] 8a to 8h are cross-sectional views illustrating steps of a method for manufacturing the printed circuit board of FIG. 6 and FIG.

[0052] 8a, a double-sided build-up process is performed based on the core insulating layer 113-1 to form a laminate having a multilayer core substrate structure including a plurality of build-up insulating layers 113-1, 113-2, a plurality of build-up wiring layers 121, 124-1, and a plurality of build-up via layers 133-1, 133-2. A first metal block 321 is formed by a plating process on the outermost build-up insulating layer 113-2, for example, the uppermost build-up insulating layer 113-2, based on the first direction.

[0053] Referring to FIG. 8b, a second metal block 322 is further formed on the first metal block 321 by a plating process, thereby forming a metal block 320 that is thicker than the first wiring layer 121 in the first direction.

[0054] 8c, a first insulating layer 111 in which a metal block 320 is embedded is formed on a plurality of build-up insulating layers 113-1 and 113-2 in a build-up process. A second wiring layer 122 and a first via layer 131 are also formed in the first insulating layer 111. At this time, a build-up insulating layer 113-3, a build-up wiring layer 124-2, and a build-up via layer 133-3 are further formed on the opposite side.

[0055] 8d, in a build-up process, a second insulating layer 112 is formed on the first insulating layer 111. Also, a third wiring layer 123 and a second via layer 132 are formed in the second insulating layer 112. At this time, a build-up insulating layer 113-3, a build-up wiring layer 124-2, and a build-up via layer 133-3 are further formed on the opposite side.

[0056] 8e, first and second resist layers 141, 142 are formed on both sides of the formed laminate. Next, first and second openings h1, h2 and a third cavity C3 are formed in the first and second resist layers 141, 142.

[0057] 8f, a second cavity C2 is formed in the first and second insulating layers 111 and 112. The second cavity C2 can be formed by laser processing. For example, the second cavity C2 can be formed by laser processing the second insulating layer 112 exposed from the third cavity C3, and the metal block 320 embedded in the first insulating layer 111 can be exposed.

[0058] 8g, a first cavity C1 is formed in the first insulating layer 111. The first cavity C1 may be formed by etching away the metal block 320. Through a series of processes, the printed circuit board 100C according to the above-mentioned example may be manufactured.

[0059] Referring to FIG. 8h, a fourth cavity C4 is formed in at least one build-up insulating layer 113-2 of the plurality of build-up insulating layers 113-1, 113-2, and 113-3. The fourth cavity C4 may be formed by laser processing. For example, the fourth cavity C4 may be formed by processing the outermost build-up insulating layer 113-2, for example, the uppermost build-up insulating layer 113-2, exposed from the first to third cavities C1, C2, and C3, of the plurality of build-up insulating layers 113-1, 113-2, and 113-3, based on the first direction. The fourth cavity C4 may expose a part of the outermost build-up wiring layer 124-1, for example, the uppermost build-up wiring layer 124-1, which is next to the first wiring layer 121 based on the first direction, of the plurality of build-up wiring layers 121, 124-1, and 124-2. Through a series of processes, the printed circuit board 100D according to the above-mentioned modified example may be manufactured.

[0060] The other contents are substantially the same as those described in the above-mentioned example of printed circuit board 100A and its modified printed circuit board 100B and an example of a manufacturing method thereof, as well as the above-mentioned other example of printed circuit board 100C and its modified printed circuit board 100D, and therefore duplicated explanations will be omitted.

[0061] 9 to 11 are cross-sectional views each showing a schematic diagram of still another example of a printed circuit board.

[0062] 9, a printed circuit board 100E according to another embodiment may have a package-on-package structure in which an electronic component 210 is mounted. For example, based on a first direction, a second package substrate 100-2 may be disposed on a first package substrate 100-1, an electronic component 210 may be disposed between the first and second package substrates 100-1 and 100-2, the first and second package substrates 100-1 and 100-2 may be connected to each other through a first electrical connection metal 221, the electronic component 210 may be mounted on the first package substrate 100-1 through a second electrical connection metal 222, at least a portion of the electronic component 210 may be disposed in a cavity C of the second package substrate 100-2, and a third electrical connection metal 223 may be attached to the underside of the first package substrate 100-1. The first package substrate 100-1 may be a core-type or coreless-type multilayer printed circuit board. The second package substrate 100-2 may be the printed circuit board 100A according to the above-mentioned example, but may have fewer layers, such as the build-up insulating layer 113, the build-up wiring layers 121 and 124, and the build-up via layer 133. If necessary, the above-mentioned printed circuit boards 100B, 100C, and 100D may be appropriately modified and applied as the second package substrate 100-2. The electronic component 210 may be an active component and / or a passive component, and may preferably include a semiconductor chip, but is not limited thereto. The first to third electrical connecting metals 221, 222, and 223 may be solder balls or the like. In this way, the printed circuit board 100E according to another example can reduce the total thickness of the module by mounting electronic components by cavity processing of the above-mentioned structure.

[0063] Referring to FIG. 10, the printed circuit board 100F according to another example may have a structure in which a mechanism is arranged in a cavity of a package substrate. For example, a mechanism 230 such as an optical cable may be arranged in a cavity C of the third package substrate 100-3. The third package substrate 100-3 may be the printed circuit board 100C according to the other example described above. As necessary, the printed circuit boards 100A, 100B, and 100D described above may be appropriately modified and applied as the third package substrate 100-3. In this way, the printed circuit board 100F according to another example may provide a deep cavity required to match the height of the chip and the mechanism when a mechanism such as an optical cable is arranged in the package substrate.

[0064] Referring to FIG. 11, the printed circuit board 100G according to another example may have a structure in which a thick component is arranged in a cavity of a package substrate. For example, the fourth package substrate 100-4 may have a thick component 250 such as a power inductor arranged in a cavity C via a fourth electrical connection metal 224 including solder or the like. The fourth package substrate 100-4 may be the printed circuit board 100D according to the above-mentioned modified example. As necessary, the above-mentioned printed circuit boards 100A, 100B, and 100C may be appropriately modified and applied as the fourth package substrate 100-4. In this way, the printed circuit board 100G according to another example may provide a deep cavity required for arranging a thick component such as a power inductor in the package substrate.

[0065] The other contents are substantially the same as those described in the above-mentioned example of printed circuit board 100A and its modified printed circuit board 100B, as well as the above-mentioned other example of printed circuit board 100C and its modified printed circuit board 100D, and therefore duplicated explanations will be omitted.

[0066] In the present invention, the inclination of the wall surface can be compared by measuring the angle of the wall surface measured inside each cavity with reference to a second direction perpendicular to the first direction.

[0067] In the present invention, the term "cover" can include not only the case of covering entirely, but also the case of covering at least a part, and can include not only the case of covering directly, but also the case of covering indirectly. Furthermore, the term "fill" can include not only the case of filling completely, but also the case of filling almost entirely, for example, the case where some gaps or voids are present.

[0068] In the present invention, the meaning of "on a cross section" can mean the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when an object is viewed from a side. Also, the meaning of "on a plane" can mean the planar shape when an object is cut horizontally, or the planar shape when an object is viewed from a top view or a bottom view.

[0069] In the present invention, the "thickness, width, length, depth" and the like can be measured with a scanning microscope or optical microscope based on a cross section obtained by polishing or cutting the printed circuit board. The cut section can be a vertical section or a horizontal section, and each value can be measured based on the required cut section. If the value is not constant, the value can be determined by averaging the values ​​measured at any five points. The upper and / or lower widths of the vias and cavities can be measured on a cross section cut along the central axis of the vias or cavities in the thickness direction of the board. The depths of the vias and cavities can be measured as the distance from the upper end to the lower end of each object on a cross section cut along the central axis of each object in the thickness direction of the board. The average width of the vias and cavities can be determined by averaging the values ​​measured for the upper width and the lower width.

[0070] In the present invention, for convenience, terms such as "lower side, lower part" are used to mean the lower direction in a first direction based on the cross section of the drawing, and terms such as "upper side, upper part" are used to mean the upper direction in the first direction. Furthermore, terms such as "side" are used to mean the second direction. The thickness direction is used to mean the first direction based on the cross section of the drawing, just like terms such as "lower side, lower part, upper side, upper part". However, this is a definition of the direction for convenience of explanation, and it goes without saying that the scope of the claims is not particularly limited by the description of the directions, and the concepts of upper / lower can be changed at any time.

[0071] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0072] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0073] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0074] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060:Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140: Speaker 100A, 100B, 100C, 100D, 100E, 100F, 100G: Printed circuit boards 100-1, 100-2, 100-3, 100-4: Package substrate 111, 112, 113, 113-1, 113-2, 113-3: insulating layer 121, 122, 123, 124, 124-1, 124-2: Wiring layer 131, 132, 133, 133-1, 133-2, 133-3: via layers 141, 142: resist layer C, C1, C2, C3, C4: Cavity 210: Electronic components 221, 222, 223: Electrically connected metals 230: Mechanical objects 250: Parts 310: Detachable carrier 320: Metal block

Claims

1. a first insulating layer having a first surface and a second surface opposed to each other in a first direction; a first wiring layer disposed on the first surface side of the first insulating layer; a second wiring layer disposed on the second surface side of the first insulating layer; a second insulating layer having a third surface and a fourth surface facing each other in the first direction, the second insulating layer being disposed on the first insulating layer such that the third surface is connected to the second surface; a third wiring layer disposed on the fourth surface side of the second insulating layer; a first cavity penetrating at least a portion of the first insulating layer from the first surface or the second surface in the first direction; a second cavity penetrating at least a portion of the second insulating layer in the first direction and connected to the first cavity, The first cavity and the second cavity have wall surfaces with different inclinations, A printed circuit board, wherein a depth of the first cavity in the first direction is smaller than a thickness of the first insulating layer and larger than each of the thicknesses of the first wiring layer and the second wiring layer.

2. The printed circuit board of claim 1 , wherein the second cavity has a wall slope greater than that of the first cavity.

3. the first cavity has substantially vertical walls; 3. The printed circuit board according to claim 2, wherein the second cavity has a tapered wall surface in which the width on a side connected to the first cavity is smaller than the width on the opposite side in cross section.

4. a resist layer having a fifth surface and a sixth surface facing each other in the first direction, the fifth surface being connected to the fourth surface, the resist layer being disposed on the second insulating layer, and having an opening exposing at least a portion of the third wiring layer; a third cavity extending through at least a portion of the resist layer in the first direction and connected to the second cavity, The printed circuit board of claim 1 , wherein the second cavity and the third cavity have wall slopes different from each other.

5. a first via layer penetrating the first insulating layer in the first direction and connecting at least a portion of the first wiring layer and the second wiring layer to each other; a second via layer penetrating the second insulating layer in the first direction and connecting at least a portion of the second wiring layer and the third wiring layer to each other; a plurality of build-up insulating layers disposed on the first surface side of the first insulating layer; a plurality of build-up wiring layers each including the first wiring layer, the build-up wiring layers being disposed on or within the plurality of build-up insulating layers in the first direction; The printed circuit board of claim 1 , further comprising: a plurality of build-up via layers each penetrating at least one of the plurality of build-up insulating layers in the first direction.

6. The printed circuit board of claim 5 , wherein the first cavity penetrates a portion of the first insulating layer from the second surface in the first direction.

7. a fourth cavity extending from the first cavity through another portion of the first insulating layer in the first direction and connected to the first cavity, the fourth cavity exposes at least a portion of at least one of the plurality of build-up wiring layers; The printed circuit board of claim 6 , wherein the fourth cavity has a wall slope greater than that of the first cavity.

8. the first cavity has substantially vertical walls; The printed circuit board according to claim 7 , wherein the fourth cavity has a tapered wall surface in which the width on a side connected to the first cavity is greater than the width on the opposite side in cross section.

9. the first cavity penetrates a portion of the first insulating layer from the first surface in the first direction; The printed circuit board of claim 5 , wherein the second cavity further penetrates another portion of the first insulating layer in the first direction from the second surface to the first cavity.

10. a fourth cavity penetrating at least a portion of at least one of the plurality of build-up insulating layers in the first direction and connected to the first cavity, the fourth cavity exposes at least a portion of at least one of the plurality of build-up wiring layers; The printed circuit board of claim 9 , wherein the fourth cavity has a wall slope greater than that of the first cavity.

11. the first cavity has substantially vertical walls; The printed circuit board according to claim 10 , wherein the fourth cavity has a tapered wall surface in which the width on a side connected to the first cavity is greater than the width on the opposite side in cross section.

12. a first insulating layer having a first cavity; a first wiring layer and a second wiring layer disposed on an upper surface and a lower surface of the first insulating layer, respectively; a second insulating layer disposed on a lower surface of the first insulating layer, covering at least a portion of the second wiring layer, and having a second cavity connected to the first cavity; a third wiring layer disposed on a lower surface of the second insulating layer; The first cavity is disposed at a level between the first wiring layer and the second wiring layer.

13. The printed circuit board according to claim 12 , wherein no wiring layer is disposed between the first wiring layer and the second wiring layer.

14. 13. The printed circuit board of claim 12, further comprising a resist layer disposed on a lower surface of the second insulating layer, covering at least a portion of the third wiring layer, having an opening that exposes at least another portion of the third wiring layer, and having a third cavity connected to the second cavity.

15. the first insulating layer further includes a fourth cavity connected to the first cavity, the fourth cavity is disposed at a level between the first wiring layer and the second wiring layer; The printed circuit board of claim 14 , wherein the fourth cavity exposes at least a portion of the first wiring layer.

16. On the cross section, the average width of the first cavity is greater than the average width of the fourth cavity; the average width of the second cavity is greater than the average width of the first cavity; 16. The printed circuit board of claim 15, wherein the average width of the third cavity is greater than the average width of the second cavity.

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